src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_string.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30
  31 #include "drm/freedreno_drmif.h"
  32
  33 #include "ir3_shader.h"
  34 #include "ir3_compiler.h"
  35 #include "ir3_nir.h"
  36
  37 int
  38 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  39 {
  40         return glsl_count_attribute_slots(type, false);
  41 }
  42
  43 static void
  44 delete_variant(struct ir3_shader_variant *v)
  45 {
  46         if (v->ir)
  47                 ir3_destroy(v->ir);
  48         if (v->bo)
  49                 fd_bo_del(v->bo);
  50         if (v->immediates)
  51                 free(v->immediates);
  52         free(v);
  53 }
  54
  55 /* for vertex shader, the inputs are loaded into registers before the shader
  56  * is executed, so max_regs from the shader instructions might not properly
  57  * reflect the # of registers actually used, especially in case passthrough
  58  * varyings.
  59  *
  60  * Likewise, for fragment shader, we can have some regs which are passed
  61  * input values but never touched by the resulting shader (ie. as result
  62  * of dead code elimination or simply because we don't know how to turn
  63  * the reg off.
  64  */
  65 static void
  66 fixup_regfootprint(struct ir3_shader_variant *v)
  67 {
  68         unsigned i;
  69
  70         for (i = 0; i < v->inputs_count; i++) {
  71                 /* skip frag inputs fetch via bary.f since their reg's are
  72                  * not written by gpu before shader starts (and in fact the
  73                  * regid's might not even be valid)
  74                  */
  75                 if (v->inputs[i].bary)
  76                         continue;
  77
  78                 /* ignore high regs that are global to all threads in a warp
  79                  * (they exist by default) (a5xx+)
  80                  */
  81                 if (v->inputs[i].regid >= regid(48,0))
  82                         continue;
  83
  84                 if (v->inputs[i].compmask) {
  85                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  86                         int32_t regid = (v->inputs[i].regid + n) >> 2;
  87                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  88                 }
  89         }
  90
  91         for (i = 0; i < v->outputs_count; i++) {
  92                 int32_t regid = (v->outputs[i].regid + 3) >> 2;
  93                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  94         }
  95 }
  96
  97 /* wrapper for ir3_assemble() which does some info fixup based on
  98  * shader state.  Non-static since used by ir3_cmdline too.
  99  */
 100 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 101 {
 102         void *bin;
 103
 104         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 105         if (!bin)
 106                 return NULL;
 107
 108         if (gpu_id >= 400) {
 109                 v->instrlen = v->info.sizedwords / (2 * 16);
 110         } else {
 111                 v->instrlen = v->info.sizedwords / (2 * 4);
 112         }
 113
 114         /* NOTE: if relative addressing is used, we set constlen in
 115          * the compiler (to worst-case value) since we don't know in
 116          * the assembler what the max addr reg value can be:
 117          */
 118         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 119
 120         fixup_regfootprint(v);
 121
 122         return bin;
 123 }
 124
 125 static void
 126 assemble_variant(struct ir3_shader_variant *v)
 127 {
 128         struct ir3_compiler *compiler = v->shader->compiler;
 129         struct shader_info *info = &v->shader->nir->info;
 130         uint32_t gpu_id = compiler->gpu_id;
 131         uint32_t sz, *bin;
 132
 133         bin = ir3_shader_assemble(v, gpu_id);
 134         sz = v->info.sizedwords * 4;
 135
 136         v->bo = fd_bo_new(compiler->dev, sz,
 137                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 138                         DRM_FREEDRENO_GEM_TYPE_KMEM,
 139                         "%s:%s", ir3_shader_stage(v->shader), info->name);
 140
 141         memcpy(fd_bo_map(v->bo), bin, sz);
 142
 143         if (ir3_shader_debug & IR3_DBG_DISASM) {
 144                 struct ir3_shader_key key = v->key;
 145                 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 146                         v->binning_pass, key.color_two_side, key.half_precision);
 147                 ir3_shader_disasm(v, bin, stdout);
 148         }
 149
 150         if (shader_debug_enabled(v->shader->type)) {
 151                 fprintf(stderr, "Native code for unnamed %s shader %s:\n",
 152                         _mesa_shader_stage_to_string(v->shader->type),
 153                         v->shader->nir->info.name);
 154                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 155                         fprintf(stderr, "SIMD0\n");
 156                 ir3_shader_disasm(v, bin, stderr);
 157         }
 158
 159         free(bin);
 160
 161         /* no need to keep the ir around beyond this point: */
 162         ir3_destroy(v->ir);
 163         v->ir = NULL;
 164 }
 165
 166 static struct ir3_shader_variant *
 167 create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 168                 bool binning_pass)
 169 {
 170         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 171         int ret;
 172
 173         if (!v)
 174                 return NULL;
 175
 176         v->id = ++shader->variant_count;
 177         v->shader = shader;
 178         v->binning_pass = binning_pass;
 179         v->key = *key;
 180         v->type = shader->type;
 181
 182         ret = ir3_compile_shader_nir(shader->compiler, v);
 183         if (ret) {
 184                 debug_error("compile failed!");
 185                 goto fail;
 186         }
 187
 188         assemble_variant(v);
 189         if (!v->bo) {
 190                 debug_error("assemble failed!");
 191                 goto fail;
 192         }
 193
 194         return v;
 195
 196 fail:
 197         delete_variant(v);
 198         return NULL;
 199 }
 200
 201 static inline struct ir3_shader_variant *
 202 shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 203                 bool *created)
 204 {
 205         struct ir3_shader_variant *v;
 206
 207         *created = false;
 208
 209         for (v = shader->variants; v; v = v->next)
 210                 if (ir3_shader_key_equal(key, &v->key))
 211                         return v;
 212
 213         /* compile new variant if it doesn't exist already: */
 214         v = create_variant(shader, key, false);
 215         if (v) {
 216                 v->next = shader->variants;
 217                 shader->variants = v;
 218                 *created = true;
 219         }
 220
 221         return v;
 222 }
 223
 224 struct ir3_shader_variant *
 225 ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 226                 bool binning_pass, bool *created)
 227 {
 228         struct ir3_shader_variant *v =
 229                         shader_variant(shader, key, created);
 230
 231         if (v && binning_pass) {
 232                 if (!v->binning)
 233                         v->binning = create_variant(shader, key, true);
 234                 return v->binning;
 235         }
 236
 237         return v;
 238 }
 239
 240 void
 241 ir3_shader_destroy(struct ir3_shader *shader)
 242 {
 243         struct ir3_shader_variant *v, *t;
 244         for (v = shader->variants; v; ) {
 245                 t = v;
 246                 v = v->next;
 247                 delete_variant(t);
 248         }
 249         ralloc_free(shader->nir);
 250         free(shader);
 251 }
 252
 253 struct ir3_shader *
 254 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
 255 {
 256         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 257
 258         shader->compiler = compiler;
 259         shader->id = ++shader->compiler->shader_count;
 260         shader->type = nir->info.stage;
 261
 262         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 263                            (nir_lower_io_options)0);
 264
 265         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 266                 /* NOTE: lower load_barycentric_at_sample first, since it
 267                  * produces load_barycentric_at_offset:
 268                  */
 269                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 270                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 271
 272                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 273         }
 274
 275         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 276
 277         /* do first pass optimization, ignoring the key: */
 278         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 279         if (ir3_shader_debug & IR3_DBG_DISASM) {
 280                 printf("dump nir%d: type=%d", shader->id, shader->type);
 281                 nir_print_shader(shader->nir, stdout);
 282         }
 283
 284         return shader;
 285 }
 286
 287 static void dump_reg(FILE *out, const char *name, uint32_t r)
 288 {
 289         if (r != regid(63,0))
 290                 fprintf(out, "; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 291 }
 292
 293 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 294                 unsigned slot, const char *name)
 295 {
 296         uint32_t regid;
 297         regid = ir3_find_output_regid(so, slot);
 298         dump_reg(out, name, regid);
 299 }
 300
 301 void
 302 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 303 {
 304         struct ir3 *ir = so->ir;
 305         struct ir3_register *reg;
 306         const char *type = ir3_shader_stage(so->shader);
 307         uint8_t regid;
 308         unsigned i;
 309
 310         for (i = 0; i < ir->ninputs; i++) {
 311                 if (!ir->inputs[i]) {
 312                         fprintf(out, "; in%d unused\n", i);
 313                         continue;
 314                 }
 315                 reg = ir->inputs[i]->regs[0];
 316                 regid = reg->num;
 317                 fprintf(out, "@in(%sr%d.%c)\tin%d\n",
 318                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 319                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 320         }
 321
 322         for (i = 0; i < ir->noutputs; i++) {
 323                 if (!ir->outputs[i]) {
 324                         fprintf(out, "; out%d unused\n", i);
 325                         continue;
 326                 }
 327                 /* kill shows up as a virtual output.. skip it! */
 328                 if (is_kill(ir->outputs[i]))
 329                         continue;
 330                 reg = ir->outputs[i]->regs[0];
 331                 regid = reg->num;
 332                 fprintf(out, "@out(%sr%d.%c)\tout%d\n",
 333                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 334                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 335         }
 336
 337         for (i = 0; i < so->immediates_count; i++) {
 338                 fprintf(out, "@const(c%d.x)\t", so->constbase.immediate + i);
 339                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 340                                 so->immediates[i].val[0],
 341                                 so->immediates[i].val[1],
 342                                 so->immediates[i].val[2],
 343                                 so->immediates[i].val[3]);
 344         }
 345
 346         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 347
 348         switch (so->type) {
 349         case MESA_SHADER_VERTEX:
 350                 fprintf(out, "; %s: outputs:", type);
 351                 for (i = 0; i < so->outputs_count; i++) {
 352                         uint8_t regid = so->outputs[i].regid;
 353                         fprintf(out, " r%d.%c (%s)",
 354                                         (regid >> 2), "xyzw"[regid & 0x3],
 355                                         gl_varying_slot_name(so->outputs[i].slot));
 356                 }
 357                 fprintf(out, "\n");
 358                 fprintf(out, "; %s: inputs:", type);
 359                 for (i = 0; i < so->inputs_count; i++) {
 360                         uint8_t regid = so->inputs[i].regid;
 361                         fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
 362                                         (regid >> 2), "xyzw"[regid & 0x3],
 363                                         so->inputs[i].compmask,
 364                                         so->inputs[i].inloc,
 365                                         so->inputs[i].bary);
 366                 }
 367                 fprintf(out, "\n");
 368                 break;
 369         case MESA_SHADER_FRAGMENT:
 370                 fprintf(out, "; %s: outputs:", type);
 371                 for (i = 0; i < so->outputs_count; i++) {
 372                         uint8_t regid = so->outputs[i].regid;
 373                         fprintf(out, " r%d.%c (%s)",
 374                                         (regid >> 2), "xyzw"[regid & 0x3],
 375                                         gl_frag_result_name(so->outputs[i].slot));
 376                 }
 377                 fprintf(out, "\n");
 378                 fprintf(out, "; %s: inputs:", type);
 379                 for (i = 0; i < so->inputs_count; i++) {
 380                         uint8_t regid = so->inputs[i].regid;
 381                         fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
 382                                         (regid >> 2), "xyzw"[regid & 0x3],
 383                                         gl_varying_slot_name(so->inputs[i].slot),
 384                                         so->inputs[i].compmask,
 385                                         so->inputs[i].inloc,
 386                                         so->inputs[i].bary);
 387                 }
 388                 fprintf(out, "\n");
 389                 break;
 390         default:
 391                 /* TODO */
 392                 break;
 393         }
 394
 395         /* print generic shader info: */
 396         fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
 397                         type, so->shader->id, so->id,
 398                         so->info.instrs_count,
 399                         so->info.max_half_reg + 1,
 400                         so->info.max_reg + 1);
 401
 402         fprintf(out, "; %d const, %u constlen\n",
 403                         so->info.max_const + 1,
 404                         so->constlen);
 405
 406         fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
 407
 408         fprintf(out, "; max_sun=%u\n", ir->max_sun);
 409
 410         /* print shader type specific info: */
 411         switch (so->type) {
 412         case MESA_SHADER_VERTEX:
 413                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 414                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 415                 break;
 416         case MESA_SHADER_FRAGMENT:
 417                 dump_reg(out, "pos (ij_pixel)",
 418                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PIXEL));
 419                 dump_reg(out, "pos (ij_centroid)",
 420                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_CENTROID));
 421                 dump_reg(out, "pos (ij_size)",
 422                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_SIZE));
 423                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 424                 if (so->color0_mrt) {
 425                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 426                 } else {
 427                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 428                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 429                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 430                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 431                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 432                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 433                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 434                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 435                 }
 436                 /* these two are hard-coded since we don't know how to
 437                  * program them to anything but all 0's...
 438                  */
 439                 if (so->frag_coord)
 440                         fprintf(out, "; fragcoord: r0.x\n");
 441                 if (so->frag_face)
 442                         fprintf(out, "; fragface: hr0.x\n");
 443                 break;
 444         default:
 445                 /* TODO */
 446                 break;
 447         }
 448
 449         fprintf(out, "\n");
 450 }
 451
 452 uint64_t
 453 ir3_shader_outputs(const struct ir3_shader *so)
 454 {
 455         return so->nir->info.outputs_written;
 456 }