2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_atomic.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
33 #include "drm/freedreno_drmif.h"
35 #include "ir3_shader.h"
36 #include "ir3_compiler.h"
40 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
42 return glsl_count_attribute_slots(type
, false);
45 /* for vertex shader, the inputs are loaded into registers before the shader
46 * is executed, so max_regs from the shader instructions might not properly
47 * reflect the # of registers actually used, especially in case passthrough
50 * Likewise, for fragment shader, we can have some regs which are passed
51 * input values but never touched by the resulting shader (ie. as result
52 * of dead code elimination or simply because we don't know how to turn
56 fixup_regfootprint(struct ir3_shader_variant
*v
)
60 for (i
= 0; i
< v
->inputs_count
; i
++) {
61 /* skip frag inputs fetch via bary.f since their reg's are
62 * not written by gpu before shader starts (and in fact the
63 * regid's might not even be valid)
65 if (v
->inputs
[i
].bary
)
68 /* ignore high regs that are global to all threads in a warp
69 * (they exist by default) (a5xx+)
71 if (v
->inputs
[i
].regid
>= regid(48,0))
74 if (v
->inputs
[i
].compmask
) {
75 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
76 int32_t regid
= v
->inputs
[i
].regid
+ n
;
77 if (v
->inputs
[i
].half
) {
79 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
81 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
84 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
89 for (i
= 0; i
< v
->outputs_count
; i
++) {
90 /* for ex, VS shaders with tess don't have normal varying outs: */
91 if (!VALIDREG(v
->outputs
[i
].regid
))
93 int32_t regid
= v
->outputs
[i
].regid
+ 3;
94 if (v
->outputs
[i
].half
) {
96 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
98 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
101 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
105 for (i
= 0; i
< v
->num_sampler_prefetch
; i
++) {
106 unsigned n
= util_last_bit(v
->sampler_prefetch
[i
].wrmask
) - 1;
107 int32_t regid
= v
->sampler_prefetch
[i
].dst
+ n
;
108 if (v
->sampler_prefetch
[i
].half_precision
) {
109 if (!v
->mergedregs
) {
110 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
112 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
115 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
120 /* wrapper for ir3_assemble() which does some info fixup based on
121 * shader state. Non-static since used by ir3_cmdline too.
123 void * ir3_shader_assemble(struct ir3_shader_variant
*v
)
125 unsigned gpu_id
= v
->shader
->compiler
->gpu_id
;
128 bin
= ir3_assemble(v
);
133 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
135 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
138 /* NOTE: if relative addressing is used, we set constlen in
139 * the compiler (to worst-case value) since we don't know in
140 * the assembler what the max addr reg value can be:
142 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
144 /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
145 * uploads are in units of 4 dwords. Round it up here to make calculations
146 * regarding the shared constlen simpler.
149 v
->constlen
= align(v
->constlen
, 4);
151 fixup_regfootprint(v
);
157 assemble_variant(struct ir3_shader_variant
*v
)
159 v
->bin
= ir3_shader_assemble(v
);
161 if (shader_debug_enabled(v
->shader
->type
)) {
162 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
163 ir3_shader_stage(v
), v
->shader
->nir
->info
.name
);
164 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
165 fprintf(stdout
, "SIMD0\n");
166 ir3_shader_disasm(v
, v
->bin
, stdout
);
169 /* no need to keep the ir around beyond this point: */
175 compile_variant(struct ir3_shader_variant
*v
)
177 int ret
= ir3_compile_shader_nir(v
->shader
->compiler
, v
);
179 debug_error("compile failed!");
185 debug_error("assemble failed!");
193 * For creating normal shader variants, 'nonbinning' is NULL. For
194 * creating binning pass shader, it is link to corresponding normal
195 * (non-binning) variant.
197 static struct ir3_shader_variant
*
198 alloc_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
199 struct ir3_shader_variant
*nonbinning
)
201 void *mem_ctx
= shader
;
202 /* hang the binning variant off it's non-binning counterpart instead
203 * of the shader, to simplify the error cleanup paths
206 mem_ctx
= nonbinning
;
207 struct ir3_shader_variant
*v
= rzalloc_size(mem_ctx
, sizeof(*v
));
212 v
->id
= ++shader
->variant_count
;
214 v
->binning_pass
= !!nonbinning
;
215 v
->nonbinning
= nonbinning
;
217 v
->type
= shader
->type
;
218 v
->mergedregs
= shader
->compiler
->gpu_id
>= 600;
220 if (!v
->binning_pass
)
221 v
->const_state
= rzalloc_size(v
, sizeof(*v
->const_state
));
227 needs_binning_variant(struct ir3_shader_variant
*v
)
229 if ((v
->type
== MESA_SHADER_VERTEX
) && ir3_has_binning_vs(&v
->key
))
234 static struct ir3_shader_variant
*
235 create_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
)
237 struct ir3_shader_variant
*v
= alloc_variant(shader
, key
, NULL
);
242 if (needs_binning_variant(v
)) {
243 v
->binning
= alloc_variant(shader
, key
, v
);
248 if (ir3_disk_cache_retrieve(shader
->compiler
, v
))
251 if (!shader
->nir_finalized
) {
252 ir3_nir_post_finalize(shader
->compiler
, shader
->nir
);
254 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
255 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
256 nir_print_shader(shader
->nir
, stdout
);
259 shader
->nir_finalized
= true;
262 if (!compile_variant(v
))
265 if (needs_binning_variant(v
) && !compile_variant(v
->binning
))
268 ir3_disk_cache_store(shader
->compiler
, v
);
277 static inline struct ir3_shader_variant
*
278 shader_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
)
280 struct ir3_shader_variant
*v
;
282 for (v
= shader
->variants
; v
; v
= v
->next
)
283 if (ir3_shader_key_equal(key
, &v
->key
))
289 struct ir3_shader_variant
*
290 ir3_shader_get_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
291 bool binning_pass
, bool *created
)
293 mtx_lock(&shader
->variants_lock
);
294 struct ir3_shader_variant
*v
= shader_variant(shader
, key
);
297 /* compile new variant if it doesn't exist already: */
298 v
= create_variant(shader
, key
);
300 v
->next
= shader
->variants
;
301 shader
->variants
= v
;
306 if (v
&& binning_pass
) {
311 mtx_unlock(&shader
->variants_lock
);
317 ir3_shader_destroy(struct ir3_shader
*shader
)
319 ralloc_free(shader
->nir
);
320 mtx_destroy(&shader
->variants_lock
);
325 * Creates a bitmask of the used bits of the shader key by this particular
326 * shader. Used by the gallium driver to skip state-dependent recompiles when
330 ir3_setup_used_key(struct ir3_shader
*shader
)
332 nir_shader
*nir
= shader
->nir
;
333 struct shader_info
*info
= &nir
->info
;
334 struct ir3_shader_key
*key
= &shader
->key_mask
;
336 /* This key flag is just used to make for a cheaper ir3_shader_key_equal
337 * check in the common case.
339 key
->has_per_samp
= true;
341 key
->safe_constlen
= true;
343 key
->ucp_enables
= 0xff;
345 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
346 key
->fsaturate_s
= ~0;
347 key
->fsaturate_t
= ~0;
348 key
->fsaturate_r
= ~0;
349 key
->fastc_srgb
= ~0;
352 if (info
->inputs_read
& VARYING_BITS_COLOR
) {
353 key
->rasterflat
= true;
354 key
->color_two_side
= true;
357 if ((info
->outputs_written
& ~(FRAG_RESULT_DEPTH
|
358 FRAG_RESULT_STENCIL
|
359 FRAG_RESULT_SAMPLE_MASK
)) != 0) {
360 key
->fclamp_color
= true;
363 /* Only used for deciding on behavior of
364 * nir_intrinsic_load_barycentric_sample
366 key
->msaa
= info
->fs
.uses_sample_qualifier
;
368 key
->tessellation
= ~0;
371 if (info
->outputs_written
& VARYING_BITS_COLOR
)
372 key
->vclamp_color
= true;
374 if (info
->stage
== MESA_SHADER_VERTEX
) {
375 key
->vsaturate_s
= ~0;
376 key
->vsaturate_t
= ~0;
377 key
->vsaturate_r
= ~0;
378 key
->vastc_srgb
= ~0;
385 /* Given an array of constlen's, decrease some of them so that the sum stays
386 * within "combined_limit" while trying to fairly share the reduction. Returns
387 * a bitfield of which stages should be trimmed.
390 trim_constlens(unsigned *constlens
,
391 unsigned first_stage
, unsigned last_stage
,
392 unsigned combined_limit
, unsigned safe_limit
)
394 unsigned cur_total
= 0;
395 for (unsigned i
= first_stage
; i
<= last_stage
; i
++) {
396 cur_total
+= constlens
[i
];
400 unsigned max_const
= 0;
401 uint32_t trimmed
= 0;
403 while (cur_total
> combined_limit
) {
404 for (unsigned i
= first_stage
; i
<= last_stage
; i
++) {
405 if (constlens
[i
] >= max_const
) {
407 max_const
= constlens
[i
];
411 assert(max_const
> safe_limit
);
412 trimmed
|= 1 << max_stage
;
413 cur_total
= cur_total
- max_const
+ safe_limit
;
414 constlens
[max_stage
] = safe_limit
;
420 /* Figures out which stages in the pipeline to use the "safe" constlen for, in
421 * order to satisfy all shared constlen limits.
424 ir3_trim_constlen(struct ir3_shader_variant
**variants
,
425 const struct ir3_compiler
*compiler
)
427 unsigned constlens
[MESA_SHADER_STAGES
] = {};
429 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
431 constlens
[i
] = variants
[i
]->constlen
;
434 uint32_t trimmed
= 0;
435 STATIC_ASSERT(MESA_SHADER_STAGES
<= 8 * sizeof(trimmed
));
437 /* There are two shared limits to take into account, the geometry limit on
438 * a6xx and the total limit. The frag limit on a6xx only matters for a
439 * single stage, so it's always satisfied with the first variant.
441 if (compiler
->gpu_id
>= 600) {
443 trim_constlens(constlens
, MESA_SHADER_VERTEX
, MESA_SHADER_GEOMETRY
,
444 compiler
->max_const_geom
, compiler
->max_const_safe
);
447 trim_constlens(constlens
, MESA_SHADER_VERTEX
, MESA_SHADER_FRAGMENT
,
448 compiler
->max_const_pipeline
, compiler
->max_const_safe
);
454 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
455 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
)
457 struct ir3_shader
*shader
= rzalloc_size(NULL
, sizeof(*shader
));
459 mtx_init(&shader
->variants_lock
, mtx_plain
);
460 shader
->compiler
= compiler
;
461 shader
->id
= p_atomic_inc_return(&shader
->compiler
->shader_count
);
462 shader
->type
= nir
->info
.stage
;
464 memcpy(&shader
->stream_output
, stream_output
, sizeof(shader
->stream_output
));
465 shader
->num_reserved_user_consts
= reserved_user_consts
;
468 ir3_disk_cache_init_shader_key(compiler
, shader
);
470 ir3_setup_used_key(shader
);
475 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
477 if (r
!= regid(63,0)) {
478 const char *reg_type
= (r
& HALF_REG_ID
) ? "hr" : "r";
479 fprintf(out
, "; %s: %s%d.%c\n", name
, reg_type
,
480 (r
& ~HALF_REG_ID
) >> 2, "xyzw"[r
& 0x3]);
484 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
485 unsigned slot
, const char *name
)
488 regid
= ir3_find_output_regid(so
, slot
);
489 dump_reg(out
, name
, regid
);
493 input_name(struct ir3_shader_variant
*so
, int i
)
495 if (so
->inputs
[i
].sysval
) {
496 return gl_system_value_name(so
->inputs
[i
].slot
);
497 } else if (so
->type
== MESA_SHADER_VERTEX
) {
498 return gl_vert_attrib_name(so
->inputs
[i
].slot
);
500 return gl_varying_slot_name(so
->inputs
[i
].slot
);
505 output_name(struct ir3_shader_variant
*so
, int i
)
507 if (so
->type
== MESA_SHADER_FRAGMENT
) {
508 return gl_frag_result_name(so
->outputs
[i
].slot
);
510 switch (so
->outputs
[i
].slot
) {
511 case VARYING_SLOT_GS_HEADER_IR3
:
513 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
514 return "GS_VERTEX_FLAGS";
515 case VARYING_SLOT_TCS_HEADER_IR3
:
518 return gl_varying_slot_name(so
->outputs
[i
].slot
);
524 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
526 struct ir3
*ir
= so
->ir
;
527 struct ir3_register
*reg
;
528 const char *type
= ir3_shader_stage(so
);
532 foreach_input_n (instr
, i
, ir
) {
533 reg
= instr
->regs
[0];
535 fprintf(out
, "@in(%sr%d.%c)\tin%d",
536 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
537 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
539 if (reg
->wrmask
> 0x1)
540 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
544 /* print pre-dispatch texture fetches: */
545 for (i
= 0; i
< so
->num_sampler_prefetch
; i
++) {
546 const struct ir3_sampler_prefetch
*fetch
= &so
->sampler_prefetch
[i
];
547 fprintf(out
, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
548 fetch
->half_precision
? "h" : "",
549 fetch
->dst
>> 2, "xyzw"[fetch
->dst
& 0x3],
550 fetch
->src
, fetch
->samp_id
, fetch
->tex_id
,
551 fetch
->wrmask
, fetch
->cmd
);
554 foreach_output_n (instr
, i
, ir
) {
555 reg
= instr
->regs
[0];
557 fprintf(out
, "@out(%sr%d.%c)\tout%d",
558 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
559 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
560 if (reg
->wrmask
> 0x1)
561 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
565 const struct ir3_const_state
*const_state
= ir3_const_state(so
);
566 for (i
= 0; i
< const_state
->immediates_count
; i
++) {
567 fprintf(out
, "@const(c%d.x)\t", const_state
->offsets
.immediate
+ i
);
568 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
569 const_state
->immediates
[i
].val
[0],
570 const_state
->immediates
[i
].val
[1],
571 const_state
->immediates
[i
].val
[2],
572 const_state
->immediates
[i
].val
[3]);
575 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
577 fprintf(out
, "; %s: outputs:", type
);
578 for (i
= 0; i
< so
->outputs_count
; i
++) {
579 uint8_t regid
= so
->outputs
[i
].regid
;
580 const char *reg_type
= so
->outputs
[i
].half
? "hr" : "r";
581 fprintf(out
, " %s%d.%c (%s)",
582 reg_type
, (regid
>> 2), "xyzw"[regid
& 0x3],
587 fprintf(out
, "; %s: inputs:", type
);
588 for (i
= 0; i
< so
->inputs_count
; i
++) {
589 uint8_t regid
= so
->inputs
[i
].regid
;
590 fprintf(out
, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
591 (regid
>> 2), "xyzw"[regid
& 0x3],
594 so
->inputs
[i
].compmask
,
600 /* print generic shader info: */
601 fprintf(out
, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
602 type
, so
->shader
->id
, so
->id
,
603 so
->info
.instrs_count
,
605 so
->info
.instrs_count
- so
->info
.nops_count
,
606 so
->info
.mov_count
, so
->info
.cov_count
,
607 so
->info
.sizedwords
);
609 fprintf(out
, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
610 type
, so
->shader
->id
, so
->id
,
612 so
->info
.max_half_reg
+ 1,
613 so
->info
.max_reg
+ 1,
616 fprintf(out
, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
617 type
, so
->shader
->id
, so
->id
,
624 /* print shader type specific info: */
626 case MESA_SHADER_VERTEX
:
627 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
628 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
630 case MESA_SHADER_FRAGMENT
:
631 dump_reg(out
, "pos (ij_pixel)",
632 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
));
633 dump_reg(out
, "pos (ij_centroid)",
634 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
));
635 dump_reg(out
, "pos (ij_size)",
636 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
));
637 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
638 if (so
->color0_mrt
) {
639 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
641 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
642 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
643 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
644 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
645 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
646 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
647 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
648 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
650 dump_reg(out
, "fragcoord",
651 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRAG_COORD
));
652 dump_reg(out
, "fragface",
653 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRONT_FACE
));
664 ir3_shader_outputs(const struct ir3_shader
*so
)
666 return so
->nir
->info
.outputs_written
;