2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 /* user-clip-plane components, up to 8x vec4's: */
64 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
67 #define IR3_MAX_SHADER_BUFFERS 32
68 #define IR3_MAX_SHADER_IMAGES 32
69 #define IR3_MAX_SO_BUFFERS 4
70 #define IR3_MAX_SO_OUTPUTS 64
71 #define IR3_MAX_CONSTANT_BUFFERS 32
75 * Describes the layout of shader consts. This includes:
76 * + Driver lowered UBO ranges
78 * + Image sizes/dimensions
79 * + Driver params (ie. IR3_DP_*)
80 * + TFBO addresses (for generations that do not have hardware streamout)
81 * + Lowered immediates
83 * For consts needed to pass internal values to shader which may or may not
84 * be required, rather than allocating worst-case const space, we scan the
85 * shader and allocate consts as-needed:
87 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
90 * + Image dimensions: needed to calculate pixel offset, but only for
91 * images that have a image_store intrinsic
93 * Layout of constant registers, each section aligned to vec4. Note
94 * that pointer size (ubo, etc) changes depending on generation.
99 * if (vertex shader) {
100 * driver params (IR3_DP_*)
101 * if (stream_output.num_outputs > 0)
102 * stream-out addresses
103 * } else if (compute_shader) {
104 * driver params (IR3_DP_*)
108 * Immediates go last mostly because they are inserted in the CP pass
109 * after the nir -> ir3 frontend.
111 * Note UBO size in bytes should be aligned to vec4
113 struct ir3_const_state
{
115 unsigned num_driver_params
; /* scalar */
118 /* user const start at zero */
120 /* NOTE that a3xx might need a section for SSBO addresses too */
123 unsigned driver_param
;
125 unsigned primitive_param
;
126 unsigned primitive_map
;
131 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
132 uint32_t count
; /* number of consts allocated */
133 /* one const allocated per SSBO which has get_buffer_size,
134 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
137 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
141 uint32_t mask
; /* bitmask of images that have image_store */
142 uint32_t count
; /* number of consts allocated */
143 /* three const allocated per image which has image_store:
144 * + cpp (bytes per pixel)
146 * + array_pitch (z pitch)
148 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
151 unsigned immediate_idx
;
152 unsigned immediates_count
;
153 unsigned immediates_size
;
160 * A single output for vertex transform feedback.
162 struct ir3_stream_output
{
163 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
164 unsigned start_component
:2; /** 0 to 3 */
165 unsigned num_components
:3; /** 1 to 4 */
166 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
167 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
168 unsigned stream
:2; /**< 0 to 3 */
172 * Stream output for vertex transform feedback.
174 struct ir3_stream_output_info
{
175 unsigned num_outputs
;
176 /** stride for an entire vertex for each buffer in dwords */
177 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
180 * Array of stream outputs, in the order they are to be written in.
181 * Selected components are tightly packed into the output buffer.
183 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
188 * Starting from a4xx, HW supports pre-dispatching texture sampling
189 * instructions prior to scheduling a shader stage, when the
190 * coordinate maps exactly to an output of the previous stage.
194 * There is a limit in the number of pre-dispatches allowed for any
197 #define IR3_MAX_SAMPLER_PREFETCH 4
200 * This is the output stream value for 'cmd', as used by blob. It may
201 * encode the return type (in 3 bits) but it hasn't been verified yet.
203 #define IR3_SAMPLER_PREFETCH_CMD 0x4
206 * Stream output for texture sampling pre-dispatches.
208 struct ir3_sampler_prefetch
{
214 uint8_t half_precision
;
219 /* Configuration key used to identify a shader variant.. different
220 * shader variants can be used to implement features not supported
221 * in hw (two sided color), binning-pass vertex shader, etc.
223 struct ir3_shader_key
{
227 * Combined Vertex/Fragment shader parameters:
229 unsigned ucp_enables
: 8;
231 /* do we need to check {v,f}saturate_{s,t,r}? */
232 unsigned has_per_samp
: 1;
235 * Vertex shader variant parameters:
237 unsigned vclamp_color
: 1;
240 * Fragment shader variant parameters:
242 unsigned sample_shading
: 1;
244 unsigned color_two_side
: 1;
245 unsigned half_precision
: 1;
246 /* used when shader needs to handle flat varyings (a4xx)
247 * for front/back color inputs to frag shader:
249 unsigned rasterflat
: 1;
250 unsigned fclamp_color
: 1;
257 /* bitmask of sampler which needs coords clamped for vertex
260 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
262 /* bitmask of sampler which needs coords clamped for frag
265 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
267 /* bitmask of ms shifts */
268 uint32_t vsamples
, fsamples
;
270 /* bitmask of samplers which need astc srgb workaround: */
271 uint16_t vastc_srgb
, fastc_srgb
;
275 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
277 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
278 if (a
->has_per_samp
|| b
->has_per_samp
)
279 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
280 return a
->global
== b
->global
;
283 /* will the two keys produce different lowering for a fragment shader? */
285 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
287 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
288 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
289 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
290 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
291 (last_key
->fsamples
!= key
->fsamples
) ||
292 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
296 if (last_key
->fclamp_color
!= key
->fclamp_color
)
299 if (last_key
->color_two_side
!= key
->color_two_side
)
302 if (last_key
->half_precision
!= key
->half_precision
)
305 if (last_key
->rasterflat
!= key
->rasterflat
)
308 if (last_key
->ucp_enables
!= key
->ucp_enables
)
314 /* will the two keys produce different lowering for a vertex shader? */
316 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
318 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
319 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
320 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
321 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
322 (last_key
->vsamples
!= key
->vsamples
) ||
323 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
327 if (last_key
->vclamp_color
!= key
->vclamp_color
)
330 if (last_key
->ucp_enables
!= key
->ucp_enables
)
336 /* clears shader-key flags which don't apply to the given shader
340 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
343 case MESA_SHADER_FRAGMENT
:
344 if (key
->has_per_samp
) {
345 key
->vsaturate_s
= 0;
346 key
->vsaturate_t
= 0;
347 key
->vsaturate_r
= 0;
350 key
->has_gs
= false; /* FS doesn't care */
353 case MESA_SHADER_VERTEX
:
354 case MESA_SHADER_GEOMETRY
:
355 key
->color_two_side
= false;
356 key
->half_precision
= false;
357 key
->rasterflat
= false;
358 if (key
->has_per_samp
) {
359 key
->fsaturate_s
= 0;
360 key
->fsaturate_t
= 0;
361 key
->fsaturate_r
= 0;
373 * On a4xx+a5xx, Images share state with textures and SSBOs:
375 * + Uses texture (cat5) state/instruction (isam) to read
376 * + Uses SSBO state and instructions (cat6) to write and for atomics
378 * Starting with a6xx, Images and SSBOs are basically the same thing,
379 * with texture state and isam also used for SSBO reads.
381 * On top of that, gallium makes the SSBO (shader_buffers) state semi
382 * sparse, with the first half of the state space used for atomic
383 * counters lowered to atomic buffers. We could ignore this, but I
384 * don't think we could *really* handle the case of a single shader
385 * that used the max # of textures + images + SSBOs. And once we are
386 * offsetting images by num_ssbos (or visa versa) to map them into
387 * the same hardware state, the hardware state has become coupled to
388 * the shader state, so at this point we might as well just use a
389 * mapping table to remap things from image/SSBO idx to hw idx.
391 * To make things less (more?) confusing, for the hw "SSBO" state
392 * (since it is really both SSBO and Image) I'll use the name "IBO"
394 struct ir3_ibo_mapping
{
395 #define IBO_INVALID 0xff
396 /* Maps logical SSBO state to hw state: */
397 uint8_t ssbo_to_ibo
[IR3_MAX_SHADER_BUFFERS
];
398 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
400 /* Maps logical Image state to hw state: */
401 uint8_t image_to_ibo
[IR3_MAX_SHADER_IMAGES
];
402 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
404 /* Maps hw state back to logical SSBO or Image state:
406 * note IBO_SSBO ORd into values to indicate that the
407 * hw slot is used for SSBO state vs Image state.
409 #define IBO_SSBO 0x80
410 uint8_t ibo_to_image
[32];
411 uint8_t tex_to_image
[32];
414 uint8_t num_tex
; /* including real textures */
415 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
418 /* Represents half register in regid */
419 #define HALF_REG_ID 0x100
421 struct ir3_shader_variant
{
424 /* variant id (for debug) */
427 struct ir3_shader_key key
;
429 /* vertex shaders can have an extra version for hwbinning pass,
430 * which is pointed to by so->binning:
434 struct ir3_shader_variant
*binning
;
435 struct ir3_shader_variant
*nonbinning
;
438 struct ir3_info info
;
441 /* Levels of nesting of flow control:
443 unsigned branchstack
;
448 /* the instructions length is in units of instruction groups
449 * (4 instructions for a3xx, 16 instructions for a4xx.. each
450 * instruction is 2 dwords):
454 /* the constants length is in units of vec4's, and is the sum of
455 * the uniforms and the built-in compiler constants
460 * + Let the frag shader determine the position/compmask for the
461 * varyings, since it is the place where we know if the varying
462 * is actually used, and if so, which components are used. So
463 * what the hw calls "outloc" is taken from the "inloc" of the
465 * + From the vert shader, we only need the output regid
468 bool frag_coord
, frag_face
, color0_mrt
;
470 /* NOTE: for input/outputs, slot is:
471 * gl_vert_attrib - for VS inputs
472 * gl_varying_slot - for VS output / FS input
473 * gl_frag_result - for FS output
476 /* varyings/outputs: */
477 unsigned outputs_count
;
482 } outputs
[32 + 2]; /* +POSITION +PSIZE */
483 bool writes_pos
, writes_smask
, writes_psize
;
485 /* attributes (VS) / varyings (FS):
486 * Note that sysval's should come *after* normal inputs.
488 unsigned inputs_count
;
493 /* location of input (ie. offset passed to bary.f, etc). This
494 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
495 * have the OUTLOCn value offset by 8, presumably to account
496 * for gl_Position/gl_PointSize)
499 /* vertex shader specific: */
500 bool sysval
: 1; /* slot is a gl_system_value */
501 /* fragment shader specific: */
502 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
503 bool rasterflat
: 1; /* special handling for emit->rasterflat */
504 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
506 enum glsl_interp_mode interpolate
;
507 } inputs
[32 + 2]; /* +POSITION +FACE */
509 /* sum of input components (scalar). For frag shaders, it only counts
510 * the varying inputs:
514 /* For frag shaders, the total number of inputs (not scalar,
515 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
519 /* Remapping table to map Image and SSBO to hw state: */
520 struct ir3_ibo_mapping image_mapping
;
522 /* number of samplers/textures (which are currently 1:1): */
525 /* is there an implicit sampler to read framebuffer (FS only).. if
526 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
527 * the last "real" texture)
531 /* do we have one or more SSBO instructions: */
534 /* do we need derivatives: */
537 /* do we have kill, image write, etc (which prevents early-z): */
542 /* for astc srgb workaround, the number/base of additional
543 * alpha tex states we need, and index of original tex states
546 unsigned base
, count
;
547 unsigned orig_idx
[16];
550 /* shader variants form a linked list: */
551 struct ir3_shader_variant
*next
;
553 /* replicated here to avoid passing extra ptrs everywhere: */
554 gl_shader_stage type
;
555 struct ir3_shader
*shader
;
557 /* texture sampler pre-dispatches */
558 uint32_t num_sampler_prefetch
;
559 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
562 struct ir3_ubo_range
{
563 uint32_t offset
; /* start offset of this block in const register file */
564 uint32_t start
, end
; /* range of block that's actually used */
567 struct ir3_ubo_analysis_state
569 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
571 uint32_t lower_count
;
572 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
577 gl_shader_stage type
;
579 /* shader id (for debug): */
581 uint32_t variant_count
;
583 /* so we know when we can disable TGSI related hacks: */
586 struct ir3_compiler
*compiler
;
588 struct ir3_ubo_analysis_state ubo_state
;
589 struct ir3_const_state const_state
;
591 struct nir_shader
*nir
;
592 struct ir3_stream_output_info stream_output
;
594 struct ir3_shader_variant
*variants
;
597 uint32_t output_size
; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
599 /* Map from driver_location to byte offset in per-primitive storage */
600 unsigned output_loc
[32];
603 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
604 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
605 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
606 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
607 void ir3_shader_destroy(struct ir3_shader
*shader
);
608 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
609 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
612 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
614 static inline const char *
615 ir3_shader_stage(struct ir3_shader
*shader
)
617 switch (shader
->type
) {
618 case MESA_SHADER_VERTEX
: return "VERT";
619 case MESA_SHADER_TESS_CTRL
: return "TCS";
620 case MESA_SHADER_TESS_EVAL
: return "TES";
621 case MESA_SHADER_GEOMETRY
: return "GEOM";
622 case MESA_SHADER_FRAGMENT
: return "FRAG";
623 case MESA_SHADER_COMPUTE
: return "CL";
625 unreachable("invalid type");
635 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
639 for (j
= 0; j
< so
->outputs_count
; j
++)
640 if (so
->outputs
[j
].slot
== slot
)
643 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
644 * in the vertex shader.. but the fragment shader doesn't know this
645 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
646 * at link time if there is no matching OUT.BCOLOR[n], we must map
647 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
648 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
650 if (slot
== VARYING_SLOT_BFC0
) {
651 slot
= VARYING_SLOT_COL0
;
652 } else if (slot
== VARYING_SLOT_BFC1
) {
653 slot
= VARYING_SLOT_COL1
;
654 } else if (slot
== VARYING_SLOT_COL0
) {
655 slot
= VARYING_SLOT_BFC0
;
656 } else if (slot
== VARYING_SLOT_COL1
) {
657 slot
= VARYING_SLOT_BFC1
;
662 for (j
= 0; j
< so
->outputs_count
; j
++)
663 if (so
->outputs
[j
].slot
== slot
)
672 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
674 while (++i
< so
->inputs_count
)
675 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
680 struct ir3_shader_linkage
{
691 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
695 debug_assert(i
< ARRAY_SIZE(l
->var
));
697 l
->var
[i
].regid
= regid
;
698 l
->var
[i
].compmask
= compmask
;
700 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
704 ir3_link_shaders(struct ir3_shader_linkage
*l
,
705 const struct ir3_shader_variant
*vs
,
706 const struct ir3_shader_variant
*fs
)
710 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
711 j
= ir3_next_varying(fs
, j
);
713 if (j
>= fs
->inputs_count
)
716 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
719 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
721 ir3_link_add(l
, vs
->outputs
[k
].regid
,
722 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
726 static inline uint32_t
727 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
730 for (j
= 0; j
< so
->outputs_count
; j
++)
731 if (so
->outputs
[j
].slot
== slot
) {
732 uint32_t regid
= so
->outputs
[j
].regid
;
733 if (so
->outputs
[j
].half
)
734 regid
|= HALF_REG_ID
;
740 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
741 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
744 static inline uint32_t
745 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
748 for (j
= 0; j
< so
->inputs_count
; j
++)
749 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
750 return so
->inputs
[j
].regid
;
754 /* calculate register footprint in terms of half-regs (ie. one full
755 * reg counts as two half-regs).
757 static inline uint32_t
758 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
760 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
763 #endif /* IR3_SHADER_H_ */