2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "compiler/shader_enums.h"
33 #include "compiler/nir/nir.h"
34 #include "util/bitscan.h"
40 /* driver param indices: */
41 enum ir3_driver_param
{
42 /* compute shader driver params: */
43 IR3_DP_NUM_WORK_GROUPS_X
= 0,
44 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
45 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
46 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
47 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
48 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
49 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
50 * glDispatchComputeIndirect() needs to load these from
51 * the info->indirect buffer. Keep that in mind when/if
52 * adding any addition CS driver params.
54 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
56 /* vertex shader driver params: */
57 IR3_DP_VTXID_BASE
= 0,
58 IR3_DP_VTXCNT_MAX
= 1,
59 /* user-clip-plane components, up to 8x vec4's: */
63 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 #define IR3_MAX_SHADER_BUFFERS 32
67 #define IR3_MAX_SHADER_IMAGES 32
68 #define IR3_MAX_SO_BUFFERS 4
69 #define IR3_MAX_SO_OUTPUTS 64
70 #define IR3_MAX_CONSTANT_BUFFERS 32
74 * For consts needed to pass internal values to shader which may or may not
75 * be required, rather than allocating worst-case const space, we scan the
76 * shader and allocate consts as-needed:
78 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
81 * + Image dimensions: needed to calculate pixel offset, but only for
82 * images that have a image_store intrinsic
84 struct ir3_driver_const_layout
{
86 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
87 uint32_t count
; /* number of consts allocated */
88 /* one const allocated per SSBO which has get_buffer_size,
89 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
92 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
96 uint32_t mask
; /* bitmask of images that have image_store */
97 uint32_t count
; /* number of consts allocated */
98 /* three const allocated per image which has image_store:
99 * + cpp (bytes per pixel)
101 * + array_pitch (z pitch)
103 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
108 * A single output for vertex transform feedback.
110 struct ir3_stream_output
{
111 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
112 unsigned start_component
:2; /** 0 to 3 */
113 unsigned num_components
:3; /** 1 to 4 */
114 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
115 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
116 unsigned stream
:2; /**< 0 to 3 */
120 * Stream output for vertex transform feedback.
122 struct ir3_stream_output_info
{
123 unsigned num_outputs
;
124 /** stride for an entire vertex for each buffer in dwords */
125 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
128 * Array of stream outputs, in the order they are to be written in.
129 * Selected components are tightly packed into the output buffer.
131 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
134 /* Configuration key used to identify a shader variant.. different
135 * shader variants can be used to implement features not supported
136 * in hw (two sided color), binning-pass vertex shader, etc.
138 struct ir3_shader_key
{
142 * Combined Vertex/Fragment shader parameters:
144 unsigned ucp_enables
: 8;
146 /* do we need to check {v,f}saturate_{s,t,r}? */
147 unsigned has_per_samp
: 1;
150 * Vertex shader variant parameters:
152 unsigned vclamp_color
: 1;
155 * Fragment shader variant parameters:
157 unsigned color_two_side
: 1;
158 unsigned half_precision
: 1;
159 /* used when shader needs to handle flat varyings (a4xx)
160 * for front/back color inputs to frag shader:
162 unsigned rasterflat
: 1;
163 unsigned fclamp_color
: 1;
168 /* bitmask of sampler which needs coords clamped for vertex
171 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
173 /* bitmask of sampler which needs coords clamped for frag
176 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
178 /* bitmask of ms shifts */
179 uint32_t vsamples
, fsamples
;
181 /* bitmask of samplers which need astc srgb workaround: */
182 uint16_t vastc_srgb
, fastc_srgb
;
186 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
188 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
189 if (a
->has_per_samp
|| b
->has_per_samp
)
190 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
191 return a
->global
== b
->global
;
194 /* will the two keys produce different lowering for a fragment shader? */
196 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
198 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
199 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
200 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
201 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
202 (last_key
->fsamples
!= key
->fsamples
) ||
203 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
207 if (last_key
->fclamp_color
!= key
->fclamp_color
)
210 if (last_key
->color_two_side
!= key
->color_two_side
)
213 if (last_key
->half_precision
!= key
->half_precision
)
216 if (last_key
->rasterflat
!= key
->rasterflat
)
219 if (last_key
->ucp_enables
!= key
->ucp_enables
)
225 /* will the two keys produce different lowering for a vertex shader? */
227 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
229 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
230 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
231 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
232 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
233 (last_key
->vsamples
!= key
->vsamples
) ||
234 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
238 if (last_key
->vclamp_color
!= key
->vclamp_color
)
241 if (last_key
->ucp_enables
!= key
->ucp_enables
)
247 /* clears shader-key flags which don't apply to the given shader
251 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
254 case MESA_SHADER_FRAGMENT
:
255 if (key
->has_per_samp
) {
256 key
->vsaturate_s
= 0;
257 key
->vsaturate_t
= 0;
258 key
->vsaturate_r
= 0;
263 case MESA_SHADER_VERTEX
:
264 key
->color_two_side
= false;
265 key
->half_precision
= false;
266 key
->rasterflat
= false;
267 if (key
->has_per_samp
) {
268 key
->fsaturate_s
= 0;
269 key
->fsaturate_t
= 0;
270 key
->fsaturate_r
= 0;
282 * On a4xx+a5xx, Images share state with textures and SSBOs:
284 * + Uses texture (cat5) state/instruction (isam) to read
285 * + Uses SSBO state and instructions (cat6) to write and for atomics
287 * Starting with a6xx, Images and SSBOs are basically the same thing,
288 * with texture state and isam also used for SSBO reads.
290 * On top of that, gallium makes the SSBO (shader_buffers) state semi
291 * sparse, with the first half of the state space used for atomic
292 * counters lowered to atomic buffers. We could ignore this, but I
293 * don't think we could *really* handle the case of a single shader
294 * that used the max # of textures + images + SSBOs. And once we are
295 * offsetting images by num_ssbos (or visa versa) to map them into
296 * the same hardware state, the hardware state has become coupled to
297 * the shader state, so at this point we might as well just use a
298 * mapping table to remap things from image/SSBO idx to hw idx.
300 * To make things less (more?) confusing, for the hw "SSBO" state
301 * (since it is really both SSBO and Image) I'll use the name "IBO"
303 struct ir3_ibo_mapping
{
304 #define IBO_INVALID 0xff
305 /* Maps logical SSBO state to hw state: */
306 uint8_t ssbo_to_ibo
[IR3_MAX_SHADER_BUFFERS
];
307 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
309 /* Maps logical Image state to hw state: */
310 uint8_t image_to_ibo
[IR3_MAX_SHADER_IMAGES
];
311 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
313 /* Maps hw state back to logical SSBO or Image state:
315 * note IBO_SSBO ORd into values to indicate that the
316 * hw slot is used for SSBO state vs Image state.
318 #define IBO_SSBO 0x80
319 uint8_t ibo_to_image
[32];
320 uint8_t tex_to_image
[32];
323 uint8_t num_tex
; /* including real textures */
324 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
327 struct ir3_shader_variant
{
330 /* variant id (for debug) */
333 struct ir3_shader_key key
;
335 /* vertex shaders can have an extra version for hwbinning pass,
336 * which is pointed to by so->binning:
339 struct ir3_shader_variant
*binning
;
341 struct ir3_driver_const_layout const_layout
;
342 struct ir3_info info
;
345 /* Levels of nesting of flow control:
347 unsigned branchstack
;
351 /* the instructions length is in units of instruction groups
352 * (4 instructions for a3xx, 16 instructions for a4xx.. each
353 * instruction is 2 dwords):
357 /* the constants length is in units of vec4's, and is the sum of
358 * the uniforms and the built-in compiler constants
362 /* number of uniforms (in vec4), not including built-in compiler
365 unsigned num_uniforms
;
370 * + Let the frag shader determine the position/compmask for the
371 * varyings, since it is the place where we know if the varying
372 * is actually used, and if so, which components are used. So
373 * what the hw calls "outloc" is taken from the "inloc" of the
375 * + From the vert shader, we only need the output regid
378 bool frag_coord
, frag_face
, color0_mrt
;
380 /* NOTE: for input/outputs, slot is:
381 * gl_vert_attrib - for VS inputs
382 * gl_varying_slot - for VS output / FS input
383 * gl_frag_result - for FS output
386 /* varyings/outputs: */
387 unsigned outputs_count
;
391 } outputs
[16 + 2]; /* +POSITION +PSIZE */
392 bool writes_pos
, writes_psize
;
394 /* attributes (VS) / varyings (FS):
395 * Note that sysval's should come *after* normal inputs.
397 unsigned inputs_count
;
403 /* location of input (ie. offset passed to bary.f, etc). This
404 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
405 * have the OUTLOCn value offset by 8, presumably to account
406 * for gl_Position/gl_PointSize)
409 /* vertex shader specific: */
410 bool sysval
: 1; /* slot is a gl_system_value */
411 /* fragment shader specific: */
412 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
413 bool rasterflat
: 1; /* special handling for emit->rasterflat */
414 enum glsl_interp_mode interpolate
;
415 } inputs
[16 + 2]; /* +POSITION +FACE */
417 /* sum of input components (scalar). For frag shaders, it only counts
418 * the varying inputs:
422 /* For frag shaders, the total number of inputs (not scalar,
423 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
427 /* Remapping table to map Image and SSBO to hw state: */
428 struct ir3_ibo_mapping image_mapping
;
430 /* number of samplers/textures (which are currently 1:1): */
433 /* do we have one or more SSBO instructions: */
436 /* do we need derivatives: */
439 /* do we have kill, image write, etc (which prevents early-z): */
442 /* Layout of constant registers, each section (in vec4). Pointer size
443 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
444 * UBO and stream-out consts.
447 /* user const start at zero */
449 /* NOTE that a3xx might need a section for SSBO addresses too */
452 unsigned driver_param
;
457 unsigned immediates_count
;
458 unsigned immediates_size
;
463 /* for astc srgb workaround, the number/base of additional
464 * alpha tex states we need, and index of original tex states
467 unsigned base
, count
;
468 unsigned orig_idx
[16];
471 /* shader variants form a linked list: */
472 struct ir3_shader_variant
*next
;
474 /* replicated here to avoid passing extra ptrs everywhere: */
475 gl_shader_stage type
;
476 struct ir3_shader
*shader
;
479 struct ir3_ubo_range
{
480 uint32_t offset
; /* start offset of this block in const register file */
481 uint32_t start
, end
; /* range of block that's actually used */
484 struct ir3_ubo_analysis_state
486 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
488 uint32_t lower_count
;
493 gl_shader_stage type
;
495 /* shader id (for debug): */
497 uint32_t variant_count
;
499 /* so we know when we can disable TGSI related hacks: */
502 struct ir3_compiler
*compiler
;
504 struct ir3_ubo_analysis_state ubo_state
;
506 struct nir_shader
*nir
;
507 struct ir3_stream_output_info stream_output
;
509 struct ir3_shader_variant
*variants
;
512 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
513 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
514 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
515 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
516 void ir3_shader_destroy(struct ir3_shader
*shader
);
517 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
518 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
521 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
523 static inline const char *
524 ir3_shader_stage(struct ir3_shader
*shader
)
526 switch (shader
->type
) {
527 case MESA_SHADER_VERTEX
: return "VERT";
528 case MESA_SHADER_FRAGMENT
: return "FRAG";
529 case MESA_SHADER_COMPUTE
: return "CL";
531 unreachable("invalid type");
541 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
545 for (j
= 0; j
< so
->outputs_count
; j
++)
546 if (so
->outputs
[j
].slot
== slot
)
549 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
550 * in the vertex shader.. but the fragment shader doesn't know this
551 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
552 * at link time if there is no matching OUT.BCOLOR[n], we must map
553 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
554 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
556 if (slot
== VARYING_SLOT_BFC0
) {
557 slot
= VARYING_SLOT_COL0
;
558 } else if (slot
== VARYING_SLOT_BFC1
) {
559 slot
= VARYING_SLOT_COL1
;
560 } else if (slot
== VARYING_SLOT_COL0
) {
561 slot
= VARYING_SLOT_BFC0
;
562 } else if (slot
== VARYING_SLOT_COL1
) {
563 slot
= VARYING_SLOT_BFC1
;
568 for (j
= 0; j
< so
->outputs_count
; j
++)
569 if (so
->outputs
[j
].slot
== slot
)
578 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
580 while (++i
< so
->inputs_count
)
581 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
586 struct ir3_shader_linkage
{
597 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
601 debug_assert(i
< ARRAY_SIZE(l
->var
));
603 l
->var
[i
].regid
= regid
;
604 l
->var
[i
].compmask
= compmask
;
606 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
610 ir3_link_shaders(struct ir3_shader_linkage
*l
,
611 const struct ir3_shader_variant
*vs
,
612 const struct ir3_shader_variant
*fs
)
616 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
617 j
= ir3_next_varying(fs
, j
);
619 if (j
>= fs
->inputs_count
)
622 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
625 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
627 ir3_link_add(l
, vs
->outputs
[k
].regid
,
628 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
632 static inline uint32_t
633 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
636 for (j
= 0; j
< so
->outputs_count
; j
++)
637 if (so
->outputs
[j
].slot
== slot
)
638 return so
->outputs
[j
].regid
;
642 static inline uint32_t
643 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
646 for (j
= 0; j
< so
->inputs_count
; j
++)
647 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
648 return so
->inputs
[j
].regid
;
652 /* calculate register footprint in terms of half-regs (ie. one full
653 * reg counts as two half-regs).
655 static inline uint32_t
656 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
658 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
661 #endif /* IR3_SHADER_H_ */