2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 IR3_DP_INSTID_BASE
= 2,
61 /* user-clip-plane components, up to 8x vec4's: */
65 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
68 #define IR3_MAX_SHADER_BUFFERS 32
69 #define IR3_MAX_SHADER_IMAGES 32
70 #define IR3_MAX_SO_BUFFERS 4
71 #define IR3_MAX_SO_STREAMS 4
72 #define IR3_MAX_SO_OUTPUTS 64
73 #define IR3_MAX_UBO_PUSH_RANGES 32
77 * Describes the layout of shader consts. This includes:
78 * + User consts + driver lowered UBO ranges
80 * + Image sizes/dimensions
81 * + Driver params (ie. IR3_DP_*)
82 * + TFBO addresses (for generations that do not have hardware streamout)
83 * + Lowered immediates
85 * For consts needed to pass internal values to shader which may or may not
86 * be required, rather than allocating worst-case const space, we scan the
87 * shader and allocate consts as-needed:
89 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
92 * + Image dimensions: needed to calculate pixel offset, but only for
93 * images that have a image_store intrinsic
95 * Layout of constant registers, each section aligned to vec4. Note
96 * that pointer size (ubo, etc) changes depending on generation.
101 * if (vertex shader) {
102 * driver params (IR3_DP_*)
103 * if (stream_output.num_outputs > 0)
104 * stream-out addresses
105 * } else if (compute_shader) {
106 * driver params (IR3_DP_*)
110 * Immediates go last mostly because they are inserted in the CP pass
111 * after the nir -> ir3 frontend.
113 * Note UBO size in bytes should be aligned to vec4
115 struct ir3_const_state
{
117 unsigned num_reserved_user_consts
;
118 unsigned num_driver_params
; /* scalar */
121 /* user const start at zero */
123 /* NOTE that a3xx might need a section for SSBO addresses too */
126 unsigned driver_param
;
128 unsigned primitive_param
;
129 unsigned primitive_map
;
134 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
135 uint32_t count
; /* number of consts allocated */
136 /* one const allocated per SSBO which has get_buffer_size,
137 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
140 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
144 uint32_t mask
; /* bitmask of images that have image_store */
145 uint32_t count
; /* number of consts allocated */
146 /* three const allocated per image which has image_store:
147 * + cpp (bytes per pixel)
149 * + array_pitch (z pitch)
151 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
154 unsigned immediate_idx
;
155 unsigned immediates_count
;
156 unsigned immediates_size
;
163 * A single output for vertex transform feedback.
165 struct ir3_stream_output
{
166 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
167 unsigned start_component
:2; /** 0 to 3 */
168 unsigned num_components
:3; /** 1 to 4 */
169 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
170 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
171 unsigned stream
:2; /**< 0 to 3 */
175 * Stream output for vertex transform feedback.
177 struct ir3_stream_output_info
{
178 unsigned num_outputs
;
179 /** stride for an entire vertex for each buffer in dwords */
180 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
183 * Array of stream outputs, in the order they are to be written in.
184 * Selected components are tightly packed into the output buffer.
186 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
191 * Starting from a4xx, HW supports pre-dispatching texture sampling
192 * instructions prior to scheduling a shader stage, when the
193 * coordinate maps exactly to an output of the previous stage.
197 * There is a limit in the number of pre-dispatches allowed for any
200 #define IR3_MAX_SAMPLER_PREFETCH 4
203 * This is the output stream value for 'cmd', as used by blob. It may
204 * encode the return type (in 3 bits) but it hasn't been verified yet.
206 #define IR3_SAMPLER_PREFETCH_CMD 0x4
207 #define IR3_SAMPLER_BINDLESS_PREFETCH_CMD 0x6
210 * Stream output for texture sampling pre-dispatches.
212 struct ir3_sampler_prefetch
{
216 uint16_t samp_bindless_id
;
217 uint16_t tex_bindless_id
;
220 uint8_t half_precision
;
225 /* Configuration key used to identify a shader variant.. different
226 * shader variants can be used to implement features not supported
227 * in hw (two sided color), binning-pass vertex shader, etc.
229 struct ir3_shader_key
{
233 * Combined Vertex/Fragment shader parameters:
235 unsigned ucp_enables
: 8;
237 /* do we need to check {v,f}saturate_{s,t,r}? */
238 unsigned has_per_samp
: 1;
241 * Vertex shader variant parameters:
243 unsigned vclamp_color
: 1;
246 * Fragment shader variant parameters:
248 unsigned sample_shading
: 1;
250 unsigned color_two_side
: 1;
251 unsigned half_precision
: 1;
252 /* used when shader needs to handle flat varyings (a4xx)
253 * for front/back color inputs to frag shader:
255 unsigned rasterflat
: 1;
256 unsigned fclamp_color
: 1;
258 /* Indicates that this is a tessellation pipeline which requires a
259 * whole different kind of vertex shader. In case of
260 * tessellation, this field also tells us which kind of output
261 * topology the TES uses, which the TCS needs to know.
263 #define IR3_TESS_NONE 0
264 #define IR3_TESS_TRIANGLES 1
265 #define IR3_TESS_QUADS 2
266 #define IR3_TESS_ISOLINES 3
267 unsigned tessellation
: 2;
274 /* bitmask of sampler which needs coords clamped for vertex
277 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
279 /* bitmask of sampler which needs coords clamped for frag
282 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
284 /* bitmask of ms shifts */
285 uint32_t vsamples
, fsamples
;
287 /* bitmask of samplers which need astc srgb workaround: */
288 uint16_t vastc_srgb
, fastc_srgb
;
292 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
294 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
295 if (a
->has_per_samp
|| b
->has_per_samp
)
296 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
297 return a
->global
== b
->global
;
300 /* will the two keys produce different lowering for a fragment shader? */
302 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
304 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
305 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
306 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
307 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
308 (last_key
->fsamples
!= key
->fsamples
) ||
309 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
313 if (last_key
->fclamp_color
!= key
->fclamp_color
)
316 if (last_key
->color_two_side
!= key
->color_two_side
)
319 if (last_key
->half_precision
!= key
->half_precision
)
322 if (last_key
->rasterflat
!= key
->rasterflat
)
325 if (last_key
->ucp_enables
!= key
->ucp_enables
)
331 /* will the two keys produce different lowering for a vertex shader? */
333 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
335 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
336 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
337 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
338 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
339 (last_key
->vsamples
!= key
->vsamples
) ||
340 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
344 if (last_key
->vclamp_color
!= key
->vclamp_color
)
347 if (last_key
->ucp_enables
!= key
->ucp_enables
)
353 /* clears shader-key flags which don't apply to the given shader
357 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
360 case MESA_SHADER_FRAGMENT
:
361 if (key
->has_per_samp
) {
362 key
->vsaturate_s
= 0;
363 key
->vsaturate_t
= 0;
364 key
->vsaturate_r
= 0;
367 key
->has_gs
= false; /* FS doesn't care */
368 key
->tessellation
= IR3_TESS_NONE
;
371 case MESA_SHADER_VERTEX
:
372 case MESA_SHADER_GEOMETRY
:
373 key
->color_two_side
= false;
374 key
->half_precision
= false;
375 key
->rasterflat
= false;
376 if (key
->has_per_samp
) {
377 key
->fsaturate_s
= 0;
378 key
->fsaturate_t
= 0;
379 key
->fsaturate_r
= 0;
384 /* VS and GS only care about whether or not we're tessellating. */
385 key
->tessellation
= !!key
->tessellation
;
387 case MESA_SHADER_TESS_CTRL
:
388 case MESA_SHADER_TESS_EVAL
:
389 key
->color_two_side
= false;
390 key
->half_precision
= false;
391 key
->rasterflat
= false;
392 if (key
->has_per_samp
) {
393 key
->fsaturate_s
= 0;
394 key
->fsaturate_t
= 0;
395 key
->fsaturate_r
= 0;
398 key
->vsaturate_s
= 0;
399 key
->vsaturate_t
= 0;
400 key
->vsaturate_r
= 0;
412 * On a4xx+a5xx, Images share state with textures and SSBOs:
414 * + Uses texture (cat5) state/instruction (isam) to read
415 * + Uses SSBO state and instructions (cat6) to write and for atomics
417 * Starting with a6xx, Images and SSBOs are basically the same thing,
418 * with texture state and isam also used for SSBO reads.
420 * On top of that, gallium makes the SSBO (shader_buffers) state semi
421 * sparse, with the first half of the state space used for atomic
422 * counters lowered to atomic buffers. We could ignore this, but I
423 * don't think we could *really* handle the case of a single shader
424 * that used the max # of textures + images + SSBOs. And once we are
425 * offsetting images by num_ssbos (or visa versa) to map them into
426 * the same hardware state, the hardware state has become coupled to
427 * the shader state, so at this point we might as well just use a
428 * mapping table to remap things from image/SSBO idx to hw idx.
430 * To make things less (more?) confusing, for the hw "SSBO" state
431 * (since it is really both SSBO and Image) I'll use the name "IBO"
433 struct ir3_ibo_mapping
{
434 #define IBO_INVALID 0xff
435 /* Maps logical SSBO state to hw tex state: */
436 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
438 /* Maps logical Image state to hw tex state: */
439 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
441 /* Maps hw state back to logical SSBO or Image state:
443 * note IBO_SSBO ORd into values to indicate that the
444 * hw slot is used for SSBO state vs Image state.
446 #define IBO_SSBO 0x80
447 uint8_t tex_to_image
[32];
449 uint8_t num_tex
; /* including real textures */
450 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
453 /* Represents half register in regid */
454 #define HALF_REG_ID 0x100
456 struct ir3_shader_variant
{
459 /* variant id (for debug) */
462 struct ir3_shader_key key
;
464 /* vertex shaders can have an extra version for hwbinning pass,
465 * which is pointed to by so->binning:
469 struct ir3_shader_variant
*binning
;
470 struct ir3_shader_variant
*nonbinning
;
473 struct ir3_info info
;
476 /* Levels of nesting of flow control:
478 unsigned branchstack
;
483 /* the instructions length is in units of instruction groups
484 * (4 instructions for a3xx, 16 instructions for a4xx.. each
485 * instruction is 2 dwords):
489 /* the constants length is in units of vec4's, and is the sum of
490 * the uniforms and the built-in compiler constants
495 * + Let the frag shader determine the position/compmask for the
496 * varyings, since it is the place where we know if the varying
497 * is actually used, and if so, which components are used. So
498 * what the hw calls "outloc" is taken from the "inloc" of the
500 * + From the vert shader, we only need the output regid
503 bool frag_coord
, frag_face
, color0_mrt
;
505 /* NOTE: for input/outputs, slot is:
506 * gl_vert_attrib - for VS inputs
507 * gl_varying_slot - for VS output / FS input
508 * gl_frag_result - for FS output
511 /* varyings/outputs: */
512 unsigned outputs_count
;
517 } outputs
[32 + 2]; /* +POSITION +PSIZE */
518 bool writes_pos
, writes_smask
, writes_psize
;
520 /* attributes (VS) / varyings (FS):
521 * Note that sysval's should come *after* normal inputs.
523 unsigned inputs_count
;
528 /* location of input (ie. offset passed to bary.f, etc). This
529 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
530 * have the OUTLOCn value offset by 8, presumably to account
531 * for gl_Position/gl_PointSize)
534 /* vertex shader specific: */
535 bool sysval
: 1; /* slot is a gl_system_value */
536 /* fragment shader specific: */
537 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
538 bool rasterflat
: 1; /* special handling for emit->rasterflat */
539 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
541 enum glsl_interp_mode interpolate
;
542 } inputs
[32 + 2]; /* +POSITION +FACE */
544 /* sum of input components (scalar). For frag shaders, it only counts
545 * the varying inputs:
549 /* For frag shaders, the total number of inputs (not scalar,
550 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
554 /* Remapping table to map Image and SSBO to hw state: */
555 struct ir3_ibo_mapping image_mapping
;
557 /* number of samplers/textures (which are currently 1:1): */
560 /* is there an implicit sampler to read framebuffer (FS only).. if
561 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
562 * the last "real" texture)
566 /* do we have one or more SSBO instructions: */
569 /* Which bindless resources are used, for filling out sp_xs_config */
575 /* do we need derivatives: */
578 bool need_fine_derivatives
;
580 /* do we have kill, image write, etc (which prevents early-z): */
585 /* for astc srgb workaround, the number/base of additional
586 * alpha tex states we need, and index of original tex states
589 unsigned base
, count
;
590 unsigned orig_idx
[16];
593 /* shader variants form a linked list: */
594 struct ir3_shader_variant
*next
;
596 /* replicated here to avoid passing extra ptrs everywhere: */
597 gl_shader_stage type
;
598 struct ir3_shader
*shader
;
600 /* texture sampler pre-dispatches */
601 uint32_t num_sampler_prefetch
;
602 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
605 static inline const char *
606 ir3_shader_stage(struct ir3_shader_variant
*v
)
609 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
610 case MESA_SHADER_TESS_CTRL
: return "TCS";
611 case MESA_SHADER_TESS_EVAL
: return "TES";
612 case MESA_SHADER_GEOMETRY
: return "GEOM";
613 case MESA_SHADER_FRAGMENT
: return "FRAG";
614 case MESA_SHADER_COMPUTE
: return "CL";
616 unreachable("invalid type");
621 struct ir3_ubo_range
{
622 uint32_t offset
; /* start offset to push in the const register file */
623 uint32_t block
; /* Which constant block */
624 uint32_t start
, end
; /* range of block that's actually used */
625 uint16_t bindless_base
; /* For bindless, which base register is used */
629 struct ir3_ubo_analysis_state
{
630 struct ir3_ubo_range range
[IR3_MAX_UBO_PUSH_RANGES
];
631 uint32_t num_enabled
;
633 uint32_t lower_count
;
634 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
639 gl_shader_stage type
;
641 /* shader id (for debug): */
643 uint32_t variant_count
;
645 struct ir3_compiler
*compiler
;
647 struct ir3_ubo_analysis_state ubo_state
;
648 struct ir3_const_state const_state
;
650 struct nir_shader
*nir
;
651 struct ir3_stream_output_info stream_output
;
653 struct ir3_shader_variant
*variants
;
656 uint32_t output_size
; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
658 /* Map from driver_location to byte offset in per-primitive storage */
659 unsigned output_loc
[32];
662 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
663 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
664 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
665 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
666 void ir3_shader_destroy(struct ir3_shader
*shader
);
667 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
668 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
671 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
678 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
682 for (j
= 0; j
< so
->outputs_count
; j
++)
683 if (so
->outputs
[j
].slot
== slot
)
686 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
687 * in the vertex shader.. but the fragment shader doesn't know this
688 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
689 * at link time if there is no matching OUT.BCOLOR[n], we must map
690 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
691 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
693 if (slot
== VARYING_SLOT_BFC0
) {
694 slot
= VARYING_SLOT_COL0
;
695 } else if (slot
== VARYING_SLOT_BFC1
) {
696 slot
= VARYING_SLOT_COL1
;
697 } else if (slot
== VARYING_SLOT_COL0
) {
698 slot
= VARYING_SLOT_BFC0
;
699 } else if (slot
== VARYING_SLOT_COL1
) {
700 slot
= VARYING_SLOT_BFC1
;
705 for (j
= 0; j
< so
->outputs_count
; j
++)
706 if (so
->outputs
[j
].slot
== slot
)
715 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
717 while (++i
< so
->inputs_count
)
718 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
723 struct ir3_shader_linkage
{
724 /* Maximum location either consumed by the fragment shader or produced by
725 * the last geometry stage, i.e. the size required for each vertex in the
730 /* Number of entries in var. */
733 /* Bitset of locations used, including ones which are only used by the FS.
737 /* Map from VS output to location. */
744 /* location for fixed-function gl_PrimitiveID passthrough */
749 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid_
, uint8_t compmask
, uint8_t loc
)
753 for (int j
= 0; j
< util_last_bit(compmask
); j
++) {
754 uint8_t comploc
= loc
+ j
;
755 l
->varmask
[comploc
/ 32] |= 1 << (comploc
% 32);
758 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
760 if (regid_
!= regid(63, 0)) {
762 debug_assert(i
< ARRAY_SIZE(l
->var
));
764 l
->var
[i
].regid
= regid_
;
765 l
->var
[i
].compmask
= compmask
;
771 ir3_link_shaders(struct ir3_shader_linkage
*l
,
772 const struct ir3_shader_variant
*vs
,
773 const struct ir3_shader_variant
*fs
,
776 /* On older platforms, varmask isn't programmed at all, and it appears
777 * that the hardware generates a mask of used VPC locations using the VS
778 * output map, and hangs if a FS bary instruction references a location
779 * not in the list. This means that we need to have a dummy entry in the
780 * VS out map for things like gl_PointCoord which aren't written by the
781 * VS. Furthermore we can't use r63.x, so just pick a random register to
782 * use if there is no VS output.
784 const unsigned default_regid
= pack_vs_out
? regid(63, 0) : regid(0, 0);
787 l
->primid_loc
= 0xff;
789 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
790 j
= ir3_next_varying(fs
, j
);
792 if (j
>= fs
->inputs_count
)
795 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
798 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
800 if (k
< 0 && fs
->inputs
[j
].slot
== VARYING_SLOT_PRIMITIVE_ID
) {
801 l
->primid_loc
= fs
->inputs
[j
].inloc
;
804 ir3_link_add(l
, k
>= 0 ? vs
->outputs
[k
].regid
: default_regid
,
805 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
809 static inline uint32_t
810 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
813 for (j
= 0; j
< so
->outputs_count
; j
++)
814 if (so
->outputs
[j
].slot
== slot
) {
815 uint32_t regid
= so
->outputs
[j
].regid
;
816 if (so
->outputs
[j
].half
)
817 regid
|= HALF_REG_ID
;
823 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
824 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
825 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
828 static inline uint32_t
829 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
832 for (j
= 0; j
< so
->inputs_count
; j
++)
833 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
834 return so
->inputs
[j
].regid
;
838 /* calculate register footprint in terms of half-regs (ie. one full
839 * reg counts as two half-regs).
841 static inline uint32_t
842 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
844 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
847 static inline uint32_t
848 ir3_shader_nibo(const struct ir3_shader_variant
*v
)
850 /* The dummy variant used in binning mode won't have an actual shader. */
854 return v
->shader
->nir
->info
.num_ssbos
+ v
->shader
->nir
->info
.num_images
;
857 #endif /* IR3_SHADER_H_ */