2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
37 #include "ir3_compiler.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
59 IR3_DP_VTXID_BASE
= 1,
60 IR3_DP_INSTID_BASE
= 2,
61 IR3_DP_VTXCNT_MAX
= 3,
62 /* user-clip-plane components, up to 8x vec4's: */
66 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
69 #define IR3_MAX_SHADER_BUFFERS 32
70 #define IR3_MAX_SHADER_IMAGES 32
71 #define IR3_MAX_SO_BUFFERS 4
72 #define IR3_MAX_SO_STREAMS 4
73 #define IR3_MAX_SO_OUTPUTS 64
74 #define IR3_MAX_UBO_PUSH_RANGES 32
77 * Description of a lowered UBO.
80 uint32_t block
; /* Which constant block */
81 uint16_t bindless_base
; /* For bindless, which base register is used */
86 * Description of a range of a lowered UBO access.
88 * Drivers should not assume that there are not multiple disjoint
89 * lowered ranges of a single UBO.
91 struct ir3_ubo_range
{
92 struct ir3_ubo_info ubo
;
93 uint32_t offset
; /* start offset to push in the const register file */
94 uint32_t start
, end
; /* range of block that's actually used */
97 struct ir3_ubo_analysis_state
{
98 struct ir3_ubo_range range
[IR3_MAX_UBO_PUSH_RANGES
];
101 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
105 * Describes the layout of shader consts. This includes:
106 * + User consts + driver lowered UBO ranges
108 * + Image sizes/dimensions
109 * + Driver params (ie. IR3_DP_*)
110 * + TFBO addresses (for generations that do not have hardware streamout)
111 * + Lowered immediates
113 * For consts needed to pass internal values to shader which may or may not
114 * be required, rather than allocating worst-case const space, we scan the
115 * shader and allocate consts as-needed:
117 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
120 * + Image dimensions: needed to calculate pixel offset, but only for
121 * images that have a image_store intrinsic
123 * Layout of constant registers, each section aligned to vec4. Note
124 * that pointer size (ubo, etc) changes depending on generation.
129 * if (vertex shader) {
130 * driver params (IR3_DP_*)
131 * if (stream_output.num_outputs > 0)
132 * stream-out addresses
133 * } else if (compute_shader) {
134 * driver params (IR3_DP_*)
138 * Immediates go last mostly because they are inserted in the CP pass
139 * after the nir -> ir3 frontend.
141 * Note UBO size in bytes should be aligned to vec4
143 struct ir3_const_state
{
145 unsigned num_driver_params
; /* scalar */
148 /* user const start at zero */
150 /* NOTE that a3xx might need a section for SSBO addresses too */
153 unsigned driver_param
;
155 unsigned primitive_param
;
156 unsigned primitive_map
;
161 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
162 uint32_t count
; /* number of consts allocated */
163 /* one const allocated per SSBO which has get_buffer_size,
164 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
167 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
171 uint32_t mask
; /* bitmask of images that have image_store */
172 uint32_t count
; /* number of consts allocated */
173 /* three const allocated per image which has image_store:
174 * + cpp (bytes per pixel)
176 * + array_pitch (z pitch)
178 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
181 unsigned immediate_idx
;
182 unsigned immediates_count
;
183 unsigned immediates_size
;
188 /* State of ubo access lowered to push consts: */
189 struct ir3_ubo_analysis_state ubo_state
;
193 * A single output for vertex transform feedback.
195 struct ir3_stream_output
{
196 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
197 unsigned start_component
:2; /** 0 to 3 */
198 unsigned num_components
:3; /** 1 to 4 */
199 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
200 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
201 unsigned stream
:2; /**< 0 to 3 */
205 * Stream output for vertex transform feedback.
207 struct ir3_stream_output_info
{
208 unsigned num_outputs
;
209 /** stride for an entire vertex for each buffer in dwords */
210 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
213 * Array of stream outputs, in the order they are to be written in.
214 * Selected components are tightly packed into the output buffer.
216 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
221 * Starting from a4xx, HW supports pre-dispatching texture sampling
222 * instructions prior to scheduling a shader stage, when the
223 * coordinate maps exactly to an output of the previous stage.
227 * There is a limit in the number of pre-dispatches allowed for any
230 #define IR3_MAX_SAMPLER_PREFETCH 4
233 * This is the output stream value for 'cmd', as used by blob. It may
234 * encode the return type (in 3 bits) but it hasn't been verified yet.
236 #define IR3_SAMPLER_PREFETCH_CMD 0x4
237 #define IR3_SAMPLER_BINDLESS_PREFETCH_CMD 0x6
240 * Stream output for texture sampling pre-dispatches.
242 struct ir3_sampler_prefetch
{
246 uint16_t samp_bindless_id
;
247 uint16_t tex_bindless_id
;
250 uint8_t half_precision
;
255 /* Configuration key used to identify a shader variant.. different
256 * shader variants can be used to implement features not supported
257 * in hw (two sided color), binning-pass vertex shader, etc.
259 * When adding to this struct, please update ir3_shader_variant()'s debug
262 struct ir3_shader_key
{
266 * Combined Vertex/Fragment shader parameters:
268 unsigned ucp_enables
: 8;
270 /* do we need to check {v,f}saturate_{s,t,r}? */
271 unsigned has_per_samp
: 1;
274 * Vertex shader variant parameters:
276 unsigned vclamp_color
: 1;
279 * Fragment shader variant parameters:
281 unsigned sample_shading
: 1;
283 unsigned color_two_side
: 1;
284 /* used when shader needs to handle flat varyings (a4xx)
285 * for front/back color inputs to frag shader:
287 unsigned rasterflat
: 1;
288 unsigned fclamp_color
: 1;
290 /* Indicates that this is a tessellation pipeline which requires a
291 * whole different kind of vertex shader. In case of
292 * tessellation, this field also tells us which kind of output
293 * topology the TES uses, which the TCS needs to know.
295 #define IR3_TESS_NONE 0
296 #define IR3_TESS_TRIANGLES 1
297 #define IR3_TESS_QUADS 2
298 #define IR3_TESS_ISOLINES 3
299 unsigned tessellation
: 2;
306 /* bitmask of sampler which needs coords clamped for vertex
309 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
311 /* bitmask of sampler which needs coords clamped for frag
314 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
316 /* bitmask of ms shifts */
317 uint32_t vsamples
, fsamples
;
319 /* bitmask of samplers which need astc srgb workaround: */
320 uint16_t vastc_srgb
, fastc_srgb
;
323 static inline unsigned
324 ir3_tess_mode(unsigned gl_tess_mode
)
326 switch (gl_tess_mode
) {
328 return IR3_TESS_ISOLINES
;
330 return IR3_TESS_TRIANGLES
;
332 return IR3_TESS_QUADS
;
334 unreachable("bad tessmode");
339 ir3_shader_key_equal(const struct ir3_shader_key
*a
, const struct ir3_shader_key
*b
)
341 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
342 if (a
->has_per_samp
|| b
->has_per_samp
)
343 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
344 return a
->global
== b
->global
;
347 /* will the two keys produce different lowering for a fragment shader? */
349 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
351 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
352 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
353 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
354 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
355 (last_key
->fsamples
!= key
->fsamples
) ||
356 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
360 if (last_key
->fclamp_color
!= key
->fclamp_color
)
363 if (last_key
->color_two_side
!= key
->color_two_side
)
366 if (last_key
->rasterflat
!= key
->rasterflat
)
369 if (last_key
->ucp_enables
!= key
->ucp_enables
)
375 /* will the two keys produce different lowering for a vertex shader? */
377 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
379 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
380 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
381 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
382 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
383 (last_key
->vsamples
!= key
->vsamples
) ||
384 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
388 if (last_key
->vclamp_color
!= key
->vclamp_color
)
391 if (last_key
->ucp_enables
!= key
->ucp_enables
)
398 * On a4xx+a5xx, Images share state with textures and SSBOs:
400 * + Uses texture (cat5) state/instruction (isam) to read
401 * + Uses SSBO state and instructions (cat6) to write and for atomics
403 * Starting with a6xx, Images and SSBOs are basically the same thing,
404 * with texture state and isam also used for SSBO reads.
406 * On top of that, gallium makes the SSBO (shader_buffers) state semi
407 * sparse, with the first half of the state space used for atomic
408 * counters lowered to atomic buffers. We could ignore this, but I
409 * don't think we could *really* handle the case of a single shader
410 * that used the max # of textures + images + SSBOs. And once we are
411 * offsetting images by num_ssbos (or visa versa) to map them into
412 * the same hardware state, the hardware state has become coupled to
413 * the shader state, so at this point we might as well just use a
414 * mapping table to remap things from image/SSBO idx to hw idx.
416 * To make things less (more?) confusing, for the hw "SSBO" state
417 * (since it is really both SSBO and Image) I'll use the name "IBO"
419 struct ir3_ibo_mapping
{
420 #define IBO_INVALID 0xff
421 /* Maps logical SSBO state to hw tex state: */
422 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
424 /* Maps logical Image state to hw tex state: */
425 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
427 /* Maps hw state back to logical SSBO or Image state:
429 * note IBO_SSBO ORd into values to indicate that the
430 * hw slot is used for SSBO state vs Image state.
432 #define IBO_SSBO 0x80
433 uint8_t tex_to_image
[32];
435 uint8_t num_tex
; /* including real textures */
436 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
439 /* Represents half register in regid */
440 #define HALF_REG_ID 0x100
442 struct ir3_shader_variant
{
445 /* variant id (for debug) */
448 struct ir3_shader_key key
;
450 /* vertex shaders can have an extra version for hwbinning pass,
451 * which is pointed to by so->binning:
455 struct ir3_shader_variant
*binning
;
456 struct ir3_shader_variant
*nonbinning
;
459 struct ir3_info info
;
462 /* The actual binary shader instructions, size given by info.sizedwords: */
465 /* Levels of nesting of flow control:
467 unsigned branchstack
;
472 /* the instructions length is in units of instruction groups
473 * (4 instructions for a3xx, 16 instructions for a4xx.. each
474 * instruction is 2 dwords):
478 /* the constants length is in units of vec4's, and is the sum of
479 * the uniforms and the built-in compiler constants
483 struct ir3_const_state
*const_state
;
486 * + Let the frag shader determine the position/compmask for the
487 * varyings, since it is the place where we know if the varying
488 * is actually used, and if so, which components are used. So
489 * what the hw calls "outloc" is taken from the "inloc" of the
491 * + From the vert shader, we only need the output regid
494 bool frag_face
, color0_mrt
;
495 uint8_t fragcoord_compmask
;
497 /* NOTE: for input/outputs, slot is:
498 * gl_vert_attrib - for VS inputs
499 * gl_varying_slot - for VS output / FS input
500 * gl_frag_result - for FS output
503 /* varyings/outputs: */
504 unsigned outputs_count
;
509 } outputs
[32 + 2]; /* +POSITION +PSIZE */
510 bool writes_pos
, writes_smask
, writes_psize
;
512 /* Size in dwords of all outputs for VS, size of entire patch for HS. */
513 uint32_t output_size
;
515 /* Map from driver_location to byte offset in per-primitive storage */
516 unsigned output_loc
[32];
518 /* attributes (VS) / varyings (FS):
519 * Note that sysval's should come *after* normal inputs.
521 unsigned inputs_count
;
526 /* location of input (ie. offset passed to bary.f, etc). This
527 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
528 * have the OUTLOCn value offset by 8, presumably to account
529 * for gl_Position/gl_PointSize)
532 /* vertex shader specific: */
533 bool sysval
: 1; /* slot is a gl_system_value */
534 /* fragment shader specific: */
535 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
536 bool rasterflat
: 1; /* special handling for emit->rasterflat */
537 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
539 enum glsl_interp_mode interpolate
;
540 } inputs
[32 + 2]; /* +POSITION +FACE */
542 /* sum of input components (scalar). For frag shaders, it only counts
543 * the varying inputs:
547 /* For frag shaders, the total number of inputs (not scalar,
548 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
552 /* Remapping table to map Image and SSBO to hw state: */
553 struct ir3_ibo_mapping image_mapping
;
555 /* number of samplers/textures (which are currently 1:1): */
558 /* is there an implicit sampler to read framebuffer (FS only).. if
559 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
560 * the last "real" texture)
564 /* do we have one or more SSBO instructions: */
567 /* Which bindless resources are used, for filling out sp_xs_config */
573 /* do we need derivatives: */
576 bool need_fine_derivatives
;
578 /* do we have image write, etc (which prevents early-z): */
581 /* do we have kill, which also prevents early-z, but not necessarily
582 * early-lrz (as long as lrz-write is disabled, which must be handled
583 * outside of ir3. Unlike other no_earlyz cases, kill doesn't have
584 * side effects that prevent early-lrz discard.
590 /* Are we using split or merged register file? */
593 /* for astc srgb workaround, the number/base of additional
594 * alpha tex states we need, and index of original tex states
597 unsigned base
, count
;
598 unsigned orig_idx
[16];
601 /* shader variants form a linked list: */
602 struct ir3_shader_variant
*next
;
604 /* replicated here to avoid passing extra ptrs everywhere: */
605 gl_shader_stage type
;
606 struct ir3_shader
*shader
;
608 /* texture sampler pre-dispatches */
609 uint32_t num_sampler_prefetch
;
610 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
613 static inline const char *
614 ir3_shader_stage(struct ir3_shader_variant
*v
)
617 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
618 case MESA_SHADER_TESS_CTRL
: return "TCS";
619 case MESA_SHADER_TESS_EVAL
: return "TES";
620 case MESA_SHADER_GEOMETRY
: return "GEOM";
621 case MESA_SHADER_FRAGMENT
: return "FRAG";
622 case MESA_SHADER_COMPUTE
: return "CL";
624 unreachable("invalid type");
631 gl_shader_stage type
;
633 /* shader id (for debug): */
635 uint32_t variant_count
;
637 /* Set by freedreno after shader_state_create, so we can emit debug info
638 * when recompiling a shader at draw time.
640 bool initial_variants_done
;
642 struct ir3_compiler
*compiler
;
644 unsigned num_reserved_user_consts
;
646 struct nir_shader
*nir
;
647 struct ir3_stream_output_info stream_output
;
649 struct ir3_shader_variant
*variants
;
652 /* Bitmask of bits of the shader key used by this shader. Used to avoid
653 * recompiles for GL NOS that doesn't actually apply to the shader.
655 struct ir3_shader_key key_mask
;
659 * In order to use the same cmdstream, in particular constlen setup and const
660 * emit, for both binning and draw pass (a6xx+), the binning pass re-uses it's
661 * corresponding draw pass shaders const_state.
663 static inline struct ir3_const_state
*
664 ir3_const_state(const struct ir3_shader_variant
*v
)
667 return v
->nonbinning
->const_state
;
668 return v
->const_state
;
671 void * ir3_shader_assemble(struct ir3_shader_variant
*v
);
672 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
673 const struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
674 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
675 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
);
676 void ir3_shader_destroy(struct ir3_shader
*shader
);
677 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
678 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
681 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
687 /* clears shader-key flags which don't apply to the given shader.
690 ir3_key_clear_unused(struct ir3_shader_key
*key
, struct ir3_shader
*shader
)
692 uint32_t *key_bits
= (uint32_t *)key
;
693 uint32_t *key_mask
= (uint32_t *)&shader
->key_mask
;
694 STATIC_ASSERT(sizeof(*key
) % 4 == 0);
695 for (int i
= 0; i
< sizeof(*key
) >> 2; i
++)
696 key_bits
[i
] &= key_mask
[i
];
700 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
704 for (j
= 0; j
< so
->outputs_count
; j
++)
705 if (so
->outputs
[j
].slot
== slot
)
708 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
709 * in the vertex shader.. but the fragment shader doesn't know this
710 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
711 * at link time if there is no matching OUT.BCOLOR[n], we must map
712 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
713 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
715 if (slot
== VARYING_SLOT_BFC0
) {
716 slot
= VARYING_SLOT_COL0
;
717 } else if (slot
== VARYING_SLOT_BFC1
) {
718 slot
= VARYING_SLOT_COL1
;
719 } else if (slot
== VARYING_SLOT_COL0
) {
720 slot
= VARYING_SLOT_BFC0
;
721 } else if (slot
== VARYING_SLOT_COL1
) {
722 slot
= VARYING_SLOT_BFC1
;
727 for (j
= 0; j
< so
->outputs_count
; j
++)
728 if (so
->outputs
[j
].slot
== slot
)
737 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
739 while (++i
< so
->inputs_count
)
740 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
745 struct ir3_shader_linkage
{
746 /* Maximum location either consumed by the fragment shader or produced by
747 * the last geometry stage, i.e. the size required for each vertex in the
752 /* Number of entries in var. */
755 /* Bitset of locations used, including ones which are only used by the FS.
759 /* Map from VS output to location. */
766 /* location for fixed-function gl_PrimitiveID passthrough */
771 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid_
, uint8_t compmask
, uint8_t loc
)
773 for (int j
= 0; j
< util_last_bit(compmask
); j
++) {
774 uint8_t comploc
= loc
+ j
;
775 l
->varmask
[comploc
/ 32] |= 1 << (comploc
% 32);
778 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
780 if (regid_
!= regid(63, 0)) {
782 debug_assert(i
< ARRAY_SIZE(l
->var
));
784 l
->var
[i
].regid
= regid_
;
785 l
->var
[i
].compmask
= compmask
;
791 ir3_link_shaders(struct ir3_shader_linkage
*l
,
792 const struct ir3_shader_variant
*vs
,
793 const struct ir3_shader_variant
*fs
,
796 /* On older platforms, varmask isn't programmed at all, and it appears
797 * that the hardware generates a mask of used VPC locations using the VS
798 * output map, and hangs if a FS bary instruction references a location
799 * not in the list. This means that we need to have a dummy entry in the
800 * VS out map for things like gl_PointCoord which aren't written by the
801 * VS. Furthermore we can't use r63.x, so just pick a random register to
802 * use if there is no VS output.
804 const unsigned default_regid
= pack_vs_out
? regid(63, 0) : regid(0, 0);
807 l
->primid_loc
= 0xff;
809 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
810 j
= ir3_next_varying(fs
, j
);
812 if (j
>= fs
->inputs_count
)
815 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
818 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
820 if (k
< 0 && fs
->inputs
[j
].slot
== VARYING_SLOT_PRIMITIVE_ID
) {
821 l
->primid_loc
= fs
->inputs
[j
].inloc
;
824 ir3_link_add(l
, k
>= 0 ? vs
->outputs
[k
].regid
: default_regid
,
825 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
829 static inline uint32_t
830 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
833 for (j
= 0; j
< so
->outputs_count
; j
++)
834 if (so
->outputs
[j
].slot
== slot
) {
835 uint32_t regid
= so
->outputs
[j
].regid
;
836 if (so
->outputs
[j
].half
)
837 regid
|= HALF_REG_ID
;
843 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
844 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
845 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
848 static inline uint32_t
849 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
852 for (j
= 0; j
< so
->inputs_count
; j
++)
853 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
854 return so
->inputs
[j
].regid
;
858 /* calculate register footprint in terms of half-regs (ie. one full
859 * reg counts as two half-regs).
861 static inline uint32_t
862 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
864 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
867 static inline uint32_t
868 ir3_shader_nibo(const struct ir3_shader_variant
*v
)
870 /* The dummy variant used in binning mode won't have an actual shader. */
874 return v
->shader
->nir
->info
.num_ssbos
+ v
->shader
->nir
->info
.num_images
;
877 #endif /* IR3_SHADER_H_ */