2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "compiler/shader_enums.h"
33 #include "compiler/nir/nir.h"
34 #include "util/bitscan.h"
40 /* driver param indices: */
41 enum ir3_driver_param
{
42 /* compute shader driver params: */
43 IR3_DP_NUM_WORK_GROUPS_X
= 0,
44 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
45 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
46 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
47 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
48 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
49 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
50 * glDispatchComputeIndirect() needs to load these from
51 * the info->indirect buffer. Keep that in mind when/if
52 * adding any addition CS driver params.
54 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
56 /* vertex shader driver params: */
57 IR3_DP_VTXID_BASE
= 0,
58 IR3_DP_VTXCNT_MAX
= 1,
59 /* user-clip-plane components, up to 8x vec4's: */
63 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 #define IR3_MAX_SHADER_BUFFERS 32
67 #define IR3_MAX_SHADER_IMAGES 32
68 #define IR3_MAX_SO_BUFFERS 4
69 #define IR3_MAX_SO_OUTPUTS 64
70 #define IR3_MAX_CONSTANT_BUFFERS 32
74 * Describes the layout of shader consts. This includes:
75 * + Driver lowered UBO ranges
77 * + Image sizes/dimensions
78 * + Driver params (ie. IR3_DP_*)
79 * + TFBO addresses (for generations that do not have hardware streamout)
80 * + Lowered immediates
82 * For consts needed to pass internal values to shader which may or may not
83 * be required, rather than allocating worst-case const space, we scan the
84 * shader and allocate consts as-needed:
86 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
89 * + Image dimensions: needed to calculate pixel offset, but only for
90 * images that have a image_store intrinsic
92 * Layout of constant registers, each section aligned to vec4. Note
93 * that pointer size (ubo, etc) changes depending on generation.
98 * if (vertex shader) {
99 * driver params (IR3_DP_*)
100 * if (stream_output.num_outputs > 0)
101 * stream-out addresses
102 * } else if (compute_shader) {
103 * driver params (IR3_DP_*)
107 * Immediates go last mostly because they are inserted in the CP pass
108 * after the nir -> ir3 frontend.
110 * Note UBO size in bytes should be aligned to vec4
112 struct ir3_const_state
{
113 /* number of uniforms (in vec4), not including built-in compiler
116 unsigned num_uniforms
;
121 /* user const start at zero */
123 /* NOTE that a3xx might need a section for SSBO addresses too */
126 unsigned driver_param
;
132 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
133 uint32_t count
; /* number of consts allocated */
134 /* one const allocated per SSBO which has get_buffer_size,
135 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
138 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
142 uint32_t mask
; /* bitmask of images that have image_store */
143 uint32_t count
; /* number of consts allocated */
144 /* three const allocated per image which has image_store:
145 * + cpp (bytes per pixel)
147 * + array_pitch (z pitch)
149 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
152 unsigned immediate_idx
;
153 unsigned immediates_count
;
154 unsigned immediates_size
;
161 * A single output for vertex transform feedback.
163 struct ir3_stream_output
{
164 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
165 unsigned start_component
:2; /** 0 to 3 */
166 unsigned num_components
:3; /** 1 to 4 */
167 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
168 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
169 unsigned stream
:2; /**< 0 to 3 */
173 * Stream output for vertex transform feedback.
175 struct ir3_stream_output_info
{
176 unsigned num_outputs
;
177 /** stride for an entire vertex for each buffer in dwords */
178 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
181 * Array of stream outputs, in the order they are to be written in.
182 * Selected components are tightly packed into the output buffer.
184 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
187 /* Configuration key used to identify a shader variant.. different
188 * shader variants can be used to implement features not supported
189 * in hw (two sided color), binning-pass vertex shader, etc.
191 struct ir3_shader_key
{
195 * Combined Vertex/Fragment shader parameters:
197 unsigned ucp_enables
: 8;
199 /* do we need to check {v,f}saturate_{s,t,r}? */
200 unsigned has_per_samp
: 1;
203 * Vertex shader variant parameters:
205 unsigned vclamp_color
: 1;
208 * Fragment shader variant parameters:
210 unsigned sample_shading
: 1;
212 unsigned color_two_side
: 1;
213 unsigned half_precision
: 1;
214 /* used when shader needs to handle flat varyings (a4xx)
215 * for front/back color inputs to frag shader:
217 unsigned rasterflat
: 1;
218 unsigned fclamp_color
: 1;
223 /* bitmask of sampler which needs coords clamped for vertex
226 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
228 /* bitmask of sampler which needs coords clamped for frag
231 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
233 /* bitmask of ms shifts */
234 uint32_t vsamples
, fsamples
;
236 /* bitmask of samplers which need astc srgb workaround: */
237 uint16_t vastc_srgb
, fastc_srgb
;
241 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
243 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
244 if (a
->has_per_samp
|| b
->has_per_samp
)
245 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
246 return a
->global
== b
->global
;
249 /* will the two keys produce different lowering for a fragment shader? */
251 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
253 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
254 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
255 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
256 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
257 (last_key
->fsamples
!= key
->fsamples
) ||
258 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
262 if (last_key
->fclamp_color
!= key
->fclamp_color
)
265 if (last_key
->color_two_side
!= key
->color_two_side
)
268 if (last_key
->half_precision
!= key
->half_precision
)
271 if (last_key
->rasterflat
!= key
->rasterflat
)
274 if (last_key
->ucp_enables
!= key
->ucp_enables
)
280 /* will the two keys produce different lowering for a vertex shader? */
282 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
284 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
285 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
286 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
287 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
288 (last_key
->vsamples
!= key
->vsamples
) ||
289 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
293 if (last_key
->vclamp_color
!= key
->vclamp_color
)
296 if (last_key
->ucp_enables
!= key
->ucp_enables
)
302 /* clears shader-key flags which don't apply to the given shader
306 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
309 case MESA_SHADER_FRAGMENT
:
310 if (key
->has_per_samp
) {
311 key
->vsaturate_s
= 0;
312 key
->vsaturate_t
= 0;
313 key
->vsaturate_r
= 0;
318 case MESA_SHADER_VERTEX
:
319 key
->color_two_side
= false;
320 key
->half_precision
= false;
321 key
->rasterflat
= false;
322 if (key
->has_per_samp
) {
323 key
->fsaturate_s
= 0;
324 key
->fsaturate_t
= 0;
325 key
->fsaturate_r
= 0;
337 * On a4xx+a5xx, Images share state with textures and SSBOs:
339 * + Uses texture (cat5) state/instruction (isam) to read
340 * + Uses SSBO state and instructions (cat6) to write and for atomics
342 * Starting with a6xx, Images and SSBOs are basically the same thing,
343 * with texture state and isam also used for SSBO reads.
345 * On top of that, gallium makes the SSBO (shader_buffers) state semi
346 * sparse, with the first half of the state space used for atomic
347 * counters lowered to atomic buffers. We could ignore this, but I
348 * don't think we could *really* handle the case of a single shader
349 * that used the max # of textures + images + SSBOs. And once we are
350 * offsetting images by num_ssbos (or visa versa) to map them into
351 * the same hardware state, the hardware state has become coupled to
352 * the shader state, so at this point we might as well just use a
353 * mapping table to remap things from image/SSBO idx to hw idx.
355 * To make things less (more?) confusing, for the hw "SSBO" state
356 * (since it is really both SSBO and Image) I'll use the name "IBO"
358 struct ir3_ibo_mapping
{
359 #define IBO_INVALID 0xff
360 /* Maps logical SSBO state to hw state: */
361 uint8_t ssbo_to_ibo
[IR3_MAX_SHADER_BUFFERS
];
362 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
364 /* Maps logical Image state to hw state: */
365 uint8_t image_to_ibo
[IR3_MAX_SHADER_IMAGES
];
366 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
368 /* Maps hw state back to logical SSBO or Image state:
370 * note IBO_SSBO ORd into values to indicate that the
371 * hw slot is used for SSBO state vs Image state.
373 #define IBO_SSBO 0x80
374 uint8_t ibo_to_image
[32];
375 uint8_t tex_to_image
[32];
378 uint8_t num_tex
; /* including real textures */
379 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
382 struct ir3_shader_variant
{
385 /* variant id (for debug) */
388 struct ir3_shader_key key
;
390 /* vertex shaders can have an extra version for hwbinning pass,
391 * which is pointed to by so->binning:
394 struct ir3_shader_variant
*binning
;
396 struct ir3_info info
;
399 /* Levels of nesting of flow control:
401 unsigned branchstack
;
406 /* the instructions length is in units of instruction groups
407 * (4 instructions for a3xx, 16 instructions for a4xx.. each
408 * instruction is 2 dwords):
412 /* the constants length is in units of vec4's, and is the sum of
413 * the uniforms and the built-in compiler constants
418 * + Let the frag shader determine the position/compmask for the
419 * varyings, since it is the place where we know if the varying
420 * is actually used, and if so, which components are used. So
421 * what the hw calls "outloc" is taken from the "inloc" of the
423 * + From the vert shader, we only need the output regid
426 bool frag_coord
, frag_face
, color0_mrt
;
428 /* NOTE: for input/outputs, slot is:
429 * gl_vert_attrib - for VS inputs
430 * gl_varying_slot - for VS output / FS input
431 * gl_frag_result - for FS output
434 /* varyings/outputs: */
435 unsigned outputs_count
;
440 } outputs
[16 + 2]; /* +POSITION +PSIZE */
441 bool writes_pos
, writes_smask
, writes_psize
;
443 /* attributes (VS) / varyings (FS):
444 * Note that sysval's should come *after* normal inputs.
446 unsigned inputs_count
;
452 /* location of input (ie. offset passed to bary.f, etc). This
453 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
454 * have the OUTLOCn value offset by 8, presumably to account
455 * for gl_Position/gl_PointSize)
458 /* vertex shader specific: */
459 bool sysval
: 1; /* slot is a gl_system_value */
460 /* fragment shader specific: */
461 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
462 bool rasterflat
: 1; /* special handling for emit->rasterflat */
463 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
465 enum glsl_interp_mode interpolate
;
466 } inputs
[16 + 2]; /* +POSITION +FACE */
468 /* sum of input components (scalar). For frag shaders, it only counts
469 * the varying inputs:
473 /* For frag shaders, the total number of inputs (not scalar,
474 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
478 /* Remapping table to map Image and SSBO to hw state: */
479 struct ir3_ibo_mapping image_mapping
;
481 /* number of samplers/textures (which are currently 1:1): */
484 /* is there an implicit sampler to read framebuffer (FS only).. if
485 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
486 * the last "real" texture)
490 /* do we have one or more SSBO instructions: */
493 /* do we need derivatives: */
496 /* do we have kill, image write, etc (which prevents early-z): */
501 /* for astc srgb workaround, the number/base of additional
502 * alpha tex states we need, and index of original tex states
505 unsigned base
, count
;
506 unsigned orig_idx
[16];
509 /* shader variants form a linked list: */
510 struct ir3_shader_variant
*next
;
512 /* replicated here to avoid passing extra ptrs everywhere: */
513 gl_shader_stage type
;
514 struct ir3_shader
*shader
;
517 struct ir3_ubo_range
{
518 uint32_t offset
; /* start offset of this block in const register file */
519 uint32_t start
, end
; /* range of block that's actually used */
522 struct ir3_ubo_analysis_state
524 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
526 uint32_t lower_count
;
531 gl_shader_stage type
;
533 /* shader id (for debug): */
535 uint32_t variant_count
;
537 /* so we know when we can disable TGSI related hacks: */
540 struct ir3_compiler
*compiler
;
542 struct ir3_ubo_analysis_state ubo_state
;
543 struct ir3_const_state const_state
;
545 struct nir_shader
*nir
;
546 struct ir3_stream_output_info stream_output
;
548 struct ir3_shader_variant
*variants
;
551 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
552 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
553 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
554 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
555 void ir3_shader_destroy(struct ir3_shader
*shader
);
556 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
557 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
560 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
562 static inline const char *
563 ir3_shader_stage(struct ir3_shader
*shader
)
565 switch (shader
->type
) {
566 case MESA_SHADER_VERTEX
: return "VERT";
567 case MESA_SHADER_FRAGMENT
: return "FRAG";
568 case MESA_SHADER_COMPUTE
: return "CL";
570 unreachable("invalid type");
580 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
584 for (j
= 0; j
< so
->outputs_count
; j
++)
585 if (so
->outputs
[j
].slot
== slot
)
588 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
589 * in the vertex shader.. but the fragment shader doesn't know this
590 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
591 * at link time if there is no matching OUT.BCOLOR[n], we must map
592 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
593 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
595 if (slot
== VARYING_SLOT_BFC0
) {
596 slot
= VARYING_SLOT_COL0
;
597 } else if (slot
== VARYING_SLOT_BFC1
) {
598 slot
= VARYING_SLOT_COL1
;
599 } else if (slot
== VARYING_SLOT_COL0
) {
600 slot
= VARYING_SLOT_BFC0
;
601 } else if (slot
== VARYING_SLOT_COL1
) {
602 slot
= VARYING_SLOT_BFC1
;
607 for (j
= 0; j
< so
->outputs_count
; j
++)
608 if (so
->outputs
[j
].slot
== slot
)
617 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
619 while (++i
< so
->inputs_count
)
620 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
625 struct ir3_shader_linkage
{
636 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
640 debug_assert(i
< ARRAY_SIZE(l
->var
));
642 l
->var
[i
].regid
= regid
;
643 l
->var
[i
].compmask
= compmask
;
645 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
649 ir3_link_shaders(struct ir3_shader_linkage
*l
,
650 const struct ir3_shader_variant
*vs
,
651 const struct ir3_shader_variant
*fs
)
655 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
656 j
= ir3_next_varying(fs
, j
);
658 if (j
>= fs
->inputs_count
)
661 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
664 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
666 ir3_link_add(l
, vs
->outputs
[k
].regid
,
667 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
671 static inline uint32_t
672 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
675 for (j
= 0; j
< so
->outputs_count
; j
++)
676 if (so
->outputs
[j
].slot
== slot
)
677 return so
->outputs
[j
].regid
;
681 static inline uint32_t
682 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
685 for (j
= 0; j
< so
->inputs_count
; j
++)
686 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
687 return so
->inputs
[j
].regid
;
691 /* calculate register footprint in terms of half-regs (ie. one full
692 * reg counts as two half-regs).
694 static inline uint32_t
695 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
697 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
700 #endif /* IR3_SHADER_H_ */