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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #include "util/ralloc.h"
30 struct ir3_validate_ctx
{
33 /* Current instruction being validated: */
34 struct ir3_instruction
*current_instr
;
36 /* Set of instructions found so far, used to validate that we
37 * don't have SSA uses that occure before def's
43 validate_error(struct ir3_validate_ctx
*ctx
, const char *condstr
)
45 fprintf(stderr
, "validation fail: %s\n", condstr
);
46 fprintf(stderr
, " -> for instruction: ");
47 ir3_print_instr(ctx
->current_instr
);
51 #define validate_assert(ctx, cond) do { \
53 validate_error(ctx, #cond); \
57 reg_class_flags(struct ir3_register
*reg
)
59 return reg
->flags
& (IR3_REG_HALF
| IR3_REG_HIGH
);
63 validate_src(struct ir3_validate_ctx
*ctx
, struct ir3_register
*reg
)
65 struct ir3_instruction
*src
= ssa(reg
);
70 validate_assert(ctx
, _mesa_set_search(ctx
->defs
, src
));
71 validate_assert(ctx
, src
->regs
[0]->wrmask
== reg
->wrmask
);
72 validate_assert(ctx
, reg_class_flags(src
->regs
[0]) == reg_class_flags(reg
));
76 validate_instr(struct ir3_validate_ctx
*ctx
, struct ir3_instruction
*instr
)
78 struct ir3_register
*last_reg
= NULL
;
80 if (writes_gpr(instr
)) {
81 if (instr
->regs
[0]->flags
& IR3_REG_RELATIV
) {
82 validate_assert(ctx
, instr
->address
);
86 foreach_src_n (reg
, n
, instr
) {
87 if (reg
->flags
& IR3_REG_RELATIV
)
88 validate_assert(ctx
, instr
->address
);
90 validate_src(ctx
, reg
);
92 /* Validate that all src's are either half of full.
94 * Note: tex instructions w/ .s2en are a bit special in
95 * that the tex/samp src reg is half-reg irrespective of
96 * the precision of other srcs. The tex/samp src is the
97 * first src reg when .s2en is set
99 if ((instr
->flags
& IR3_INSTR_S2EN
) && (n
< 2)) {
101 validate_assert(ctx
, reg
->flags
& IR3_REG_HALF
);
104 validate_assert(ctx
, (last_reg
->flags
& IR3_REG_HALF
) == (reg
->flags
& IR3_REG_HALF
));
110 _mesa_set_add(ctx
->defs
, instr
);
112 /* Check that src/dst types match the register types, and for
113 * instructions that have different opcodes depending on type,
114 * that the opcodes are correct.
116 switch (opc_cat(instr
->opc
)) {
117 case 1: /* move instructions */
118 if (instr
->regs
[0]->flags
& IR3_REG_HALF
) {
119 validate_assert(ctx
, instr
->cat1
.dst_type
== half_type(instr
->cat1
.dst_type
));
121 validate_assert(ctx
, instr
->cat1
.dst_type
== full_type(instr
->cat1
.dst_type
));
123 if (instr
->regs
[1]->flags
& IR3_REG_HALF
) {
124 validate_assert(ctx
, instr
->cat1
.src_type
== half_type(instr
->cat1
.src_type
));
126 validate_assert(ctx
, instr
->cat1
.src_type
== full_type(instr
->cat1
.src_type
));
130 /* Validate that cat3 opc matches the src type. We've already checked that all
131 * the src regs are same type
133 if (instr
->regs
[1]->flags
& IR3_REG_HALF
) {
134 validate_assert(ctx
, instr
->opc
== cat3_half_opc(instr
->opc
));
136 validate_assert(ctx
, instr
->opc
== cat3_full_opc(instr
->opc
));
140 /* Validate that cat4 opc matches the dst type: */
141 if (instr
->regs
[0]->flags
& IR3_REG_HALF
) {
142 validate_assert(ctx
, instr
->opc
== cat4_half_opc(instr
->opc
));
144 validate_assert(ctx
, instr
->opc
== cat4_full_opc(instr
->opc
));
148 if (instr
->regs
[0]->flags
& IR3_REG_HALF
) {
149 validate_assert(ctx
, instr
->cat5
.type
== half_type(instr
->cat5
.type
));
151 validate_assert(ctx
, instr
->cat5
.type
== full_type(instr
->cat5
.type
));
158 ir3_validate(struct ir3
*ir
)
169 struct ir3_validate_ctx
*ctx
= ralloc_size(NULL
, sizeof(*ctx
));
172 ctx
->defs
= _mesa_pointer_set_create(ctx
);
174 foreach_block (block
, &ir
->block_list
) {
175 foreach_instr (instr
, &block
->instr_list
) {
176 ctx
->current_instr
= instr
;
177 validate_instr(ctx
, instr
);