2 * Copyright (C) 2018 Jonathan Marek <jonathan@marek.ca>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jonathan Marek <jonathan@marek.ca>
25 * Rob Clark <robclark@freedesktop.org>
28 #include "util/u_half.h"
29 #include "adreno_common.xml.h"
30 #include "adreno_pm4.xml.h"
33 #define REG(_x) REG_A2XX_ ## _x
34 #include "freedreno_perfcntr.h"
36 static const struct fd_perfcntr_countable pa_su_countables
[] = {
37 COUNTABLE(PERF_PAPC_PASX_REQ
, UINT64
, AVERAGE
),
38 COUNTABLE(PERF_PAPC_PASX_FIRST_VECTOR
, UINT64
, AVERAGE
),
39 COUNTABLE(PERF_PAPC_PASX_SECOND_VECTOR
, UINT64
, AVERAGE
),
40 COUNTABLE(PERF_PAPC_PASX_FIRST_DEAD
, UINT64
, AVERAGE
),
41 COUNTABLE(PERF_PAPC_PASX_SECOND_DEAD
, UINT64
, AVERAGE
),
42 COUNTABLE(PERF_PAPC_PASX_VTX_KILL_DISCARD
, UINT64
, AVERAGE
),
43 COUNTABLE(PERF_PAPC_PASX_VTX_NAN_DISCARD
, UINT64
, AVERAGE
),
44 COUNTABLE(PERF_PAPC_PA_INPUT_PRIM
, UINT64
, AVERAGE
),
45 COUNTABLE(PERF_PAPC_PA_INPUT_NULL_PRIM
, UINT64
, AVERAGE
),
46 COUNTABLE(PERF_PAPC_PA_INPUT_EVENT_FLAG
, UINT64
, AVERAGE
),
47 COUNTABLE(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT
, UINT64
, AVERAGE
),
48 COUNTABLE(PERF_PAPC_PA_INPUT_END_OF_PACKET
, UINT64
, AVERAGE
),
49 COUNTABLE(PERF_PAPC_CLPR_CULL_PRIM
, UINT64
, AVERAGE
),
50 COUNTABLE(PERF_PAPC_CLPR_VV_CULL_PRIM
, UINT64
, AVERAGE
),
51 COUNTABLE(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM
, UINT64
, AVERAGE
),
52 COUNTABLE(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM
, UINT64
, AVERAGE
),
53 COUNTABLE(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM
, UINT64
, AVERAGE
),
54 COUNTABLE(PERF_PAPC_CLPR_VV_CLIP_PRIM
, UINT64
, AVERAGE
),
55 COUNTABLE(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE
, UINT64
, AVERAGE
),
56 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1
, UINT64
, AVERAGE
),
57 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2
, UINT64
, AVERAGE
),
58 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3
, UINT64
, AVERAGE
),
59 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4
, UINT64
, AVERAGE
),
60 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5
, UINT64
, AVERAGE
),
61 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6
, UINT64
, AVERAGE
),
62 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_NEAR
, UINT64
, AVERAGE
),
63 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_FAR
, UINT64
, AVERAGE
),
64 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_LEFT
, UINT64
, AVERAGE
),
65 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT
, UINT64
, AVERAGE
),
66 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_TOP
, UINT64
, AVERAGE
),
67 COUNTABLE(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM
, UINT64
, AVERAGE
),
68 COUNTABLE(PERF_PAPC_CLSM_NULL_PRIM
, UINT64
, AVERAGE
),
69 COUNTABLE(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM
, UINT64
, AVERAGE
),
70 COUNTABLE(PERF_PAPC_CLSM_CLIP_PRIM
, UINT64
, AVERAGE
),
71 COUNTABLE(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM
, UINT64
, AVERAGE
),
72 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_1
, UINT64
, AVERAGE
),
73 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_2
, UINT64
, AVERAGE
),
74 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_3
, UINT64
, AVERAGE
),
75 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_4
, UINT64
, AVERAGE
),
76 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_5
, UINT64
, AVERAGE
),
77 COUNTABLE(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7
, UINT64
, AVERAGE
),
78 COUNTABLE(PERF_PAPC_CLSM_NON_TRIVIAL_CULL
, UINT64
, AVERAGE
),
79 COUNTABLE(PERF_PAPC_SU_INPUT_PRIM
, UINT64
, AVERAGE
),
80 COUNTABLE(PERF_PAPC_SU_INPUT_CLIP_PRIM
, UINT64
, AVERAGE
),
81 COUNTABLE(PERF_PAPC_SU_INPUT_NULL_PRIM
, UINT64
, AVERAGE
),
82 COUNTABLE(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM
, UINT64
, AVERAGE
),
83 COUNTABLE(PERF_PAPC_SU_BACK_FACE_CULL_PRIM
, UINT64
, AVERAGE
),
84 COUNTABLE(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM
, UINT64
, AVERAGE
),
85 COUNTABLE(PERF_PAPC_SU_POLYMODE_FACE_CULL
, UINT64
, AVERAGE
),
86 COUNTABLE(PERF_PAPC_SU_POLYMODE_BACK_CULL
, UINT64
, AVERAGE
),
87 COUNTABLE(PERF_PAPC_SU_POLYMODE_FRONT_CULL
, UINT64
, AVERAGE
),
88 COUNTABLE(PERF_PAPC_SU_POLYMODE_INVALID_FILL
, UINT64
, AVERAGE
),
89 COUNTABLE(PERF_PAPC_SU_OUTPUT_PRIM
, UINT64
, AVERAGE
),
90 COUNTABLE(PERF_PAPC_SU_OUTPUT_CLIP_PRIM
, UINT64
, AVERAGE
),
91 COUNTABLE(PERF_PAPC_SU_OUTPUT_NULL_PRIM
, UINT64
, AVERAGE
),
92 COUNTABLE(PERF_PAPC_SU_OUTPUT_EVENT_FLAG
, UINT64
, AVERAGE
),
93 COUNTABLE(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT
, UINT64
, AVERAGE
),
94 COUNTABLE(PERF_PAPC_SU_OUTPUT_END_OF_PACKET
, UINT64
, AVERAGE
),
95 COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE
, UINT64
, AVERAGE
),
96 COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK
, UINT64
, AVERAGE
),
97 COUNTABLE(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT
, UINT64
, AVERAGE
),
98 COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE
, UINT64
, AVERAGE
),
99 COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK
, UINT64
, AVERAGE
),
100 COUNTABLE(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT
, UINT64
, AVERAGE
),
101 COUNTABLE(PERF_PAPC_PASX_REQ_IDLE
, UINT64
, AVERAGE
),
102 COUNTABLE(PERF_PAPC_PASX_REQ_BUSY
, UINT64
, AVERAGE
),
103 COUNTABLE(PERF_PAPC_PASX_REQ_STALLED
, UINT64
, AVERAGE
),
104 COUNTABLE(PERF_PAPC_PASX_REC_IDLE
, UINT64
, AVERAGE
),
105 COUNTABLE(PERF_PAPC_PASX_REC_BUSY
, UINT64
, AVERAGE
),
106 COUNTABLE(PERF_PAPC_PASX_REC_STARVED_SX
, UINT64
, AVERAGE
),
107 COUNTABLE(PERF_PAPC_PASX_REC_STALLED
, UINT64
, AVERAGE
),
108 COUNTABLE(PERF_PAPC_PASX_REC_STALLED_POS_MEM
, UINT64
, AVERAGE
),
109 COUNTABLE(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN
, UINT64
, AVERAGE
),
110 COUNTABLE(PERF_PAPC_CCGSM_IDLE
, UINT64
, AVERAGE
),
111 COUNTABLE(PERF_PAPC_CCGSM_BUSY
, UINT64
, AVERAGE
),
112 COUNTABLE(PERF_PAPC_CCGSM_STALLED
, UINT64
, AVERAGE
),
113 COUNTABLE(PERF_PAPC_CLPRIM_IDLE
, UINT64
, AVERAGE
),
114 COUNTABLE(PERF_PAPC_CLPRIM_BUSY
, UINT64
, AVERAGE
),
115 COUNTABLE(PERF_PAPC_CLPRIM_STALLED
, UINT64
, AVERAGE
),
116 COUNTABLE(PERF_PAPC_CLPRIM_STARVED_CCGSM
, UINT64
, AVERAGE
),
117 COUNTABLE(PERF_PAPC_CLIPSM_IDLE
, UINT64
, AVERAGE
),
118 COUNTABLE(PERF_PAPC_CLIPSM_BUSY
, UINT64
, AVERAGE
),
119 COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH
, UINT64
, AVERAGE
),
120 COUNTABLE(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ
, UINT64
, AVERAGE
),
121 COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIPGA
, UINT64
, AVERAGE
),
122 COUNTABLE(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP
, UINT64
, AVERAGE
),
123 COUNTABLE(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM
, UINT64
, AVERAGE
),
124 COUNTABLE(PERF_PAPC_CLIPGA_IDLE
, UINT64
, AVERAGE
),
125 COUNTABLE(PERF_PAPC_CLIPGA_BUSY
, UINT64
, AVERAGE
),
126 COUNTABLE(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP
, UINT64
, AVERAGE
),
127 COUNTABLE(PERF_PAPC_CLIPGA_STALLED
, UINT64
, AVERAGE
),
128 COUNTABLE(PERF_PAPC_CLIP_IDLE
, UINT64
, AVERAGE
),
129 COUNTABLE(PERF_PAPC_CLIP_BUSY
, UINT64
, AVERAGE
),
130 COUNTABLE(PERF_PAPC_SU_IDLE
, UINT64
, AVERAGE
),
131 COUNTABLE(PERF_PAPC_SU_BUSY
, UINT64
, AVERAGE
),
132 COUNTABLE(PERF_PAPC_SU_STARVED_CLIP
, UINT64
, AVERAGE
),
133 COUNTABLE(PERF_PAPC_SU_STALLED_SC
, UINT64
, AVERAGE
),
134 COUNTABLE(PERF_PAPC_SU_FACENESS_CULL
, UINT64
, AVERAGE
),
137 static const struct fd_perfcntr_countable pa_sc_countables
[] = {
138 COUNTABLE(SC_SR_WINDOW_VALID
, UINT64
, AVERAGE
),
139 COUNTABLE(SC_CW_WINDOW_VALID
, UINT64
, AVERAGE
),
140 COUNTABLE(SC_QM_WINDOW_VALID
, UINT64
, AVERAGE
),
141 COUNTABLE(SC_FW_WINDOW_VALID
, UINT64
, AVERAGE
),
142 COUNTABLE(SC_EZ_WINDOW_VALID
, UINT64
, AVERAGE
),
143 COUNTABLE(SC_IT_WINDOW_VALID
, UINT64
, AVERAGE
),
144 COUNTABLE(SC_STARVED_BY_PA
, UINT64
, AVERAGE
),
145 COUNTABLE(SC_STALLED_BY_RB_TILE
, UINT64
, AVERAGE
),
146 COUNTABLE(SC_STALLED_BY_RB_SAMP
, UINT64
, AVERAGE
),
147 COUNTABLE(SC_STARVED_BY_RB_EZ
, UINT64
, AVERAGE
),
148 COUNTABLE(SC_STALLED_BY_SAMPLE_FF
, UINT64
, AVERAGE
),
149 COUNTABLE(SC_STALLED_BY_SQ
, UINT64
, AVERAGE
),
150 COUNTABLE(SC_STALLED_BY_SP
, UINT64
, AVERAGE
),
151 COUNTABLE(SC_TOTAL_NO_PRIMS
, UINT64
, AVERAGE
),
152 COUNTABLE(SC_NON_EMPTY_PRIMS
, UINT64
, AVERAGE
),
153 COUNTABLE(SC_NO_TILES_PASSING_QM
, UINT64
, AVERAGE
),
154 COUNTABLE(SC_NO_PIXELS_PRE_EZ
, UINT64
, AVERAGE
),
155 COUNTABLE(SC_NO_PIXELS_POST_EZ
, UINT64
, AVERAGE
),
158 static const struct fd_perfcntr_countable vgt_countables
[] = {
159 COUNTABLE(VGT_SQ_EVENT_WINDOW_ACTIVE
, UINT64
, AVERAGE
),
160 COUNTABLE(VGT_SQ_SEND
, UINT64
, AVERAGE
),
161 COUNTABLE(VGT_SQ_STALLED
, UINT64
, AVERAGE
),
162 COUNTABLE(VGT_SQ_STARVED_BUSY
, UINT64
, AVERAGE
),
163 COUNTABLE(VGT_SQ_STARVED_IDLE
, UINT64
, AVERAGE
),
164 COUNTABLE(VGT_SQ_STATIC
, UINT64
, AVERAGE
),
165 COUNTABLE(VGT_PA_EVENT_WINDOW_ACTIVE
, UINT64
, AVERAGE
),
166 COUNTABLE(VGT_PA_CLIP_V_SEND
, UINT64
, AVERAGE
),
167 COUNTABLE(VGT_PA_CLIP_V_STALLED
, UINT64
, AVERAGE
),
168 COUNTABLE(VGT_PA_CLIP_V_STARVED_BUSY
, UINT64
, AVERAGE
),
169 COUNTABLE(VGT_PA_CLIP_V_STARVED_IDLE
, UINT64
, AVERAGE
),
170 COUNTABLE(VGT_PA_CLIP_V_STATIC
, UINT64
, AVERAGE
),
171 COUNTABLE(VGT_PA_CLIP_P_SEND
, UINT64
, AVERAGE
),
172 COUNTABLE(VGT_PA_CLIP_P_STALLED
, UINT64
, AVERAGE
),
173 COUNTABLE(VGT_PA_CLIP_P_STARVED_BUSY
, UINT64
, AVERAGE
),
174 COUNTABLE(VGT_PA_CLIP_P_STARVED_IDLE
, UINT64
, AVERAGE
),
175 COUNTABLE(VGT_PA_CLIP_P_STATIC
, UINT64
, AVERAGE
),
176 COUNTABLE(VGT_PA_CLIP_S_SEND
, UINT64
, AVERAGE
),
177 COUNTABLE(VGT_PA_CLIP_S_STALLED
, UINT64
, AVERAGE
),
178 COUNTABLE(VGT_PA_CLIP_S_STARVED_BUSY
, UINT64
, AVERAGE
),
179 COUNTABLE(VGT_PA_CLIP_S_STARVED_IDLE
, UINT64
, AVERAGE
),
180 COUNTABLE(VGT_PA_CLIP_S_STATIC
, UINT64
, AVERAGE
),
181 COUNTABLE(RBIU_FIFOS_EVENT_WINDOW_ACTIVE
, UINT64
, AVERAGE
),
182 COUNTABLE(RBIU_IMMED_DATA_FIFO_STARVED
, UINT64
, AVERAGE
),
183 COUNTABLE(RBIU_IMMED_DATA_FIFO_STALLED
, UINT64
, AVERAGE
),
184 COUNTABLE(RBIU_DMA_REQUEST_FIFO_STARVED
, UINT64
, AVERAGE
),
185 COUNTABLE(RBIU_DMA_REQUEST_FIFO_STALLED
, UINT64
, AVERAGE
),
186 COUNTABLE(RBIU_DRAW_INITIATOR_FIFO_STARVED
, UINT64
, AVERAGE
),
187 COUNTABLE(RBIU_DRAW_INITIATOR_FIFO_STALLED
, UINT64
, AVERAGE
),
188 COUNTABLE(BIN_PRIM_NEAR_CULL
, UINT64
, AVERAGE
),
189 COUNTABLE(BIN_PRIM_ZERO_CULL
, UINT64
, AVERAGE
),
190 COUNTABLE(BIN_PRIM_FAR_CULL
, UINT64
, AVERAGE
),
191 COUNTABLE(BIN_PRIM_BIN_CULL
, UINT64
, AVERAGE
),
192 COUNTABLE(BIN_PRIM_FACE_CULL
, UINT64
, AVERAGE
),
193 COUNTABLE(SPARE34
, UINT64
, AVERAGE
),
194 COUNTABLE(SPARE35
, UINT64
, AVERAGE
),
195 COUNTABLE(SPARE36
, UINT64
, AVERAGE
),
196 COUNTABLE(SPARE37
, UINT64
, AVERAGE
),
197 COUNTABLE(SPARE38
, UINT64
, AVERAGE
),
198 COUNTABLE(SPARE39
, UINT64
, AVERAGE
),
199 COUNTABLE(TE_SU_IN_VALID
, UINT64
, AVERAGE
),
200 COUNTABLE(TE_SU_IN_READ
, UINT64
, AVERAGE
),
201 COUNTABLE(TE_SU_IN_PRIM
, UINT64
, AVERAGE
),
202 COUNTABLE(TE_SU_IN_EOP
, UINT64
, AVERAGE
),
203 COUNTABLE(TE_SU_IN_NULL_PRIM
, UINT64
, AVERAGE
),
204 COUNTABLE(TE_WK_IN_VALID
, UINT64
, AVERAGE
),
205 COUNTABLE(TE_WK_IN_READ
, UINT64
, AVERAGE
),
206 COUNTABLE(TE_OUT_PRIM_VALID
, UINT64
, AVERAGE
),
207 COUNTABLE(TE_OUT_PRIM_READ
, UINT64
, AVERAGE
),
210 static const struct fd_perfcntr_countable tcr_countables
[] = {
211 COUNTABLE(DGMMPD_IPMUX0_STALL
, UINT64
, AVERAGE
),
212 COUNTABLE(DGMMPD_IPMUX_ALL_STALL
, UINT64
, AVERAGE
),
213 COUNTABLE(OPMUX0_L2_WRITES
, UINT64
, AVERAGE
),
216 static const struct fd_perfcntr_countable tp0_countables
[] = {
217 COUNTABLE(POINT_QUADS
, UINT64
, AVERAGE
),
218 COUNTABLE(BILIN_QUADS
, UINT64
, AVERAGE
),
219 COUNTABLE(ANISO_QUADS
, UINT64
, AVERAGE
),
220 COUNTABLE(MIP_QUADS
, UINT64
, AVERAGE
),
221 COUNTABLE(VOL_QUADS
, UINT64
, AVERAGE
),
222 COUNTABLE(MIP_VOL_QUADS
, UINT64
, AVERAGE
),
223 COUNTABLE(MIP_ANISO_QUADS
, UINT64
, AVERAGE
),
224 COUNTABLE(VOL_ANISO_QUADS
, UINT64
, AVERAGE
),
225 COUNTABLE(ANISO_2_1_QUADS
, UINT64
, AVERAGE
),
226 COUNTABLE(ANISO_4_1_QUADS
, UINT64
, AVERAGE
),
227 COUNTABLE(ANISO_6_1_QUADS
, UINT64
, AVERAGE
),
228 COUNTABLE(ANISO_8_1_QUADS
, UINT64
, AVERAGE
),
229 COUNTABLE(ANISO_10_1_QUADS
, UINT64
, AVERAGE
),
230 COUNTABLE(ANISO_12_1_QUADS
, UINT64
, AVERAGE
),
231 COUNTABLE(ANISO_14_1_QUADS
, UINT64
, AVERAGE
),
232 COUNTABLE(ANISO_16_1_QUADS
, UINT64
, AVERAGE
),
233 COUNTABLE(MIP_VOL_ANISO_QUADS
, UINT64
, AVERAGE
),
234 COUNTABLE(ALIGN_2_QUADS
, UINT64
, AVERAGE
),
235 COUNTABLE(ALIGN_4_QUADS
, UINT64
, AVERAGE
),
236 COUNTABLE(PIX_0_QUAD
, UINT64
, AVERAGE
),
237 COUNTABLE(PIX_1_QUAD
, UINT64
, AVERAGE
),
238 COUNTABLE(PIX_2_QUAD
, UINT64
, AVERAGE
),
239 COUNTABLE(PIX_3_QUAD
, UINT64
, AVERAGE
),
240 COUNTABLE(PIX_4_QUAD
, UINT64
, AVERAGE
),
241 COUNTABLE(TP_MIPMAP_LOD0
, UINT64
, AVERAGE
),
242 COUNTABLE(TP_MIPMAP_LOD1
, UINT64
, AVERAGE
),
243 COUNTABLE(TP_MIPMAP_LOD2
, UINT64
, AVERAGE
),
244 COUNTABLE(TP_MIPMAP_LOD3
, UINT64
, AVERAGE
),
245 COUNTABLE(TP_MIPMAP_LOD4
, UINT64
, AVERAGE
),
246 COUNTABLE(TP_MIPMAP_LOD5
, UINT64
, AVERAGE
),
247 COUNTABLE(TP_MIPMAP_LOD6
, UINT64
, AVERAGE
),
248 COUNTABLE(TP_MIPMAP_LOD7
, UINT64
, AVERAGE
),
249 COUNTABLE(TP_MIPMAP_LOD8
, UINT64
, AVERAGE
),
250 COUNTABLE(TP_MIPMAP_LOD9
, UINT64
, AVERAGE
),
251 COUNTABLE(TP_MIPMAP_LOD10
, UINT64
, AVERAGE
),
252 COUNTABLE(TP_MIPMAP_LOD11
, UINT64
, AVERAGE
),
253 COUNTABLE(TP_MIPMAP_LOD12
, UINT64
, AVERAGE
),
254 COUNTABLE(TP_MIPMAP_LOD13
, UINT64
, AVERAGE
),
255 COUNTABLE(TP_MIPMAP_LOD14
, UINT64
, AVERAGE
),
258 static const struct fd_perfcntr_countable tcm_countables
[] = {
259 COUNTABLE(QUAD0_RD_LAT_FIFO_EMPTY
, UINT64
, AVERAGE
),
260 COUNTABLE(QUAD0_RD_LAT_FIFO_4TH_FULL
, UINT64
, AVERAGE
),
261 COUNTABLE(QUAD0_RD_LAT_FIFO_HALF_FULL
, UINT64
, AVERAGE
),
262 COUNTABLE(QUAD0_RD_LAT_FIFO_FULL
, UINT64
, AVERAGE
),
263 COUNTABLE(QUAD0_RD_LAT_FIFO_LT_4TH_FULL
, UINT64
, AVERAGE
),
264 COUNTABLE(READ_STARVED_QUAD0
, UINT64
, AVERAGE
),
265 COUNTABLE(READ_STARVED
, UINT64
, AVERAGE
),
266 COUNTABLE(READ_STALLED_QUAD0
, UINT64
, AVERAGE
),
267 COUNTABLE(READ_STALLED
, UINT64
, AVERAGE
),
268 COUNTABLE(VALID_READ_QUAD0
, UINT64
, AVERAGE
),
269 COUNTABLE(TC_TP_STARVED_QUAD0
, UINT64
, AVERAGE
),
270 COUNTABLE(TC_TP_STARVED
, UINT64
, AVERAGE
),
273 static const struct fd_perfcntr_countable tcf_countables
[] = {
274 COUNTABLE(VALID_CYCLES
, UINT64
, AVERAGE
),
275 COUNTABLE(SINGLE_PHASES
, UINT64
, AVERAGE
),
276 COUNTABLE(ANISO_PHASES
, UINT64
, AVERAGE
),
277 COUNTABLE(MIP_PHASES
, UINT64
, AVERAGE
),
278 COUNTABLE(VOL_PHASES
, UINT64
, AVERAGE
),
279 COUNTABLE(MIP_VOL_PHASES
, UINT64
, AVERAGE
),
280 COUNTABLE(MIP_ANISO_PHASES
, UINT64
, AVERAGE
),
281 COUNTABLE(VOL_ANISO_PHASES
, UINT64
, AVERAGE
),
282 COUNTABLE(ANISO_2_1_PHASES
, UINT64
, AVERAGE
),
283 COUNTABLE(ANISO_4_1_PHASES
, UINT64
, AVERAGE
),
284 COUNTABLE(ANISO_6_1_PHASES
, UINT64
, AVERAGE
),
285 COUNTABLE(ANISO_8_1_PHASES
, UINT64
, AVERAGE
),
286 COUNTABLE(ANISO_10_1_PHASES
, UINT64
, AVERAGE
),
287 COUNTABLE(ANISO_12_1_PHASES
, UINT64
, AVERAGE
),
288 COUNTABLE(ANISO_14_1_PHASES
, UINT64
, AVERAGE
),
289 COUNTABLE(ANISO_16_1_PHASES
, UINT64
, AVERAGE
),
290 COUNTABLE(MIP_VOL_ANISO_PHASES
, UINT64
, AVERAGE
),
291 COUNTABLE(ALIGN_2_PHASES
, UINT64
, AVERAGE
),
292 COUNTABLE(ALIGN_4_PHASES
, UINT64
, AVERAGE
),
293 COUNTABLE(TPC_BUSY
, UINT64
, AVERAGE
),
294 COUNTABLE(TPC_STALLED
, UINT64
, AVERAGE
),
295 COUNTABLE(TPC_STARVED
, UINT64
, AVERAGE
),
296 COUNTABLE(TPC_WORKING
, UINT64
, AVERAGE
),
297 COUNTABLE(TPC_WALKER_BUSY
, UINT64
, AVERAGE
),
298 COUNTABLE(TPC_WALKER_STALLED
, UINT64
, AVERAGE
),
299 COUNTABLE(TPC_WALKER_WORKING
, UINT64
, AVERAGE
),
300 COUNTABLE(TPC_ALIGNER_BUSY
, UINT64
, AVERAGE
),
301 COUNTABLE(TPC_ALIGNER_STALLED
, UINT64
, AVERAGE
),
302 COUNTABLE(TPC_ALIGNER_STALLED_BY_BLEND
, UINT64
, AVERAGE
),
303 COUNTABLE(TPC_ALIGNER_STALLED_BY_CACHE
, UINT64
, AVERAGE
),
304 COUNTABLE(TPC_ALIGNER_WORKING
, UINT64
, AVERAGE
),
305 COUNTABLE(TPC_BLEND_BUSY
, UINT64
, AVERAGE
),
306 COUNTABLE(TPC_BLEND_SYNC
, UINT64
, AVERAGE
),
307 COUNTABLE(TPC_BLEND_STARVED
, UINT64
, AVERAGE
),
308 COUNTABLE(TPC_BLEND_WORKING
, UINT64
, AVERAGE
),
309 COUNTABLE(OPCODE_0x00
, UINT64
, AVERAGE
),
310 COUNTABLE(OPCODE_0x01
, UINT64
, AVERAGE
),
311 COUNTABLE(OPCODE_0x04
, UINT64
, AVERAGE
),
312 COUNTABLE(OPCODE_0x10
, UINT64
, AVERAGE
),
313 COUNTABLE(OPCODE_0x11
, UINT64
, AVERAGE
),
314 COUNTABLE(OPCODE_0x12
, UINT64
, AVERAGE
),
315 COUNTABLE(OPCODE_0x13
, UINT64
, AVERAGE
),
316 COUNTABLE(OPCODE_0x18
, UINT64
, AVERAGE
),
317 COUNTABLE(OPCODE_0x19
, UINT64
, AVERAGE
),
318 COUNTABLE(OPCODE_0x1A
, UINT64
, AVERAGE
),
319 COUNTABLE(OPCODE_OTHER
, UINT64
, AVERAGE
),
320 COUNTABLE(IN_FIFO_0_EMPTY
, UINT64
, AVERAGE
),
321 COUNTABLE(IN_FIFO_0_LT_HALF_FULL
, UINT64
, AVERAGE
),
322 COUNTABLE(IN_FIFO_0_HALF_FULL
, UINT64
, AVERAGE
),
323 COUNTABLE(IN_FIFO_0_FULL
, UINT64
, AVERAGE
),
324 COUNTABLE(IN_FIFO_TPC_EMPTY
, UINT64
, AVERAGE
),
325 COUNTABLE(IN_FIFO_TPC_LT_HALF_FULL
, UINT64
, AVERAGE
),
326 COUNTABLE(IN_FIFO_TPC_HALF_FULL
, UINT64
, AVERAGE
),
327 COUNTABLE(IN_FIFO_TPC_FULL
, UINT64
, AVERAGE
),
328 COUNTABLE(TPC_TC_XFC
, UINT64
, AVERAGE
),
329 COUNTABLE(TPC_TC_STATE
, UINT64
, AVERAGE
),
330 COUNTABLE(TC_STALL
, UINT64
, AVERAGE
),
331 COUNTABLE(QUAD0_TAPS
, UINT64
, AVERAGE
),
332 COUNTABLE(QUADS
, UINT64
, AVERAGE
),
333 COUNTABLE(TCA_SYNC_STALL
, UINT64
, AVERAGE
),
334 COUNTABLE(TAG_STALL
, UINT64
, AVERAGE
),
335 COUNTABLE(TCB_SYNC_STALL
, UINT64
, AVERAGE
),
336 COUNTABLE(TCA_VALID
, UINT64
, AVERAGE
),
337 COUNTABLE(PROBES_VALID
, UINT64
, AVERAGE
),
338 COUNTABLE(MISS_STALL
, UINT64
, AVERAGE
),
339 COUNTABLE(FETCH_FIFO_STALL
, UINT64
, AVERAGE
),
340 COUNTABLE(TCO_STALL
, UINT64
, AVERAGE
),
341 COUNTABLE(ANY_STALL
, UINT64
, AVERAGE
),
342 COUNTABLE(TAG_MISSES
, UINT64
, AVERAGE
),
343 COUNTABLE(TAG_HITS
, UINT64
, AVERAGE
),
344 COUNTABLE(SUB_TAG_MISSES
, UINT64
, AVERAGE
),
345 COUNTABLE(SET0_INVALIDATES
, UINT64
, AVERAGE
),
346 COUNTABLE(SET1_INVALIDATES
, UINT64
, AVERAGE
),
347 COUNTABLE(SET2_INVALIDATES
, UINT64
, AVERAGE
),
348 COUNTABLE(SET3_INVALIDATES
, UINT64
, AVERAGE
),
349 COUNTABLE(SET0_TAG_MISSES
, UINT64
, AVERAGE
),
350 COUNTABLE(SET1_TAG_MISSES
, UINT64
, AVERAGE
),
351 COUNTABLE(SET2_TAG_MISSES
, UINT64
, AVERAGE
),
352 COUNTABLE(SET3_TAG_MISSES
, UINT64
, AVERAGE
),
353 COUNTABLE(SET0_TAG_HITS
, UINT64
, AVERAGE
),
354 COUNTABLE(SET1_TAG_HITS
, UINT64
, AVERAGE
),
355 COUNTABLE(SET2_TAG_HITS
, UINT64
, AVERAGE
),
356 COUNTABLE(SET3_TAG_HITS
, UINT64
, AVERAGE
),
357 COUNTABLE(SET0_SUB_TAG_MISSES
, UINT64
, AVERAGE
),
358 COUNTABLE(SET1_SUB_TAG_MISSES
, UINT64
, AVERAGE
),
359 COUNTABLE(SET2_SUB_TAG_MISSES
, UINT64
, AVERAGE
),
360 COUNTABLE(SET3_SUB_TAG_MISSES
, UINT64
, AVERAGE
),
361 COUNTABLE(SET0_EVICT1
, UINT64
, AVERAGE
),
362 COUNTABLE(SET0_EVICT2
, UINT64
, AVERAGE
),
363 COUNTABLE(SET0_EVICT3
, UINT64
, AVERAGE
),
364 COUNTABLE(SET0_EVICT4
, UINT64
, AVERAGE
),
365 COUNTABLE(SET0_EVICT5
, UINT64
, AVERAGE
),
366 COUNTABLE(SET0_EVICT6
, UINT64
, AVERAGE
),
367 COUNTABLE(SET0_EVICT7
, UINT64
, AVERAGE
),
368 COUNTABLE(SET0_EVICT8
, UINT64
, AVERAGE
),
369 COUNTABLE(SET1_EVICT1
, UINT64
, AVERAGE
),
370 COUNTABLE(SET1_EVICT2
, UINT64
, AVERAGE
),
371 COUNTABLE(SET1_EVICT3
, UINT64
, AVERAGE
),
372 COUNTABLE(SET1_EVICT4
, UINT64
, AVERAGE
),
373 COUNTABLE(SET1_EVICT5
, UINT64
, AVERAGE
),
374 COUNTABLE(SET1_EVICT6
, UINT64
, AVERAGE
),
375 COUNTABLE(SET1_EVICT7
, UINT64
, AVERAGE
),
376 COUNTABLE(SET1_EVICT8
, UINT64
, AVERAGE
),
377 COUNTABLE(SET2_EVICT1
, UINT64
, AVERAGE
),
378 COUNTABLE(SET2_EVICT2
, UINT64
, AVERAGE
),
379 COUNTABLE(SET2_EVICT3
, UINT64
, AVERAGE
),
380 COUNTABLE(SET2_EVICT4
, UINT64
, AVERAGE
),
381 COUNTABLE(SET2_EVICT5
, UINT64
, AVERAGE
),
382 COUNTABLE(SET2_EVICT6
, UINT64
, AVERAGE
),
383 COUNTABLE(SET2_EVICT7
, UINT64
, AVERAGE
),
384 COUNTABLE(SET2_EVICT8
, UINT64
, AVERAGE
),
385 COUNTABLE(SET3_EVICT1
, UINT64
, AVERAGE
),
386 COUNTABLE(SET3_EVICT2
, UINT64
, AVERAGE
),
387 COUNTABLE(SET3_EVICT3
, UINT64
, AVERAGE
),
388 COUNTABLE(SET3_EVICT4
, UINT64
, AVERAGE
),
389 COUNTABLE(SET3_EVICT5
, UINT64
, AVERAGE
),
390 COUNTABLE(SET3_EVICT6
, UINT64
, AVERAGE
),
391 COUNTABLE(SET3_EVICT7
, UINT64
, AVERAGE
),
392 COUNTABLE(SET3_EVICT8
, UINT64
, AVERAGE
),
393 COUNTABLE(FF_EMPTY
, UINT64
, AVERAGE
),
394 COUNTABLE(FF_LT_HALF_FULL
, UINT64
, AVERAGE
),
395 COUNTABLE(FF_HALF_FULL
, UINT64
, AVERAGE
),
396 COUNTABLE(FF_FULL
, UINT64
, AVERAGE
),
397 COUNTABLE(FF_XFC
, UINT64
, AVERAGE
),
398 COUNTABLE(FF_STALLED
, UINT64
, AVERAGE
),
399 COUNTABLE(FG_MASKS
, UINT64
, AVERAGE
),
400 COUNTABLE(FG_LEFT_MASKS
, UINT64
, AVERAGE
),
401 COUNTABLE(FG_LEFT_MASK_STALLED
, UINT64
, AVERAGE
),
402 COUNTABLE(FG_LEFT_NOT_DONE_STALL
, UINT64
, AVERAGE
),
403 COUNTABLE(FG_LEFT_FG_STALL
, UINT64
, AVERAGE
),
404 COUNTABLE(FG_LEFT_SECTORS
, UINT64
, AVERAGE
),
405 COUNTABLE(FG0_REQUESTS
, UINT64
, AVERAGE
),
406 COUNTABLE(FG0_STALLED
, UINT64
, AVERAGE
),
407 COUNTABLE(MEM_REQ512
, UINT64
, AVERAGE
),
408 COUNTABLE(MEM_REQ_SENT
, UINT64
, AVERAGE
),
409 COUNTABLE(MEM_LOCAL_READ_REQ
, UINT64
, AVERAGE
),
410 COUNTABLE(TC0_MH_STALLED
, UINT64
, AVERAGE
),
413 static const struct fd_perfcntr_countable sq_countables
[] = {
414 COUNTABLE(SQ_PIXEL_VECTORS_SUB
, UINT64
, AVERAGE
),
415 COUNTABLE(SQ_VERTEX_VECTORS_SUB
, UINT64
, AVERAGE
),
416 COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD0
, UINT64
, AVERAGE
),
417 COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD0
, UINT64
, AVERAGE
),
418 COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD0
, UINT64
, AVERAGE
),
419 COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD0
, UINT64
, AVERAGE
),
420 COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD1
, UINT64
, AVERAGE
),
421 COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD1
, UINT64
, AVERAGE
),
422 COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD1
, UINT64
, AVERAGE
),
423 COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD1
, UINT64
, AVERAGE
),
424 COUNTABLE(SQ_EXPORT_CYCLES
, UINT64
, AVERAGE
),
425 COUNTABLE(SQ_ALU_CST_WRITTEN
, UINT64
, AVERAGE
),
426 COUNTABLE(SQ_TEX_CST_WRITTEN
, UINT64
, AVERAGE
),
427 COUNTABLE(SQ_ALU_CST_STALL
, UINT64
, AVERAGE
),
428 COUNTABLE(SQ_ALU_TEX_STALL
, UINT64
, AVERAGE
),
429 COUNTABLE(SQ_INST_WRITTEN
, UINT64
, AVERAGE
),
430 COUNTABLE(SQ_BOOLEAN_WRITTEN
, UINT64
, AVERAGE
),
431 COUNTABLE(SQ_LOOPS_WRITTEN
, UINT64
, AVERAGE
),
432 COUNTABLE(SQ_PIXEL_SWAP_IN
, UINT64
, AVERAGE
),
433 COUNTABLE(SQ_PIXEL_SWAP_OUT
, UINT64
, AVERAGE
),
434 COUNTABLE(SQ_VERTEX_SWAP_IN
, UINT64
, AVERAGE
),
435 COUNTABLE(SQ_VERTEX_SWAP_OUT
, UINT64
, AVERAGE
),
436 COUNTABLE(SQ_ALU_VTX_INST_ISSUED
, UINT64
, AVERAGE
),
437 COUNTABLE(SQ_TEX_VTX_INST_ISSUED
, UINT64
, AVERAGE
),
438 COUNTABLE(SQ_VC_VTX_INST_ISSUED
, UINT64
, AVERAGE
),
439 COUNTABLE(SQ_CF_VTX_INST_ISSUED
, UINT64
, AVERAGE
),
440 COUNTABLE(SQ_ALU_PIX_INST_ISSUED
, UINT64
, AVERAGE
),
441 COUNTABLE(SQ_TEX_PIX_INST_ISSUED
, UINT64
, AVERAGE
),
442 COUNTABLE(SQ_VC_PIX_INST_ISSUED
, UINT64
, AVERAGE
),
443 COUNTABLE(SQ_CF_PIX_INST_ISSUED
, UINT64
, AVERAGE
),
444 COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD0
, UINT64
, AVERAGE
),
445 COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD0
, UINT64
, AVERAGE
),
446 COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD1
, UINT64
, AVERAGE
),
447 COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD1
, UINT64
, AVERAGE
),
448 COUNTABLE(SQ_ALU_NOPS
, UINT64
, AVERAGE
),
449 COUNTABLE(SQ_PRED_SKIP
, UINT64
, AVERAGE
),
450 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD0_VTX
, UINT64
, AVERAGE
),
451 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD1_VTX
, UINT64
, AVERAGE
),
452 COUNTABLE(SQ_SYNC_TEX_STALL_VTX
, UINT64
, AVERAGE
),
453 COUNTABLE(SQ_SYNC_VC_STALL_VTX
, UINT64
, AVERAGE
),
454 COUNTABLE(SQ_CONSTANTS_USED_SIMD0
, UINT64
, AVERAGE
),
455 COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD0
, UINT64
, AVERAGE
),
456 COUNTABLE(SQ_GPR_STALL_VTX
, UINT64
, AVERAGE
),
457 COUNTABLE(SQ_GPR_STALL_PIX
, UINT64
, AVERAGE
),
458 COUNTABLE(SQ_VTX_RS_STALL
, UINT64
, AVERAGE
),
459 COUNTABLE(SQ_PIX_RS_STALL
, UINT64
, AVERAGE
),
460 COUNTABLE(SQ_SX_PC_FULL
, UINT64
, AVERAGE
),
461 COUNTABLE(SQ_SX_EXP_BUFF_FULL
, UINT64
, AVERAGE
),
462 COUNTABLE(SQ_SX_POS_BUFF_FULL
, UINT64
, AVERAGE
),
463 COUNTABLE(SQ_INTERP_QUADS
, UINT64
, AVERAGE
),
464 COUNTABLE(SQ_INTERP_ACTIVE
, UINT64
, AVERAGE
),
465 COUNTABLE(SQ_IN_PIXEL_STALL
, UINT64
, AVERAGE
),
466 COUNTABLE(SQ_IN_VTX_STALL
, UINT64
, AVERAGE
),
467 COUNTABLE(SQ_VTX_CNT
, UINT64
, AVERAGE
),
468 COUNTABLE(SQ_VTX_VECTOR2
, UINT64
, AVERAGE
),
469 COUNTABLE(SQ_VTX_VECTOR3
, UINT64
, AVERAGE
),
470 COUNTABLE(SQ_VTX_VECTOR4
, UINT64
, AVERAGE
),
471 COUNTABLE(SQ_PIXEL_VECTOR1
, UINT64
, AVERAGE
),
472 COUNTABLE(SQ_PIXEL_VECTOR23
, UINT64
, AVERAGE
),
473 COUNTABLE(SQ_PIXEL_VECTOR4
, UINT64
, AVERAGE
),
474 COUNTABLE(SQ_CONSTANTS_USED_SIMD1
, UINT64
, AVERAGE
),
475 COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD1
, UINT64
, AVERAGE
),
476 COUNTABLE(SQ_SX_MEM_EXP_FULL
, UINT64
, AVERAGE
),
477 COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD2
, UINT64
, AVERAGE
),
478 COUNTABLE(SQ_ALU1_ACTIVE_VTX_SIMD2
, UINT64
, AVERAGE
),
479 COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD2
, UINT64
, AVERAGE
),
480 COUNTABLE(SQ_ALU1_ACTIVE_PIX_SIMD2
, UINT64
, AVERAGE
),
481 COUNTABLE(SQ_ALU0_ACTIVE_VTX_SIMD3
, UINT64
, AVERAGE
),
482 COUNTABLE(SQ_PERFCOUNT_VTX_QUAL_TP_DONE
, UINT64
, AVERAGE
),
483 COUNTABLE(SQ_ALU0_ACTIVE_PIX_SIMD3
, UINT64
, AVERAGE
),
484 COUNTABLE(SQ_PERFCOUNT_PIX_QUAL_TP_DONE
, UINT64
, AVERAGE
),
485 COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD2
, UINT64
, AVERAGE
),
486 COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD2
, UINT64
, AVERAGE
),
487 COUNTABLE(SQ_ALU0_FIFO_EMPTY_SIMD3
, UINT64
, AVERAGE
),
488 COUNTABLE(SQ_ALU1_FIFO_EMPTY_SIMD3
, UINT64
, AVERAGE
),
489 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD2_VTX
, UINT64
, AVERAGE
),
490 COUNTABLE(SQ_PERFCOUNT_VTX_POP_THREAD
, UINT64
, AVERAGE
),
491 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD0_PIX
, UINT64
, AVERAGE
),
492 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD1_PIX
, UINT64
, AVERAGE
),
493 COUNTABLE(SQ_SYNC_ALU_STALL_SIMD2_PIX
, UINT64
, AVERAGE
),
494 COUNTABLE(SQ_PERFCOUNT_PIX_POP_THREAD
, UINT64
, AVERAGE
),
495 COUNTABLE(SQ_SYNC_TEX_STALL_PIX
, UINT64
, AVERAGE
),
496 COUNTABLE(SQ_SYNC_VC_STALL_PIX
, UINT64
, AVERAGE
),
497 COUNTABLE(SQ_CONSTANTS_USED_SIMD2
, UINT64
, AVERAGE
),
498 COUNTABLE(SQ_CONSTANTS_SENT_SP_SIMD2
, UINT64
, AVERAGE
),
499 COUNTABLE(SQ_PERFCOUNT_VTX_DEALLOC_ACK
, UINT64
, AVERAGE
),
500 COUNTABLE(SQ_PERFCOUNT_PIX_DEALLOC_ACK
, UINT64
, AVERAGE
),
501 COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD0
, UINT64
, AVERAGE
),
502 COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD0
, UINT64
, AVERAGE
),
503 COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD1
, UINT64
, AVERAGE
),
504 COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD1
, UINT64
, AVERAGE
),
505 COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD2
, UINT64
, AVERAGE
),
506 COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD2
, UINT64
, AVERAGE
),
507 COUNTABLE(SQ_ALU0_FIFO_FULL_SIMD3
, UINT64
, AVERAGE
),
508 COUNTABLE(SQ_ALU1_FIFO_FULL_SIMD3
, UINT64
, AVERAGE
),
509 COUNTABLE(VC_PERF_STATIC
, UINT64
, AVERAGE
),
510 COUNTABLE(VC_PERF_STALLED
, UINT64
, AVERAGE
),
511 COUNTABLE(VC_PERF_STARVED
, UINT64
, AVERAGE
),
512 COUNTABLE(VC_PERF_SEND
, UINT64
, AVERAGE
),
513 COUNTABLE(VC_PERF_ACTUAL_STARVED
, UINT64
, AVERAGE
),
514 COUNTABLE(PIXEL_THREAD_0_ACTIVE
, UINT64
, AVERAGE
),
515 COUNTABLE(VERTEX_THREAD_0_ACTIVE
, UINT64
, AVERAGE
),
516 COUNTABLE(PIXEL_THREAD_0_NUMBER
, UINT64
, AVERAGE
),
517 COUNTABLE(VERTEX_THREAD_0_NUMBER
, UINT64
, AVERAGE
),
518 COUNTABLE(VERTEX_EVENT_NUMBER
, UINT64
, AVERAGE
),
519 COUNTABLE(PIXEL_EVENT_NUMBER
, UINT64
, AVERAGE
),
520 COUNTABLE(PTRBUFF_EF_PUSH
, UINT64
, AVERAGE
),
521 COUNTABLE(PTRBUFF_EF_POP_EVENT
, UINT64
, AVERAGE
),
522 COUNTABLE(PTRBUFF_EF_POP_NEW_VTX
, UINT64
, AVERAGE
),
523 COUNTABLE(PTRBUFF_EF_POP_DEALLOC
, UINT64
, AVERAGE
),
524 COUNTABLE(PTRBUFF_EF_POP_PVECTOR
, UINT64
, AVERAGE
),
525 COUNTABLE(PTRBUFF_EF_POP_PVECTOR_X
, UINT64
, AVERAGE
),
526 COUNTABLE(PTRBUFF_EF_POP_PVECTOR_VNZ
, UINT64
, AVERAGE
),
527 COUNTABLE(PTRBUFF_PB_DEALLOC
, UINT64
, AVERAGE
),
528 COUNTABLE(PTRBUFF_PI_STATE_PPB_POP
, UINT64
, AVERAGE
),
529 COUNTABLE(PTRBUFF_PI_RTR
, UINT64
, AVERAGE
),
530 COUNTABLE(PTRBUFF_PI_READ_EN
, UINT64
, AVERAGE
),
531 COUNTABLE(PTRBUFF_PI_BUFF_SWAP
, UINT64
, AVERAGE
),
532 COUNTABLE(PTRBUFF_SQ_FREE_BUFF
, UINT64
, AVERAGE
),
533 COUNTABLE(PTRBUFF_SQ_DEC
, UINT64
, AVERAGE
),
534 COUNTABLE(PTRBUFF_SC_VALID_CNTL_EVENT
, UINT64
, AVERAGE
),
535 COUNTABLE(PTRBUFF_SC_VALID_IJ_XFER
, UINT64
, AVERAGE
),
536 COUNTABLE(PTRBUFF_SC_NEW_VECTOR_1_Q
, UINT64
, AVERAGE
),
537 COUNTABLE(PTRBUFF_QUAL_NEW_VECTOR
, UINT64
, AVERAGE
),
538 COUNTABLE(PTRBUFF_QUAL_EVENT
, UINT64
, AVERAGE
),
539 COUNTABLE(PTRBUFF_END_BUFFER
, UINT64
, AVERAGE
),
540 COUNTABLE(PTRBUFF_FILL_QUAD
, UINT64
, AVERAGE
),
541 COUNTABLE(VERTS_WRITTEN_SPI
, UINT64
, AVERAGE
),
542 COUNTABLE(TP_FETCH_INSTR_EXEC
, UINT64
, AVERAGE
),
543 COUNTABLE(TP_FETCH_INSTR_REQ
, UINT64
, AVERAGE
),
544 COUNTABLE(TP_DATA_RETURN
, UINT64
, AVERAGE
),
545 COUNTABLE(SPI_WRITE_CYCLES_SP
, UINT64
, AVERAGE
),
546 COUNTABLE(SPI_WRITES_SP
, UINT64
, AVERAGE
),
547 COUNTABLE(SP_ALU_INSTR_EXEC
, UINT64
, AVERAGE
),
548 COUNTABLE(SP_CONST_ADDR_TO_SQ
, UINT64
, AVERAGE
),
549 COUNTABLE(SP_PRED_KILLS_TO_SQ
, UINT64
, AVERAGE
),
550 COUNTABLE(SP_EXPORT_CYCLES_TO_SX
, UINT64
, AVERAGE
),
551 COUNTABLE(SP_EXPORTS_TO_SX
, UINT64
, AVERAGE
),
552 COUNTABLE(SQ_CYCLES_ELAPSED
, UINT64
, AVERAGE
),
553 COUNTABLE(SQ_TCFS_OPT_ALLOC_EXEC
, UINT64
, AVERAGE
),
554 COUNTABLE(SQ_TCFS_NO_OPT_ALLOC
, UINT64
, AVERAGE
),
555 COUNTABLE(SQ_ALU0_NO_OPT_ALLOC
, UINT64
, AVERAGE
),
556 COUNTABLE(SQ_ALU1_NO_OPT_ALLOC
, UINT64
, AVERAGE
),
557 COUNTABLE(SQ_TCFS_ARB_XFC_CNT
, UINT64
, AVERAGE
),
558 COUNTABLE(SQ_ALU0_ARB_XFC_CNT
, UINT64
, AVERAGE
),
559 COUNTABLE(SQ_ALU1_ARB_XFC_CNT
, UINT64
, AVERAGE
),
560 COUNTABLE(SQ_TCFS_CFS_UPDATE_CNT
, UINT64
, AVERAGE
),
561 COUNTABLE(SQ_ALU0_CFS_UPDATE_CNT
, UINT64
, AVERAGE
),
562 COUNTABLE(SQ_ALU1_CFS_UPDATE_CNT
, UINT64
, AVERAGE
),
563 COUNTABLE(SQ_VTX_PUSH_THREAD_CNT
, UINT64
, AVERAGE
),
564 COUNTABLE(SQ_VTX_POP_THREAD_CNT
, UINT64
, AVERAGE
),
565 COUNTABLE(SQ_PIX_PUSH_THREAD_CNT
, UINT64
, AVERAGE
),
566 COUNTABLE(SQ_PIX_POP_THREAD_CNT
, UINT64
, AVERAGE
),
567 COUNTABLE(SQ_PIX_TOTAL
, UINT64
, AVERAGE
),
568 COUNTABLE(SQ_PIX_KILLED
, UINT64
, AVERAGE
),
571 static const struct fd_perfcntr_countable sx_countables
[] = {
572 COUNTABLE(SX_EXPORT_VECTORS
, UINT64
, AVERAGE
),
573 COUNTABLE(SX_DUMMY_QUADS
, UINT64
, AVERAGE
),
574 COUNTABLE(SX_ALPHA_FAIL
, UINT64
, AVERAGE
),
575 COUNTABLE(SX_RB_QUAD_BUSY
, UINT64
, AVERAGE
),
576 COUNTABLE(SX_RB_COLOR_BUSY
, UINT64
, AVERAGE
),
577 COUNTABLE(SX_RB_QUAD_STALL
, UINT64
, AVERAGE
),
578 COUNTABLE(SX_RB_COLOR_STALL
, UINT64
, AVERAGE
),
581 static const struct fd_perfcntr_countable mh_countables
[] = {
582 COUNTABLE(CP_R0_REQUESTS
, UINT64
, AVERAGE
),
583 COUNTABLE(CP_R1_REQUESTS
, UINT64
, AVERAGE
),
584 COUNTABLE(CP_R2_REQUESTS
, UINT64
, AVERAGE
),
585 COUNTABLE(CP_R3_REQUESTS
, UINT64
, AVERAGE
),
586 COUNTABLE(CP_R4_REQUESTS
, UINT64
, AVERAGE
),
587 COUNTABLE(CP_TOTAL_READ_REQUESTS
, UINT64
, AVERAGE
),
588 COUNTABLE(CP_TOTAL_WRITE_REQUESTS
, UINT64
, AVERAGE
),
589 COUNTABLE(CP_TOTAL_REQUESTS
, UINT64
, AVERAGE
),
590 COUNTABLE(CP_DATA_BYTES_WRITTEN
, UINT64
, AVERAGE
),
591 COUNTABLE(CP_WRITE_CLEAN_RESPONSES
, UINT64
, AVERAGE
),
592 COUNTABLE(CP_R0_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
593 COUNTABLE(CP_R1_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
594 COUNTABLE(CP_R2_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
595 COUNTABLE(CP_R3_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
596 COUNTABLE(CP_R4_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
597 COUNTABLE(CP_TOTAL_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
598 COUNTABLE(CP_R0_DATA_BEATS_READ
, UINT64
, AVERAGE
),
599 COUNTABLE(CP_R1_DATA_BEATS_READ
, UINT64
, AVERAGE
),
600 COUNTABLE(CP_R2_DATA_BEATS_READ
, UINT64
, AVERAGE
),
601 COUNTABLE(CP_R3_DATA_BEATS_READ
, UINT64
, AVERAGE
),
602 COUNTABLE(CP_R4_DATA_BEATS_READ
, UINT64
, AVERAGE
),
603 COUNTABLE(CP_TOTAL_DATA_BEATS_READ
, UINT64
, AVERAGE
),
604 COUNTABLE(VGT_R0_REQUESTS
, UINT64
, AVERAGE
),
605 COUNTABLE(VGT_R1_REQUESTS
, UINT64
, AVERAGE
),
606 COUNTABLE(VGT_TOTAL_REQUESTS
, UINT64
, AVERAGE
),
607 COUNTABLE(VGT_R0_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
608 COUNTABLE(VGT_R1_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
609 COUNTABLE(VGT_TOTAL_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
610 COUNTABLE(VGT_R0_DATA_BEATS_READ
, UINT64
, AVERAGE
),
611 COUNTABLE(VGT_R1_DATA_BEATS_READ
, UINT64
, AVERAGE
),
612 COUNTABLE(VGT_TOTAL_DATA_BEATS_READ
, UINT64
, AVERAGE
),
613 COUNTABLE(TC_TOTAL_REQUESTS
, UINT64
, AVERAGE
),
614 COUNTABLE(TC_ROQ_REQUESTS
, UINT64
, AVERAGE
),
615 COUNTABLE(TC_INFO_SENT
, UINT64
, AVERAGE
),
616 COUNTABLE(TC_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
617 COUNTABLE(TC_DATA_BEATS_READ
, UINT64
, AVERAGE
),
618 COUNTABLE(TCD_BURSTS_READ
, UINT64
, AVERAGE
),
619 COUNTABLE(RB_REQUESTS
, UINT64
, AVERAGE
),
620 COUNTABLE(RB_DATA_BYTES_WRITTEN
, UINT64
, AVERAGE
),
621 COUNTABLE(RB_WRITE_CLEAN_RESPONSES
, UINT64
, AVERAGE
),
622 COUNTABLE(AXI_READ_REQUESTS_ID_0
, UINT64
, AVERAGE
),
623 COUNTABLE(AXI_READ_REQUESTS_ID_1
, UINT64
, AVERAGE
),
624 COUNTABLE(AXI_READ_REQUESTS_ID_2
, UINT64
, AVERAGE
),
625 COUNTABLE(AXI_READ_REQUESTS_ID_3
, UINT64
, AVERAGE
),
626 COUNTABLE(AXI_READ_REQUESTS_ID_4
, UINT64
, AVERAGE
),
627 COUNTABLE(AXI_READ_REQUESTS_ID_5
, UINT64
, AVERAGE
),
628 COUNTABLE(AXI_READ_REQUESTS_ID_6
, UINT64
, AVERAGE
),
629 COUNTABLE(AXI_READ_REQUESTS_ID_7
, UINT64
, AVERAGE
),
630 COUNTABLE(AXI_TOTAL_READ_REQUESTS
, UINT64
, AVERAGE
),
631 COUNTABLE(AXI_WRITE_REQUESTS_ID_0
, UINT64
, AVERAGE
),
632 COUNTABLE(AXI_WRITE_REQUESTS_ID_1
, UINT64
, AVERAGE
),
633 COUNTABLE(AXI_WRITE_REQUESTS_ID_2
, UINT64
, AVERAGE
),
634 COUNTABLE(AXI_WRITE_REQUESTS_ID_3
, UINT64
, AVERAGE
),
635 COUNTABLE(AXI_WRITE_REQUESTS_ID_4
, UINT64
, AVERAGE
),
636 COUNTABLE(AXI_WRITE_REQUESTS_ID_5
, UINT64
, AVERAGE
),
637 COUNTABLE(AXI_WRITE_REQUESTS_ID_6
, UINT64
, AVERAGE
),
638 COUNTABLE(AXI_WRITE_REQUESTS_ID_7
, UINT64
, AVERAGE
),
639 COUNTABLE(AXI_TOTAL_WRITE_REQUESTS
, UINT64
, AVERAGE
),
640 COUNTABLE(AXI_TOTAL_REQUESTS_ID_0
, UINT64
, AVERAGE
),
641 COUNTABLE(AXI_TOTAL_REQUESTS_ID_1
, UINT64
, AVERAGE
),
642 COUNTABLE(AXI_TOTAL_REQUESTS_ID_2
, UINT64
, AVERAGE
),
643 COUNTABLE(AXI_TOTAL_REQUESTS_ID_3
, UINT64
, AVERAGE
),
644 COUNTABLE(AXI_TOTAL_REQUESTS_ID_4
, UINT64
, AVERAGE
),
645 COUNTABLE(AXI_TOTAL_REQUESTS_ID_5
, UINT64
, AVERAGE
),
646 COUNTABLE(AXI_TOTAL_REQUESTS_ID_6
, UINT64
, AVERAGE
),
647 COUNTABLE(AXI_TOTAL_REQUESTS_ID_7
, UINT64
, AVERAGE
),
648 COUNTABLE(AXI_TOTAL_REQUESTS
, UINT64
, AVERAGE
),
649 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_0
, UINT64
, AVERAGE
),
650 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_1
, UINT64
, AVERAGE
),
651 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_2
, UINT64
, AVERAGE
),
652 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_3
, UINT64
, AVERAGE
),
653 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_4
, UINT64
, AVERAGE
),
654 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_5
, UINT64
, AVERAGE
),
655 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_6
, UINT64
, AVERAGE
),
656 COUNTABLE(AXI_READ_CHANNEL_BURSTS_ID_7
, UINT64
, AVERAGE
),
657 COUNTABLE(AXI_READ_CHANNEL_TOTAL_BURSTS
, UINT64
, AVERAGE
),
658 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0
, UINT64
, AVERAGE
),
659 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1
, UINT64
, AVERAGE
),
660 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2
, UINT64
, AVERAGE
),
661 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3
, UINT64
, AVERAGE
),
662 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4
, UINT64
, AVERAGE
),
663 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5
, UINT64
, AVERAGE
),
664 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6
, UINT64
, AVERAGE
),
665 COUNTABLE(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7
, UINT64
, AVERAGE
),
666 COUNTABLE(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ
, UINT64
, AVERAGE
),
667 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_0
, UINT64
, AVERAGE
),
668 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_1
, UINT64
, AVERAGE
),
669 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_2
, UINT64
, AVERAGE
),
670 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_3
, UINT64
, AVERAGE
),
671 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_4
, UINT64
, AVERAGE
),
672 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_5
, UINT64
, AVERAGE
),
673 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_6
, UINT64
, AVERAGE
),
674 COUNTABLE(AXI_WRITE_CHANNEL_BURSTS_ID_7
, UINT64
, AVERAGE
),
675 COUNTABLE(AXI_WRITE_CHANNEL_TOTAL_BURSTS
, UINT64
, AVERAGE
),
676 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0
, UINT64
, AVERAGE
),
677 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1
, UINT64
, AVERAGE
),
678 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2
, UINT64
, AVERAGE
),
679 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3
, UINT64
, AVERAGE
),
680 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4
, UINT64
, AVERAGE
),
681 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5
, UINT64
, AVERAGE
),
682 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6
, UINT64
, AVERAGE
),
683 COUNTABLE(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7
, UINT64
, AVERAGE
),
684 COUNTABLE(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN
, UINT64
, AVERAGE
),
685 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0
, UINT64
, AVERAGE
),
686 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1
, UINT64
, AVERAGE
),
687 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2
, UINT64
, AVERAGE
),
688 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3
, UINT64
, AVERAGE
),
689 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4
, UINT64
, AVERAGE
),
690 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5
, UINT64
, AVERAGE
),
691 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6
, UINT64
, AVERAGE
),
692 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7
, UINT64
, AVERAGE
),
693 COUNTABLE(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES
, UINT64
, AVERAGE
),
694 COUNTABLE(TOTAL_MMU_MISSES
, UINT64
, AVERAGE
),
695 COUNTABLE(MMU_READ_MISSES
, UINT64
, AVERAGE
),
696 COUNTABLE(MMU_WRITE_MISSES
, UINT64
, AVERAGE
),
697 COUNTABLE(TOTAL_MMU_HITS
, UINT64
, AVERAGE
),
698 COUNTABLE(MMU_READ_HITS
, UINT64
, AVERAGE
),
699 COUNTABLE(MMU_WRITE_HITS
, UINT64
, AVERAGE
),
700 COUNTABLE(SPLIT_MODE_TC_HITS
, UINT64
, AVERAGE
),
701 COUNTABLE(SPLIT_MODE_TC_MISSES
, UINT64
, AVERAGE
),
702 COUNTABLE(SPLIT_MODE_NON_TC_HITS
, UINT64
, AVERAGE
),
703 COUNTABLE(SPLIT_MODE_NON_TC_MISSES
, UINT64
, AVERAGE
),
704 COUNTABLE(STALL_AWAITING_TLB_MISS_FETCH
, UINT64
, AVERAGE
),
705 COUNTABLE(MMU_TLB_MISS_READ_BURSTS_RECEIVED
, UINT64
, AVERAGE
),
706 COUNTABLE(MMU_TLB_MISS_DATA_BEATS_READ
, UINT64
, AVERAGE
),
707 COUNTABLE(CP_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
708 COUNTABLE(VGT_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
709 COUNTABLE(TC_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
710 COUNTABLE(TC_ROQ_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
711 COUNTABLE(TC_CYCLES_HELD_OFF_TCD_FULL
, UINT64
, AVERAGE
),
712 COUNTABLE(RB_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
713 COUNTABLE(TOTAL_CYCLES_ANY_CLNT_HELD_OFF
, UINT64
, AVERAGE
),
714 COUNTABLE(TLB_MISS_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
715 COUNTABLE(AXI_READ_REQUEST_HELD_OFF
, UINT64
, AVERAGE
),
716 COUNTABLE(AXI_WRITE_REQUEST_HELD_OFF
, UINT64
, AVERAGE
),
717 COUNTABLE(AXI_REQUEST_HELD_OFF
, UINT64
, AVERAGE
),
718 COUNTABLE(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT
, UINT64
, AVERAGE
),
719 COUNTABLE(AXI_WRITE_DATA_HELD_OFF
, UINT64
, AVERAGE
),
720 COUNTABLE(CP_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
721 COUNTABLE(VGT_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
722 COUNTABLE(TC_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
723 COUNTABLE(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
724 COUNTABLE(RB_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
725 COUNTABLE(TOTAL_SAME_PAGE_BANK_REQUESTS
, UINT64
, AVERAGE
),
726 COUNTABLE(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT
, UINT64
, AVERAGE
),
727 COUNTABLE(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT
, UINT64
, AVERAGE
),
728 COUNTABLE(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT
, UINT64
, AVERAGE
),
729 COUNTABLE(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT
, UINT64
, AVERAGE
),
730 COUNTABLE(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT
, UINT64
, AVERAGE
),
731 COUNTABLE(TOTAL_MH_READ_REQUESTS
, UINT64
, AVERAGE
),
732 COUNTABLE(TOTAL_MH_WRITE_REQUESTS
, UINT64
, AVERAGE
),
733 COUNTABLE(TOTAL_MH_REQUESTS
, UINT64
, AVERAGE
),
734 COUNTABLE(MH_BUSY
, UINT64
, AVERAGE
),
735 COUNTABLE(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE
, UINT64
, AVERAGE
),
736 COUNTABLE(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE
, UINT64
, AVERAGE
),
737 COUNTABLE(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE
, UINT64
, AVERAGE
),
738 COUNTABLE(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE
, UINT64
, AVERAGE
),
739 COUNTABLE(TC_ROQ_N_VALID_ENTRIES
, UINT64
, AVERAGE
),
740 COUNTABLE(ARQ_N_ENTRIES
, UINT64
, AVERAGE
),
741 COUNTABLE(WDB_N_ENTRIES
, UINT64
, AVERAGE
),
742 COUNTABLE(MH_READ_LATENCY_OUTST_REQ_SUM
, UINT64
, AVERAGE
),
743 COUNTABLE(MC_READ_LATENCY_OUTST_REQ_SUM
, UINT64
, AVERAGE
),
744 COUNTABLE(MC_TOTAL_READ_REQUESTS
, UINT64
, AVERAGE
),
745 COUNTABLE(ELAPSED_CYCLES_MH_GATED_CLK
, UINT64
, AVERAGE
),
746 COUNTABLE(ELAPSED_CLK_CYCLES
, UINT64
, AVERAGE
),
747 COUNTABLE(CP_W_16B_REQUESTS
, UINT64
, AVERAGE
),
748 COUNTABLE(CP_W_32B_REQUESTS
, UINT64
, AVERAGE
),
749 COUNTABLE(TC_16B_REQUESTS
, UINT64
, AVERAGE
),
750 COUNTABLE(TC_32B_REQUESTS
, UINT64
, AVERAGE
),
751 COUNTABLE(PA_REQUESTS
, UINT64
, AVERAGE
),
752 COUNTABLE(PA_DATA_BYTES_WRITTEN
, UINT64
, AVERAGE
),
753 COUNTABLE(PA_WRITE_CLEAN_RESPONSES
, UINT64
, AVERAGE
),
754 COUNTABLE(PA_CYCLES_HELD_OFF
, UINT64
, AVERAGE
),
755 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_0
, UINT64
, AVERAGE
),
756 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_1
, UINT64
, AVERAGE
),
757 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_2
, UINT64
, AVERAGE
),
758 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_3
, UINT64
, AVERAGE
),
759 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_4
, UINT64
, AVERAGE
),
760 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_5
, UINT64
, AVERAGE
),
761 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_6
, UINT64
, AVERAGE
),
762 COUNTABLE(AXI_READ_REQUEST_DATA_BEATS_ID_7
, UINT64
, AVERAGE
),
763 COUNTABLE(AXI_TOTAL_READ_REQUEST_DATA_BEATS
, UINT64
, AVERAGE
),
766 static const struct fd_perfcntr_countable rb_countables
[] = {
767 COUNTABLE(RBPERF_CNTX_BUSY
, UINT64
, AVERAGE
),
768 COUNTABLE(RBPERF_CNTX_BUSY_MAX
, UINT64
, AVERAGE
),
769 COUNTABLE(RBPERF_SX_QUAD_STARVED
, UINT64
, AVERAGE
),
770 COUNTABLE(RBPERF_SX_QUAD_STARVED_MAX
, UINT64
, AVERAGE
),
771 COUNTABLE(RBPERF_GA_GC_CH0_SYS_REQ
, UINT64
, AVERAGE
),
772 COUNTABLE(RBPERF_GA_GC_CH0_SYS_REQ_MAX
, UINT64
, AVERAGE
),
773 COUNTABLE(RBPERF_GA_GC_CH1_SYS_REQ
, UINT64
, AVERAGE
),
774 COUNTABLE(RBPERF_GA_GC_CH1_SYS_REQ_MAX
, UINT64
, AVERAGE
),
775 COUNTABLE(RBPERF_MH_STARVED
, UINT64
, AVERAGE
),
776 COUNTABLE(RBPERF_MH_STARVED_MAX
, UINT64
, AVERAGE
),
777 COUNTABLE(RBPERF_AZ_BC_COLOR_BUSY
, UINT64
, AVERAGE
),
778 COUNTABLE(RBPERF_AZ_BC_COLOR_BUSY_MAX
, UINT64
, AVERAGE
),
779 COUNTABLE(RBPERF_AZ_BC_Z_BUSY
, UINT64
, AVERAGE
),
780 COUNTABLE(RBPERF_AZ_BC_Z_BUSY_MAX
, UINT64
, AVERAGE
),
781 COUNTABLE(RBPERF_RB_SC_TILE_RTR_N
, UINT64
, AVERAGE
),
782 COUNTABLE(RBPERF_RB_SC_TILE_RTR_N_MAX
, UINT64
, AVERAGE
),
783 COUNTABLE(RBPERF_RB_SC_SAMP_RTR_N
, UINT64
, AVERAGE
),
784 COUNTABLE(RBPERF_RB_SC_SAMP_RTR_N_MAX
, UINT64
, AVERAGE
),
785 COUNTABLE(RBPERF_RB_SX_QUAD_RTR_N
, UINT64
, AVERAGE
),
786 COUNTABLE(RBPERF_RB_SX_QUAD_RTR_N_MAX
, UINT64
, AVERAGE
),
787 COUNTABLE(RBPERF_RB_SX_COLOR_RTR_N
, UINT64
, AVERAGE
),
788 COUNTABLE(RBPERF_RB_SX_COLOR_RTR_N_MAX
, UINT64
, AVERAGE
),
789 COUNTABLE(RBPERF_RB_SC_SAMP_LZ_BUSY
, UINT64
, AVERAGE
),
790 COUNTABLE(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX
, UINT64
, AVERAGE
),
791 COUNTABLE(RBPERF_ZXP_STALL
, UINT64
, AVERAGE
),
792 COUNTABLE(RBPERF_ZXP_STALL_MAX
, UINT64
, AVERAGE
),
793 COUNTABLE(RBPERF_EVENT_PENDING
, UINT64
, AVERAGE
),
794 COUNTABLE(RBPERF_EVENT_PENDING_MAX
, UINT64
, AVERAGE
),
795 COUNTABLE(RBPERF_RB_MH_VALID
, UINT64
, AVERAGE
),
796 COUNTABLE(RBPERF_RB_MH_VALID_MAX
, UINT64
, AVERAGE
),
797 COUNTABLE(RBPERF_SX_RB_QUAD_SEND
, UINT64
, AVERAGE
),
798 COUNTABLE(RBPERF_SX_RB_COLOR_SEND
, UINT64
, AVERAGE
),
799 COUNTABLE(RBPERF_SC_RB_TILE_SEND
, UINT64
, AVERAGE
),
800 COUNTABLE(RBPERF_SC_RB_SAMPLE_SEND
, UINT64
, AVERAGE
),
801 COUNTABLE(RBPERF_SX_RB_MEM_EXPORT
, UINT64
, AVERAGE
),
802 COUNTABLE(RBPERF_SX_RB_QUAD_EVENT
, UINT64
, AVERAGE
),
803 COUNTABLE(RBPERF_SC_RB_TILE_EVENT_FILTERED
, UINT64
, AVERAGE
),
804 COUNTABLE(RBPERF_SC_RB_TILE_EVENT_ALL
, UINT64
, AVERAGE
),
805 COUNTABLE(RBPERF_RB_SC_EZ_SEND
, UINT64
, AVERAGE
),
806 COUNTABLE(RBPERF_RB_SX_INDEX_SEND
, UINT64
, AVERAGE
),
807 COUNTABLE(RBPERF_GMEM_INTFO_RD
, UINT64
, AVERAGE
),
808 COUNTABLE(RBPERF_GMEM_INTF1_RD
, UINT64
, AVERAGE
),
809 COUNTABLE(RBPERF_GMEM_INTFO_WR
, UINT64
, AVERAGE
),
810 COUNTABLE(RBPERF_GMEM_INTF1_WR
, UINT64
, AVERAGE
),
811 COUNTABLE(RBPERF_RB_CP_CONTEXT_DONE
, UINT64
, AVERAGE
),
812 COUNTABLE(RBPERF_RB_CP_CACHE_FLUSH
, UINT64
, AVERAGE
),
813 COUNTABLE(RBPERF_ZPASS_DONE
, UINT64
, AVERAGE
),
814 COUNTABLE(RBPERF_ZCMD_VALID
, UINT64
, AVERAGE
),
815 COUNTABLE(RBPERF_CCMD_VALID
, UINT64
, AVERAGE
),
816 COUNTABLE(RBPERF_ACCUM_GRANT
, UINT64
, AVERAGE
),
817 COUNTABLE(RBPERF_ACCUM_C0_GRANT
, UINT64
, AVERAGE
),
818 COUNTABLE(RBPERF_ACCUM_C1_GRANT
, UINT64
, AVERAGE
),
819 COUNTABLE(RBPERF_ACCUM_FULL_BE_WR
, UINT64
, AVERAGE
),
820 COUNTABLE(RBPERF_ACCUM_REQUEST_NO_GRANT
, UINT64
, AVERAGE
),
821 COUNTABLE(RBPERF_ACCUM_TIMEOUT_PULSE
, UINT64
, AVERAGE
),
822 COUNTABLE(RBPERF_ACCUM_LIN_TIMEOUT_PULSE
, UINT64
, AVERAGE
),
823 COUNTABLE(RBPERF_ACCUM_CAM_HIT_FLUSHING
, UINT64
, AVERAGE
),
826 static const struct fd_perfcntr_counter pa_su_counters
[] = {
827 COUNTER(PA_SU_PERFCOUNTER0_SELECT
, PA_SU_PERFCOUNTER0_LOW
, PA_SU_PERFCOUNTER0_HI
),
828 COUNTER(PA_SU_PERFCOUNTER1_SELECT
, PA_SU_PERFCOUNTER1_LOW
, PA_SU_PERFCOUNTER1_HI
),
829 COUNTER(PA_SU_PERFCOUNTER2_SELECT
, PA_SU_PERFCOUNTER2_LOW
, PA_SU_PERFCOUNTER2_HI
),
830 COUNTER(PA_SU_PERFCOUNTER3_SELECT
, PA_SU_PERFCOUNTER3_LOW
, PA_SU_PERFCOUNTER3_HI
),
833 static const struct fd_perfcntr_counter pa_sc_counters
[] = {
834 COUNTER(PA_SC_PERFCOUNTER0_SELECT
, PA_SC_PERFCOUNTER0_LOW
, PA_SC_PERFCOUNTER0_HI
),
837 static const struct fd_perfcntr_counter vgt_counters
[] = {
838 COUNTER(VGT_PERFCOUNTER0_SELECT
, VGT_PERFCOUNTER0_LOW
, VGT_PERFCOUNTER0_HI
),
839 COUNTER(VGT_PERFCOUNTER1_SELECT
, VGT_PERFCOUNTER1_LOW
, VGT_PERFCOUNTER1_HI
),
840 COUNTER(VGT_PERFCOUNTER2_SELECT
, VGT_PERFCOUNTER2_LOW
, VGT_PERFCOUNTER2_HI
),
841 COUNTER(VGT_PERFCOUNTER3_SELECT
, VGT_PERFCOUNTER3_LOW
, VGT_PERFCOUNTER3_HI
),
844 static const struct fd_perfcntr_counter tcr_counters
[] = {
845 COUNTER(TCR_PERFCOUNTER0_SELECT
, TCR_PERFCOUNTER0_LOW
, TCR_PERFCOUNTER0_HI
),
846 COUNTER(TCR_PERFCOUNTER1_SELECT
, TCR_PERFCOUNTER1_LOW
, TCR_PERFCOUNTER1_HI
),
849 static const struct fd_perfcntr_counter tp0_counters
[] = {
850 COUNTER(TP0_PERFCOUNTER0_SELECT
, TP0_PERFCOUNTER0_LOW
, TP0_PERFCOUNTER0_HI
),
851 COUNTER(TP0_PERFCOUNTER1_SELECT
, TP0_PERFCOUNTER1_LOW
, TP0_PERFCOUNTER1_HI
),
854 static const struct fd_perfcntr_counter tcm_counters
[] = {
855 COUNTER(TCM_PERFCOUNTER0_SELECT
, TCM_PERFCOUNTER0_LOW
, TCM_PERFCOUNTER0_HI
),
856 COUNTER(TCM_PERFCOUNTER1_SELECT
, TCM_PERFCOUNTER1_LOW
, TCM_PERFCOUNTER1_HI
),
859 static const struct fd_perfcntr_counter tcf_counters
[] = {
860 COUNTER(TCF_PERFCOUNTER0_SELECT
, TCF_PERFCOUNTER0_LOW
, TCF_PERFCOUNTER0_HI
),
861 COUNTER(TCF_PERFCOUNTER1_SELECT
, TCF_PERFCOUNTER1_LOW
, TCF_PERFCOUNTER1_HI
),
862 COUNTER(TCF_PERFCOUNTER2_SELECT
, TCF_PERFCOUNTER2_LOW
, TCF_PERFCOUNTER2_HI
),
863 COUNTER(TCF_PERFCOUNTER3_SELECT
, TCF_PERFCOUNTER3_LOW
, TCF_PERFCOUNTER3_HI
),
864 COUNTER(TCF_PERFCOUNTER4_SELECT
, TCF_PERFCOUNTER4_LOW
, TCF_PERFCOUNTER4_HI
),
865 COUNTER(TCF_PERFCOUNTER5_SELECT
, TCF_PERFCOUNTER5_LOW
, TCF_PERFCOUNTER5_HI
),
866 COUNTER(TCF_PERFCOUNTER6_SELECT
, TCF_PERFCOUNTER6_LOW
, TCF_PERFCOUNTER6_HI
),
867 COUNTER(TCF_PERFCOUNTER7_SELECT
, TCF_PERFCOUNTER7_LOW
, TCF_PERFCOUNTER7_HI
),
868 COUNTER(TCF_PERFCOUNTER8_SELECT
, TCF_PERFCOUNTER8_LOW
, TCF_PERFCOUNTER8_HI
),
869 COUNTER(TCF_PERFCOUNTER9_SELECT
, TCF_PERFCOUNTER9_LOW
, TCF_PERFCOUNTER9_HI
),
870 COUNTER(TCF_PERFCOUNTER10_SELECT
, TCF_PERFCOUNTER10_LOW
, TCF_PERFCOUNTER10_HI
),
871 COUNTER(TCF_PERFCOUNTER11_SELECT
, TCF_PERFCOUNTER11_LOW
, TCF_PERFCOUNTER11_HI
),
874 static const struct fd_perfcntr_counter sq_counters
[] = {
875 COUNTER(SQ_PERFCOUNTER0_SELECT
, SQ_PERFCOUNTER0_LOW
, SQ_PERFCOUNTER0_HI
),
876 COUNTER(SQ_PERFCOUNTER1_SELECT
, SQ_PERFCOUNTER1_LOW
, SQ_PERFCOUNTER1_HI
),
877 COUNTER(SQ_PERFCOUNTER2_SELECT
, SQ_PERFCOUNTER2_LOW
, SQ_PERFCOUNTER2_HI
),
878 COUNTER(SQ_PERFCOUNTER3_SELECT
, SQ_PERFCOUNTER3_LOW
, SQ_PERFCOUNTER3_HI
),
881 static const struct fd_perfcntr_countable rbbm_countables
[] = {
882 COUNTABLE(RBBM1_COUNT
, UINT64
, AVERAGE
),
883 COUNTABLE(RBBM1_NRT_BUSY
, UINT64
, AVERAGE
),
884 COUNTABLE(RBBM1_RB_BUSY
, UINT64
, AVERAGE
),
885 COUNTABLE(RBBM1_SQ_CNTX0_BUSY
, UINT64
, AVERAGE
),
886 COUNTABLE(RBBM1_SQ_CNTX17_BUSY
, UINT64
, AVERAGE
),
887 COUNTABLE(RBBM1_VGT_BUSY
, UINT64
, AVERAGE
),
888 COUNTABLE(RBBM1_VGT_NODMA_BUSY
, UINT64
, AVERAGE
),
889 COUNTABLE(RBBM1_PA_BUSY
, UINT64
, AVERAGE
),
890 COUNTABLE(RBBM1_SC_CNTX_BUSY
, UINT64
, AVERAGE
),
891 COUNTABLE(RBBM1_TPC_BUSY
, UINT64
, AVERAGE
),
892 COUNTABLE(RBBM1_TC_BUSY
, UINT64
, AVERAGE
),
893 COUNTABLE(RBBM1_SX_BUSY
, UINT64
, AVERAGE
),
894 COUNTABLE(RBBM1_CP_COHER_BUSY
, UINT64
, AVERAGE
),
895 COUNTABLE(RBBM1_CP_NRT_BUSY
, UINT64
, AVERAGE
),
896 COUNTABLE(RBBM1_GFX_IDLE_STALL
, UINT64
, AVERAGE
),
897 COUNTABLE(RBBM1_INTERRUPT
, UINT64
, AVERAGE
),
900 static const struct fd_perfcntr_countable cp_countables
[] = {
901 COUNTABLE(ALWAYS_COUNT
, UINT64
, AVERAGE
),
902 COUNTABLE(TRANS_FIFO_FULL
, UINT64
, AVERAGE
),
903 COUNTABLE(TRANS_FIFO_AF
, UINT64
, AVERAGE
),
904 COUNTABLE(RCIU_PFPTRANS_WAIT
, UINT64
, AVERAGE
),
905 COUNTABLE(RCIU_NRTTRANS_WAIT
, UINT64
, AVERAGE
),
906 COUNTABLE(CSF_NRT_READ_WAIT
, UINT64
, AVERAGE
),
907 COUNTABLE(CSF_I1_FIFO_FULL
, UINT64
, AVERAGE
),
908 COUNTABLE(CSF_I2_FIFO_FULL
, UINT64
, AVERAGE
),
909 COUNTABLE(CSF_ST_FIFO_FULL
, UINT64
, AVERAGE
),
910 COUNTABLE(CSF_RING_ROQ_FULL
, UINT64
, AVERAGE
),
911 COUNTABLE(CSF_I1_ROQ_FULL
, UINT64
, AVERAGE
),
912 COUNTABLE(CSF_I2_ROQ_FULL
, UINT64
, AVERAGE
),
913 COUNTABLE(CSF_ST_ROQ_FULL
, UINT64
, AVERAGE
),
914 COUNTABLE(MIU_TAG_MEM_FULL
, UINT64
, AVERAGE
),
915 COUNTABLE(MIU_WRITECLEAN
, UINT64
, AVERAGE
),
916 COUNTABLE(MIU_NRT_WRITE_STALLED
, UINT64
, AVERAGE
),
917 COUNTABLE(MIU_NRT_READ_STALLED
, UINT64
, AVERAGE
),
918 COUNTABLE(ME_WRITE_CONFIRM_FIFO_FULL
, UINT64
, AVERAGE
),
919 COUNTABLE(ME_VS_DEALLOC_FIFO_FULL
, UINT64
, AVERAGE
),
920 COUNTABLE(ME_PS_DEALLOC_FIFO_FULL
, UINT64
, AVERAGE
),
921 COUNTABLE(ME_REGS_VS_EVENT_FIFO_FULL
, UINT64
, AVERAGE
),
922 COUNTABLE(ME_REGS_PS_EVENT_FIFO_FULL
, UINT64
, AVERAGE
),
923 COUNTABLE(ME_REGS_CF_EVENT_FIFO_FULL
, UINT64
, AVERAGE
),
924 COUNTABLE(ME_MICRO_RB_STARVED
, UINT64
, AVERAGE
),
925 COUNTABLE(ME_MICRO_I1_STARVED
, UINT64
, AVERAGE
),
926 COUNTABLE(ME_MICRO_I2_STARVED
, UINT64
, AVERAGE
),
927 COUNTABLE(ME_MICRO_ST_STARVED
, UINT64
, AVERAGE
),
928 COUNTABLE(RCIU_RBBM_DWORD_SENT
, UINT64
, AVERAGE
),
929 COUNTABLE(ME_BUSY_CLOCKS
, UINT64
, AVERAGE
),
930 COUNTABLE(ME_WAIT_CONTEXT_AVAIL
, UINT64
, AVERAGE
),
931 COUNTABLE(PFP_TYPE0_PACKET
, UINT64
, AVERAGE
),
932 COUNTABLE(PFP_TYPE3_PACKET
, UINT64
, AVERAGE
),
933 COUNTABLE(CSF_RB_WPTR_NEQ_RPTR
, UINT64
, AVERAGE
),
934 COUNTABLE(CSF_I1_SIZE_NEQ_ZERO
, UINT64
, AVERAGE
),
935 COUNTABLE(CSF_I2_SIZE_NEQ_ZERO
, UINT64
, AVERAGE
),
936 COUNTABLE(CSF_RBI1I2_FETCHING
, UINT64
, AVERAGE
),
939 static const struct fd_perfcntr_counter sx_counters
[] = {
940 COUNTER(SX_PERFCOUNTER0_SELECT
, SX_PERFCOUNTER0_LOW
, SX_PERFCOUNTER0_HI
),
943 static const struct fd_perfcntr_counter mh_counters
[] = {
944 COUNTER(MH_PERFCOUNTER0_SELECT
, MH_PERFCOUNTER0_LOW
, MH_PERFCOUNTER0_HI
),
945 COUNTER(MH_PERFCOUNTER1_SELECT
, MH_PERFCOUNTER1_LOW
, MH_PERFCOUNTER1_HI
),
948 static const struct fd_perfcntr_counter rbbm_counters
[] = {
949 COUNTER(RBBM_PERFCOUNTER1_SELECT
, RBBM_PERFCOUNTER1_LO
, RBBM_PERFCOUNTER1_HI
),
952 static const struct fd_perfcntr_counter cp_counters
[] = {
953 COUNTER(CP_PERFCOUNTER_SELECT
, CP_PERFCOUNTER_LO
, CP_PERFCOUNTER_HI
),
956 static const struct fd_perfcntr_counter rb_counters
[] = {
957 COUNTER(RB_PERFCOUNTER0_SELECT
, RB_PERFCOUNTER0_LOW
, RB_PERFCOUNTER0_HI
),
960 const struct fd_perfcntr_group a2xx_perfcntr_groups
[] = {
961 GROUP("CP", cp_counters
, cp_countables
),
962 GROUP("PA_SU", pa_su_counters
, pa_su_countables
),
963 GROUP("PA_SC", pa_sc_counters
, pa_sc_countables
),
964 GROUP("VGT", vgt_counters
, vgt_countables
),
965 GROUP("TCR", tcr_counters
, tcr_countables
),
966 GROUP("TP0", tp0_counters
, tp0_countables
),
967 GROUP("TCM", tcm_counters
, tcm_countables
),
968 GROUP("TCF", tcf_counters
, tcf_countables
),
969 GROUP("SQ", sq_counters
, sq_countables
),
970 GROUP("SX", sx_counters
, sx_countables
),
971 GROUP("MH", mh_counters
, mh_countables
),
972 GROUP("RBBM", rbbm_counters
, rbbm_countables
),
973 GROUP("RB", rb_counters
, rb_countables
),
976 const unsigned a2xx_num_perfcntr_groups
= ARRAY_SIZE(a2xx_perfcntr_groups
);