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freedreno: update generated headers
[mesa.git] / src / freedreno / registers / a2xx.xml.h
1 #ifndef A2XX_XML
2 #define A2XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-06-11 15:59:35)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2019 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum a2xx_rb_dither_type {
50 DITHER_PIXEL = 0,
51 DITHER_SUBPIXEL = 1,
52 };
53
54 enum a2xx_colorformatx {
55 COLORX_4_4_4_4 = 0,
56 COLORX_1_5_5_5 = 1,
57 COLORX_5_6_5 = 2,
58 COLORX_8 = 3,
59 COLORX_8_8 = 4,
60 COLORX_8_8_8_8 = 5,
61 COLORX_S8_8_8_8 = 6,
62 COLORX_16_FLOAT = 7,
63 COLORX_16_16_FLOAT = 8,
64 COLORX_16_16_16_16_FLOAT = 9,
65 COLORX_32_FLOAT = 10,
66 COLORX_32_32_FLOAT = 11,
67 COLORX_32_32_32_32_FLOAT = 12,
68 COLORX_2_3_3 = 13,
69 COLORX_8_8_8 = 14,
70 };
71
72 enum a2xx_sq_surfaceformat {
73 FMT_1_REVERSE = 0,
74 FMT_1 = 1,
75 FMT_8 = 2,
76 FMT_1_5_5_5 = 3,
77 FMT_5_6_5 = 4,
78 FMT_6_5_5 = 5,
79 FMT_8_8_8_8 = 6,
80 FMT_2_10_10_10 = 7,
81 FMT_8_A = 8,
82 FMT_8_B = 9,
83 FMT_8_8 = 10,
84 FMT_Cr_Y1_Cb_Y0 = 11,
85 FMT_Y1_Cr_Y0_Cb = 12,
86 FMT_5_5_5_1 = 13,
87 FMT_8_8_8_8_A = 14,
88 FMT_4_4_4_4 = 15,
89 FMT_8_8_8 = 16,
90 FMT_DXT1 = 18,
91 FMT_DXT2_3 = 19,
92 FMT_DXT4_5 = 20,
93 FMT_10_10_10_2 = 21,
94 FMT_24_8 = 22,
95 FMT_16 = 24,
96 FMT_16_16 = 25,
97 FMT_16_16_16_16 = 26,
98 FMT_16_EXPAND = 27,
99 FMT_16_16_EXPAND = 28,
100 FMT_16_16_16_16_EXPAND = 29,
101 FMT_16_FLOAT = 30,
102 FMT_16_16_FLOAT = 31,
103 FMT_16_16_16_16_FLOAT = 32,
104 FMT_32 = 33,
105 FMT_32_32 = 34,
106 FMT_32_32_32_32 = 35,
107 FMT_32_FLOAT = 36,
108 FMT_32_32_FLOAT = 37,
109 FMT_32_32_32_32_FLOAT = 38,
110 FMT_ATI_TC_RGB = 39,
111 FMT_ATI_TC_RGBA = 40,
112 FMT_ATI_TC_555_565_RGB = 41,
113 FMT_ATI_TC_555_565_RGBA = 42,
114 FMT_ATI_TC_RGBA_INTERP = 43,
115 FMT_ATI_TC_555_565_RGBA_INTERP = 44,
116 FMT_ETC1_RGBA_INTERP = 46,
117 FMT_ETC1_RGB = 47,
118 FMT_ETC1_RGBA = 48,
119 FMT_DXN = 49,
120 FMT_2_3_3 = 51,
121 FMT_2_10_10_10_AS_16_16_16_16 = 54,
122 FMT_10_10_10_2_AS_16_16_16_16 = 55,
123 FMT_32_32_32_FLOAT = 57,
124 FMT_DXT3A = 58,
125 FMT_DXT5A = 59,
126 FMT_CTX1 = 60,
127 };
128
129 enum a2xx_sq_ps_vtx_mode {
130 POSITION_1_VECTOR = 0,
131 POSITION_2_VECTORS_UNUSED = 1,
132 POSITION_2_VECTORS_SPRITE = 2,
133 POSITION_2_VECTORS_EDGE = 3,
134 POSITION_2_VECTORS_KILL = 4,
135 POSITION_2_VECTORS_SPRITE_KILL = 5,
136 POSITION_2_VECTORS_EDGE_KILL = 6,
137 MULTIPASS = 7,
138 };
139
140 enum a2xx_sq_sample_cntl {
141 CENTROIDS_ONLY = 0,
142 CENTERS_ONLY = 1,
143 CENTROIDS_AND_CENTERS = 2,
144 };
145
146 enum a2xx_dx_clip_space {
147 DXCLIP_OPENGL = 0,
148 DXCLIP_DIRECTX = 1,
149 };
150
151 enum a2xx_pa_su_sc_polymode {
152 POLY_DISABLED = 0,
153 POLY_DUALMODE = 1,
154 };
155
156 enum a2xx_rb_edram_mode {
157 EDRAM_NOP = 0,
158 COLOR_DEPTH = 4,
159 DEPTH_ONLY = 5,
160 EDRAM_COPY = 6,
161 };
162
163 enum a2xx_pa_sc_pattern_bit_order {
164 LITTLE = 0,
165 BIG = 1,
166 };
167
168 enum a2xx_pa_sc_auto_reset_cntl {
169 NEVER = 0,
170 EACH_PRIMITIVE = 1,
171 EACH_PACKET = 2,
172 };
173
174 enum a2xx_pa_pixcenter {
175 PIXCENTER_D3D = 0,
176 PIXCENTER_OGL = 1,
177 };
178
179 enum a2xx_pa_roundmode {
180 TRUNCATE = 0,
181 ROUND = 1,
182 ROUNDTOEVEN = 2,
183 ROUNDTOODD = 3,
184 };
185
186 enum a2xx_pa_quantmode {
187 ONE_SIXTEENTH = 0,
188 ONE_EIGTH = 1,
189 ONE_QUARTER = 2,
190 ONE_HALF = 3,
191 ONE = 4,
192 };
193
194 enum a2xx_rb_copy_sample_select {
195 SAMPLE_0 = 0,
196 SAMPLE_1 = 1,
197 SAMPLE_2 = 2,
198 SAMPLE_3 = 3,
199 SAMPLE_01 = 4,
200 SAMPLE_23 = 5,
201 SAMPLE_0123 = 6,
202 };
203
204 enum a2xx_rb_blend_opcode {
205 BLEND2_DST_PLUS_SRC = 0,
206 BLEND2_SRC_MINUS_DST = 1,
207 BLEND2_MIN_DST_SRC = 2,
208 BLEND2_MAX_DST_SRC = 3,
209 BLEND2_DST_MINUS_SRC = 4,
210 BLEND2_DST_PLUS_SRC_BIAS = 5,
211 };
212
213 enum a2xx_su_perfcnt_select {
214 PERF_PAPC_PASX_REQ = 0,
215 PERF_PAPC_PASX_FIRST_VECTOR = 2,
216 PERF_PAPC_PASX_SECOND_VECTOR = 3,
217 PERF_PAPC_PASX_FIRST_DEAD = 4,
218 PERF_PAPC_PASX_SECOND_DEAD = 5,
219 PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
220 PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
221 PERF_PAPC_PA_INPUT_PRIM = 8,
222 PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
223 PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
224 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
225 PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
226 PERF_PAPC_CLPR_CULL_PRIM = 13,
227 PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
228 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
229 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
230 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
231 PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
232 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
233 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
234 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
235 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
236 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
237 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
238 PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
239 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
240 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
241 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
242 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
243 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
244 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
245 PERF_PAPC_CLSM_NULL_PRIM = 36,
246 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
247 PERF_PAPC_CLSM_CLIP_PRIM = 38,
248 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
249 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
250 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
251 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
252 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
253 PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
254 PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
255 PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
256 PERF_PAPC_SU_INPUT_PRIM = 47,
257 PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
258 PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
259 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
260 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
261 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
262 PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
263 PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
264 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
265 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
266 PERF_PAPC_SU_OUTPUT_PRIM = 57,
267 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
268 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
269 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
270 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
271 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
272 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
273 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
274 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
275 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
276 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
277 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
278 PERF_PAPC_PASX_REQ_IDLE = 69,
279 PERF_PAPC_PASX_REQ_BUSY = 70,
280 PERF_PAPC_PASX_REQ_STALLED = 71,
281 PERF_PAPC_PASX_REC_IDLE = 72,
282 PERF_PAPC_PASX_REC_BUSY = 73,
283 PERF_PAPC_PASX_REC_STARVED_SX = 74,
284 PERF_PAPC_PASX_REC_STALLED = 75,
285 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
286 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
287 PERF_PAPC_CCGSM_IDLE = 78,
288 PERF_PAPC_CCGSM_BUSY = 79,
289 PERF_PAPC_CCGSM_STALLED = 80,
290 PERF_PAPC_CLPRIM_IDLE = 81,
291 PERF_PAPC_CLPRIM_BUSY = 82,
292 PERF_PAPC_CLPRIM_STALLED = 83,
293 PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
294 PERF_PAPC_CLIPSM_IDLE = 85,
295 PERF_PAPC_CLIPSM_BUSY = 86,
296 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
297 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
298 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
299 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
300 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
301 PERF_PAPC_CLIPGA_IDLE = 92,
302 PERF_PAPC_CLIPGA_BUSY = 93,
303 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
304 PERF_PAPC_CLIPGA_STALLED = 95,
305 PERF_PAPC_CLIP_IDLE = 96,
306 PERF_PAPC_CLIP_BUSY = 97,
307 PERF_PAPC_SU_IDLE = 98,
308 PERF_PAPC_SU_BUSY = 99,
309 PERF_PAPC_SU_STARVED_CLIP = 100,
310 PERF_PAPC_SU_STALLED_SC = 101,
311 PERF_PAPC_SU_FACENESS_CULL = 102,
312 };
313
314 enum a2xx_sc_perfcnt_select {
315 SC_SR_WINDOW_VALID = 0,
316 SC_CW_WINDOW_VALID = 1,
317 SC_QM_WINDOW_VALID = 2,
318 SC_FW_WINDOW_VALID = 3,
319 SC_EZ_WINDOW_VALID = 4,
320 SC_IT_WINDOW_VALID = 5,
321 SC_STARVED_BY_PA = 6,
322 SC_STALLED_BY_RB_TILE = 7,
323 SC_STALLED_BY_RB_SAMP = 8,
324 SC_STARVED_BY_RB_EZ = 9,
325 SC_STALLED_BY_SAMPLE_FF = 10,
326 SC_STALLED_BY_SQ = 11,
327 SC_STALLED_BY_SP = 12,
328 SC_TOTAL_NO_PRIMS = 13,
329 SC_NON_EMPTY_PRIMS = 14,
330 SC_NO_TILES_PASSING_QM = 15,
331 SC_NO_PIXELS_PRE_EZ = 16,
332 SC_NO_PIXELS_POST_EZ = 17,
333 };
334
335 enum a2xx_vgt_perfcount_select {
336 VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
337 VGT_SQ_SEND = 1,
338 VGT_SQ_STALLED = 2,
339 VGT_SQ_STARVED_BUSY = 3,
340 VGT_SQ_STARVED_IDLE = 4,
341 VGT_SQ_STATIC = 5,
342 VGT_PA_EVENT_WINDOW_ACTIVE = 6,
343 VGT_PA_CLIP_V_SEND = 7,
344 VGT_PA_CLIP_V_STALLED = 8,
345 VGT_PA_CLIP_V_STARVED_BUSY = 9,
346 VGT_PA_CLIP_V_STARVED_IDLE = 10,
347 VGT_PA_CLIP_V_STATIC = 11,
348 VGT_PA_CLIP_P_SEND = 12,
349 VGT_PA_CLIP_P_STALLED = 13,
350 VGT_PA_CLIP_P_STARVED_BUSY = 14,
351 VGT_PA_CLIP_P_STARVED_IDLE = 15,
352 VGT_PA_CLIP_P_STATIC = 16,
353 VGT_PA_CLIP_S_SEND = 17,
354 VGT_PA_CLIP_S_STALLED = 18,
355 VGT_PA_CLIP_S_STARVED_BUSY = 19,
356 VGT_PA_CLIP_S_STARVED_IDLE = 20,
357 VGT_PA_CLIP_S_STATIC = 21,
358 RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
359 RBIU_IMMED_DATA_FIFO_STARVED = 23,
360 RBIU_IMMED_DATA_FIFO_STALLED = 24,
361 RBIU_DMA_REQUEST_FIFO_STARVED = 25,
362 RBIU_DMA_REQUEST_FIFO_STALLED = 26,
363 RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
364 RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
365 BIN_PRIM_NEAR_CULL = 29,
366 BIN_PRIM_ZERO_CULL = 30,
367 BIN_PRIM_FAR_CULL = 31,
368 BIN_PRIM_BIN_CULL = 32,
369 BIN_PRIM_FACE_CULL = 33,
370 SPARE34 = 34,
371 SPARE35 = 35,
372 SPARE36 = 36,
373 SPARE37 = 37,
374 SPARE38 = 38,
375 SPARE39 = 39,
376 TE_SU_IN_VALID = 40,
377 TE_SU_IN_READ = 41,
378 TE_SU_IN_PRIM = 42,
379 TE_SU_IN_EOP = 43,
380 TE_SU_IN_NULL_PRIM = 44,
381 TE_WK_IN_VALID = 45,
382 TE_WK_IN_READ = 46,
383 TE_OUT_PRIM_VALID = 47,
384 TE_OUT_PRIM_READ = 48,
385 };
386
387 enum a2xx_tcr_perfcount_select {
388 DGMMPD_IPMUX0_STALL = 0,
389 DGMMPD_IPMUX_ALL_STALL = 4,
390 OPMUX0_L2_WRITES = 5,
391 };
392
393 enum a2xx_tp_perfcount_select {
394 POINT_QUADS = 0,
395 BILIN_QUADS = 1,
396 ANISO_QUADS = 2,
397 MIP_QUADS = 3,
398 VOL_QUADS = 4,
399 MIP_VOL_QUADS = 5,
400 MIP_ANISO_QUADS = 6,
401 VOL_ANISO_QUADS = 7,
402 ANISO_2_1_QUADS = 8,
403 ANISO_4_1_QUADS = 9,
404 ANISO_6_1_QUADS = 10,
405 ANISO_8_1_QUADS = 11,
406 ANISO_10_1_QUADS = 12,
407 ANISO_12_1_QUADS = 13,
408 ANISO_14_1_QUADS = 14,
409 ANISO_16_1_QUADS = 15,
410 MIP_VOL_ANISO_QUADS = 16,
411 ALIGN_2_QUADS = 17,
412 ALIGN_4_QUADS = 18,
413 PIX_0_QUAD = 19,
414 PIX_1_QUAD = 20,
415 PIX_2_QUAD = 21,
416 PIX_3_QUAD = 22,
417 PIX_4_QUAD = 23,
418 TP_MIPMAP_LOD0 = 24,
419 TP_MIPMAP_LOD1 = 25,
420 TP_MIPMAP_LOD2 = 26,
421 TP_MIPMAP_LOD3 = 27,
422 TP_MIPMAP_LOD4 = 28,
423 TP_MIPMAP_LOD5 = 29,
424 TP_MIPMAP_LOD6 = 30,
425 TP_MIPMAP_LOD7 = 31,
426 TP_MIPMAP_LOD8 = 32,
427 TP_MIPMAP_LOD9 = 33,
428 TP_MIPMAP_LOD10 = 34,
429 TP_MIPMAP_LOD11 = 35,
430 TP_MIPMAP_LOD12 = 36,
431 TP_MIPMAP_LOD13 = 37,
432 TP_MIPMAP_LOD14 = 38,
433 };
434
435 enum a2xx_tcm_perfcount_select {
436 QUAD0_RD_LAT_FIFO_EMPTY = 0,
437 QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
438 QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
439 QUAD0_RD_LAT_FIFO_FULL = 5,
440 QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
441 READ_STARVED_QUAD0 = 28,
442 READ_STARVED = 32,
443 READ_STALLED_QUAD0 = 33,
444 READ_STALLED = 37,
445 VALID_READ_QUAD0 = 38,
446 TC_TP_STARVED_QUAD0 = 42,
447 TC_TP_STARVED = 46,
448 };
449
450 enum a2xx_tcf_perfcount_select {
451 VALID_CYCLES = 0,
452 SINGLE_PHASES = 1,
453 ANISO_PHASES = 2,
454 MIP_PHASES = 3,
455 VOL_PHASES = 4,
456 MIP_VOL_PHASES = 5,
457 MIP_ANISO_PHASES = 6,
458 VOL_ANISO_PHASES = 7,
459 ANISO_2_1_PHASES = 8,
460 ANISO_4_1_PHASES = 9,
461 ANISO_6_1_PHASES = 10,
462 ANISO_8_1_PHASES = 11,
463 ANISO_10_1_PHASES = 12,
464 ANISO_12_1_PHASES = 13,
465 ANISO_14_1_PHASES = 14,
466 ANISO_16_1_PHASES = 15,
467 MIP_VOL_ANISO_PHASES = 16,
468 ALIGN_2_PHASES = 17,
469 ALIGN_4_PHASES = 18,
470 TPC_BUSY = 19,
471 TPC_STALLED = 20,
472 TPC_STARVED = 21,
473 TPC_WORKING = 22,
474 TPC_WALKER_BUSY = 23,
475 TPC_WALKER_STALLED = 24,
476 TPC_WALKER_WORKING = 25,
477 TPC_ALIGNER_BUSY = 26,
478 TPC_ALIGNER_STALLED = 27,
479 TPC_ALIGNER_STALLED_BY_BLEND = 28,
480 TPC_ALIGNER_STALLED_BY_CACHE = 29,
481 TPC_ALIGNER_WORKING = 30,
482 TPC_BLEND_BUSY = 31,
483 TPC_BLEND_SYNC = 32,
484 TPC_BLEND_STARVED = 33,
485 TPC_BLEND_WORKING = 34,
486 OPCODE_0x00 = 35,
487 OPCODE_0x01 = 36,
488 OPCODE_0x04 = 37,
489 OPCODE_0x10 = 38,
490 OPCODE_0x11 = 39,
491 OPCODE_0x12 = 40,
492 OPCODE_0x13 = 41,
493 OPCODE_0x18 = 42,
494 OPCODE_0x19 = 43,
495 OPCODE_0x1A = 44,
496 OPCODE_OTHER = 45,
497 IN_FIFO_0_EMPTY = 56,
498 IN_FIFO_0_LT_HALF_FULL = 57,
499 IN_FIFO_0_HALF_FULL = 58,
500 IN_FIFO_0_FULL = 59,
501 IN_FIFO_TPC_EMPTY = 72,
502 IN_FIFO_TPC_LT_HALF_FULL = 73,
503 IN_FIFO_TPC_HALF_FULL = 74,
504 IN_FIFO_TPC_FULL = 75,
505 TPC_TC_XFC = 76,
506 TPC_TC_STATE = 77,
507 TC_STALL = 78,
508 QUAD0_TAPS = 79,
509 QUADS = 83,
510 TCA_SYNC_STALL = 84,
511 TAG_STALL = 85,
512 TCB_SYNC_STALL = 88,
513 TCA_VALID = 89,
514 PROBES_VALID = 90,
515 MISS_STALL = 91,
516 FETCH_FIFO_STALL = 92,
517 TCO_STALL = 93,
518 ANY_STALL = 94,
519 TAG_MISSES = 95,
520 TAG_HITS = 96,
521 SUB_TAG_MISSES = 97,
522 SET0_INVALIDATES = 98,
523 SET1_INVALIDATES = 99,
524 SET2_INVALIDATES = 100,
525 SET3_INVALIDATES = 101,
526 SET0_TAG_MISSES = 102,
527 SET1_TAG_MISSES = 103,
528 SET2_TAG_MISSES = 104,
529 SET3_TAG_MISSES = 105,
530 SET0_TAG_HITS = 106,
531 SET1_TAG_HITS = 107,
532 SET2_TAG_HITS = 108,
533 SET3_TAG_HITS = 109,
534 SET0_SUB_TAG_MISSES = 110,
535 SET1_SUB_TAG_MISSES = 111,
536 SET2_SUB_TAG_MISSES = 112,
537 SET3_SUB_TAG_MISSES = 113,
538 SET0_EVICT1 = 114,
539 SET0_EVICT2 = 115,
540 SET0_EVICT3 = 116,
541 SET0_EVICT4 = 117,
542 SET0_EVICT5 = 118,
543 SET0_EVICT6 = 119,
544 SET0_EVICT7 = 120,
545 SET0_EVICT8 = 121,
546 SET1_EVICT1 = 130,
547 SET1_EVICT2 = 131,
548 SET1_EVICT3 = 132,
549 SET1_EVICT4 = 133,
550 SET1_EVICT5 = 134,
551 SET1_EVICT6 = 135,
552 SET1_EVICT7 = 136,
553 SET1_EVICT8 = 137,
554 SET2_EVICT1 = 146,
555 SET2_EVICT2 = 147,
556 SET2_EVICT3 = 148,
557 SET2_EVICT4 = 149,
558 SET2_EVICT5 = 150,
559 SET2_EVICT6 = 151,
560 SET2_EVICT7 = 152,
561 SET2_EVICT8 = 153,
562 SET3_EVICT1 = 162,
563 SET3_EVICT2 = 163,
564 SET3_EVICT3 = 164,
565 SET3_EVICT4 = 165,
566 SET3_EVICT5 = 166,
567 SET3_EVICT6 = 167,
568 SET3_EVICT7 = 168,
569 SET3_EVICT8 = 169,
570 FF_EMPTY = 178,
571 FF_LT_HALF_FULL = 179,
572 FF_HALF_FULL = 180,
573 FF_FULL = 181,
574 FF_XFC = 182,
575 FF_STALLED = 183,
576 FG_MASKS = 184,
577 FG_LEFT_MASKS = 185,
578 FG_LEFT_MASK_STALLED = 186,
579 FG_LEFT_NOT_DONE_STALL = 187,
580 FG_LEFT_FG_STALL = 188,
581 FG_LEFT_SECTORS = 189,
582 FG0_REQUESTS = 195,
583 FG0_STALLED = 196,
584 MEM_REQ512 = 199,
585 MEM_REQ_SENT = 200,
586 MEM_LOCAL_READ_REQ = 202,
587 TC0_MH_STALLED = 203,
588 };
589
590 enum a2xx_sq_perfcnt_select {
591 SQ_PIXEL_VECTORS_SUB = 0,
592 SQ_VERTEX_VECTORS_SUB = 1,
593 SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
594 SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
595 SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
596 SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
597 SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
598 SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
599 SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
600 SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
601 SQ_EXPORT_CYCLES = 10,
602 SQ_ALU_CST_WRITTEN = 11,
603 SQ_TEX_CST_WRITTEN = 12,
604 SQ_ALU_CST_STALL = 13,
605 SQ_ALU_TEX_STALL = 14,
606 SQ_INST_WRITTEN = 15,
607 SQ_BOOLEAN_WRITTEN = 16,
608 SQ_LOOPS_WRITTEN = 17,
609 SQ_PIXEL_SWAP_IN = 18,
610 SQ_PIXEL_SWAP_OUT = 19,
611 SQ_VERTEX_SWAP_IN = 20,
612 SQ_VERTEX_SWAP_OUT = 21,
613 SQ_ALU_VTX_INST_ISSUED = 22,
614 SQ_TEX_VTX_INST_ISSUED = 23,
615 SQ_VC_VTX_INST_ISSUED = 24,
616 SQ_CF_VTX_INST_ISSUED = 25,
617 SQ_ALU_PIX_INST_ISSUED = 26,
618 SQ_TEX_PIX_INST_ISSUED = 27,
619 SQ_VC_PIX_INST_ISSUED = 28,
620 SQ_CF_PIX_INST_ISSUED = 29,
621 SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
622 SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
623 SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
624 SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
625 SQ_ALU_NOPS = 34,
626 SQ_PRED_SKIP = 35,
627 SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
628 SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
629 SQ_SYNC_TEX_STALL_VTX = 38,
630 SQ_SYNC_VC_STALL_VTX = 39,
631 SQ_CONSTANTS_USED_SIMD0 = 40,
632 SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
633 SQ_GPR_STALL_VTX = 42,
634 SQ_GPR_STALL_PIX = 43,
635 SQ_VTX_RS_STALL = 44,
636 SQ_PIX_RS_STALL = 45,
637 SQ_SX_PC_FULL = 46,
638 SQ_SX_EXP_BUFF_FULL = 47,
639 SQ_SX_POS_BUFF_FULL = 48,
640 SQ_INTERP_QUADS = 49,
641 SQ_INTERP_ACTIVE = 50,
642 SQ_IN_PIXEL_STALL = 51,
643 SQ_IN_VTX_STALL = 52,
644 SQ_VTX_CNT = 53,
645 SQ_VTX_VECTOR2 = 54,
646 SQ_VTX_VECTOR3 = 55,
647 SQ_VTX_VECTOR4 = 56,
648 SQ_PIXEL_VECTOR1 = 57,
649 SQ_PIXEL_VECTOR23 = 58,
650 SQ_PIXEL_VECTOR4 = 59,
651 SQ_CONSTANTS_USED_SIMD1 = 60,
652 SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
653 SQ_SX_MEM_EXP_FULL = 62,
654 SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
655 SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
656 SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
657 SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
658 SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
659 SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
660 SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
661 SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
662 SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
663 SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
664 SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
665 SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
666 SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
667 SQ_PERFCOUNT_VTX_POP_THREAD = 76,
668 SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
669 SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
670 SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
671 SQ_PERFCOUNT_PIX_POP_THREAD = 80,
672 SQ_SYNC_TEX_STALL_PIX = 81,
673 SQ_SYNC_VC_STALL_PIX = 82,
674 SQ_CONSTANTS_USED_SIMD2 = 83,
675 SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
676 SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
677 SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
678 SQ_ALU0_FIFO_FULL_SIMD0 = 87,
679 SQ_ALU1_FIFO_FULL_SIMD0 = 88,
680 SQ_ALU0_FIFO_FULL_SIMD1 = 89,
681 SQ_ALU1_FIFO_FULL_SIMD1 = 90,
682 SQ_ALU0_FIFO_FULL_SIMD2 = 91,
683 SQ_ALU1_FIFO_FULL_SIMD2 = 92,
684 SQ_ALU0_FIFO_FULL_SIMD3 = 93,
685 SQ_ALU1_FIFO_FULL_SIMD3 = 94,
686 VC_PERF_STATIC = 95,
687 VC_PERF_STALLED = 96,
688 VC_PERF_STARVED = 97,
689 VC_PERF_SEND = 98,
690 VC_PERF_ACTUAL_STARVED = 99,
691 PIXEL_THREAD_0_ACTIVE = 100,
692 VERTEX_THREAD_0_ACTIVE = 101,
693 PIXEL_THREAD_0_NUMBER = 102,
694 VERTEX_THREAD_0_NUMBER = 103,
695 VERTEX_EVENT_NUMBER = 104,
696 PIXEL_EVENT_NUMBER = 105,
697 PTRBUFF_EF_PUSH = 106,
698 PTRBUFF_EF_POP_EVENT = 107,
699 PTRBUFF_EF_POP_NEW_VTX = 108,
700 PTRBUFF_EF_POP_DEALLOC = 109,
701 PTRBUFF_EF_POP_PVECTOR = 110,
702 PTRBUFF_EF_POP_PVECTOR_X = 111,
703 PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
704 PTRBUFF_PB_DEALLOC = 113,
705 PTRBUFF_PI_STATE_PPB_POP = 114,
706 PTRBUFF_PI_RTR = 115,
707 PTRBUFF_PI_READ_EN = 116,
708 PTRBUFF_PI_BUFF_SWAP = 117,
709 PTRBUFF_SQ_FREE_BUFF = 118,
710 PTRBUFF_SQ_DEC = 119,
711 PTRBUFF_SC_VALID_CNTL_EVENT = 120,
712 PTRBUFF_SC_VALID_IJ_XFER = 121,
713 PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
714 PTRBUFF_QUAL_NEW_VECTOR = 123,
715 PTRBUFF_QUAL_EVENT = 124,
716 PTRBUFF_END_BUFFER = 125,
717 PTRBUFF_FILL_QUAD = 126,
718 VERTS_WRITTEN_SPI = 127,
719 TP_FETCH_INSTR_EXEC = 128,
720 TP_FETCH_INSTR_REQ = 129,
721 TP_DATA_RETURN = 130,
722 SPI_WRITE_CYCLES_SP = 131,
723 SPI_WRITES_SP = 132,
724 SP_ALU_INSTR_EXEC = 133,
725 SP_CONST_ADDR_TO_SQ = 134,
726 SP_PRED_KILLS_TO_SQ = 135,
727 SP_EXPORT_CYCLES_TO_SX = 136,
728 SP_EXPORTS_TO_SX = 137,
729 SQ_CYCLES_ELAPSED = 138,
730 SQ_TCFS_OPT_ALLOC_EXEC = 139,
731 SQ_TCFS_NO_OPT_ALLOC = 140,
732 SQ_ALU0_NO_OPT_ALLOC = 141,
733 SQ_ALU1_NO_OPT_ALLOC = 142,
734 SQ_TCFS_ARB_XFC_CNT = 143,
735 SQ_ALU0_ARB_XFC_CNT = 144,
736 SQ_ALU1_ARB_XFC_CNT = 145,
737 SQ_TCFS_CFS_UPDATE_CNT = 146,
738 SQ_ALU0_CFS_UPDATE_CNT = 147,
739 SQ_ALU1_CFS_UPDATE_CNT = 148,
740 SQ_VTX_PUSH_THREAD_CNT = 149,
741 SQ_VTX_POP_THREAD_CNT = 150,
742 SQ_PIX_PUSH_THREAD_CNT = 151,
743 SQ_PIX_POP_THREAD_CNT = 152,
744 SQ_PIX_TOTAL = 153,
745 SQ_PIX_KILLED = 154,
746 };
747
748 enum a2xx_sx_perfcnt_select {
749 SX_EXPORT_VECTORS = 0,
750 SX_DUMMY_QUADS = 1,
751 SX_ALPHA_FAIL = 2,
752 SX_RB_QUAD_BUSY = 3,
753 SX_RB_COLOR_BUSY = 4,
754 SX_RB_QUAD_STALL = 5,
755 SX_RB_COLOR_STALL = 6,
756 };
757
758 enum a2xx_rbbm_perfcount1_sel {
759 RBBM1_COUNT = 0,
760 RBBM1_NRT_BUSY = 1,
761 RBBM1_RB_BUSY = 2,
762 RBBM1_SQ_CNTX0_BUSY = 3,
763 RBBM1_SQ_CNTX17_BUSY = 4,
764 RBBM1_VGT_BUSY = 5,
765 RBBM1_VGT_NODMA_BUSY = 6,
766 RBBM1_PA_BUSY = 7,
767 RBBM1_SC_CNTX_BUSY = 8,
768 RBBM1_TPC_BUSY = 9,
769 RBBM1_TC_BUSY = 10,
770 RBBM1_SX_BUSY = 11,
771 RBBM1_CP_COHER_BUSY = 12,
772 RBBM1_CP_NRT_BUSY = 13,
773 RBBM1_GFX_IDLE_STALL = 14,
774 RBBM1_INTERRUPT = 15,
775 };
776
777 enum a2xx_cp_perfcount_sel {
778 ALWAYS_COUNT = 0,
779 TRANS_FIFO_FULL = 1,
780 TRANS_FIFO_AF = 2,
781 RCIU_PFPTRANS_WAIT = 3,
782 RCIU_NRTTRANS_WAIT = 6,
783 CSF_NRT_READ_WAIT = 8,
784 CSF_I1_FIFO_FULL = 9,
785 CSF_I2_FIFO_FULL = 10,
786 CSF_ST_FIFO_FULL = 11,
787 CSF_RING_ROQ_FULL = 13,
788 CSF_I1_ROQ_FULL = 14,
789 CSF_I2_ROQ_FULL = 15,
790 CSF_ST_ROQ_FULL = 16,
791 MIU_TAG_MEM_FULL = 18,
792 MIU_WRITECLEAN = 19,
793 MIU_NRT_WRITE_STALLED = 22,
794 MIU_NRT_READ_STALLED = 23,
795 ME_WRITE_CONFIRM_FIFO_FULL = 24,
796 ME_VS_DEALLOC_FIFO_FULL = 25,
797 ME_PS_DEALLOC_FIFO_FULL = 26,
798 ME_REGS_VS_EVENT_FIFO_FULL = 27,
799 ME_REGS_PS_EVENT_FIFO_FULL = 28,
800 ME_REGS_CF_EVENT_FIFO_FULL = 29,
801 ME_MICRO_RB_STARVED = 30,
802 ME_MICRO_I1_STARVED = 31,
803 ME_MICRO_I2_STARVED = 32,
804 ME_MICRO_ST_STARVED = 33,
805 RCIU_RBBM_DWORD_SENT = 40,
806 ME_BUSY_CLOCKS = 41,
807 ME_WAIT_CONTEXT_AVAIL = 42,
808 PFP_TYPE0_PACKET = 43,
809 PFP_TYPE3_PACKET = 44,
810 CSF_RB_WPTR_NEQ_RPTR = 45,
811 CSF_I1_SIZE_NEQ_ZERO = 46,
812 CSF_I2_SIZE_NEQ_ZERO = 47,
813 CSF_RBI1I2_FETCHING = 48,
814 };
815
816 enum a2xx_rb_perfcnt_select {
817 RBPERF_CNTX_BUSY = 0,
818 RBPERF_CNTX_BUSY_MAX = 1,
819 RBPERF_SX_QUAD_STARVED = 2,
820 RBPERF_SX_QUAD_STARVED_MAX = 3,
821 RBPERF_GA_GC_CH0_SYS_REQ = 4,
822 RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
823 RBPERF_GA_GC_CH1_SYS_REQ = 6,
824 RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
825 RBPERF_MH_STARVED = 8,
826 RBPERF_MH_STARVED_MAX = 9,
827 RBPERF_AZ_BC_COLOR_BUSY = 10,
828 RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
829 RBPERF_AZ_BC_Z_BUSY = 12,
830 RBPERF_AZ_BC_Z_BUSY_MAX = 13,
831 RBPERF_RB_SC_TILE_RTR_N = 14,
832 RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
833 RBPERF_RB_SC_SAMP_RTR_N = 16,
834 RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
835 RBPERF_RB_SX_QUAD_RTR_N = 18,
836 RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
837 RBPERF_RB_SX_COLOR_RTR_N = 20,
838 RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
839 RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
840 RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
841 RBPERF_ZXP_STALL = 24,
842 RBPERF_ZXP_STALL_MAX = 25,
843 RBPERF_EVENT_PENDING = 26,
844 RBPERF_EVENT_PENDING_MAX = 27,
845 RBPERF_RB_MH_VALID = 28,
846 RBPERF_RB_MH_VALID_MAX = 29,
847 RBPERF_SX_RB_QUAD_SEND = 30,
848 RBPERF_SX_RB_COLOR_SEND = 31,
849 RBPERF_SC_RB_TILE_SEND = 32,
850 RBPERF_SC_RB_SAMPLE_SEND = 33,
851 RBPERF_SX_RB_MEM_EXPORT = 34,
852 RBPERF_SX_RB_QUAD_EVENT = 35,
853 RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
854 RBPERF_SC_RB_TILE_EVENT_ALL = 37,
855 RBPERF_RB_SC_EZ_SEND = 38,
856 RBPERF_RB_SX_INDEX_SEND = 39,
857 RBPERF_GMEM_INTFO_RD = 40,
858 RBPERF_GMEM_INTF1_RD = 41,
859 RBPERF_GMEM_INTFO_WR = 42,
860 RBPERF_GMEM_INTF1_WR = 43,
861 RBPERF_RB_CP_CONTEXT_DONE = 44,
862 RBPERF_RB_CP_CACHE_FLUSH = 45,
863 RBPERF_ZPASS_DONE = 46,
864 RBPERF_ZCMD_VALID = 47,
865 RBPERF_CCMD_VALID = 48,
866 RBPERF_ACCUM_GRANT = 49,
867 RBPERF_ACCUM_C0_GRANT = 50,
868 RBPERF_ACCUM_C1_GRANT = 51,
869 RBPERF_ACCUM_FULL_BE_WR = 52,
870 RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
871 RBPERF_ACCUM_TIMEOUT_PULSE = 54,
872 RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
873 RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
874 };
875
876 enum adreno_mmu_clnt_beh {
877 BEH_NEVR = 0,
878 BEH_TRAN_RNG = 1,
879 BEH_TRAN_FLT = 2,
880 };
881
882 enum sq_tex_clamp {
883 SQ_TEX_WRAP = 0,
884 SQ_TEX_MIRROR = 1,
885 SQ_TEX_CLAMP_LAST_TEXEL = 2,
886 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
887 SQ_TEX_CLAMP_HALF_BORDER = 4,
888 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
889 SQ_TEX_CLAMP_BORDER = 6,
890 SQ_TEX_MIRROR_ONCE_BORDER = 7,
891 };
892
893 enum sq_tex_swiz {
894 SQ_TEX_X = 0,
895 SQ_TEX_Y = 1,
896 SQ_TEX_Z = 2,
897 SQ_TEX_W = 3,
898 SQ_TEX_ZERO = 4,
899 SQ_TEX_ONE = 5,
900 };
901
902 enum sq_tex_filter {
903 SQ_TEX_FILTER_POINT = 0,
904 SQ_TEX_FILTER_BILINEAR = 1,
905 SQ_TEX_FILTER_BASEMAP = 2,
906 SQ_TEX_FILTER_USE_FETCH_CONST = 3,
907 };
908
909 enum sq_tex_aniso_filter {
910 SQ_TEX_ANISO_FILTER_DISABLED = 0,
911 SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
912 SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
913 SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
914 SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
915 SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
916 SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
917 };
918
919 enum sq_tex_dimension {
920 SQ_TEX_DIMENSION_1D = 0,
921 SQ_TEX_DIMENSION_2D = 1,
922 SQ_TEX_DIMENSION_3D = 2,
923 SQ_TEX_DIMENSION_CUBE = 3,
924 };
925
926 enum sq_tex_border_color {
927 SQ_TEX_BORDER_COLOR_BLACK = 0,
928 SQ_TEX_BORDER_COLOR_WHITE = 1,
929 SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
930 SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
931 };
932
933 enum sq_tex_sign {
934 SQ_TEX_SIGN_UNISIGNED = 0,
935 SQ_TEX_SIGN_SIGNED = 1,
936 SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
937 SQ_TEX_SIGN_GAMMA = 3,
938 };
939
940 enum sq_tex_endian {
941 SQ_TEX_ENDIAN_NONE = 0,
942 SQ_TEX_ENDIAN_8IN16 = 1,
943 SQ_TEX_ENDIAN_8IN32 = 2,
944 SQ_TEX_ENDIAN_16IN32 = 3,
945 };
946
947 enum sq_tex_clamp_policy {
948 SQ_TEX_CLAMP_POLICY_D3D = 0,
949 SQ_TEX_CLAMP_POLICY_OGL = 1,
950 };
951
952 enum sq_tex_num_format {
953 SQ_TEX_NUM_FORMAT_FRAC = 0,
954 SQ_TEX_NUM_FORMAT_INT = 1,
955 };
956
957 enum sq_tex_type {
958 SQ_TEX_TYPE_0 = 0,
959 SQ_TEX_TYPE_1 = 1,
960 SQ_TEX_TYPE_2 = 2,
961 SQ_TEX_TYPE_3 = 3,
962 };
963
964 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
965
966 #define REG_A2XX_RBBM_CNTL 0x0000003b
967
968 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c
969
970 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0
971
972 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
973
974 #define REG_A2XX_MH_MMU_CONFIG 0x00000040
975 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
976 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
977 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
978 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
979 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
980 {
981 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
982 }
983 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
984 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
985 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
986 {
987 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
988 }
989 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
990 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
991 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
992 {
993 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
994 }
995 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
996 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
997 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
998 {
999 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
1000 }
1001 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
1002 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
1003 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1004 {
1005 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
1006 }
1007 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
1008 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
1009 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1010 {
1011 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
1012 }
1013 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
1014 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
1015 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1016 {
1017 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
1018 }
1019 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
1020 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
1021 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1022 {
1023 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
1024 }
1025 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
1026 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
1027 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1028 {
1029 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
1030 }
1031 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
1032 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
1033 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1034 {
1035 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
1036 }
1037 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
1038 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
1039 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
1040 {
1041 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
1042 }
1043
1044 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
1045 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff
1046 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0
1047 static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
1048 {
1049 return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
1050 }
1051 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000
1052 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12
1053 static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
1054 {
1055 return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
1056 }
1057
1058 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042
1059
1060 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043
1061
1062 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
1063
1064 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
1065 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001
1066 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002
1067
1068 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
1069
1070 #define REG_A2XX_MH_MMU_MPU_END 0x00000047
1071
1072 #define REG_A2XX_NQWAIT_UNTIL 0x00000394
1073
1074 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
1075
1076 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
1077
1078 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
1079
1080 #define REG_A2XX_RBBM_DEBUG 0x0000039b
1081
1082 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
1083 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001
1084 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002
1085 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004
1086 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008
1087 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010
1088 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020
1089 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040
1090 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080
1091 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100
1092 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200
1093 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400
1094 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800
1095 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000
1096 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000
1097 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000
1098 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000
1099 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000
1100 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000
1101 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000
1102 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000
1103 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000
1104 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000
1105 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000
1106 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000
1107 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000
1108 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000
1109 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000
1110 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000
1111 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000
1112 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000
1113 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000
1114 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000
1115
1116 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
1117
1118 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0
1119
1120 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1
1121
1122 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3
1123
1124 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4
1125 #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001
1126 #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002
1127 #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000
1128
1129 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5
1130
1131 #define REG_A2XX_RBBM_INT_ACK 0x000003b6
1132
1133 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
1134 #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020
1135 #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000
1136 #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000
1137 #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000
1138
1139 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9
1140
1141 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa
1142
1143 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444
1144
1145 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445
1146
1147 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446
1148
1149 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
1150
1151 #define REG_A2XX_RBBM_STATUS 0x000005d0
1152 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f
1153 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0
1154 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
1155 {
1156 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
1157 }
1158 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020
1159 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100
1160 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200
1161 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400
1162 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800
1163 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000
1164 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000
1165 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000
1166 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000
1167 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000
1168 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000
1169 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000
1170 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000
1171 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000
1172 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000
1173 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000
1174 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000
1175 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000
1176 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000
1177
1178 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40
1179 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f
1180 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0
1181 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
1182 {
1183 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
1184 }
1185 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040
1186 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080
1187 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100
1188 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200
1189 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00
1190 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10
1191 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
1192 {
1193 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
1194 }
1195 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000
1196 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000
1197 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000
1198 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000
1199 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16
1200 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
1201 {
1202 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
1203 }
1204 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000
1205 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000
1206 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000
1207 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
1208 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
1209
1210 #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42
1211 #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001
1212 #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002
1213 #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004
1214
1215 #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43
1216
1217 #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44
1218
1219 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54
1220
1221 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55
1222
1223 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
1224 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1225 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
1226 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
1227 {
1228 assert(!(val & 0x1f));
1229 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
1230 }
1231 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1232 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1233 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1234 {
1235 assert(!(val & 0x1f));
1236 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
1237 }
1238
1239 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
1240
1241 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
1242
1243 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
1244
1245 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
1246
1247 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38
1248
1249 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39
1250
1251 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44
1252
1253 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80
1254
1255 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80
1256
1257 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81
1258
1259 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
1260
1261 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
1262 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0
1263 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5
1264 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
1265 {
1266 return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
1267 }
1268
1269 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
1270 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001
1271 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0
1272 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4
1273 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
1274 {
1275 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
1276 }
1277 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000
1278 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12
1279 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
1280 {
1281 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
1282 }
1283
1284 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
1285
1286 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
1287 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff
1288 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0
1289 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
1290 {
1291 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
1292 }
1293 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000
1294 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16
1295 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
1296 {
1297 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
1298 }
1299
1300 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
1301
1302 #define REG_A2XX_SQ_INT_CNTL 0x00000d34
1303
1304 #define REG_A2XX_SQ_INT_STATUS 0x00000d35
1305
1306 #define REG_A2XX_SQ_INT_ACK 0x00000d36
1307
1308 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae
1309
1310 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf
1311
1312 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0
1313
1314 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1
1315
1316 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2
1317
1318 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3
1319
1320 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4
1321
1322 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5
1323
1324 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6
1325
1326 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7
1327
1328 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8
1329
1330 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9
1331
1332 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba
1333
1334 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb
1335
1336 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc
1337
1338 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd
1339
1340 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe
1341
1342 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf
1343
1344 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0
1345
1346 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1
1347
1348 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00
1349 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001
1350
1351 #define REG_A2XX_TP0_CHICKEN 0x00000e1e
1352
1353 #define REG_A2XX_RB_BC_CONTROL 0x00000f01
1354 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001
1355 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006
1356 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1
1357 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
1358 {
1359 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
1360 }
1361 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008
1362 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010
1363 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020
1364 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040
1365 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080
1366 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00
1367 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8
1368 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
1369 {
1370 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
1371 }
1372 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000
1373 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000
1374 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000
1375 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000
1376 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000
1377 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18
1378 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
1379 {
1380 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
1381 }
1382 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000
1383 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000
1384 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23
1385 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
1386 {
1387 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
1388 }
1389 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000
1390 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27
1391 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
1392 {
1393 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
1394 }
1395 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000
1396 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000
1397 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000
1398
1399 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02
1400
1401 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26
1402
1403 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27
1404
1405 #define REG_A2XX_RB_SURFACE_INFO 0x00002000
1406 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff
1407 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0
1408 static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
1409 {
1410 return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
1411 }
1412 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000
1413 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14
1414 static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
1415 {
1416 return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
1417 }
1418
1419 #define REG_A2XX_RB_COLOR_INFO 0x00002001
1420 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
1421 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0
1422 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
1423 {
1424 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
1425 }
1426 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030
1427 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4
1428 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
1429 {
1430 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
1431 }
1432 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040
1433 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180
1434 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7
1435 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
1436 {
1437 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
1438 }
1439 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600
1440 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9
1441 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
1442 {
1443 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
1444 }
1445 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000
1446 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
1447 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
1448 {
1449 assert(!(val & 0xfff));
1450 return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
1451 }
1452
1453 #define REG_A2XX_RB_DEPTH_INFO 0x00002002
1454 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
1455 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1456 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
1457 {
1458 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1459 }
1460 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1461 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
1462 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1463 {
1464 assert(!(val & 0xfff));
1465 return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1466 }
1467
1468 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
1469
1470 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006
1471
1472 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e
1473 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
1474 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
1475 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
1476 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1477 {
1478 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
1479 }
1480 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
1481 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
1482 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1483 {
1484 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
1485 }
1486
1487 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f
1488 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
1489 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
1490 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
1491 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1492 {
1493 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
1494 }
1495 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
1496 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
1497 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1498 {
1499 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
1500 }
1501
1502 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080
1503 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff
1504 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
1505 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
1506 {
1507 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
1508 }
1509 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000
1510 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
1511 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
1512 {
1513 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
1514 }
1515 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000
1516
1517 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081
1518 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
1519 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
1520 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
1521 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
1522 {
1523 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
1524 }
1525 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
1526 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
1527 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
1528 {
1529 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
1530 }
1531
1532 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082
1533 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
1534 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
1535 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
1536 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
1537 {
1538 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
1539 }
1540 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
1541 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
1542 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
1543 {
1544 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
1545 }
1546
1547 #define REG_A2XX_UNKNOWN_2010 0x00002010
1548
1549 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100
1550
1551 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101
1552
1553 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102
1554
1555 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103
1556
1557 #define REG_A2XX_RB_COLOR_MASK 0x00002104
1558 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001
1559 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002
1560 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004
1561 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008
1562
1563 #define REG_A2XX_RB_BLEND_RED 0x00002105
1564
1565 #define REG_A2XX_RB_BLEND_GREEN 0x00002106
1566
1567 #define REG_A2XX_RB_BLEND_BLUE 0x00002107
1568
1569 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108
1570
1571 #define REG_A2XX_RB_FOG_COLOR 0x00002109
1572 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff
1573 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0
1574 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
1575 {
1576 return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
1577 }
1578 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00
1579 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8
1580 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
1581 {
1582 return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
1583 }
1584 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000
1585 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16
1586 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
1587 {
1588 return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
1589 }
1590
1591 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
1592 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1593 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1594 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1595 {
1596 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1597 }
1598 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1599 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1600 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1601 {
1602 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1603 }
1604 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1605 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1606 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1607 {
1608 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1609 }
1610
1611 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d
1612 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1613 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1614 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1615 {
1616 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
1617 }
1618 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1619 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1620 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1621 {
1622 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1623 }
1624 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1625 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1626 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1627 {
1628 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1629 }
1630
1631 #define REG_A2XX_RB_ALPHA_REF 0x0000210e
1632
1633 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f
1634 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff
1635 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0
1636 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
1637 {
1638 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
1639 }
1640
1641 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110
1642 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff
1643 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0
1644 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
1645 {
1646 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
1647 }
1648
1649 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111
1650 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff
1651 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0
1652 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
1653 {
1654 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
1655 }
1656
1657 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112
1658 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff
1659 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0
1660 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
1661 {
1662 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
1663 }
1664
1665 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113
1666 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff
1667 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0
1668 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
1669 {
1670 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
1671 }
1672
1673 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114
1674 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff
1675 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0
1676 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
1677 {
1678 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
1679 }
1680
1681 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180
1682 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff
1683 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0
1684 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
1685 {
1686 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
1687 }
1688 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00
1689 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8
1690 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
1691 {
1692 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
1693 }
1694 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000
1695 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000
1696 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000
1697 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000
1698 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000
1699 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20
1700 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
1701 {
1702 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
1703 }
1704 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000
1705 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24
1706 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
1707 {
1708 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
1709 }
1710 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000
1711 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27
1712 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
1713 {
1714 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
1715 }
1716 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000
1717
1718 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181
1719 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001
1720 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002
1721 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c
1722 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2
1723 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
1724 {
1725 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
1726 }
1727 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00
1728 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8
1729 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
1730 {
1731 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
1732 }
1733 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000
1734 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000
1735 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
1736
1737 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
1738 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff
1739 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0
1740 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
1741 {
1742 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
1743 }
1744 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000
1745 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16
1746 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
1747 {
1748 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
1749 }
1750
1751 #define REG_A2XX_SQ_WRAPPING_0 0x00002183
1752 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f
1753 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0
1754 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
1755 {
1756 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
1757 }
1758 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0
1759 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4
1760 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
1761 {
1762 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
1763 }
1764 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00
1765 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8
1766 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
1767 {
1768 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
1769 }
1770 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000
1771 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12
1772 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
1773 {
1774 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
1775 }
1776 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000
1777 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16
1778 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
1779 {
1780 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
1781 }
1782 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000
1783 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20
1784 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
1785 {
1786 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
1787 }
1788 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000
1789 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24
1790 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
1791 {
1792 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
1793 }
1794 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000
1795 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28
1796 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
1797 {
1798 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
1799 }
1800
1801 #define REG_A2XX_SQ_WRAPPING_1 0x00002184
1802 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f
1803 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0
1804 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
1805 {
1806 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
1807 }
1808 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0
1809 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4
1810 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
1811 {
1812 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
1813 }
1814 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00
1815 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8
1816 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
1817 {
1818 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
1819 }
1820 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000
1821 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12
1822 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
1823 {
1824 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
1825 }
1826 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000
1827 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16
1828 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
1829 {
1830 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
1831 }
1832 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000
1833 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20
1834 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
1835 {
1836 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
1837 }
1838 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000
1839 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24
1840 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
1841 {
1842 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
1843 }
1844 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000
1845 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28
1846 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
1847 {
1848 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
1849 }
1850
1851 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
1852 #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff
1853 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0
1854 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
1855 {
1856 return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
1857 }
1858 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000
1859 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12
1860 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
1861 {
1862 return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
1863 }
1864
1865 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
1866 #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff
1867 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0
1868 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
1869 {
1870 return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
1871 }
1872 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000
1873 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12
1874 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
1875 {
1876 return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
1877 }
1878
1879 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
1880
1881 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
1882 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
1883 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
1884 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
1885 {
1886 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
1887 }
1888 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
1889 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
1890 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
1891 {
1892 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
1893 }
1894 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
1895 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
1896 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
1897 {
1898 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
1899 }
1900 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
1901 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
1902 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
1903 {
1904 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
1905 }
1906 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
1907 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
1908 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
1909 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000
1910 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24
1911 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
1912 {
1913 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
1914 }
1915
1916 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd
1917
1918 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200
1919 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001
1920 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002
1921 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004
1922 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008
1923 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070
1924 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4
1925 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
1926 {
1927 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
1928 }
1929 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080
1930 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700
1931 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8
1932 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
1933 {
1934 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
1935 }
1936 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800
1937 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11
1938 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
1939 {
1940 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
1941 }
1942 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000
1943 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14
1944 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
1945 {
1946 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
1947 }
1948 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000
1949 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17
1950 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
1951 {
1952 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
1953 }
1954 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000
1955 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20
1956 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
1957 {
1958 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
1959 }
1960 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000
1961 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23
1962 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
1963 {
1964 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
1965 }
1966 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000
1967 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26
1968 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
1969 {
1970 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
1971 }
1972 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000
1973 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29
1974 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
1975 {
1976 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
1977 }
1978
1979 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201
1980 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f
1981 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0
1982 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
1983 {
1984 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
1985 }
1986 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0
1987 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5
1988 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
1989 {
1990 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
1991 }
1992 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00
1993 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8
1994 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
1995 {
1996 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
1997 }
1998 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000
1999 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16
2000 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
2001 {
2002 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
2003 }
2004 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000
2005 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21
2006 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
2007 {
2008 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
2009 }
2010 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000
2011 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24
2012 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
2013 {
2014 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
2015 }
2016 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000
2017 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000
2018
2019 #define REG_A2XX_RB_COLORCONTROL 0x00002202
2020 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007
2021 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0
2022 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
2023 {
2024 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
2025 }
2026 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008
2027 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010
2028 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020
2029 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040
2030 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080
2031 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00
2032 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8
2033 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
2034 {
2035 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
2036 }
2037 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000
2038 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12
2039 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
2040 {
2041 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
2042 }
2043 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000
2044 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14
2045 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
2046 {
2047 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
2048 }
2049 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000
2050 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000
2051 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24
2052 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
2053 {
2054 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
2055 }
2056 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000
2057 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26
2058 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
2059 {
2060 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
2061 }
2062 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000
2063 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28
2064 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
2065 {
2066 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
2067 }
2068 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000
2069 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30
2070 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
2071 {
2072 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
2073 }
2074
2075 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203
2076 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007
2077 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0
2078 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
2079 {
2080 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
2081 }
2082 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038
2083 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3
2084 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
2085 {
2086 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
2087 }
2088 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0
2089 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6
2090 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
2091 {
2092 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
2093 }
2094
2095 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204
2096 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
2097 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000
2098 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000
2099 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19
2100 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
2101 {
2102 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
2103 }
2104 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000
2105 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000
2106 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000
2107 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000
2108 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000
2109
2110 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205
2111 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001
2112 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002
2113 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004
2114 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018
2115 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3
2116 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
2117 {
2118 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
2119 }
2120 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0
2121 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5
2122 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
2123 {
2124 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
2125 }
2126 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700
2127 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8
2128 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
2129 {
2130 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
2131 }
2132 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800
2133 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000
2134 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000
2135 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000
2136 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000
2137 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000
2138 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000
2139 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000
2140 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000
2141 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000
2142 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000
2143 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000
2144 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000
2145 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000
2146 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000
2147 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000
2148
2149 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206
2150 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001
2151 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002
2152 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004
2153 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008
2154 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010
2155 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020
2156 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100
2157 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200
2158 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400
2159 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800
2160
2161 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207
2162 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007
2163 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0
2164 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
2165 {
2166 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
2167 }
2168 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038
2169 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3
2170 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
2171 {
2172 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
2173 }
2174 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0
2175 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6
2176 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
2177 {
2178 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
2179 }
2180
2181 #define REG_A2XX_RB_MODECONTROL 0x00002208
2182 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007
2183 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0
2184 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
2185 {
2186 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
2187 }
2188
2189 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209
2190
2191 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a
2192
2193 #define REG_A2XX_CLEAR_COLOR 0x0000220b
2194 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff
2195 #define A2XX_CLEAR_COLOR_RED__SHIFT 0
2196 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
2197 {
2198 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
2199 }
2200 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00
2201 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8
2202 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
2203 {
2204 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
2205 }
2206 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000
2207 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16
2208 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
2209 {
2210 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
2211 }
2212 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000
2213 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24
2214 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
2215 {
2216 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
2217 }
2218
2219 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210
2220
2221 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280
2222 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff
2223 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0
2224 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
2225 {
2226 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
2227 }
2228 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000
2229 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16
2230 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
2231 {
2232 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
2233 }
2234
2235 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281
2236 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2237 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0
2238 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
2239 {
2240 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
2241 }
2242 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2243 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16
2244 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
2245 {
2246 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
2247 }
2248
2249 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282
2250 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff
2251 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0
2252 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
2253 {
2254 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
2255 }
2256
2257 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283
2258 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff
2259 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0
2260 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
2261 {
2262 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
2263 }
2264 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000
2265 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16
2266 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
2267 {
2268 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
2269 }
2270 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000
2271 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28
2272 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
2273 {
2274 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
2275 }
2276 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000
2277 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29
2278 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
2279 {
2280 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
2281 }
2282
2283 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
2284 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001
2285 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e
2286 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1
2287 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
2288 {
2289 return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
2290 }
2291 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100
2292
2293 #define REG_A2XX_VGT_ENHANCE 0x00002294
2294
2295 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300
2296 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff
2297 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0
2298 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
2299 {
2300 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
2301 }
2302 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100
2303 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200
2304 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
2305
2306 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
2307 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007
2308 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0
2309 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
2310 {
2311 return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
2312 }
2313 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000
2314 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13
2315 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
2316 {
2317 return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
2318 }
2319
2320 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
2321 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
2322 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0
2323 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
2324 {
2325 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
2326 }
2327 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006
2328 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1
2329 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
2330 {
2331 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
2332 }
2333 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380
2334 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7
2335 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
2336 {
2337 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
2338 }
2339
2340 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303
2341 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff
2342 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0
2343 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
2344 {
2345 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
2346 }
2347
2348 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304
2349 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff
2350 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0
2351 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
2352 {
2353 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
2354 }
2355
2356 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305
2357 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff
2358 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0
2359 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
2360 {
2361 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
2362 }
2363
2364 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306
2365 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff
2366 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0
2367 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
2368 {
2369 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
2370 }
2371
2372 #define REG_A2XX_SQ_VS_CONST 0x00002307
2373 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff
2374 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0
2375 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
2376 {
2377 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
2378 }
2379 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000
2380 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12
2381 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
2382 {
2383 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
2384 }
2385
2386 #define REG_A2XX_SQ_PS_CONST 0x00002308
2387 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff
2388 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0
2389 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
2390 {
2391 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
2392 }
2393 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000
2394 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12
2395 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
2396 {
2397 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
2398 }
2399
2400 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309
2401
2402 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a
2403
2404 #define REG_A2XX_PA_SC_AA_MASK 0x00002312
2405
2406 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
2407 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
2408 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0
2409 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
2410 {
2411 return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
2412 }
2413
2414 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
2415 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003
2416 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0
2417 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
2418 {
2419 return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
2420 }
2421
2422 #define REG_A2XX_RB_COPY_CONTROL 0x00002318
2423 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
2424 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0
2425 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
2426 {
2427 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
2428 }
2429 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008
2430 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0
2431 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4
2432 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
2433 {
2434 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
2435 }
2436
2437 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319
2438
2439 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a
2440 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff
2441 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0
2442 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
2443 {
2444 assert(!(val & 0x1f));
2445 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
2446 }
2447
2448 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b
2449 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007
2450 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0
2451 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
2452 {
2453 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
2454 }
2455 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008
2456 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0
2457 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4
2458 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
2459 {
2460 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
2461 }
2462 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
2463 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
2464 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
2465 {
2466 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
2467 }
2468 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
2469 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
2470 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
2471 {
2472 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
2473 }
2474 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000
2475 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12
2476 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
2477 {
2478 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
2479 }
2480 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000
2481 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000
2482 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000
2483 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000
2484
2485 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c
2486 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff
2487 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0
2488 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
2489 {
2490 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
2491 }
2492 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000
2493 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13
2494 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
2495 {
2496 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
2497 }
2498
2499 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d
2500
2501 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324
2502
2503 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326
2504
2505 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340
2506
2507 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357
2508
2509 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360
2510
2511 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380
2512
2513 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383
2514
2515 #define REG_A2XX_SQ_CONSTANT_0 0x00004000
2516
2517 #define REG_A2XX_SQ_FETCH_0 0x00004800
2518
2519 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900
2520
2521 #define REG_A2XX_SQ_CF_LOOP 0x00004908
2522
2523 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29
2524
2525 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a
2526
2527 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
2528
2529 #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88
2530
2531 #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89
2532
2533 #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a
2534
2535 #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b
2536
2537 #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c
2538
2539 #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d
2540
2541 #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e
2542
2543 #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f
2544
2545 #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90
2546
2547 #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91
2548
2549 #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92
2550
2551 #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93
2552
2553 #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98
2554
2555 #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99
2556
2557 #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a
2558
2559 #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48
2560
2561 #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49
2562
2563 #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a
2564
2565 #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b
2566
2567 #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c
2568
2569 #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e
2570
2571 #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50
2572
2573 #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52
2574
2575 #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d
2576
2577 #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f
2578
2579 #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51
2580
2581 #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53
2582
2583 #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05
2584
2585 #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08
2586
2587 #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06
2588
2589 #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09
2590
2591 #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07
2592
2593 #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a
2594
2595 #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f
2596
2597 #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20
2598
2599 #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21
2600
2601 #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22
2602
2603 #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23
2604
2605 #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24
2606
2607 #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54
2608
2609 #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57
2610
2611 #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55
2612
2613 #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58
2614
2615 #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56
2616
2617 #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59
2618
2619 #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a
2620
2621 #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d
2622
2623 #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60
2624
2625 #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63
2626
2627 #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66
2628
2629 #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69
2630
2631 #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c
2632
2633 #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f
2634
2635 #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72
2636
2637 #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75
2638
2639 #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78
2640
2641 #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b
2642
2643 #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b
2644
2645 #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e
2646
2647 #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61
2648
2649 #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64
2650
2651 #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67
2652
2653 #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a
2654
2655 #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d
2656
2657 #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70
2658
2659 #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73
2660
2661 #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76
2662
2663 #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79
2664
2665 #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c
2666
2667 #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c
2668
2669 #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f
2670
2671 #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62
2672
2673 #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65
2674
2675 #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68
2676
2677 #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b
2678
2679 #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e
2680
2681 #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71
2682
2683 #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74
2684
2685 #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77
2686
2687 #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a
2688
2689 #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d
2690
2691 #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8
2692
2693 #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9
2694
2695 #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca
2696
2697 #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb
2698
2699 #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc
2700
2701 #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd
2702
2703 #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce
2704
2705 #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf
2706
2707 #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0
2708
2709 #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1
2710
2711 #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2
2712
2713 #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3
2714
2715 #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4
2716
2717 #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8
2718
2719 #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9
2720
2721 #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46
2722
2723 #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a
2724
2725 #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47
2726
2727 #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b
2728
2729 #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48
2730
2731 #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c
2732
2733 #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49
2734
2735 #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d
2736
2737 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
2738
2739 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
2740
2741 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
2742
2743 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445
2744
2745 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446
2746
2747 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
2748
2749 #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
2750
2751 #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
2752
2753 #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
2754
2755 #define REG_A2XX_SQ_TEX_0 0x00000000
2756 #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
2757 #define A2XX_SQ_TEX_0_TYPE__SHIFT 0
2758 static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
2759 {
2760 return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK;
2761 }
2762 #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c
2763 #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2
2764 static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
2765 {
2766 return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK;
2767 }
2768 #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030
2769 #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4
2770 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
2771 {
2772 return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK;
2773 }
2774 #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0
2775 #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6
2776 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
2777 {
2778 return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK;
2779 }
2780 #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300
2781 #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8
2782 static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
2783 {
2784 return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK;
2785 }
2786 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
2787 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
2788 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
2789 {
2790 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
2791 }
2792 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000
2793 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13
2794 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
2795 {
2796 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
2797 }
2798 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000
2799 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16
2800 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
2801 {
2802 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
2803 }
2804 #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000
2805 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22
2806 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
2807 {
2808 assert(!(val & 0x1f));
2809 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
2810 }
2811 #define A2XX_SQ_TEX_0_TILED 0x00000002
2812
2813 #define REG_A2XX_SQ_TEX_1 0x00000001
2814 #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f
2815 #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0
2816 static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
2817 {
2818 return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK;
2819 }
2820 #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0
2821 #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6
2822 static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
2823 {
2824 return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK;
2825 }
2826 #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300
2827 #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8
2828 static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
2829 {
2830 return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK;
2831 }
2832 #define A2XX_SQ_TEX_1_STACKED 0x00000400
2833 #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800
2834 #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11
2835 static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
2836 {
2837 return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK;
2838 }
2839 #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000
2840 #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12
2841 static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
2842 {
2843 assert(!(val & 0xfff));
2844 return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
2845 }
2846
2847 #define REG_A2XX_SQ_TEX_2 0x00000002
2848 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
2849 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0
2850 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
2851 {
2852 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
2853 }
2854 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000
2855 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13
2856 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
2857 {
2858 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
2859 }
2860 #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000
2861 #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26
2862 static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
2863 {
2864 return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK;
2865 }
2866
2867 #define REG_A2XX_SQ_TEX_3 0x00000003
2868 #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001
2869 #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0
2870 static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
2871 {
2872 return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK;
2873 }
2874 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
2875 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
2876 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
2877 {
2878 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
2879 }
2880 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070
2881 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4
2882 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
2883 {
2884 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
2885 }
2886 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380
2887 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7
2888 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
2889 {
2890 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
2891 }
2892 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00
2893 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10
2894 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
2895 {
2896 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
2897 }
2898 #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000
2899 #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13
2900 static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val)
2901 {
2902 return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
2903 }
2904 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
2905 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
2906 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
2907 {
2908 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
2909 }
2910 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000
2911 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21
2912 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
2913 {
2914 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
2915 }
2916 #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000
2917 #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23
2918 static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
2919 {
2920 return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK;
2921 }
2922 #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000
2923 #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25
2924 static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
2925 {
2926 return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK;
2927 }
2928 #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000
2929 #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31
2930 static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
2931 {
2932 return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK;
2933 }
2934
2935 #define REG_A2XX_SQ_TEX_4 0x00000004
2936 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001
2937 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0
2938 static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
2939 {
2940 return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK;
2941 }
2942 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002
2943 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1
2944 static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
2945 {
2946 return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK;
2947 }
2948 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c
2949 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2
2950 static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
2951 {
2952 return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK;
2953 }
2954 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0
2955 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6
2956 static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
2957 {
2958 return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK;
2959 }
2960 #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400
2961 #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800
2962 #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000
2963 #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12
2964 static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
2965 {
2966 return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK;
2967 }
2968 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000
2969 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22
2970 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
2971 {
2972 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK;
2973 }
2974 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000
2975 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27
2976 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
2977 {
2978 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK;
2979 }
2980
2981 #define REG_A2XX_SQ_TEX_5 0x00000005
2982 #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003
2983 #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0
2984 static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
2985 {
2986 return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK;
2987 }
2988 #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004
2989 #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018
2990 #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3
2991 static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
2992 {
2993 return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK;
2994 }
2995 #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0
2996 #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5
2997 static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
2998 {
2999 return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK;
3000 }
3001 #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600
3002 #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9
3003 static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
3004 {
3005 return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK;
3006 }
3007 #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800
3008 #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000
3009 #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12
3010 static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
3011 {
3012 assert(!(val & 0xfff));
3013 return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
3014 }
3015
3016
3017 #endif /* A2XX_XML */