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freedreno/a6xx: Define the register fields for polygon fill mode.
[mesa.git] / src / freedreno / registers / a3xx.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5 <import file="freedreno_copyright.xml"/>
6 <import file="adreno/adreno_common.xml"/>
7 <import file="adreno/adreno_pm4.xml"/>
8
9 <enum name="a3xx_tile_mode">
10 <value name="LINEAR" value="0"/>
11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
14 </enum>
15
16 <enum name="a3xx_state_block_id">
17 <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
18 <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
19 <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
20 <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
21 </enum>
22
23 <enum name="a3xx_cache_opcode">
24 <value name="INVALIDATE" value="1"/>
25 </enum>
26
27 <enum name="a3xx_vtx_fmt">
28 <value name="VFMT_32_FLOAT" value="0x0"/>
29 <value name="VFMT_32_32_FLOAT" value="0x1"/>
30 <value name="VFMT_32_32_32_FLOAT" value="0x2"/>
31 <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
32
33 <value name="VFMT_16_FLOAT" value="0x4"/>
34 <value name="VFMT_16_16_FLOAT" value="0x5"/>
35 <value name="VFMT_16_16_16_FLOAT" value="0x6"/>
36 <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
37
38 <value name="VFMT_32_FIXED" value="0x8"/>
39 <value name="VFMT_32_32_FIXED" value="0x9"/>
40 <value name="VFMT_32_32_32_FIXED" value="0xa"/>
41 <value name="VFMT_32_32_32_32_FIXED" value="0xb"/>
42
43 <value name="VFMT_16_SINT" value="0x10"/>
44 <value name="VFMT_16_16_SINT" value="0x11"/>
45 <value name="VFMT_16_16_16_SINT" value="0x12"/>
46 <value name="VFMT_16_16_16_16_SINT" value="0x13"/>
47 <value name="VFMT_16_UINT" value="0x14"/>
48 <value name="VFMT_16_16_UINT" value="0x15"/>
49 <value name="VFMT_16_16_16_UINT" value="0x16"/>
50 <value name="VFMT_16_16_16_16_UINT" value="0x17"/>
51 <value name="VFMT_16_SNORM" value="0x18"/>
52 <value name="VFMT_16_16_SNORM" value="0x19"/>
53 <value name="VFMT_16_16_16_SNORM" value="0x1a"/>
54 <value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>
55 <value name="VFMT_16_UNORM" value="0x1c"/>
56 <value name="VFMT_16_16_UNORM" value="0x1d"/>
57 <value name="VFMT_16_16_16_UNORM" value="0x1e"/>
58 <value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>
59
60 <!-- seems to be no NORM variants for 32bit.. -->
61 <value name="VFMT_32_UINT" value="0x20"/>
62 <value name="VFMT_32_32_UINT" value="0x21"/>
63 <value name="VFMT_32_32_32_UINT" value="0x22"/>
64 <value name="VFMT_32_32_32_32_UINT" value="0x23"/>
65 <value name="VFMT_32_SINT" value="0x24"/>
66 <value name="VFMT_32_32_SINT" value="0x25"/>
67 <value name="VFMT_32_32_32_SINT" value="0x26"/>
68 <value name="VFMT_32_32_32_32_SINT" value="0x27"/>
69
70 <value name="VFMT_8_UINT" value="0x28"/>
71 <value name="VFMT_8_8_UINT" value="0x29"/>
72 <value name="VFMT_8_8_8_UINT" value="0x2a"/>
73 <value name="VFMT_8_8_8_8_UINT" value="0x2b"/>
74 <value name="VFMT_8_UNORM" value="0x2c"/>
75 <value name="VFMT_8_8_UNORM" value="0x2d"/>
76 <value name="VFMT_8_8_8_UNORM" value="0x2e"/>
77 <value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>
78 <value name="VFMT_8_SINT" value="0x30"/>
79 <value name="VFMT_8_8_SINT" value="0x31"/>
80 <value name="VFMT_8_8_8_SINT" value="0x32"/>
81 <value name="VFMT_8_8_8_8_SINT" value="0x33"/>
82 <value name="VFMT_8_SNORM" value="0x34"/>
83 <value name="VFMT_8_8_SNORM" value="0x35"/>
84 <value name="VFMT_8_8_8_SNORM" value="0x36"/>
85 <value name="VFMT_8_8_8_8_SNORM" value="0x37"/>
86 <value name="VFMT_10_10_10_2_UINT" value="0x38"/>
87 <value name="VFMT_10_10_10_2_UNORM" value="0x39"/>
88 <value name="VFMT_10_10_10_2_SINT" value="0x3a"/>
89 <value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>
90 <value name="VFMT_2_10_10_10_UINT" value="0x3c"/>
91 <value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>
92 <value name="VFMT_2_10_10_10_SINT" value="0x3e"/>
93 <value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>
94
95 <value name="VFMT_NONE" value="0xff"/>
96 </enum>
97
98 <enum name="a3xx_tex_fmt">
99 <value name="TFMT_5_6_5_UNORM" value="0x4"/>
100 <value name="TFMT_5_5_5_1_UNORM" value="0x5"/>
101 <value name="TFMT_4_4_4_4_UNORM" value="0x7"/>
102 <value name="TFMT_Z16_UNORM" value="0x9"/>
103 <value name="TFMT_X8Z24_UNORM" value="0xa"/>
104 <value name="TFMT_Z32_FLOAT" value="0xb"/>
105
106 <!--
107 The NV12 tiled/linear formats seem to require gang'd sampler
108 slots (ie. sampler state N plus N+1) for Y and UV planes.
109 They fetch yuv in single sam instruction, but still require
110 colorspace conversion in the shader.
111 -->
112 <value name="TFMT_UV_64X32" value="0x10"/>
113 <value name="TFMT_VU_64X32" value="0x11"/>
114 <value name="TFMT_Y_64X32" value="0x12"/>
115 <value name="TFMT_NV12_64X32" value="0x13"/>
116 <value name="TFMT_UV_LINEAR" value="0x14"/>
117 <value name="TFMT_VU_LINEAR" value="0x15"/>
118 <value name="TFMT_Y_LINEAR" value="0x16"/>
119 <value name="TFMT_NV12_LINEAR" value="0x17"/>
120 <value name="TFMT_I420_Y" value="0x18"/>
121 <value name="TFMT_I420_U" value="0x1a"/>
122 <value name="TFMT_I420_V" value="0x1b"/>
123
124 <value name="TFMT_ATC_RGB" value="0x20"/>
125 <value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>
126 <value name="TFMT_ETC1" value="0x22"/>
127 <value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>
128
129 <value name="TFMT_DXT1" value="0x24"/>
130 <value name="TFMT_DXT3" value="0x25"/>
131 <value name="TFMT_DXT5" value="0x26"/>
132
133 <value name="TFMT_2_10_10_10_UNORM" value="0x28"/>
134 <value name="TFMT_10_10_10_2_UNORM" value="0x29"/>
135 <value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>
136 <value name="TFMT_11_11_10_FLOAT" value="0x2b"/>
137 <value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA -->
138 <value name="TFMT_L8_UNORM" value="0x2d"/>
139 <value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->
140
141 <!--
142 NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way
143 to float16, float32.. but they seem to use non-standard swizzle too..
144 perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,
145 0xn3 for 1, 2, 3, 4 components respectively..
146
147 Only formats filled in below are the ones that have been observed by
148 the blob or tested.. you can guess what the missing ones are..
149 -->
150
151 <value name="TFMT_8_UNORM" value="0x30"/> <!-- GL_LUMINANCE -->
152 <value name="TFMT_8_8_UNORM" value="0x31"/>
153 <value name="TFMT_8_8_8_UNORM" value="0x32"/>
154 <value name="TFMT_8_8_8_8_UNORM" value="0x33"/>
155
156 <value name="TFMT_8_SNORM" value="0x34"/>
157 <value name="TFMT_8_8_SNORM" value="0x35"/>
158 <value name="TFMT_8_8_8_SNORM" value="0x36"/>
159 <value name="TFMT_8_8_8_8_SNORM" value="0x37"/>
160
161 <value name="TFMT_8_UINT" value="0x38"/>
162 <value name="TFMT_8_8_UINT" value="0x39"/>
163 <value name="TFMT_8_8_8_UINT" value="0x3a"/>
164 <value name="TFMT_8_8_8_8_UINT" value="0x3b"/>
165
166 <value name="TFMT_8_SINT" value="0x3c"/>
167 <value name="TFMT_8_8_SINT" value="0x3d"/>
168 <value name="TFMT_8_8_8_SINT" value="0x3e"/>
169 <value name="TFMT_8_8_8_8_SINT" value="0x3f"/>
170
171 <value name="TFMT_16_FLOAT" value="0x40"/>
172 <value name="TFMT_16_16_FLOAT" value="0x41"/>
173 <!-- TFMT_FLOAT_16_16_16 -->
174 <value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>
175
176 <value name="TFMT_16_UINT" value="0x44"/>
177 <value name="TFMT_16_16_UINT" value="0x45"/>
178 <value name="TFMT_16_16_16_16_UINT" value="0x47"/>
179
180 <value name="TFMT_16_SINT" value="0x48"/>
181 <value name="TFMT_16_16_SINT" value="0x49"/>
182 <value name="TFMT_16_16_16_16_SINT" value="0x4b"/>
183
184 <value name="TFMT_16_UNORM" value="0x4c"/>
185 <value name="TFMT_16_16_UNORM" value="0x4d"/>
186 <value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>
187
188 <value name="TFMT_16_SNORM" value="0x50"/>
189 <value name="TFMT_16_16_SNORM" value="0x51"/>
190 <value name="TFMT_16_16_16_16_SNORM" value="0x53"/>
191
192 <value name="TFMT_32_FLOAT" value="0x54"/>
193 <value name="TFMT_32_32_FLOAT" value="0x55"/>
194 <!-- TFMT_32_32_32_FLOAT -->
195 <value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>
196
197 <value name="TFMT_32_UINT" value="0x58"/>
198 <value name="TFMT_32_32_UINT" value="0x59"/>
199 <value name="TFMT_32_32_32_32_UINT" value="0x5b"/>
200
201 <value name="TFMT_32_SINT" value="0x5c"/>
202 <value name="TFMT_32_32_SINT" value="0x5d"/>
203 <value name="TFMT_32_32_32_32_SINT" value="0x5f"/>
204
205 <value name="TFMT_2_10_10_10_UINT" value="0x60"/>
206 <value name="TFMT_10_10_10_2_UINT" value="0x61"/>
207
208 <value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>
209 <value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>
210 <value name="TFMT_ETC2_R11_SNORM" value="0x72"/>
211 <value name="TFMT_ETC2_R11_UNORM" value="0x73"/>
212 <value name="TFMT_ETC2_RGBA8" value="0x74"/>
213 <value name="TFMT_ETC2_RGB8A1" value="0x75"/>
214 <value name="TFMT_ETC2_RGB8" value="0x76"/>
215
216 <value name="TFMT_NONE" value="0xff"/>
217 </enum>
218
219 <enum name="a3xx_tex_fetchsize">
220 <doc>
221 Size pixel to fetch, in bytes. Doesn't seem to be required, setting
222 it to 0x0 seems to work ok, but may be less optimal.
223 </doc>
224 <value name="TFETCH_DISABLE" value="0"/>
225 <value name="TFETCH_1_BYTE" value="1"/>
226 <value name="TFETCH_2_BYTE" value="2"/>
227 <value name="TFETCH_4_BYTE" value="3"/>
228 <value name="TFETCH_8_BYTE" value="4"/>
229 <value name="TFETCH_16_BYTE" value="5"/>
230 </enum>
231
232 <enum name="a3xx_color_fmt">
233 <value name="RB_R5G6B5_UNORM" value="0x00"/>
234 <value name="RB_R5G5B5A1_UNORM" value="0x01"/>
235 <value name="RB_R4G4B4A4_UNORM" value="0x03"/>
236 <value name="RB_R8G8B8_UNORM" value="0x04"/>
237 <value name="RB_R8G8B8A8_UNORM" value="0x08"/>
238 <value name="RB_R8G8B8A8_SNORM" value="0x09"/>
239 <value name="RB_R8G8B8A8_UINT" value="0x0a"/>
240 <value name="RB_R8G8B8A8_SINT" value="0x0b"/>
241 <value name="RB_R8G8_UNORM" value="0x0c"/>
242 <value name="RB_R8G8_SNORM" value="0x0d"/>
243 <value name="RB_R8G8_UINT" value="0x0e"/>
244 <value name="RB_R8G8_SINT" value="0x0f"/>
245 <value name="RB_R10G10B10A2_UNORM" value="0x10"/>
246 <value name="RB_A2R10G10B10_UNORM" value="0x11"/>
247 <value name="RB_R10G10B10A2_UINT" value="0x12"/>
248 <value name="RB_A2R10G10B10_UINT" value="0x13"/>
249
250 <value name="RB_A8_UNORM" value="0x14"/>
251 <value name="RB_R8_UNORM" value="0x15"/>
252
253 <value name="RB_R16_FLOAT" value="0x18"/>
254 <value name="RB_R16G16_FLOAT" value="0x19"/>
255 <value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->
256 <value name="RB_R11G11B10_FLOAT" value="0x1c"/>
257
258 <value name="RB_R16_SNORM" value="0x20"/>
259 <value name="RB_R16G16_SNORM" value="0x21"/>
260 <value name="RB_R16G16B16A16_SNORM" value="0x23"/>
261
262 <value name="RB_R16_UNORM" value="0x24"/>
263 <value name="RB_R16G16_UNORM" value="0x25"/>
264 <value name="RB_R16G16B16A16_UNORM" value="0x27"/>
265
266 <value name="RB_R16_SINT" value="0x28"/>
267 <value name="RB_R16G16_SINT" value="0x29"/>
268 <value name="RB_R16G16B16A16_SINT" value="0x2b"/>
269
270 <value name="RB_R16_UINT" value="0x2c"/>
271 <value name="RB_R16G16_UINT" value="0x2d"/>
272 <value name="RB_R16G16B16A16_UINT" value="0x2f"/>
273
274 <value name="RB_R32_FLOAT" value="0x30"/>
275 <value name="RB_R32G32_FLOAT" value="0x31"/>
276 <value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->
277
278 <value name="RB_R32_SINT" value="0x34"/>
279 <value name="RB_R32G32_SINT" value="0x35"/>
280 <value name="RB_R32G32B32A32_SINT" value="0x37"/>
281
282 <value name="RB_R32_UINT" value="0x38"/>
283 <value name="RB_R32G32_UINT" value="0x39"/>
284 <value name="RB_R32G32B32A32_UINT" value="0x3b"/>
285
286 <value name="RB_NONE" value="0xff"/>
287 </enum>
288
289 <enum name="a3xx_cp_perfcounter_select">
290 <value value="0x00" name="CP_ALWAYS_COUNT"/>
291 <value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>
292 <value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>
293 <value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>
294 <value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>
295 <value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>
296 <value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>
297 <value value="0x0c" name="CP_RESERVED_12"/>
298 <value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>
299 <value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>
300 <value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>
301 <value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>
302 <value value="0x11" name="CP_RESERVED_17"/>
303 <value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>
304 <value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>
305 <value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>
306 <value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>
307 <value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>
308 <value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>
309 <value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>
310 <value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>
311 <value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>
312 <value value="0x29" name="CP_ME_BUSY_CLOCKS"/>
313 <value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>
314 <value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>
315 <value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>
316 <value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>
317 <value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>
318 <value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>
319 <value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>
320 </enum>
321
322 <enum name="a3xx_gras_tse_perfcounter_select">
323 <value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>
324 <value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>
325 <value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>
326 <value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>
327 <value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>
328 <value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>
329 <value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>
330 <value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>
331 <value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>
332 <value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>
333 <value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>
334 <value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>
335 <value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>
336 <value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>
337 <value value="0x0e" name="GRAS_TSERASPERF_STALL"/>
338 </enum>
339
340 <enum name="a3xx_gras_ras_perfcounter_select">
341 <value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>
342 <value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>
343 <value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>
344 <value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>
345 <value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>
346 <value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>
347 <value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>
348 </enum>
349
350 <enum name="a3xx_hlsq_perfcounter_select">
351 <value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>
352 <value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>
353 <value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>
354 <value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>
355 <value value="0x04" name="HLSQ_PERF_TP_STATE"/>
356 <value value="0x05" name="HLSQ_PERF_QUADS"/>
357 <value value="0x06" name="HLSQ_PERF_PIXELS"/>
358 <value value="0x07" name="HLSQ_PERF_VERTICES"/>
359 <value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>
360 <value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>
361 <value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>
362 <value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>
363 <value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>
364 <value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>
365 <value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>
366 <value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>
367 <value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>
368 <value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>
369 <value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>
370 <value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>
371 <value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>
372 <value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>
373 <value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>
374 <value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>
375 <value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>
376 <value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>
377 <value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>
378 <value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>
379 <value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>
380 </enum>
381
382 <enum name="a3xx_pc_perfcounter_select">
383 <value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>
384 <value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>
385 <value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>
386 <value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>
387 <value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>
388 <value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>
389 <value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>
390 <value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>
391 <value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>
392 <value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>
393 <value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>
394 <value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>
395 <value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>
396 </enum>
397
398 <enum name="a3xx_rb_perfcounter_select">
399 <value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>
400 <value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>
401 <value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>
402 <value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>
403 <value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>
404 <value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>
405 <value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>
406 <value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>
407 <value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>
408 <value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>
409 <value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>
410 <value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>
411 <value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>
412 <value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>
413 <value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>
414 <value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>
415 <value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>
416 </enum>
417
418 <enum name="a3xx_rbbm_perfcounter_select">
419 <value value="0" name="RBBM_ALAWYS_ON"/>
420 <value value="1" name="RBBM_VBIF_BUSY"/>
421 <value value="2" name="RBBM_TSE_BUSY"/>
422 <value value="3" name="RBBM_RAS_BUSY"/>
423 <value value="4" name="RBBM_PC_DCALL_BUSY"/>
424 <value value="5" name="RBBM_PC_VSD_BUSY"/>
425 <value value="6" name="RBBM_VFD_BUSY"/>
426 <value value="7" name="RBBM_VPC_BUSY"/>
427 <value value="8" name="RBBM_UCHE_BUSY"/>
428 <value value="9" name="RBBM_VSC_BUSY"/>
429 <value value="10" name="RBBM_HLSQ_BUSY"/>
430 <value value="11" name="RBBM_ANY_RB_BUSY"/>
431 <value value="12" name="RBBM_ANY_TEX_BUSY"/>
432 <value value="13" name="RBBM_ANY_USP_BUSY"/>
433 <value value="14" name="RBBM_ANY_MARB_BUSY"/>
434 <value value="15" name="RBBM_ANY_ARB_BUSY"/>
435 <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
436 <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
437 <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
438 <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
439 <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
440 <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
441 <value value="22" name="RBBM_RBBM_STATUS_MASKED"/>
442 </enum>
443
444 <enum name="a3xx_sp_perfcounter_select">
445 <value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>
446 <value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>
447 <value value="0x02" name="SP_LM_ATOMICS"/>
448 <value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>
449 <value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>
450 <value value="0x05" name="SP_UCHE_ATOMICS"/>
451 <value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>
452 <value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>
453 <value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>
454 <value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>
455 <value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>
456 <value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>
457 <value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>
458 <value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>
459 <value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>
460 <value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>
461 <value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>
462 <value value="0x11" name="SP_VS_INSTRUCTIONS"/>
463 <value value="0x12" name="SP_FS_INSTRUCTIONS"/>
464 <value value="0x13" name="SP_ADDR_LOCK_COUNT"/>
465 <value value="0x14" name="SP_UCHE_READ_TRANS"/>
466 <value value="0x15" name="SP_UCHE_WRITE_TRANS"/>
467 <value value="0x16" name="SP_EXPORT_VPC_TRANS"/>
468 <value value="0x17" name="SP_EXPORT_RB_TRANS"/>
469 <value value="0x18" name="SP_PIXELS_KILLED"/>
470 <value value="0x19" name="SP_ICL1_REQUESTS"/>
471 <value value="0x1a" name="SP_ICL1_MISSES"/>
472 <value value="0x1b" name="SP_ICL0_REQUESTS"/>
473 <value value="0x1c" name="SP_ICL0_MISSES"/>
474 <value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>
475 <value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>
476 <value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>
477 <value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>
478 <value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>
479 <value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>
480 <value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>
481 <value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>
482 </enum>
483
484 <enum name="a3xx_tp_perfcounter_select">
485 <value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>
486 <value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>
487 <value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>
488 <value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>
489 <value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>
490 <value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>
491 <value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>
492 <value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>
493 <value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>
494 <value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>
495 <value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>
496 <value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>
497 <value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>
498 <value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>
499 <value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>
500 <value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>
501 <value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>
502 <value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>
503 <value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>
504 <value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>
505 <value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>
506 <value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>
507 <value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>
508 <value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>
509 <value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>
510 <value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>
511 <value value="0x1a" name="TPL1_TPPERF_LATENCY"/>
512 <value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>
513 </enum>
514
515 <enum name="a3xx_vfd_perfcounter_select">
516 <value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>
517 <value value="1" name="VFD_PERF_UCHE_TRANS"/>
518 <value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>
519 <value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>
520 <value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>
521 <value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>
522 <value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>
523 <value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>
524 <value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>
525 <value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>
526 </enum>
527
528 <enum name="a3xx_vpc_perfcounter_select">
529 <value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>
530 <value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>
531 <value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>
532 <value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>
533 <value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>
534 <value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>
535 </enum>
536
537 <enum name="a3xx_uche_perfcounter_select">
538 <value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>
539 <value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>
540 <value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>
541 <value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>
542 <value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>
543 <value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>
544 <value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>
545 <value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>
546 <value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>
547 <value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>
548 <value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>
549 <value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>
550 <value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>
551 <value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>
552 <value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>
553 <value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>
554 <value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>
555 <value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>
556 </enum>
557
558 <enum name="a3xx_intp_mode">
559 <value name="SMOOTH" value="0"/>
560 <value name="FLAT" value="1"/>
561 <value name="ZERO" value="2"/>
562 <value name="ONE" value="3"/>
563 </enum>
564
565 <enum name="a3xx_repl_mode">
566 <value name="S" value="1"/>
567 <value name="T" value="2"/>
568 <value name="ONE_T" value="3"/>
569 </enum>
570
571 <domain name="A3XX" width="32">
572 <!-- RBBM registers -->
573 <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
574 <reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>
575 <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
576 <reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>
577 <reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>
578 <reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>
579 <reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>
580 <reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>
581 <reg32 offset="0x0022" name="RBBM_AHB_CMD"/>
582 <reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>
583 <reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>
584 <reg32 offset="0x0030" name="RBBM_STATUS">
585 <bitfield name="HI_BUSY" pos="0" type="boolean"/>
586 <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
587 <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
588 <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
589 <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
590 <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
591 <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
592 <bitfield name="RB_BUSY" pos="18" type="boolean"/>
593 <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
594 <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
595 <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
596 <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
597 <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
598 <bitfield name="SP_BUSY" pos="24" type="boolean"/>
599 <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
600 <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
601 <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
602 <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
603 <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
604 <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
605 <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
606 </reg32>
607 <!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->
608 <reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>
609 <reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
610 <reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>
611 <reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>
612 <reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>
613 <reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>
614 <reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>
615
616 <bitset name="A3XX_INT0">
617 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
618 <bitfield name="RBBM_AHB_ERROR" pos="1"/>
619 <bitfield name="RBBM_REG_TIMEOUT" pos="2"/>
620 <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/>
621 <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/>
622 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5"/>
623 <bitfield name="VFD_ERROR" pos="6"/>
624 <bitfield name="CP_SW_INT" pos="7"/>
625 <bitfield name="CP_T0_PACKET_IN_IB" pos="8"/>
626 <bitfield name="CP_OPCODE_ERROR" pos="9"/>
627 <bitfield name="CP_RESERVED_BIT_ERROR" pos="10"/>
628 <bitfield name="CP_HW_FAULT" pos="11"/>
629 <bitfield name="CP_DMA" pos="12"/>
630 <bitfield name="CP_IB2_INT" pos="13"/>
631 <bitfield name="CP_IB1_INT" pos="14"/>
632 <bitfield name="CP_RB_INT" pos="15"/>
633 <bitfield name="CP_REG_PROTECT_FAULT" pos="16"/>
634 <bitfield name="CP_RB_DONE_TS" pos="17"/>
635 <bitfield name="CP_VS_DONE_TS" pos="18"/>
636 <bitfield name="CP_PS_DONE_TS" pos="19"/>
637 <bitfield name="CACHE_FLUSH_TS" pos="20"/>
638 <bitfield name="CP_AHB_ERROR_HALT" pos="21"/>
639 <bitfield name="MISC_HANG_DETECT" pos="24"/>
640 <bitfield name="UCHE_OOB_ACCESS" pos="25"/>
641 </bitset>
642
643
644 <!--
645 set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare
646 to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
647 way for fw to raise and irq:
648 -->
649 <reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>
650 <reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>
651 <reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>
652 <reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>
653 <reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">
654 <bitfield name="ENABLE" pos="0" type="boolean"/>
655 </reg32>
656 <reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>
657 <reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>
658 <reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
659 <reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
660 <reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>
661 <reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>
662 <reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>
663 <reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>
664 <reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>
665 <reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>
666 <reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>
667 <reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>
668 <reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>
669 <reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>
670 <reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>
671 <reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>
672 <reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>
673 <reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>
674 <reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>
675 <reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>
676 <reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>
677 <reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>
678 <reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>
679 <reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>
680 <reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>
681 <reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>
682 <reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>
683 <reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>
684 <reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>
685 <reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>
686 <reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>
687 <reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>
688 <reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>
689 <reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>
690 <reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>
691 <reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>
692 <reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>
693 <reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>
694 <reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>
695 <reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>
696 <reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>
697 <reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>
698 <reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>
699 <reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>
700 <reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>
701 <reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>
702 <reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>
703 <reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>
704 <reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>
705 <reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>
706 <reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>
707 <reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>
708 <reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>
709 <reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>
710 <reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>
711 <reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>
712 <reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>
713 <reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>
714 <reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>
715 <reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>
716 <reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>
717 <reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>
718 <reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>
719 <reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>
720 <reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>
721 <reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>
722 <reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>
723 <reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>
724 <reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>
725 <reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>
726 <reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>
727 <reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>
728 <reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>
729 <reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>
730 <reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>
731 <reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>
732 <reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>
733 <reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>
734 <reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>
735 <reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>
736 <reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>
737 <reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>
738 <reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>
739 <reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>
740 <reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>
741 <reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>
742 <reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>
743 <reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>
744 <reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>
745 <reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>
746 <reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>
747 <reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>
748 <reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>
749 <reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>
750 <reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>
751 <reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>
752 <reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>
753 <reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>
754 <reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>
755 <reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>
756
757 <!-- CP registers -->
758 <reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>
759 <reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>
760 <reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>
761 <reg32 offset="0x01cd" name="CP_ROQ_DATA"/>
762 <reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>
763 <reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>
764 <reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>
765 <!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->
766 <reg32 offset="0x01da" name="CP_MEQ_ADDR"/>
767 <reg32 offset="0x01db" name="CP_MEQ_DATA"/>
768 <reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>
769 <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
770
771 <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>
772 <reg32 offset="0x045c" name="CP_HW_FAULT"/>
773 <reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>
774 <reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>
775 <array offset="0x0460" name="CP_PROTECT" stride="1" length="16">
776 <reg32 offset="0x0" name="REG"/>
777 </array>
778 <reg32 offset="0x054d" name="CP_AHB_FAULT"/>
779
780 <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>
781 <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>
782 <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
783
784 <!-- these I guess or either SP or HLSQ since related to shader core setup: -->
785 <reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">
786 <doc>
787 The pair of MEM_SIZE/ADDR registers get programmed
788 in sequence with the size/addr of each buffer.
789 </doc>
790 </reg32>
791 <reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>
792
793 <!-- GRAS registers -->
794 <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
795 <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/> <!-- is it more bits? -->
796 <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
797 <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
798 <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
799 <bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>
800 <bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>
801 <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">
802 <doc>aka clip_halfz</doc>
803 </bitfield>
804 <!-- set when gl_FragCoord.z is enabled in frag shader: -->
805 <bitfield name="ZCOORD" pos="23" type="boolean"/>
806 <bitfield name="WCOORD" pos="24" type="boolean"/>
807 <!-- set when frag shader writes z (so early z test disabled: -->
808 <bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>
809 <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
810 </reg32>
811 <reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">
812 <bitfield name="HORZ" low="0" high="9" type="uint"/>
813 <bitfield name="VERT" low="10" high="19" type="uint"/>
814 </reg32>
815 <reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>
816 <reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>
817 <reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>
818 <reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>
819 <reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>
820 <reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>
821 <reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">
822 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
823 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
824 </reg32>
825 <reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
826 <reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">
827 <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
828 <doc>range of -8.0 to 8.0</doc>
829 </reg32>
830 <reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">
831 <doc>range of -512.0 to 512.0</doc>
832 </reg32>
833 <reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">
834 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
835 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
836 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
837 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
838 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
839 </reg32>
840 <reg32 offset="0x2072" name="GRAS_SC_CONTROL">
841 <!-- complete wild-ass-guess for sizes of these bitfields.. -->
842 <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
843 <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
844 <bitfield name="RASTER_MODE" low="12" high="15"/>
845 </reg32>
846
847 <reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
848 <reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
849 <reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
850 <reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
851
852 <!-- RB registers -->
853 <reg32 offset="0x20c0" name="RB_MODE_CONTROL">
854 <!-- guess on the # of bits here.. -->
855 <bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>
856 <doc>
857 RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS
858 </doc>
859 <bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>
860 <bitfield name="MRT" low="12" high="13" type="uint">
861 <doc>render targets - 1</doc>
862 </bitfield>
863 <bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>
864 <bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>
865 </reg32>
866 <reg32 offset="0x20c1" name="RB_RENDER_CONTROL">
867 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
868 <bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>
869 <bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>
870 <!-- set when gl_FrontFacing is accessed in frag shader: -->
871 <bitfield name="FACENESS" pos="3" type="boolean"/>
872 <bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>
873 <bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>
874 <!--
875 ENABLE_GMEM not set on mem2gmem.. so possibly it is actually
876 controlling blend or readback from GMEM??
877 -->
878 <bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
879 <bitfield name="COORD_MASK" low="14" high="17" type="hex"/>
880 <bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
881 <bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
882 <bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
883 <bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>
884 <bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>
885 <bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>
886 </reg32>
887 <reg32 offset="0x20c2" name="RB_MSAA_CONTROL">
888 <bitfield name="DISABLE" pos="10" type="boolean"/>
889 <bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>
890 <bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>
891 </reg32>
892 <reg32 offset="0x20c3" name="RB_ALPHA_REF">
893 <bitfield name="UINT" low="8" high="15" type="hex"/>
894 <bitfield name="FLOAT" low="16" high="31" type="float"/>
895 </reg32>
896 <array offset="0x20c4" name="RB_MRT" stride="4" length="4">
897 <reg32 offset="0x0" name="CONTROL">
898 <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
899 <!-- both these bits seem to get set when enabling GL_BLEND.. -->
900 <bitfield name="BLEND" pos="4" type="boolean"/>
901 <bitfield name="BLEND2" pos="5" type="boolean"/>
902 <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
903 <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
904 <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
905 </reg32>
906 <reg32 offset="0x1" name="BUF_INFO">
907 <bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>
908 <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>
909 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
910 <bitfield name="COLOR_SRGB" pos="14" type="boolean"/>
911 <doc>
912 Pitch (actually, appears to be pitch in bytes, so really is a stride)
913 in GMEM, so pitch of the current tile.
914 </doc>
915 <bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>
916 </reg32>
917 <reg32 offset="0x2" name="BUF_BASE">
918 <doc>offset into GMEM (or system memory address in bypass mode)</doc>
919 <bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>
920 </reg32>
921 <reg32 offset="0x3" name="BLEND_CONTROL">
922 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
923 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
924 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
925 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
926 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
927 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
928 <bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>
929 </reg32>
930 </array>
931
932 <reg32 offset="0x20e4" name="RB_BLEND_RED">
933 <bitfield name="UINT" low="0" high="7" type="hex"/>
934 <bitfield name="FLOAT" low="16" high="31" type="float"/>
935 </reg32>
936 <reg32 offset="0x20e5" name="RB_BLEND_GREEN">
937 <bitfield name="UINT" low="0" high="7" type="hex"/>
938 <bitfield name="FLOAT" low="16" high="31" type="float"/>
939 </reg32>
940 <reg32 offset="0x20e6" name="RB_BLEND_BLUE">
941 <bitfield name="UINT" low="0" high="7" type="hex"/>
942 <bitfield name="FLOAT" low="16" high="31" type="float"/>
943 </reg32>
944 <reg32 offset="0x20e7" name="RB_BLEND_ALPHA">
945 <bitfield name="UINT" low="0" high="7" type="hex"/>
946 <bitfield name="FLOAT" low="16" high="31" type="float"/>
947 </reg32>
948
949 <reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>
950 <reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>
951 <reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>
952 <reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>
953 <reg32 offset="0x20ec" name="RB_COPY_CONTROL">
954 <!-- not sure # of bits -->
955 <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
956 <bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>
957 <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
958 <bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>
959 <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
960 <bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->
961 <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
962 </reg32>
963 <reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">
964 <bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>
965 </reg32>
966 <reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">
967 <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
968 <!-- not actually sure about max pitch... -->
969 <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
970 </reg32>
971 <reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">
972 <bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>
973 <bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>
974 <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
975 <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
976 <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
977 <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
978 </reg32>
979 <reg32 offset="0x2100" name="RB_DEPTH_CONTROL">
980 <!--
981 guessing that this matches a2xx with the stencil fields
982 moved out into RB_STENCIL_CONTROL?
983 -->
984 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
985 <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
986 <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
987 <bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
988 <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
989 <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
990 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
991 <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/>
992 </reg32>
993 <reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
994 <doc>seems to be always set to 0x00000000</doc>
995 </reg32>
996 <reg32 offset="0x2102" name="RB_DEPTH_INFO">
997 <bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>
998 <doc>
999 DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
1000 bin_w * bin_h / 1024 (possible rounded up to multiple of
1001 something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
1002 80.. so maybe it needs to be multiple of 8??
1003 </doc>
1004 <bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>
1005 </reg32>
1006 <reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">
1007 <doc>
1008 Pitch of depth buffer or combined depth+stencil buffer
1009 in z24s8 cases.
1010 </doc>
1011 </reg32>
1012 <reg32 offset="0x2104" name="RB_STENCIL_CONTROL">
1013 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1014 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
1015 <!--
1016 set for stencil operations that require read from stencil
1017 buffer, but not for example for stencil clear (which does
1018 not require read).. so guessing this is analogous to
1019 READ_DEST_ENABLE for color buffer..
1020 -->
1021 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
1022 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
1023 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
1024 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
1025 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1026 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1027 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1028 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1029 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1030 </reg32>
1031 <reg32 offset="0x2105" name="RB_STENCIL_CLEAR">
1032 <doc>seems to be always set to 0x00000000</doc>
1033 </reg32>
1034 <reg32 offset="0x2106" name="RB_STENCIL_INFO">
1035 <doc>Base address for stencil when not using interleaved depth/stencil</doc>
1036 <bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>
1037 </reg32>
1038 <reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">
1039 <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
1040 </reg32>
1041 <reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1042 <reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1043 <!-- VSC == visibility stream c?? -->
1044 <reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">
1045 <doc>seems to be set to 0x00000002 during binning pass</doc>
1046 <bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>
1047 </reg32>
1048 <reg32 offset="0x210e" name="RB_WINDOW_OFFSET">
1049 <doc>X/Y offset of current bin</doc>
1050 <bitfield name="X" low="0" high="15" type="uint"/>
1051 <bitfield name="Y" low="16" high="31" type="uint"/>
1052 </reg32>
1053 <reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">
1054 <bitfield name="RESET" pos="0" type="boolean"/>
1055 <bitfield name="COPY" pos="1" type="boolean"/>
1056 </reg32>
1057 <reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>
1058 <reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>
1059 <reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>
1060
1061 <!-- PC registers -->
1062 <reg32 offset="0x21e1" name="VGT_BIN_BASE">
1063 <doc>
1064 seems to be where firmware writes BIN_DATA_ADDR from
1065 CP_SET_BIN_DATA packet.. probably should be called
1066 PC_BIN_BASE (just using name from yamato for now)
1067 </doc>
1068 </reg32>
1069 <reg32 offset="0x21e2" name="VGT_BIN_SIZE">
1070 <doc>probably should be PC_BIN_SIZE</doc>
1071 </reg32>
1072 <reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">
1073 <doc>SIZE is current pipe width * height (in tiles)</doc>
1074 <bitfield name="SIZE" low="16" high="21" type="uint"/>
1075 <doc>
1076 N is some sort of slot # between 0..(SIZE-1). In case
1077 multiple tiles use same pipe, each tile gets unique slot #
1078 </doc>
1079 <bitfield name="N" low="22" high="26" type="uint"/>
1080 </reg32>
1081 <reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>
1082 <reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">
1083 <doc>
1084 STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4
1085 (but, in cases where you'd expect 1, the blob driver uses
1086 2, so possibly 0 (no varying) or minimum of 2)
1087 </doc>
1088 <bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>
1089 <bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
1090 <bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
1091 <bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>
1092 <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
1093 <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
1094 <!-- PSIZE bit set if gl_PointSize written: -->
1095 <bitfield name="PSIZE" pos="26" type="boolean"/>
1096 </reg32>
1097 <reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>
1098
1099 <!-- HLSQ registers -->
1100 <bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">
1101 <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1102 <bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>
1103 <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
1104 </bitset>
1105 <bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">
1106 <!-- are these a3xx_regid?? -->
1107 <bitfield name="STARTENTRY" low="0" high="8"/>
1108 <bitfield name="ENDENTRY" low="16" high="24"/>
1109 </bitset>
1110
1111 <reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">
1112 <bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>
1113 <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
1114 <bitfield name="COMPUTEMODE" pos="8" type="boolean"/>
1115 <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
1116 <bitfield name="RESERVED2" pos="10" type="boolean"/>
1117 <bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>
1118 <bitfield name="FSONLYTEX" pos="25" type="boolean"/>
1119 <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
1120 <bitfield name="CONSTMODE" pos="27" type="uint"/>
1121 <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
1122 <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
1123 <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
1124 <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
1125 </reg32>
1126 <reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">
1127 <bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>
1128 <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
1129 <bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>
1130 <bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>
1131 </reg32>
1132 <reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">
1133 <bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>
1134 <bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>
1135 <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
1136 </reg32>
1137 <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
1138 <!-- register loaded with position (bary.f, gl_FragCoord, etc) -->
1139 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1140 </reg32>
1141 <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
1142 <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
1143 <reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
1144 <reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
1145 <reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">
1146 <bitfield name="WORKDIM" low="0" high="1" type="uint"/>
1147 <bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>
1148 <bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>
1149 <bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>
1150 </reg32>
1151 <array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">
1152 <doc>indexed by dimension</doc>
1153 <reg32 offset="0" name="SIZE" type="uint"/>
1154 <reg32 offset="1" name="OFFSET" type="uint"/>
1155 </array>
1156 <reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>
1157 <reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>
1158 <reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>
1159 <array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">
1160 <doc>indexed by dimension, global_size / local_size</doc>
1161 <reg32 offset="0" name="RATIO" type="uint"/>
1162 </array>
1163 <reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>
1164 <reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>
1165 <reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>
1166
1167 <!-- VFD registers -->
1168 <reg32 offset="0x2240" name="VFD_CONTROL_0">
1169 <doc>
1170 TOTALATTRTOVS is # of attributes to vertex shader, in register
1171 slots (ie. vec4+vec3 -> 7)
1172 </doc>
1173 <bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>
1174 <bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>
1175 <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
1176 <bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>
1177 <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
1178 <bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>
1179 </reg32>
1180 <reg32 offset="0x2241" name="VFD_CONTROL_1">
1181 <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
1182 <bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>
1183 <bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>
1184 <bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>
1185 <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
1186 <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
1187 </reg32>
1188 <reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>
1189 <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
1190 <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
1191 <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
1192 <array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
1193 <reg32 offset="0x0" name="INSTR_0">
1194 <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
1195 <bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>
1196 <bitfield name="INSTANCED" pos="16" type="boolean"/>
1197 <bitfield name="SWITCHNEXT" pos="17" type="boolean"/>
1198 <bitfield name="INDEXCODE" low="18" high="23" type="uint"/>
1199 <bitfield name="STEPRATE" low="24" high="31" type="uint"/>
1200 </reg32>
1201 <reg32 offset="0x1" name="INSTR_1"/>
1202 </array>
1203 <array offset="0x2266" name="VFD_DECODE" stride="1" length="16">
1204 <reg32 offset="0x0" name="INSTR">
1205 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
1206 <!-- not sure if this is a bit flag and another flag above it, or?? -->
1207 <bitfield name="CONSTFILL" pos="4" type="boolean"/>
1208 <bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>
1209 <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
1210 <bitfield name="INT" pos="20" type="boolean"/>
1211 <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
1212 <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
1213 <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
1214 <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
1215 <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
1216 </reg32>
1217 </array>
1218 <reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">
1219 <bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>
1220 <!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->
1221 <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
1222 </reg32>
1223
1224 <!-- VPC registers -->
1225 <reg32 offset="0x2280" name="VPC_ATTR">
1226 <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
1227 <!-- PSIZE bit set if gl_PointSize written: -->
1228 <bitfield name="PSIZE" pos="9" type="boolean"/>
1229 <bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>
1230 <bitfield name="LMSIZE" low="28" high="31" type="uint"/>
1231 </reg32>
1232 <reg32 offset="0x2281" name="VPC_PACK">
1233 <!-- these are always seem to be set to same as TOTALATTR -->
1234 <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
1235 <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
1236 </reg32>
1237 <!--
1238 varying interpolate mode. One field per scalar/component
1239 (since varying slots are scalar, so things don't have to
1240 be aligned to vec4).
1241 4 regs * 16 scalar components each => 16 vec4
1242 -->
1243 <array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">
1244 <reg32 offset="0x0" name="MODE">
1245 <bitfield name="C0" low="0" high="1" type="a3xx_intp_mode"/>
1246 <bitfield name="C1" low="2" high="3" type="a3xx_intp_mode"/>
1247 <bitfield name="C2" low="4" high="5" type="a3xx_intp_mode"/>
1248 <bitfield name="C3" low="6" high="7" type="a3xx_intp_mode"/>
1249 <bitfield name="C4" low="8" high="9" type="a3xx_intp_mode"/>
1250 <bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>
1251 <bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>
1252 <bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>
1253 <bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>
1254 <bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>
1255 <bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>
1256 <bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>
1257 <bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>
1258 <bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>
1259 <bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>
1260 <bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>
1261 </reg32>
1262 </array>
1263 <array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">
1264 <reg32 offset="0x0" name="MODE">
1265 <bitfield name="C0" low="0" high="1" type="a3xx_repl_mode"/>
1266 <bitfield name="C1" low="2" high="3" type="a3xx_repl_mode"/>
1267 <bitfield name="C2" low="4" high="5" type="a3xx_repl_mode"/>
1268 <bitfield name="C3" low="6" high="7" type="a3xx_repl_mode"/>
1269 <bitfield name="C4" low="8" high="9" type="a3xx_repl_mode"/>
1270 <bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>
1271 <bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>
1272 <bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>
1273 <bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>
1274 <bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>
1275 <bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>
1276 <bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>
1277 <bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>
1278 <bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>
1279 <bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>
1280 <bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>
1281 </reg32>
1282 </array>
1283 <reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>
1284 <reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>
1285
1286 <!-- SP registers -->
1287 <bitset name="a3xx_vs_fs_length_reg" inline="yes">
1288 <bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>
1289 </bitset>
1290
1291 <bitset name="sp_vs_fs_obj_offset_reg" inline="yes">
1292 <bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>
1293 <doc>
1294 From register spec:
1295 SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
1296 start offset in on chip RAM,
1297 128bit aligned
1298 </doc>
1299 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1300 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1301 </bitset>
1302
1303 <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
1304 <!-- this bit is set during resolve pass: -->
1305 <bitfield name="RESOLVE" pos="16" type="boolean"/>
1306 <bitfield name="CONSTMODE" pos="18" type="uint"/>
1307 <bitfield name="BINNING" pos="19" type="boolean"/>
1308 <bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>
1309 <!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->
1310 <bitfield name="L0MODE" low="22" high="23" type="uint"/>
1311 </reg32>
1312 <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">
1313 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1314 <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
1315 <!-- maybe CACHEINVALID is two bits?? -->
1316 <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1317 <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
1318 <doc>
1319 The full/half register footprint is in units of four components,
1320 so if r0.x is used, that counts as all of r0.[xyzw] as used.
1321 There are separate full/half register footprint values as the
1322 full and half registers are independent (not overlapping).
1323 Presumably the thread scheduler hardware allocates the full/half
1324 register names from the actual physical register file and
1325 handles the register renaming.
1326 </doc>
1327 <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1328 <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1329 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1330 <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1331 <doc>
1332 From regspec:
1333 SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
1334 If bit31 is 1, it means overflow
1335 or any long shader.
1336 </doc>
1337 <bitfield name="LENGTH" low="24" high="31" type="uint"/>
1338 </reg32>
1339 <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
1340 <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1341 <!--
1342 not sure about full vs half const.. I can't get blob generate
1343 something with a mediump/lowp uniform.
1344 -->
1345 <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
1346 <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
1347 </reg32>
1348 <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
1349 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1350 <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
1351 <bitfield name="POS2DMODE" pos="16" type="boolean"/>
1352 <bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>
1353 </reg32>
1354 <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">
1355 <reg32 offset="0x0" name="REG">
1356 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
1357 <bitfield name="A_HALF" pos="8" type="boolean"/>
1358 <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1359 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
1360 <bitfield name="B_HALF" pos="24" type="boolean"/>
1361 <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1362 </reg32>
1363 </array>
1364 <array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">
1365 <reg32 offset="0x0" name="REG">
1366 <doc>
1367 These seem to be offsets for storage of the varyings.
1368 Always seems to start from 8, possibly loc 0 and 4
1369 are for gl_Position and gl_PointSize?
1370 </doc>
1371 <bitfield name="OUTLOC0" low="0" high="6" type="uint"/>
1372 <bitfield name="OUTLOC1" low="8" high="14" type="uint"/>
1373 <bitfield name="OUTLOC2" low="16" high="22" type="uint"/>
1374 <bitfield name="OUTLOC3" low="24" high="30" type="uint"/>
1375 </reg32>
1376 </array>
1377 <reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
1378 <doc>
1379 SP_VS_OBJ_START_REG contains pointer to the vertex shader program,
1380 immediately followed by the binning shader program (although I
1381 guess that is probably just re-using the same gpu buffer)
1382 </doc>
1383 <reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>
1384 <reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">
1385 <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
1386 <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
1387 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
1388 </reg32>
1389 <reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">
1390 <bitfield name="BURSTLEN" low="0" high="4"/>
1391 <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
1392 </reg32>
1393 <reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>
1394 <reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
1395 <reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">
1396 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1397 <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
1398 <!-- maybe CACHEINVALID is two bits?? -->
1399 <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1400 <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
1401 <doc>
1402 The full/half register footprint is in units of four components,
1403 so if r0.x is used, that counts as all of r0.[xyzw] as used.
1404 There are separate full/half register footprint values as the
1405 full and half registers are independent (not overlapping).
1406 Presumably the thread scheduler hardware allocates the full/half
1407 register names from the actual physical register file and
1408 handles the register renaming.
1409 </doc>
1410 <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1411 <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1412 <bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>
1413 <bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>
1414 <bitfield name="OUTORDERED" pos="19" type="boolean"/>
1415 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1416 <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1417 <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
1418 <bitfield name="COMPUTEMODE" pos="23" type="boolean"/>
1419 <doc>
1420 From regspec:
1421 SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
1422 If bit31 is 1, it means overflow
1423 or any long shader.
1424 </doc>
1425 <bitfield name="LENGTH" low="24" high="31" type="uint"/>
1426 </reg32>
1427 <reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
1428 <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1429 <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
1430 <bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
1431 <bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
1432 </reg32>
1433 <reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
1434 <doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>
1435 <reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>
1436 <reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">
1437 <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
1438 <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
1439 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
1440 </reg32>
1441 <reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">
1442 <bitfield name="BURSTLEN" low="0" high="4"/>
1443 <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
1444 </reg32>
1445 <reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>
1446 <reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">
1447 <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
1448 </reg32>
1449 <reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">
1450 <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
1451 </reg32>
1452 <reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">
1453 <bitfield name="MRT" low="0" high="1" type="uint">
1454 <doc>render targets - 1</doc>
1455 </bitfield>
1456 <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
1457 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
1458 </reg32>
1459 <array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">
1460 <reg32 offset="0x0" name="REG">
1461 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1462 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
1463 <bitfield name="SINT" pos="10" type="boolean"/>
1464 <bitfield name="UINT" pos="11" type="boolean"/>
1465 </reg32>
1466 </array>
1467 <array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">
1468 <reg32 offset="0x0" name="REG">
1469 <bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>
1470 </reg32>
1471 </array>
1472 <reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
1473
1474 <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>
1475 <!-- TPL1 registers -->
1476 <!-- assume VS/FS_TEX_OFFSET is same -->
1477 <bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">
1478 <bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>
1479 <bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>
1480 <!-- not sure the size of this: -->
1481 <bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>
1482 </bitset>
1483 <reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
1484 <reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
1485 <reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
1486 <reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
1487
1488 <!-- VBIF registers -->
1489 <reg32 offset="0x3001" name="VBIF_CLKON"/>
1490 <reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>
1491 <reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>
1492 <reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>
1493 <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
1494 <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
1495 <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
1496 <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
1497 <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
1498 <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
1499 <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
1500 <reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>
1501 <reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>
1502 <reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>
1503 <reg32 offset="0x303c" name="VBIF_ARB_CTL"/>
1504 <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
1505 <reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>
1506 <reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>
1507 <reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>
1508
1509 <bitset name="a3xx_vbif_perf_cnt" inline="yes">
1510 <bitfield name="CNT0" pos="0" type="boolean"/>
1511 <bitfield name="CNT1" pos="1" type="boolean"/>
1512 <bitfield name="PWRCNT0" pos="2" type="boolean"/>
1513 <bitfield name="PWRCNT1" pos="3" type="boolean"/>
1514 <bitfield name="PWRCNT2" pos="4" type="boolean"/>
1515 </bitset>
1516
1517 <reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>
1518 <reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>
1519 <reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>
1520 <reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>
1521 <reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>
1522 <reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>
1523 <reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>
1524 <reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>
1525 <reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>
1526 <reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>
1527 <reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>
1528 <reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>
1529 <reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>
1530
1531
1532 <reg32 offset="0x0c01" name="VSC_BIN_SIZE">
1533 <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1534 <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1535 </reg32>
1536
1537 <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>
1538 <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1539 <reg32 offset="0x0" name="CONFIG">
1540 <doc>
1541 Configures the mapping between VSC_PIPE buffer and
1542 bin, X/Y specify the bin index in the horiz/vert
1543 direction (0,0 is upper left, 0,1 is leftmost bin
1544 on second row, and so on). W/H specify the number
1545 of bins assigned to this VSC_PIPE in the horiz/vert
1546 dimension.
1547 </doc>
1548 <bitfield name="X" low="0" high="9" type="uint"/>
1549 <bitfield name="Y" low="10" high="19" type="uint"/>
1550 <bitfield name="W" low="20" high="23" type="uint"/>
1551 <bitfield name="H" low="24" high="27" type="uint"/>
1552 </reg32>
1553 <reg32 offset="0x1" name="DATA_ADDRESS"/>
1554 <reg32 offset="0x2" name="DATA_LENGTH"/>
1555 </array>
1556 <reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">
1557 <doc>seems to be set to 0x00000001 during binning pass</doc>
1558 <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
1559 </reg32>
1560 <reg32 offset="0x0c3d" name="UNKNOWN_0C3D">
1561 <doc>seems to be always set to 0x00000001</doc>
1562 </reg32>
1563 <reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>
1564 <reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>
1565 <reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>
1566 <reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>
1567 <reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">
1568 <doc>seems to be always set to 0x00000001</doc>
1569 </reg32>
1570
1571 <reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
1572 <reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
1573 <reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
1574 <reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
1575 <array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">
1576 <reg32 offset="0x0" name="X"/>
1577 <reg32 offset="0x1" name="Y"/>
1578 <reg32 offset="0x2" name="Z"/>
1579 <reg32 offset="0x3" name="W"/>
1580 </array>
1581 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
1582 <reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>
1583 <reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>
1584 <reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>
1585 <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
1586 <bitfield name="WIDTH" low="0" high="13" type="uint"/>
1587 <bitfield name="HEIGHT" low="14" high="27" type="uint"/>
1588 </reg32>
1589 <reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1590 <reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1591 <reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1592 <reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1593 <reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1594 <reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1595 <reg32 offset="0x0e43" name="UNKNOWN_0E43">
1596 <doc>seems to be always set to 0x00000001</doc>
1597 </reg32>
1598 <reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>
1599 <reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>
1600 <reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>
1601 <reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>
1602 <reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>
1603 <reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>
1604 <reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>
1605 <reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>
1606 <reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>
1607 <reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>
1608 <reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>
1609 <reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>
1610 <reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>
1611 <reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">
1612 <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
1613 <bitfield name="ADDR" low="0" high="27" type="hex"/>
1614 </reg32>
1615 <reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">
1616 <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
1617 <bitfield name="ADDR" low="0" high="27" type="hex"/>
1618 <!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->
1619 <bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>
1620 <bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>
1621 </reg32>
1622 <reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>
1623 <reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>
1624 <reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>
1625 <reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>
1626 <reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>
1627 <reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>
1628 <reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>
1629 <reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>
1630 <reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>
1631 <reg32 offset="0x0ee0" name="UNKNOWN_0EE0">
1632 <doc>seems to be always set to 0x00000003</doc>
1633 </reg32>
1634 <reg32 offset="0x0f03" name="UNKNOWN_0F03">
1635 <doc>seems to be always set to 0x00000001</doc>
1636 </reg32>
1637 <reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>
1638 <reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>
1639 <reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>
1640 <reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>
1641 <reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>
1642 <reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>
1643
1644 <!-- this seems to be the register that CP_RUN_OPENCL writes: -->
1645 <reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>
1646
1647 <!-- seems to be same as a2xx according to fwdump.. -->
1648 <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
1649 <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
1650 <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
1651 </domain>
1652
1653 <domain name="A3XX_TEX_SAMP" width="32">
1654 <doc>Texture sampler dwords</doc>
1655 <enum name="a3xx_tex_filter">
1656 <value name="A3XX_TEX_NEAREST" value="0"/>
1657 <value name="A3XX_TEX_LINEAR" value="1"/>
1658 <value name="A3XX_TEX_ANISO" value="2"/>
1659 </enum>
1660 <enum name="a3xx_tex_clamp">
1661 <value name="A3XX_TEX_REPEAT" value="0"/>
1662 <value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>
1663 <value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>
1664 <value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>
1665 <value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>
1666 </enum>
1667 <enum name="a3xx_tex_aniso">
1668 <value name="A3XX_TEX_ANISO_1" value="0"/>
1669 <value name="A3XX_TEX_ANISO_2" value="1"/>
1670 <value name="A3XX_TEX_ANISO_4" value="2"/>
1671 <value name="A3XX_TEX_ANISO_8" value="3"/>
1672 <value name="A3XX_TEX_ANISO_16" value="4"/>
1673 </enum>
1674 <reg32 offset="0" name="0">
1675 <bitfield name="CLAMPENABLE" pos="0" type="boolean"/>
1676 <bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>
1677 <bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>
1678 <bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>
1679 <bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>
1680 <bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>
1681 <bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>
1682 <bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>
1683 <bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>
1684 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>
1685 <!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->
1686 <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
1687 </reg32>
1688 <reg32 offset="1" name="1">
1689 <bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>
1690 <bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>
1691 <bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>
1692 </reg32>
1693 </domain>
1694
1695 <domain name="A3XX_TEX_CONST" width="32">
1696 <doc>Texture constant dwords</doc>
1697 <enum name="a3xx_tex_swiz">
1698 <!-- same as a2xx? -->
1699 <value name="A3XX_TEX_X" value="0"/>
1700 <value name="A3XX_TEX_Y" value="1"/>
1701 <value name="A3XX_TEX_Z" value="2"/>
1702 <value name="A3XX_TEX_W" value="3"/>
1703 <value name="A3XX_TEX_ZERO" value="4"/>
1704 <value name="A3XX_TEX_ONE" value="5"/>
1705 </enum>
1706 <enum name="a3xx_tex_type">
1707 <value name="A3XX_TEX_1D" value="0"/>
1708 <value name="A3XX_TEX_2D" value="1"/>
1709 <value name="A3XX_TEX_CUBE" value="2"/>
1710 <value name="A3XX_TEX_3D" value="3"/>
1711 </enum>
1712 <enum name="a3xx_tex_msaa">
1713 <value name="A3XX_TPL1_MSAA1X" value="0"/>
1714 <value name="A3XX_TPL1_MSAA2X" value="1"/>
1715 <value name="A3XX_TPL1_MSAA4X" value="2"/>
1716 <value name="A3XX_TPL1_MSAA8X" value="3"/>
1717 </enum>
1718 <reg32 offset="0" name="0">
1719 <bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>
1720 <bitfield name="SRGB" pos="2" type="boolean"/>
1721 <bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>
1722 <bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>
1723 <bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>
1724 <bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>
1725 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
1726 <bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>
1727 <bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>
1728 <bitfield name="NOCONVERT" pos="29" type="boolean"/>
1729 <bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>
1730 </reg32>
1731 <reg32 offset="1" name="1">
1732 <bitfield name="HEIGHT" low="0" high="13" type="uint"/>
1733 <bitfield name="WIDTH" low="14" high="27" type="uint"/>
1734 <bitfield name="FETCHSIZE" low="28" high="31" type="a3xx_tex_fetchsize"/>
1735 </reg32>
1736 <reg32 offset="2" name="2">
1737 <doc>INDX is index of texture address(es) in MIPMAP state block</doc>
1738 <bitfield name="INDX" low="0" high="8" type="uint"/>
1739 <doc>Pitch in bytes (so actually stride)</doc>
1740 <bitfield name="PITCH" low="12" high="29" type="uint"/>
1741 <doc>SWAP bit is set for BGRA instead of RGBA</doc>
1742 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
1743 </reg32>
1744 <reg32 offset="3" name="3">
1745 <!--
1746 Update: the two LAYERSZn seem not to be the same thing.
1747 According to Ilia's experimentation the first one goes up
1748 to at *least* bit 14..
1749 -->
1750 <bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>
1751 <bitfield name="DEPTH" low="17" high="27" type="uint"/>
1752 <bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>
1753 </reg32>
1754 </domain>
1755
1756 </database>