src/freedreno/registers/a5xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <enum name="a5xx_color_fmt">
  10         <value value="0x02" name="RB5_A8_UNORM"/>
  11         <value value="0x03" name="RB5_R8_UNORM"/>
  12         <value value="0x04" name="RB5_R8_SNORM"/>
  13         <value value="0x05" name="RB5_R8_UINT"/>
  14         <value value="0x06" name="RB5_R8_SINT"/>
  15         <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
  16         <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
  17         <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
  18         <value value="0x0f" name="RB5_R8G8_UNORM"/>
  19         <value value="0x10" name="RB5_R8G8_SNORM"/>
  20         <value value="0x11" name="RB5_R8G8_UINT"/>
  21         <value value="0x12" name="RB5_R8G8_SINT"/>
  22         <value value="0x15" name="RB5_R16_UNORM"/>
  23         <value value="0x16" name="RB5_R16_SNORM"/>
  24         <value value="0x17" name="RB5_R16_FLOAT"/>
  25         <value value="0x18" name="RB5_R16_UINT"/>
  26         <value value="0x19" name="RB5_R16_SINT"/>
  27         <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
  28         <value value="0x31" name="RB5_R8G8B8_UNORM"/>
  29         <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
  30         <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
  31         <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
  32         <value value="0x37" name="RB5_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
  33         <value value="0x3a" name="RB5_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
  34         <value value="0x42" name="RB5_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
  35         <value value="0x43" name="RB5_R16G16_UNORM"/>
  36         <value value="0x44" name="RB5_R16G16_SNORM"/>
  37         <value value="0x45" name="RB5_R16G16_FLOAT"/>
  38         <value value="0x46" name="RB5_R16G16_UINT"/>
  39         <value value="0x47" name="RB5_R16G16_SINT"/>
  40         <value value="0x4a" name="RB5_R32_FLOAT"/>
  41         <value value="0x4b" name="RB5_R32_UINT"/>
  42         <value value="0x4c" name="RB5_R32_SINT"/>
  43         <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
  44         <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
  45         <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
  46         <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
  47         <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
  48         <value value="0x67" name="RB5_R32G32_FLOAT"/>
  49         <value value="0x68" name="RB5_R32G32_UINT"/>
  50         <value value="0x69" name="RB5_R32G32_SINT"/>
  51         <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
  52         <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
  53         <value value="0x84" name="RB5_R32G32B32A32_SINT"/>
  54
  55         <value value="0xff" name="RB5_NONE"/>
  56 </enum>
  57
  58 <enum name="a5xx_tile_mode">
  59         <value name="TILE5_LINEAR" value="0"/>
  60         <value name="TILE5_2" value="2"/>
  61         <value name="TILE5_3" value="3"/>
  62 </enum>
  63
  64 <enum name="a5xx_vtx_fmt" prefix="chipset">
  65         <value value="0x03" name="VFMT5_8_UNORM"/>
  66         <value value="0x04" name="VFMT5_8_SNORM"/>
  67         <value value="0x05" name="VFMT5_8_UINT"/>
  68         <value value="0x06" name="VFMT5_8_SINT"/>
  69
  70         <value value="0x0f" name="VFMT5_8_8_UNORM"/>
  71         <value value="0x10" name="VFMT5_8_8_SNORM"/>
  72         <value value="0x11" name="VFMT5_8_8_UINT"/>
  73         <value value="0x12" name="VFMT5_8_8_SINT"/>
  74
  75         <value value="0x15" name="VFMT5_16_UNORM"/>
  76         <value value="0x16" name="VFMT5_16_SNORM"/>
  77         <value value="0x17" name="VFMT5_16_FLOAT"/>
  78         <value value="0x18" name="VFMT5_16_UINT"/>
  79         <value value="0x19" name="VFMT5_16_SINT"/>
  80
  81         <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
  82         <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
  83         <value value="0x23" name="VFMT5_8_8_8_UINT"/>
  84         <value value="0x24" name="VFMT5_8_8_8_SINT"/>
  85
  86         <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
  87         <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
  88         <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
  89         <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
  90
  91         <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
  92         <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
  93         <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
  94         <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
  95
  96         <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
  97
  98         <value value="0x43" name="VFMT5_16_16_UNORM"/>
  99         <value value="0x44" name="VFMT5_16_16_SNORM"/>
 100         <value value="0x45" name="VFMT5_16_16_FLOAT"/>
 101         <value value="0x46" name="VFMT5_16_16_UINT"/>
 102         <value value="0x47" name="VFMT5_16_16_SINT"/>
 103
 104         <value value="0x48" name="VFMT5_32_UNORM"/>
 105         <value value="0x49" name="VFMT5_32_SNORM"/>
 106         <value value="0x4a" name="VFMT5_32_FLOAT"/>
 107         <value value="0x4b" name="VFMT5_32_UINT"/>
 108         <value value="0x4c" name="VFMT5_32_SINT"/>
 109         <value value="0x4d" name="VFMT5_32_FIXED"/>
 110
 111         <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
 112         <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
 113         <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
 114         <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
 115         <value value="0x5c" name="VFMT5_16_16_16_SINT"/>
 116
 117         <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
 118         <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
 119         <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
 120         <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
 121         <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
 122
 123         <value value="0x65" name="VFMT5_32_32_UNORM"/>
 124         <value value="0x66" name="VFMT5_32_32_SNORM"/>
 125         <value value="0x67" name="VFMT5_32_32_FLOAT"/>
 126         <value value="0x68" name="VFMT5_32_32_UINT"/>
 127         <value value="0x69" name="VFMT5_32_32_SINT"/>
 128         <value value="0x6a" name="VFMT5_32_32_FIXED"/>
 129
 130         <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
 131         <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
 132         <value value="0x72" name="VFMT5_32_32_32_UINT"/>
 133         <value value="0x73" name="VFMT5_32_32_32_SINT"/>
 134         <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
 135         <value value="0x75" name="VFMT5_32_32_32_FIXED"/>
 136
 137         <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
 138         <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
 139         <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
 140         <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
 141         <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
 142         <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
 143
 144         <value value="0xff" name="VFMT5_NONE"/>
 145 </enum>
 146
 147 <enum name="a5xx_tex_fmt">
 148         <value value="0x02" name="TFMT5_A8_UNORM"/>
 149         <value value="0x03" name="TFMT5_8_UNORM"/>
 150         <value value="0x04" name="TFMT5_8_SNORM"/>
 151         <value value="0x05" name="TFMT5_8_UINT"/>
 152         <value value="0x06" name="TFMT5_8_SINT"/>
 153         <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
 154         <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
 155         <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
 156         <value value="0x0f" name="TFMT5_8_8_UNORM"/>
 157         <value value="0x10" name="TFMT5_8_8_SNORM"/>
 158         <value value="0x11" name="TFMT5_8_8_UINT"/>
 159         <value value="0x12" name="TFMT5_8_8_SINT"/>
 160         <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
 161         <value value="0x15" name="TFMT5_16_UNORM"/>
 162         <value value="0x16" name="TFMT5_16_SNORM"/>
 163         <value value="0x17" name="TFMT5_16_FLOAT"/>
 164         <value value="0x18" name="TFMT5_16_UINT"/>
 165         <value value="0x19" name="TFMT5_16_SINT"/>
 166         <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
 167         <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
 168         <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
 169         <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
 170         <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
 171         <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
 172         <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
 173         <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
 174         <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
 175         <value value="0x43" name="TFMT5_16_16_UNORM"/>
 176         <value value="0x44" name="TFMT5_16_16_SNORM"/>
 177         <value value="0x45" name="TFMT5_16_16_FLOAT"/>
 178         <value value="0x46" name="TFMT5_16_16_UINT"/>
 179         <value value="0x47" name="TFMT5_16_16_SINT"/>
 180         <value value="0x4a" name="TFMT5_32_FLOAT"/>
 181         <value value="0x4b" name="TFMT5_32_UINT"/>
 182         <value value="0x4c" name="TFMT5_32_SINT"/>
 183         <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
 184         <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
 185         <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
 186         <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
 187         <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
 188         <value value="0x67" name="TFMT5_32_32_FLOAT"/>
 189         <value value="0x68" name="TFMT5_32_32_UINT"/>
 190         <value value="0x69" name="TFMT5_32_32_SINT"/>
 191         <value value="0x72" name="TFMT5_32_32_32_UINT"/>
 192         <value value="0x73" name="TFMT5_32_32_32_SINT"/>
 193         <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
 194         <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
 195         <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
 196         <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
 197         <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
 198
 199         <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
 200         <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
 201         <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
 202         <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
 203         <value value="0xaf" name="TFMT5_ETC1"/>
 204         <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
 205         <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
 206         <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
 207         <value value="0xb3" name="TFMT5_DXT1"/>
 208         <value value="0xb4" name="TFMT5_DXT3"/>
 209         <value value="0xb5" name="TFMT5_DXT5"/>
 210         <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
 211         <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
 212         <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
 213         <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
 214         <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
 215         <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
 216         <value value="0xc0" name="TFMT5_BPTC"/>
 217         <value value="0xc1" name="TFMT5_ASTC_4x4"/>
 218         <value value="0xc2" name="TFMT5_ASTC_5x4"/>
 219         <value value="0xc3" name="TFMT5_ASTC_5x5"/>
 220         <value value="0xc4" name="TFMT5_ASTC_6x5"/>
 221         <value value="0xc5" name="TFMT5_ASTC_6x6"/>
 222         <value value="0xc6" name="TFMT5_ASTC_8x5"/>
 223         <value value="0xc7" name="TFMT5_ASTC_8x6"/>
 224         <value value="0xc8" name="TFMT5_ASTC_8x8"/>
 225         <value value="0xc9" name="TFMT5_ASTC_10x5"/>
 226         <value value="0xca" name="TFMT5_ASTC_10x6"/>
 227         <value value="0xcb" name="TFMT5_ASTC_10x8"/>
 228         <value value="0xcc" name="TFMT5_ASTC_10x10"/>
 229         <value value="0xcd" name="TFMT5_ASTC_12x10"/>
 230         <value value="0xce" name="TFMT5_ASTC_12x12"/>
 231
 232         <value value="0xff" name="TFMT5_NONE"/>
 233 </enum>
 234
 235 <enum name="a5xx_tex_fetchsize">
 236         <doc>
 237                 Size pixel to fetch, in bytes.  Doesn't seem to be required, setting
 238                 it to 0x0 seems to work ok, but may be less optimal.
 239         </doc>
 240         <value name="TFETCH5_1_BYTE"  value="0"/>
 241         <value name="TFETCH5_2_BYTE"  value="1"/>
 242         <value name="TFETCH5_4_BYTE"  value="2"/>
 243         <value name="TFETCH5_8_BYTE"  value="3"/>
 244         <value name="TFETCH5_16_BYTE" value="4"/>
 245 </enum>
 246
 247 <enum name="a5xx_depth_format">
 248         <value name="DEPTH5_NONE" value="0"/>
 249         <value name="DEPTH5_16" value="1"/>
 250         <value name="DEPTH5_24_8" value="2"/>
 251         <value name="DEPTH5_32" value="4"/>
 252 </enum>
 253
 254 <enum name="a5xx_blit_buf">
 255         <value value="0" name="BLIT_MRT0"/>
 256         <value value="1" name="BLIT_MRT1"/>
 257         <value value="2" name="BLIT_MRT2"/>
 258         <value value="3" name="BLIT_MRT3"/>
 259         <value value="4" name="BLIT_MRT4"/>
 260         <value value="5" name="BLIT_MRT5"/>
 261         <value value="6" name="BLIT_MRT6"/>
 262         <value value="7" name="BLIT_MRT7"/>
 263         <value value="8" name="BLIT_ZS"/>       <!-- depth or combined depth+stencil -->
 264         <value value="9" name="BLIT_S"/>        <!-- separate stencil -->
 265 </enum>
 266
 267 <!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
 268 <enum name="a5xx_cp_perfcounter_select">
 269         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 270         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 271         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 272         <value value="3" name="PERF_CP_PFP_IDLE"/>
 273         <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
 274         <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
 275         <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
 276         <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
 277         <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
 278         <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
 279         <value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
 280         <value value="11" name="PERF_CP_ME_IDLE"/>
 281         <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
 282         <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
 283         <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
 284         <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
 285         <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
 286         <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
 287         <value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
 288         <value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
 289         <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
 290         <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 291         <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 292         <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 293         <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 294         <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 295         <value value="26" name="PERF_CP_MODE_SWITCH"/>
 296         <value value="27" name="PERF_CP_ZPASS_DONE"/>
 297         <value value="28" name="PERF_CP_CONTEXT_DONE"/>
 298         <value value="29" name="PERF_CP_CACHE_FLUSH"/>
 299         <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
 300 </enum>
 301
 302 <enum name="a5xx_rbbm_perfcounter_select">
 303         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 304         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 305         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 306         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 307         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 308         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 309         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 310         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 311         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 312         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 313         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 314         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 315         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 316         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 317 </enum>
 318
 319 <enum name="a5xx_pc_perfcounter_select">
 320         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 321         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 322         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 323         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 324         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 325         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 326         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 327         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 328         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 329         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 330         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 331         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 332         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 333         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 334         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 335         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 336         <value value="16" name="PERF_PC_INSTANCES"/>
 337         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 338         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 339         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 340         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 341         <value value="21" name="PERF_PC_IA_VERTICES"/>
 342         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 343         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 344         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 345         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 346         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 347         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 348         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 349         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 350         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 351         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 352         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 353         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 354         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 355         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 356         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 357 </enum>
 358
 359 <enum name="a5xx_vfd_perfcounter_select">
 360         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 361         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 362         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 363         <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
 364         <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
 365         <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 366         <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 367         <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
 368         <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
 369         <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
 370         <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 371         <value value="11" name="PERF_VFD_RBUFFER_FULL"/>
 372         <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 373         <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 374         <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
 375         <value value="15" name="PERF_VFD_INSTRUCTIONS"/>
 376         <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 377         <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 378         <value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
 379         <value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
 380         <value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
 381         <value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
 382         <value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
 383         <value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
 384         <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
 385         <value value="25" name="PERF_VFD_1_BURST_REQ"/>
 386         <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 387         <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 388         <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 389         <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 390         <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
 391 </enum>
 392
 393 <enum name="a5xx_hlsq_perfcounter_select">
 394         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 395         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 396         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 397         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 398         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 399         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 400         <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
 401         <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
 402         <value value="8" name="PERF_HLSQ_QUADS"/>
 403         <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
 404         <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
 405         <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
 406         <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
 407         <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
 408         <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 409 </enum>
 410
 411 <enum name="a5xx_vpc_perfcounter_select">
 412         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 413         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 414         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 415         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 416         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 417         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 418         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 419         <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
 420         <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
 421         <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 422         <value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
 423         <value value="11" name="PERF_VPC_SP_COMPONENTS"/>
 424         <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
 425         <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
 426         <value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
 427         <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
 428         <value value="16" name="PERF_VPC_GRANT_PHASES"/>
 429 </enum>
 430
 431 <enum name="a5xx_tse_perfcounter_select">
 432         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 433         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 434         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 435         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 436         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 437         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 438         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 439         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 440         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 441         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 442         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 443         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 444         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 445         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 446         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 447         <value value="15" name="PERF_TSE_CINVOCATION"/>
 448         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 449         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 450         <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
 451 </enum>
 452
 453 <enum name="a5xx_ras_perfcounter_select">
 454         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 455         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 456         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 457         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 458         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 459         <value value="5" name="PERF_RAS_8X4_TILES"/>
 460         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 461         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 462         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 463         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 464 </enum>
 465
 466 <enum name="a5xx_lrz_perfcounter_select">
 467         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 468         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 469         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 470         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 471         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 472         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 473         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 474         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 475         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 476         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 477         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 478         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 479         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 480         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 481         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 482         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 483         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 484         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 485         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 486 </enum>
 487
 488 <enum name="a5xx_uche_perfcounter_select">
 489         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 490         <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
 491         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 492         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 493         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 494         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 495         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 496         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 497         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 498         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 499         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 500         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 501         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 502         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 503         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 504         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 505         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 506         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 507         <value value="18" name="PERF_UCHE_EVICTS"/>
 508         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 509         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 510         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 511         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 512         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 513         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 514         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 515         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 516         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 517         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 518         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 519         <value value="30" name="PERF_UCHE_FLAG_COUNT"/>
 520 </enum>
 521
 522 <enum name="a5xx_tp_perfcounter_select">
 523         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 524         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 525         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 526         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 527         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 528         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 529         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 530         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 531         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 532         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 533         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 534         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 535         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 536         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 537         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 538         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 539         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 540         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 541         <value value="18" name="PERF_TP_QUADS_1D"/>
 542         <value value="19" name="PERF_TP_QUADS_2D"/>
 543         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 544         <value value="21" name="PERF_TP_QUADS_3D"/>
 545         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 546         <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
 547         <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
 548         <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 549         <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
 550         <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
 551         <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 552         <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 553         <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 554         <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 555         <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 556         <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 557         <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 558         <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
 559         <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
 560         <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 561         <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 562         <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 563         <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 564         <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 565 </enum>
 566
 567 <enum name="a5xx_sp_perfcounter_select">
 568         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 569         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 570         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 571         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 572         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 573         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 574         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 575         <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
 576         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 577         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 578         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 579         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 580         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 581         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 582         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 583         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 584         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 585         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 586         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 587         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 588         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 589         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 590         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 591         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 592         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 593         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 594         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 595         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 596         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 597         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 598         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 599         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 600         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 601         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 602         <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
 603         <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 604         <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 605         <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 606         <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 607         <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 608         <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 609         <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 610         <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 611         <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 612         <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
 613         <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
 614         <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
 615         <value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
 616         <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
 617         <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
 618         <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
 619         <value value="51" name="PERF_SP_PIXELS_KILLED"/>
 620         <value value="52" name="PERF_SP_ICL1_REQUESTS"/>
 621         <value value="53" name="PERF_SP_ICL1_MISSES"/>
 622         <value value="54" name="PERF_SP_ICL0_REQUESTS"/>
 623         <value value="55" name="PERF_SP_ICL0_MISSES"/>
 624         <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
 625         <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
 626         <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
 627         <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
 628         <value value="60" name="PERF_SP_GPR_READ"/>
 629         <value value="61" name="PERF_SP_GPR_WRITE"/>
 630         <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
 631         <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
 632         <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
 633 </enum>
 634
 635 <enum name="a5xx_rb_perfcounter_select">
 636         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 637         <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
 638         <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 639         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 640         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 641         <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 642         <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
 643         <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 644         <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
 645         <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 646         <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 647         <value value="11" name="PERF_RB_Z_WORKLOAD"/>
 648         <value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
 649         <value value="13" name="PERF_RB_Z_READ"/>
 650         <value value="14" name="PERF_RB_Z_WRITE"/>
 651         <value value="15" name="PERF_RB_C_READ"/>
 652         <value value="16" name="PERF_RB_C_WRITE"/>
 653         <value value="17" name="PERF_RB_TOTAL_PASS"/>
 654         <value value="18" name="PERF_RB_Z_PASS"/>
 655         <value value="19" name="PERF_RB_Z_FAIL"/>
 656         <value value="20" name="PERF_RB_S_FAIL"/>
 657         <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 658         <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 659         <value value="23" name="RB_RESERVED"/>
 660         <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
 661         <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 662         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 663         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 664         <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 665         <value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
 666 </enum>
 667
 668 <enum name="a5xx_rb_samples_perfcounter_select">
 669         <value value="0" name="TOTAL_SAMPLES"/>
 670         <value value="1" name="ZPASS_SAMPLES"/>
 671         <value value="2" name="ZFAIL_SAMPLES"/>
 672         <value value="3" name="SFAIL_SAMPLES"/>
 673 </enum>
 674
 675 <enum name="a5xx_vsc_perfcounter_select">
 676         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 677         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 678         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 679         <value value="3" name="PERF_VSC_EOT_NUM"/>
 680 </enum>
 681
 682 <enum name="a5xx_ccu_perfcounter_select">
 683         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 684         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 685         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 686         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 687         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 688         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 689         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 690         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 691         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 692         <value value="9" name="PERF_CCU_GMEM_READ"/>
 693         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 694         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 695         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 696         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 697         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 698         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 699         <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 700         <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 701         <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 702         <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 703         <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 704         <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
 705         <value value="22" name="PERF_CCU_2D_RD_REQ"/>
 706         <value value="23" name="PERF_CCU_2D_WR_REQ"/>
 707         <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
 708         <value value="25" name="PERF_CCU_2D_PIXELS"/>
 709 </enum>
 710
 711 <enum name="a5xx_cmp_perfcounter_select">
 712         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
 713         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 714         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 715         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 716         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 717         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 718         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 719         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 720         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 721         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 722         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 723         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 724         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 725         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 726         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 727         <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 728         <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 729         <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 730         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 731         <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 732         <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 733         <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 734         <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
 735         <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
 736 </enum>
 737
 738 <enum name="a5xx_vbif_perfcounter_select">
 739         <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
 740         <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
 741         <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
 742         <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
 743         <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
 744         <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
 745         <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
 746         <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
 747         <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
 748         <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
 749         <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
 750         <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
 751         <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
 752         <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
 753         <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
 754         <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
 755         <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
 756         <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
 757         <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
 758         <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
 759         <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
 760         <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
 761         <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
 762         <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
 763         <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
 764         <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
 765         <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
 766         <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
 767         <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
 768         <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
 769         <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
 770         <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
 771         <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
 772         <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
 773         <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
 774         <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
 775         <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
 776         <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
 777         <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
 778         <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
 779         <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
 780         <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
 781         <value value="42" name="AXI_TOTAL_REQUESTS"/>
 782         <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
 783         <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
 784         <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
 785         <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
 786         <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
 787         <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
 788         <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
 789         <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
 790         <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
 791         <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
 792         <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
 793         <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
 794         <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
 795         <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
 796         <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
 797         <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
 798         <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
 799         <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
 800         <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
 801         <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
 802         <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
 803         <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
 804         <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
 805         <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
 806         <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
 807         <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
 808         <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
 809         <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
 810         <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
 811         <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
 812         <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
 813         <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
 814         <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
 815         <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
 816         <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
 817         <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
 818         <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
 819         <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
 820         <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
 821         <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
 822         <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
 823         <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
 824         <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
 825 </enum>
 826
 827 <domain name="A5XX" width="32">
 828         <bitset name="A5XX_INT0">
 829                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 830                 <bitfield name="RBBM_AHB_ERROR" pos="1"/>
 831                 <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/>
 832                 <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/>
 833                 <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/>
 834                 <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/>
 835                 <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/>
 836                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 837                 <bitfield name="CP_SW" pos="8"/>
 838                 <bitfield name="CP_HW_ERROR" pos="9"/>
 839                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 840                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 841                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 842                 <bitfield name="CP_IB2" pos="13"/>
 843                 <bitfield name="CP_IB1" pos="14"/>
 844                 <bitfield name="CP_RB" pos="15"/>
 845                 <bitfield name="CP_UNUSED_1" pos="16"/>
 846                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 847                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 848                 <bitfield name="UNKNOWN_1" pos="19"/>
 849                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 850                 <bitfield name="UNUSED_2" pos="21"/>
 851                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 852                 <bitfield name="MISC_HANG_DETECT" pos="23"/>
 853                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 854                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 855                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 856                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 857                 <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/>
 858                 <bitfield name="GPMU_FIRMWARE" pos="29"/>
 859                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 860                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 861         </bitset>
 862
 863         <!-- CP Interrupt bits -->
 864         <bitset name="A5XX_CP_INT">
 865                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 866                 <bitfield name="CP_RESERVED_BIT_ERROR" pos="1"/>
 867                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 868                 <bitfield name="CP_DMA_ERROR" pos="3"/>
 869                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 870                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 871         </bitset>
 872
 873         <!-- CP registers -->
 874         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 875         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 876         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 877         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
 878         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 879         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 880         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 881         <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
 882         <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
 883         <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
 884         <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
 885         <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
 886         <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
 887         <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
 888         <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
 889         <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
 890         <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
 891         <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
 892         <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
 893         <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
 894         <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
 895         <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
 896         <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
 897         <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
 898         <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
 899         <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
 900         <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
 901         <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
 902         <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
 903         <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
 904         <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
 905         <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
 906         <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
 907         <reg32 offset="0x0831" name="CP_CNTL"/>
 908         <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
 909         <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
 910         <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
 911         <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
 912         <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
 913         <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
 914         <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
 915         <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
 916         <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
 917         <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
 918         <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
 919         <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
 920         <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
 921         <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL"/>
 922         <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
 923         <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
 924         <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
 925         <reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
 926         <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
 927         <reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
 928         <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
 929         <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
 930         <reg32 offset="0x0b22" name="CP_IB2_BASE"/>
 931         <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
 932         <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
 933         <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
 934                 <reg32 offset="0x0" name="REG" type="uint"/>
 935         </array>
 936         <array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
 937                 <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
 938         </array>
 939         <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
 940         <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
 941         <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
 942         <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
 943         <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
 944         <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
 945         <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
 946         <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
 947         <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
 948         <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
 949         <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL"/>
 950         <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
 951         <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
 952         <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
 953         <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>
 954
 955         <!-- RBBM registers -->
 956         <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
 957         <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
 958         <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
 959         <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
 960 <!--
 961 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0
 962 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8
 963 #define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT    0x10
 964 #define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT  0x18
 965  -->
 966         <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
 967         <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
 968         <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
 969         <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
 970         <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
 971         <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
 972         <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
 973         <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
 974         <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
 975         <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
 976         <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
 977         <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
 978         <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
 979         <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
 980         <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
 981         <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
 982         <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
 983         <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
 984         <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
 985         <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
 986         <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
 987         <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
 988         <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
 989         <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
 990         <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
 991         <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
 992         <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
 993         <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
 994         <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
 995         <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
 996         <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
 997         <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
 998         <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
 999                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
1000                 <bitfield name="RBBM_AHB_ERROR" pos="1"/>
1001                 <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/>
1002                 <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/>
1003                 <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/>
1004                 <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/>
1005                 <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/>
1006                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
1007                 <bitfield name="CP_SW" pos="8"/>
1008                 <bitfield name="CP_HW_ERROR" pos="9"/>
1009                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
1010                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
1011                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
1012                 <bitfield name="CP_IB2" pos="13"/>
1013                 <bitfield name="CP_IB1" pos="14"/>
1014                 <bitfield name="CP_RB" pos="15"/>
1015                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
1016                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
1017                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
1018                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
1019                 <bitfield name="MISC_HANG_DETECT" pos="23"/>
1020                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
1021                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
1022                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
1023                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
1024                 <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/>
1025                 <bitfield name="GPMU_FIRMWARE" pos="29"/>
1026                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
1027                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
1028         </reg32>
1029         <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
1030         <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
1031         <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
1032         <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1033         <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1034         <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
1035         <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
1036         <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
1037         <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
1038         <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
1039         <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
1040         <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
1041         <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
1042         <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
1043         <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
1044         <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
1045         <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
1046         <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
1047         <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
1048         <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
1049         <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
1050         <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
1051         <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
1052         <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
1053         <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
1054         <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
1055         <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
1056         <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
1057         <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
1058         <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1059         <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1060         <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1061         <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
1062         <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
1063         <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
1064         <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
1065         <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
1066         <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
1067         <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
1068         <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
1069         <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
1070         <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
1071         <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
1072         <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
1073         <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
1074         <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
1075         <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
1076         <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
1077         <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
1078         <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
1079         <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
1080         <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
1081         <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
1082         <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
1083         <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
1084         <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
1085         <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
1086         <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
1087         <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
1088         <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
1089         <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
1090         <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
1091         <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
1092         <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
1093         <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1094         <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1095         <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1096         <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1097         <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
1098         <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
1099         <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
1100         <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
1101         <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
1102         <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
1103         <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
1104         <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
1105         <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
1106         <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
1107         <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
1108         <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
1109         <reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
1110         <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
1111         <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
1112         <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
1113         <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
1114         <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
1115         <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
1116         <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
1117         <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
1118         <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
1119         <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
1120         <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
1121         <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
1122         <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
1123         <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
1124         <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
1125         <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
1126         <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
1127         <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
1128         <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
1129         <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
1130         <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
1131         <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
1132         <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
1133         <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
1134         <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
1135         <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
1136         <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
1137         <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
1138         <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
1139         <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
1140         <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
1141         <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
1142         <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
1143         <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
1144         <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
1145         <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
1146         <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
1147         <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
1148         <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
1149         <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
1150         <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
1151         <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
1152         <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
1153         <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
1154         <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
1155         <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
1156         <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
1157         <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
1158         <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
1159         <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
1160         <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
1161         <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
1162         <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
1163         <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
1164         <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
1165         <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
1166         <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
1167         <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
1168         <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
1169         <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
1170         <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
1171         <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
1172         <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
1173         <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
1174         <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
1175         <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
1176         <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
1177         <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
1178         <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
1179         <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
1180         <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
1181         <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
1182         <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
1183         <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
1184         <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
1185         <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
1186         <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
1187         <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
1188         <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
1189         <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
1190         <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
1191         <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
1192         <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
1193         <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
1194         <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
1195         <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
1196         <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
1197         <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
1198         <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
1199         <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
1200         <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
1201         <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1202         <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1203         <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1204         <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1205         <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1206         <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1207         <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1208         <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1209         <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1210         <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1211         <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1212         <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1213         <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1214         <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1215         <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1216         <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1217         <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
1218         <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
1219         <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
1220         <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
1221         <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
1222         <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
1223         <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
1224         <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
1225         <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
1226         <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
1227         <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
1228         <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
1229         <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
1230         <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
1231         <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
1232         <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
1233         <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
1234         <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
1235         <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
1236         <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
1237         <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
1238         <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
1239         <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
1240         <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
1241         <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
1242         <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
1243         <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
1244         <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
1245         <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
1246         <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
1247         <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
1248         <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
1249         <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
1250         <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
1251         <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
1252         <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
1253         <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
1254         <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
1255         <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
1256         <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
1257         <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
1258         <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
1259         <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
1260         <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
1261         <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
1262         <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
1263         <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
1264         <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
1265         <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
1266         <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
1267         <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
1268         <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
1269         <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
1270         <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
1271         <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
1272         <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
1273         <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
1274         <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
1275         <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
1276         <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
1277         <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
1278         <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
1279         <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
1280         <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
1281         <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
1282         <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
1283         <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
1284         <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
1285         <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
1286         <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
1287         <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
1288         <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
1289         <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
1290         <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
1291         <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
1292         <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
1293         <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
1294         <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
1295         <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
1296         <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
1297         <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
1298         <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
1299         <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
1300         <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
1301         <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
1302         <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
1303         <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
1304         <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
1305         <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
1306         <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
1307         <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
1308         <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
1309         <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
1310         <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
1311         <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
1312         <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
1313         <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
1314         <reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/>
1315         <reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/>
1316         <reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/>
1317         <reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/>
1318         <reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/>
1319         <reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/>
1320         <reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/>
1321         <reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/>
1322         <reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/>
1323         <reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/>
1324         <reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/>
1325         <reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/>
1326         <reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/>
1327         <reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/>
1328         <reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/>
1329         <reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/>
1330         <reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/>
1331         <reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/>
1332         <reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/>
1333         <reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/>
1334         <reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/>
1335         <reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/>
1336         <reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/>
1337         <reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/>
1338         <reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/>
1339         <reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/>
1340         <reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/>
1341         <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/>
1342         <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/>
1343         <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/>
1344         <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/>
1345         <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/>
1346         <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/>
1347         <reg32 offset="0x04f5" name="RBBM_STATUS">
1348                 <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" />
1349                 <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" />
1350                 <bitfield high="29" low="29" name="HLSQ_BUSY" />
1351                 <bitfield high="28" low="28" name="VSC_BUSY" />
1352                 <bitfield high="27" low="27" name="TPL1_BUSY" />
1353                 <bitfield high="26" low="26" name="SP_BUSY" />
1354                 <bitfield high="25" low="25" name="UCHE_BUSY" />
1355                 <bitfield high="24" low="24" name="VPC_BUSY" />
1356                 <bitfield high="23" low="23" name="VFDP_BUSY" />
1357                 <bitfield high="22" low="22" name="VFD_BUSY" />
1358                 <bitfield high="21" low="21" name="TESS_BUSY" />
1359                 <bitfield high="20" low="20" name="PC_VSD_BUSY" />
1360                 <bitfield high="19" low="19" name="PC_DCALL_BUSY" />
1361                 <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" />
1362                 <bitfield high="17" low="17" name="DCOM_BUSY" />
1363                 <bitfield high="16" low="16" name="COM_BUSY" />
1364                 <bitfield high="15" low="15" name="LRZ_BUZY" />
1365                 <bitfield high="14" low="14" name="A2D_DSP_BUSY" />
1366                 <bitfield high="13" low="13" name="CCUFCHE_BUSY" />
1367                 <bitfield high="12" low="12" name="RB_BUSY" />
1368                 <bitfield high="11" low="11" name="RAS_BUSY" />
1369                 <bitfield high="10" low="10" name="TSE_BUSY" />
1370                 <bitfield high="9" low="9" name="VBIF_BUSY" />
1371                 <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" />
1372                 <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" />
1373                 <bitfield high="6" low="6" name="CP_BUSY" />
1374                 <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" />
1375                 <bitfield high="4" low="4" name="CP_CRASH_BUSY" />
1376                 <bitfield high="3" low="3" name="CP_ETS_BUSY" />
1377                 <bitfield high="2" low="2" name="CP_PFP_BUSY" />
1378                 <bitfield high="1" low="1" name="CP_ME_BUSY" />
1379                 <bitfield high="0" low="0" name="HI_BUSY" />
1380         </reg32>
1381         <reg32 offset="0x0530" name="RBBM_STATUS3"/>
1382         <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/>
1383         <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1384         <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1385         <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/>
1386         <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/>
1387         <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/>
1388         <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/>
1389         <reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/>
1390         <reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/>
1391         <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
1392         <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1393         <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1394         <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1395         <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
1396         <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
1397         <reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/>
1398         <reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/>
1399         <reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/>
1400         <reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/>
1401         <reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/>
1402         <reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/>
1403         <reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/>
1404         <reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/>
1405         <reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/>
1406         <reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/>
1407         <reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/>
1408         <reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/>
1409         <reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/>
1410         <reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/>
1411         <reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/>
1412         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1413         <reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/>
1414         <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
1415         <reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1416         <reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1417         <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1418         <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
1419         <reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/>
1420         <reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/>
1421         <reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/>
1422         <reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/>
1423         <reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1424
1425         <!-- VSC registers -->
1426         <reg32 offset="0x0bc2" name="VSC_BIN_SIZE">
1427                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1428                 <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
1429                 <!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
1430         </reg32>
1431         <reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
1432         <reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
1433         <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
1434         <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
1435         <array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
1436                 <reg32 offset="0x0" name="REG">
1437                         <doc>
1438                                 Configures the mapping between VSC_PIPE buffer and
1439                                 bin, X/Y specify the bin index in the horiz/vert
1440                                 direction (0,0 is upper left, 0,1 is leftmost bin
1441                                 on second row, and so on).  W/H specify the number
1442                                 of bins assigned to this VSC_PIPE in the horiz/vert
1443                                 dimension.
1444                         </doc>
1445                         <bitfield name="X" low="0" high="9" type="uint"/>
1446                         <bitfield name="Y" low="10" high="19" type="uint"/>
1447                         <bitfield name="W" low="20" high="23" type="uint"/>
1448                         <bitfield name="H" low="24" high="27" type="uint"/>
1449                 </reg32>
1450         </array>
1451         <array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16">
1452                 <reg32 offset="0x0" name="LO"/>
1453                 <reg32 offset="0x1" name="HI"/>
1454         </array>
1455         <array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16">
1456                 <reg32 offset="0x0" name="REG"/>
1457         </array>
1458         <reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/>
1459         <reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/>
1460
1461         <!-- used for some blits?? -->
1462         <reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/>
1463
1464         <!-- GRAS registers -->
1465         <reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL"/>
1466         <reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/>
1467         <reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/>
1468         <reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/>
1469         <reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/>
1470         <reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/>
1471         <reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/>
1472         <reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/>
1473         <reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/>
1474         <reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/>
1475         <reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/>
1476         <reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/>
1477         <reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/>
1478
1479         <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
1480         <reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL"/>
1481         <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
1482         <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
1483         <reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/>
1484         <reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/>
1485         <reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/>
1486         <reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/>
1487         <reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/>
1488         <reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/>
1489         <reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/>
1490         <reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/>
1491         <reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/>
1492         <reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/>
1493         <reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/>
1494         <reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/>
1495         <reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/>
1496         <reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/>
1497         <reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/>
1498         <reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/>
1499         <reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/>
1500         <reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/>
1501         <reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/>
1502         <reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/>
1503         <reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/>
1504         <reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/>
1505
1506         <reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL">
1507                 <bitfield name="TWOPASSUSEWFI" pos="8" type="boolean"/>
1508         </reg32>
1509         <reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL"/>
1510         <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
1511         <reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
1512         <reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
1513         <reg32 offset="0x0d06" name="PC_START_INDEX"/>
1514         <reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
1515         <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
1516         <reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
1517         <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
1518         <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
1519         <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
1520         <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/>
1521         <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/>
1522         <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/>
1523         <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/>
1524         <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/>
1525
1526         <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/>
1527         <reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/>
1528         <reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/>
1529         <reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL"/>
1530         <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
1531         <reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/>
1532         <reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/>
1533         <reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/>
1534         <reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/>
1535         <reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/>
1536         <reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/>
1537         <reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/>
1538         <reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/>
1539         <reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/>
1540         <reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/>
1541         <reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1542
1543         <reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL"/>
1544         <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
1545         <reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/>
1546         <reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/>
1547         <reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/>
1548         <reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/>
1549         <reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/>
1550         <reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
1551         <reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
1552         <reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
1553         <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL"/> <!-- always 00000400? -->
1554         <reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL"/>
1555         <reg32 offset="0x0e62" name="VPC_MODE_CNTL">
1556                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1557         </reg32>
1558         <reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/>
1559         <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/>
1560         <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/>
1561         <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
1562
1563         <reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL"/>
1564         <reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
1565         <reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
1566         <reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
1567         <reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
1568         <reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
1569         <reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
1570         <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
1571         <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
1572         <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
1573         <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
1574         <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
1575         <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
1576         <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
1577         <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
1578         <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
1579         <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
1580         <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
1581         <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
1582         <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/>
1583         <reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/>
1584         <reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/>
1585         <reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/>
1586         <reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/>
1587         <reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/>
1588         <reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/>
1589         <reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/>
1590         <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
1591         <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
1592         <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
1593         <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
1594         <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
1595
1596         <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
1597         <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL"/>
1598         <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
1599         <reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0"  type="a5xx_sp_perfcounter_select"/>
1600         <reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1"  type="a5xx_sp_perfcounter_select"/>
1601         <reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2"  type="a5xx_sp_perfcounter_select"/>
1602         <reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3"  type="a5xx_sp_perfcounter_select"/>
1603         <reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4"  type="a5xx_sp_perfcounter_select"/>
1604         <reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5"  type="a5xx_sp_perfcounter_select"/>
1605         <reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6"  type="a5xx_sp_perfcounter_select"/>
1606         <reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7"  type="a5xx_sp_perfcounter_select"/>
1607         <reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8"  type="a5xx_sp_perfcounter_select"/>
1608         <reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9"  type="a5xx_sp_perfcounter_select"/>
1609         <reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/>
1610         <reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/>
1611         <reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/>
1612         <reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/>
1613         <reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/>
1614         <reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/>
1615
1616         <reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL"/>
1617         <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
1618         <reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/>
1619         <reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/>
1620         <reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/>
1621         <reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/>
1622         <reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/>
1623         <reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/>
1624         <reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/>
1625         <reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/>
1626         <reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/>
1627         <reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/>
1628         <reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/>
1629         <reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/>
1630
1631         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1632         <reg32 offset="0x3001" name="VBIF_CLKON"/>
1633 <!--
1634 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK   0x1
1635 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT  0x1
1636  -->
1637         <reg32 offset="0x3028" name="VBIF_ABIT_SORT"/>
1638         <reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/>
1639         <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
1640         <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
1641         <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
1642         <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
1643         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1644 <!--
1645 #define A5XX_VBIF_XIN_HALT_CTRL0_MASK      0xF
1646 #define A510_VBIF_XIN_HALT_CTRL0_MASK      0x7
1647  -->
1648         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1649         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1650 <!--
1651 #define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK    0x1
1652 #define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT   0x0
1653  -->
1654         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1655         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
1656 <!--
1657 #define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK  0xF
1658 #define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0
1659  -->
1660         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1661         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
1662 <!--
1663 #define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK     0xF
1664 #define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT    0x0
1665  -->
1666         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1667         <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
1668         <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
1669         <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
1670         <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
1671         <reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/>
1672         <reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/>
1673         <reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/>
1674         <reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/>
1675         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/>
1676         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/>
1677         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/>
1678         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/>
1679         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1680         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1681         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1682         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1683         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1684         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1685         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1686         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1687         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1688         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1689         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1690         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1691         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1692         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1693         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1694         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1695         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1696
1697         <reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/>
1698         <reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/>
1699         <reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/>
1700         <reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/>
1701         <reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/>
1702         <reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS">
1703                 <bitfield name="PWR_ON" pos="20" type="boolean"/>
1704         </reg32>
1705         <reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS">
1706                 <bitfield name="PWR_ON" pos="20" type="boolean"/>
1707         </reg32>
1708         <reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/>
1709         <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
1710         <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
1711         <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
1712         <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
1713         <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
1714         <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
1715         <reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/>
1716         <reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/>
1717
1718 <!--
1719 /* COUNTABLE FOR SP PERFCOUNTER */
1720 #define A5XX_SP_ALU_ACTIVE_CYCLES          0x1
1721 #define A5XX_SP0_ICL1_MISSES               0x35
1722 #define A5XX_SP_FS_CFLOW_INSTRUCTIONS      0x27
1723
1724 /* COUNTABLE FOR TSE PERFCOUNTER */
1725 #define A5XX_TSE_INPUT_PRIM_NUM            0x6
1726  -->
1727         <reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/>
1728         <reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/>
1729         <reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/>
1730         <reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/>
1731         <reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/>
1732         <reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/>
1733         <reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/>
1734         <reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/>
1735         <reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/>
1736         <reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/>
1737         <reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/>
1738         <reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/>
1739         <reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/>
1740         <reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/>
1741         <reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/>
1742         <reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/>
1743         <reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/>
1744         <reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/>
1745         <reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/>
1746         <reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/>
1747         <reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/>
1748         <reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/>
1749         <reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/>
1750         <reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/>
1751         <reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/>
1752         <reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/>
1753         <reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/>
1754         <reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/>
1755         <reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/>
1756         <reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/>
1757         <reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/>
1758         <reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/>
1759         <reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/>
1760         <reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/>
1761         <reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/>
1762         <reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/>
1763         <reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/>
1764         <reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/>
1765         <reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/>
1766         <reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/>
1767         <reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/>
1768         <reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/>
1769         <reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/>
1770         <reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/>
1771         <reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/>
1772         <reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/>
1773         <reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/>
1774         <reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/>
1775         <reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/>
1776         <reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/>
1777         <reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/>
1778         <reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/>
1779         <reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/>
1780         <reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/>
1781         <reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/>
1782         <reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/>
1783         <reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/>
1784         <reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/>
1785         <reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/>
1786         <reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/>
1787         <reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/>
1788         <reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/>
1789         <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
1790         <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
1791         <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
1792         <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
1793         <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
1794         <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
1795         <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
1796         <reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/>
1797         <reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/>
1798         <reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/>
1799         <reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/>
1800         <reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/>
1801         <reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/>
1802         <reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/>
1803         <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
1804         <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
1805         <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
1806         <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
1807         <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
1808         <reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
1809         <reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
1810         <reg32 offset="0xb80f" name="GDPM_INT_EN"/>
1811         <reg32 offset="0xb811" name="GDPM_INT_MASK"/>
1812         <reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/>
1813         <reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
1814         <reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
1815         <reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
1816         <reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
1817         <reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/>
1818         <reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
1819
1820
1821         <reg32 offset="0xe000" name="GRAS_CL_CNTL">
1822                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1823         </reg32>
1824         <reg32 offset="0xe001" name="UNKNOWN_E001"/> <!-- always 00000000? -->
1825         <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
1826         <reg32 offset="0xe005" name="GRAS_CNTL">
1827                 <!-- see also RB_RENDER_CONTROL0 -->
1828                 <bitfield name="VARYING" pos="0" type="boolean"/>
1829                 <!--
1830                 bit 3 set when blob turns on WCOORD.. which also corresponds to
1831                 register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
1832                 shader does not use).. possibly providing wcoord in an alternate
1833                 way??
1834                 Also, when that happens, VARYING bits are turned on as well.
1835                  -->
1836                 <bitfield name="UNK3" pos="3" type="boolean"/>
1837                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1838         </reg32>
1839         <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1840                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1841                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1842         </reg32>
1843         <reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1844         <reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1845         <reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1846         <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1847         <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1848         <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1849         <reg32 offset="0xe090" name="GRAS_SU_CNTL">
1850                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1851                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1852                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1853                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1854                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1855                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1856                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1857         </reg32>
1858         <reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
1859                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1860                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1861         </reg32>
1862         <reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1863         <reg32 offset="0xe093" name="GRAS_SU_LAYERED"/>
1864         <reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1865                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1866                 <bitfield name="UNK1" pos="1" type="boolean"/>
1867         </reg32>
1868         <reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1869         <reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1870         <reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1871         <!-- duplicates RB_DEPTH_INFO0: -->
1872         <reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1873                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
1874         </reg32>
1875         <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
1876         <!--
1877         guessing about window/screen/extent, I think they can in the end be
1878         used interchangeably?
1879          -->
1880         <reg32 offset="0xe0a0" name="GRAS_SC_CNTL">
1881                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1882                 <bitfield name="SAMPLES_PASSED" pos="15" type="boolean"/>
1883         </reg32>
1884         <!-- note, 0x4 for binning pass when frag writes z?? -->
1885         <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
1886         <reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL">
1887                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1888         </reg32>
1889         <reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL">
1890                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1891                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1892         </reg32>
1893         <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
1894         <reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1895         <reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1896         <reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1897         <reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1898         <reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1899         <reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1900
1901         <doc>
1902                 LRZ:  (Low Resolution Z ??)
1903                 ----
1904
1905                 I think it serves two functions, early discard of primitives in binning
1906                 pass without needing full resolution depth buffer, and also functions as
1907                 a depth-prepass, used during the GMEM draws to discard primitives that
1908                 would not be visible due to later draws.
1909
1910                 The LRZ buffer always seems to be z16 format, regardless of actual
1911                 depth buffer format.
1912
1913                 Note that LRZ write should be disabled when blend/stencil/etc is enabled,
1914                 since the occluded primitive can still contribute to final color value
1915                 of a fragment.
1916
1917                 Only enabled for GL_LESS/GL_LEQUAL/GL_GREATER/GL_GEQUAL?
1918         </doc>
1919         <reg32 offset="0xe100" name="GRAS_LRZ_CNTL">
1920                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1921                 <doc>LRZ write also disabled for blend/etc.</doc>
1922                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1923                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1924                 <bitfield name="GREATER" pos="2" type="boolean"/>
1925                 <!--
1926                 b3 set sometimes, when depth buffer isn't cleared.. maybe it
1927                 invalidates the LRZ buffer?  (Or just the covered positions?
1928                  -->
1929         </reg32>
1930         <reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1931         <reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1932         <!--
1933         lzr pitch is depth pitch (in pixels) / 8 (aligned to 32)..
1934          -->
1935         <doc>
1936                 Pitch is depth width (in pixels) / 8 (aligned to 32).  Height
1937                 is also divided by 8 (ie. covers 8x8 pixels)
1938         </doc>
1939         <reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
1940         <reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1941         <reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1942
1943         <reg32 offset="0xe140" name="RB_CNTL">
1944                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1945                 <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
1946                 <bitfield name="BYPASS" pos="17" type="boolean"/>
1947         </reg32>
1948         <reg32 offset="0xe141" name="RB_RENDER_CNTL">
1949 <!--
1950 bit 3 set for normal draws
1951 bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
1952         for z32 with no stencil, but maybe in that case separate z/s not used?
1953         see mrt-fbo-* zs=2)
1954  -->
1955                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1956                 <bitfield name="SAMPLES_PASSED" pos="6" type="boolean"/>
1957                 <bitfield name="DISABLE_COLOR_PIPE" pos="7" type="boolean"/>
1958                 <!-- why everything twice?? maybe read vs write? -->
1959                 <!-- UBWC flag buffer enabled for depth/stencil: -->
1960                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
1961                 <bitfield name="FLAG_DEPTH2" pos="15" type="boolean"/>
1962                 <!-- bitmask of MRTs using UBWC flag buffer: -->
1963                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
1964                 <bitfield name="FLAG_MRTS2" low="24" high="31"/>
1965         </reg32>
1966         <reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL">
1967                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1968         </reg32>
1969         <reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL">
1970                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1971                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1972         </reg32>
1973         <!--
1974         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
1975         name comes from kernel and is probably right)
1976          -->
1977         <reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
1978                 <!-- see also GRAS_CNTL -->
1979                 <bitfield name="VARYING" pos="0" type="boolean"/>
1980                 <!--
1981                 bit 3 set when blob turns on WCOORD.. which also corresponds to
1982                 register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
1983                 shader does not use).. possibly providing wcoord in an alternate
1984                 way??
1985                 Also, when that happens, VARYING bits are turned on as well.
1986                  -->
1987                 <bitfield name="UNK3" pos="3" type="boolean"/>
1988                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1989         </reg32>
1990         <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
1991                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
1992                 <bitfield name="FACENESS" pos="1" type="boolean"/>
1993                 <bitfield name="SAMPLEID" pos="2" type="boolean"/>
1994         </reg32>
1995         <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL">
1996                 <!-- bit0 set except for binning pass.. -->
1997                 <bitfield name="MRT" low="0" high="3" type="uint"/>
1998                 <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
1999         </reg32>
2000         <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS">
2001                 <bitfield name="RT0" low="0" high="3"/>
2002                 <bitfield name="RT1" low="4" high="7"/>
2003                 <bitfield name="RT2" low="8" high="11"/>
2004                 <bitfield name="RT3" low="12" high="15"/>
2005                 <bitfield name="RT4" low="16" high="19"/>
2006                 <bitfield name="RT5" low="20" high="23"/>
2007                 <bitfield name="RT6" low="24" high="27"/>
2008                 <bitfield name="RT7" low="28" high="31"/>
2009         </reg32>
2010         <array offset="0xe150" name="RB_MRT" stride="7" length="8">
2011                 <reg32 offset="0x0" name="CONTROL">
2012                         <bitfield name="BLEND" pos="0" type="boolean"/>
2013                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2014                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2015                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2016                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2017                 </reg32>
2018                 <reg32 offset="0x1" name="BLEND_CONTROL">
2019                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2020                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2021                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2022                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2023                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2024                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2025                 </reg32>
2026                 <reg32 offset="0x2" name="BUF_INFO">
2027                         <!--
2028                         not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx,
2029                         or if it is inherent in the format.  Will have to play with bits
2030                         once we get things working and see what happens.  If it is a diff
2031                         field, it doesn't seem to have the same encoding as a3xx/a4xx.
2032                          -->
2033                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2034                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2035                         <bitfield name="DITHER_MODE" low="11" high="12" type="adreno_rb_dither_mode"/>
2036                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2037                         <bitfield name="COLOR_SRGB" pos="15" type="boolean"/>
2038                 </reg32>
2039                 <!--
2040                 at least in gmem, things seem to be aligned to pitch of 64..
2041                 maybe an artifact of tiled format used in gmem?
2042                  -->
2043                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2044                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2045                 <reg32 offset="0x5" name="BASE_LO"/>
2046                 <reg32 offset="0x6" name="BASE_HI"/>
2047         </array>
2048         <reg32 offset="0xe1a0" name="RB_BLEND_RED">
2049                 <bitfield name="UINT" low="0" high="7" type="hex"/>
2050                 <bitfield name="SINT" low="8" high="15" type="hex"/>
2051                 <bitfield name="FLOAT" low="16" high="31" type="float"/>
2052         </reg32>
2053         <reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/>
2054         <reg32 offset="0xe1a2" name="RB_BLEND_GREEN">
2055                 <bitfield name="UINT" low="0" high="7" type="hex"/>
2056                 <bitfield name="SINT" low="8" high="15" type="hex"/>
2057                 <bitfield name="FLOAT" low="16" high="31" type="float"/>
2058         </reg32>
2059         <reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/>
2060         <reg32 offset="0xe1a4" name="RB_BLEND_BLUE">
2061                 <bitfield name="UINT" low="0" high="7" type="hex"/>
2062                 <bitfield name="SINT" low="8" high="15" type="hex"/>
2063                 <bitfield name="FLOAT" low="16" high="31" type="float"/>
2064         </reg32>
2065         <reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/>
2066         <reg32 offset="0xe1a6" name="RB_BLEND_ALPHA">
2067                 <bitfield name="UINT" low="0" high="7" type="hex"/>
2068                 <bitfield name="SINT" low="8" high="15" type="hex"/>
2069                 <bitfield name="FLOAT" low="16" high="31" type="float"/>
2070         </reg32>
2071         <reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/>
2072         <reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL">
2073                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2074                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2075                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2076         </reg32>
2077         <reg32 offset="0xe1a9" name="RB_BLEND_CNTL">
2078                 <!-- per-mrt enable bit -->
2079                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2080                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2081                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2082                 <!-- a guess? -->
2083                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2084         </reg32>
2085         <reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL">
2086                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2087                 <bitfield name="UNK1" pos="1" type="boolean"/>
2088         </reg32>
2089         <reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
2090                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2091                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2092                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2093                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2094                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2095         </reg32>
2096         <reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
2097                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
2098         </reg32>
2099         <reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
2100         <reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
2101         <reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2102                 <doc>stride of depth/stencil buffer</doc>
2103         </reg32>
2104         <reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2105                 <doc>size of layer</doc>
2106         </reg32>
2107         <reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL">
2108                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2109                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2110                 <!--
2111                         set for stencil operations that require read from stencil
2112                         buffer, but not for example for stencil clear (which does
2113                         not require read).. so guessing this is analogous to
2114                         READ_DEST_ENABLE for color buffer..
2115                  -->
2116                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2117                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2118                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2119                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2120                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2121                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2122                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2123                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2124                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2125         </reg32>
2126         <reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
2127                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2128         </reg32>
2129         <reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
2130         <reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
2131         <reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
2132         <reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
2133         <reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
2134         <reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
2135         <reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2136         <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL">
2137                 <bitfield name="COPY" pos="1" type="boolean"/>
2138         </reg32>
2139
2140         <doc>
2141                 Blits:
2142                 ------
2143
2144                 Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous
2145                 generations where they shared most of the gl pipeline and were
2146                 triggered by CP_DRAW_INDX*
2147
2148                 For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of
2149                 blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination
2150                 gpuaddr.  The gmem offset is taken from RB_MRT[n].BASE_LO/HI
2151
2152                 For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI
2153                 for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI
2154                 (I suppose this is just to avoid trashing RB_MRT[1..7]??)
2155         </doc>
2156         <reg32 offset="0xe210" name="RB_BLIT_CNTL">
2157                 <bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/>
2158         </reg32>
2159         <reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2160         <reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2161         <reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3">
2162                 <!-- if b0 set, output is in TILE5_3 format -->
2163                 <bitfield name="TILED" pos="0" type="boolean"/>
2164         <!--
2165                 0xe213:
2166                         0x0 mem->gmem
2167                         0xf gmem->mem with flag buffer (color)
2168                         0x4 gmem->mem without flag buffer (color)
2169                         0x7 BYPASS mode flag buffer result (ie. on readpix)
2170                             also for gmem->mem preserving tiling
2171         -->
2172         </reg32>
2173         <reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
2174         <reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
2175         <reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2176         <!-- array-pitch is size of layer -->
2177         <reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2178         <reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/>
2179         <reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/>
2180         <reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/>
2181         <reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/>
2182         <reg32 offset="0xe21c" name="RB_CLEAR_CNTL">
2183                 <bitfield name="FAST_CLEAR" pos="1" type="boolean"/>
2184                 <bitfield name="MSAA_RESOLVE" pos="2" type="boolean"/>
2185                 <doc>
2186                         For MASK, if RB_BLIT_CNTL.BUF=BLIT_ZS:
2187                                 1 - depth
2188                                 2 - stencil
2189                                 3 - depth+stencil
2190                         if RB_BLIT_CNTL.BUF=BLIT_MRTn
2191                                 then probably a component mask, I always see 0xf
2192                 </doc>
2193                 <bitfield name="MASK" low="4" high="7"/>
2194         </reg32>
2195
2196         <doc>
2197                 Buffer Metadata (flag buffers):
2198                 -------------------------------
2199
2200                 Blob seems to stick some metadata at the front of the buffer,
2201                 both z/s and MRT.  I think this is same as UBWC (bandwidth
2202                 compression) metadata that mdp 1.7 and later supports.  See
2203                 1d3fae5698ce5358caab87a15383b690941697e8 in downstream kernel.
2204                 UBWC seems to stand for "universal bandwidth compression".
2205
2206                 Before glReadPixels() it does a pair of BYPASS blits (at least
2207                 if metadata is used) presumably to resolve metadata.
2208
2209                 NOTES: see: getUBwcBlockSize(), getUBwcMetaBufferSize() at
2210                 https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgralloc/alloc_controller.cpp
2211                 (note that bpp in bytes, not bits, so really cpp)
2212
2213                 Example Layout 2d w/ mipmap levels:
2214
2215                         100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500)
2216                                 base=c072e000, offset=16384, size=1703936
2217
2218                                 color           flags
2219                         0       c073a000        c0732000        - level 0 flags is address
2220                         1       c0838000        c0834000          programmed in texture state
2221                         2       c0879000        c0877000
2222                         3       c089a000        c0899000
2223                         4       c08ab000        c08aa000
2224                         5       c08b4000        c08b3000
2225                         6       c08b9000        c08b8000
2226                         7       c08bc000        c08bb000
2227                         8       c08be000        c08bd000
2228                         9       c08c0000        c08bf000
2229                         10      c08c2000        c08c1000
2230
2231                 ARRAY_PITCH is the combined size of all the levels plus flags,
2232                 so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
2233                 takes up a minimum of 2 pages (since color and flags parts are
2234                 each page aligned.
2235
2236                         { TILE_MODE = TILE5_3 | SWIZ_X = A5XX_TEX_X | SWIZ_Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_FLOAT | SWAP = WZYX }
2237                         { WIDTH = 100 | HEIGHT = 2000 }
2238                         { FETCHSIZE = TFETCH5_4_BYTE | PITCH = 512 | TYPE = A5XX_TEX_2D }
2239                         { ARRAY_PITCH = 1642496 | 0x18800000 }  - NOTE c2dc always has 0x18800000 but
2240                         { BASE_LO = 0xc0732000 }                  this varies for blob gles driver..
2241                         { BASE_HI = 0 | DEPTH = 1 }               not sure what it is
2242
2243
2244         </doc>
2245         <reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2246         <reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2247         <reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2248         </reg32>
2249         <array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
2250                 <reg32 offset="0" name="ADDR_LO"/>
2251                 <reg32 offset="1" name="ADDR_HI"/>
2252                 <reg32 offset="2" name="PITCH" shr="6" type="uint"/>
2253                 <!-- array-pitch is size of layer -->
2254                 <reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/>
2255         </array>
2256         <reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
2257         <reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
2258         <reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
2259         <!-- array-pitch is size of layer -->
2260         <reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
2261
2262         <reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2263         <reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2264
2265         <reg32 offset="0xe280" name="VPC_CNTL_0">
2266                 <doc>
2267                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2268                         plus # of transform-feedback (streamout) varyings if using the
2269                         hw streamout (rather than stg instructions in shader)
2270                 </doc>
2271                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2272                 <bitfield name="VARYING" pos="11" type="boolean"/>
2273         </reg32>
2274         <array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8">
2275                 <reg32 offset="0x0" name="MODE"/>
2276         </array>
2277         <array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2278                 <reg32 offset="0x0" name="MODE"/>
2279         </array>
2280         <reg32 offset="0xe292" name="UNKNOWN_E292"/>
2281         <reg32 offset="0xe293" name="UNKNOWN_E293"/>
2282         <array offset="0xe294" name="VPC_VAR" stride="1" length="4">
2283                 <!-- one bit per varying component: -->
2284                 <reg32 offset="0" name="DISABLE"/>
2285         </array>
2286         <reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/>
2287         <reg32 offset="0xe29a" name="UNKNOWN_E29A"/>
2288         <reg32 offset="0xe29d" name="VPC_PACK">
2289                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2290                 <!--
2291                 This seems to be the OUTLOC for the psize output.  It could possibly
2292                 be the max-OUTLOC position, but it is only set when VS writes psize
2293                 (and blob always puts psize at highest OUTLOC)
2294                  -->
2295                 <bitfield name="PSIZELOC" low="8" high="15" type="uint"/>
2296         </reg32>
2297         <reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/>
2298
2299         <doc>
2300                 Stream-Out:
2301                 -----------
2302
2303                 VPC_SO[0..3] registers setup details about streamout buffers, and
2304                 number of components to write to each.
2305
2306                 VPC_SO_PROG provides the mapping between output varyings and the SO
2307                 buffers.  It is written multiple times (via a CP_CONTEXT_REG_BUNCH
2308                 packet, not sure if that matters), each write can handle up to two
2309                 components of stream-out output.  Order matches up to OUTLOC,
2310                 including padding.  So, if outputting first 3 varyings:
2311
2312                         SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 }
2313                         SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf }
2314                         SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 }
2315
2316                 Then:
2317
2318                         VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN }
2319                         VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN }
2320                         VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN }
2321                         VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 }
2322                         VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN }
2323
2324                 Note that varying order is OUTLOC0, OUTLOC2, OUTLOC1, and note
2325                 the padding between OUTLOC1 and OUTLOC2.
2326
2327                 The BUF bitfield indicates which of the four streamout buffers
2328                 to write into at the specified offset.
2329
2330                 The VPC_SO[n].FLUSH_BASE_LO/HI is used for hw to write back next
2331                 offset which gets loaded back into VPC_SO[n].BUFFER_OFFSET via a
2332                 CP_MEM_TO_REG.  Probably can be ignored until we have GS/etc, at
2333                 which point we can't calculate the offset on the CPU.
2334         </doc>
2335         <reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL">
2336                 <bitfield name="BUF0" pos="0" type="boolean"/>
2337                 <bitfield name="BUF1" pos="3" type="boolean"/>
2338                 <bitfield name="BUF2" pos="6" type="boolean"/>
2339                 <bitfield name="BUF3" pos="9" type="boolean"/>
2340                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2341         </reg32>
2342         <reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE">
2343                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2344         </reg32>
2345         <reg32 offset="0xe2a3" name="VPC_SO_CNTL">
2346                 <!-- always 0x10000 when SO enabled.. -->
2347                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2348         </reg32>
2349         <reg32 offset="0xe2a4" name="VPC_SO_PROG">
2350                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2351                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2352                 <bitfield name="A_EN" pos="11" type="boolean"/>
2353                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2354                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2355                 <bitfield name="B_EN" pos="23" type="boolean"/>
2356         </reg32>
2357         <array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
2358                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2359                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2360                 <reg32 offset="2" name="BUFFER_SIZE"/>
2361                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2362                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2363                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2364                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2365         </array>
2366
2367         <reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
2368                 <!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) -->
2369                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2370                 <bitfield name="PRIMITIVE_RESTART" pos="8" type="boolean"/>
2371                 <bitfield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used -->
2372                 <bitfield name="PROVOKING_VTX_LAST" pos="10" type="boolean"/>
2373         </reg32>
2374         <reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL">
2375                 <bitfield name="PSIZE" pos="11" type="boolean"/>
2376         </reg32>
2377         <reg32 offset="0xe388" name="PC_RASTER_CNTL">
2378                 <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2379                 <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
2380                 <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
2381         </reg32>
2382         <reg32 offset="0xe389" name="UNKNOWN_E389"/>
2383         <reg32 offset="0xe38c" name="PC_RESTART_INDEX"/>
2384         <reg32 offset="0xe38d" name="PC_GS_LAYERED"/>
2385         <reg32 offset="0xe38e" name="PC_GS_PARAM">
2386                 <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
2387                 <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 -->
2388                 <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
2389         </reg32>
2390         <reg32 offset="0xe38f" name="PC_HS_PARAM">
2391                 <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2392                 <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
2393                 <bitfield name="CW" pos="23" type="boolean"/>
2394                 <bitfield name="CONNECTED" pos="24" type="boolean"/>
2395         </reg32>
2396         <reg32 offset="0xe3b0" name="PC_POWER_CNTL"/>
2397
2398         <reg32 offset="0xe400" name="VFD_CONTROL_0">
2399                 <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2400         </reg32>
2401         <reg32 offset="0xe401" name="VFD_CONTROL_1">
2402                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2403                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2404                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2405         </reg32>
2406         <reg32 offset="0xe402" name="VFD_CONTROL_2">
2407                 <bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? -->
2408         </reg32>
2409         <reg32 offset="0xe403" name="VFD_CONTROL_3">
2410                 <bitfield name="REGID_PATCHID" low="8" high="15" type="a3xx_regid"/>
2411                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2412                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2413         </reg32>
2414         <reg32 offset="0xe404" name="VFD_CONTROL_4">
2415         </reg32>
2416         <reg32 offset="0xe405" name="VFD_CONTROL_5">
2417                 <!-- b0 set if gl_PrimitiveID used in fs ?? -->
2418         </reg32>
2419         <reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
2420         <reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
2421         <array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
2422                 <reg32 offset="0x0" name="BASE_LO"/>
2423                 <reg32 offset="0x1" name="BASE_HI"/>
2424                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2425                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2426         </array>
2427         <array offset="0xe48a" name="VFD_DECODE" stride="2" length="32">
2428                 <reg32 offset="0x0" name="INSTR">
2429                         <!-- IDX appears to index into VFD_FETCH[] -->
2430                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2431                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2432                         <bitfield name="FORMAT" low="20" high="27" type="a5xx_vtx_fmt"/>
2433                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2434                         <bitfield name="UNK30" pos="30" type="boolean"/>
2435                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2436                 </reg32>
2437                 <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
2438         </array>
2439         <array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32">
2440                 <reg32 offset="0x0" name="INSTR">
2441                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2442                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2443                 </reg32>
2444         </array>
2445         <reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/>
2446
2447         <!-- 0x0 for compute, 0x10 for 3d? -->
2448         <reg32 offset="0xe580" name="SP_SP_CNTL"/>
2449
2450         <bitset name="a5xx_xs_config" inline="yes">
2451                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2452                 <bitfield name="CONSTOBJECTOFFSET" low="1" high="7" type="uint"/>
2453                 <bitfield name="SHADEROBJOFFSET" low="8" high="14" type="uint"/>
2454         </bitset>
2455         <bitset name="a5xx_xs_cntl" inline="yes">
2456                 <bitfield name="SSBO_ENABLE" pos="0" type="boolean"/>
2457                 <!--
2458                 no idea high bit.. could be this is amount of on-chip memory used
2459                 rather than total size?
2460                  -->
2461                 <bitfield name="INSTRLEN" low="1" high="31" type="uint"/>
2462         </bitset>
2463         <bitset name="a5xx_sp_xs_ctrl_reg0" inline="yes">
2464                 <!-- bit1 + bit2 set for "buffer" mode (ie. shader small enough to fit internally) -->
2465                 <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2466                 <bitfield name="THREADSIZE" pos="3" type="a3xx_threadsize"/>
2467                 <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
2468                 <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
2469                 <bitfield name="VARYING" pos="16" type="boolean"/>
2470                 <bitfield name="PIXLODENABLE" pos="20" type="boolean"/>
2471                 <!-- seems to be nesting level for flow control:.. -->
2472                 <bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/>
2473         </bitset>
2474         <!-- assuming things appear in same relative order as a4xx: -->
2475         <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
2476         <reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/>
2477         <reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/>
2478         <reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/>
2479         <reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/>
2480         <reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/>
2481         <reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/>
2482         <reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/>
2483         <reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/>
2484         <reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2485         <reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL">
2486                 <!-- # of VS outputs including pos/psize -->
2487                 <bitfield name="VSOUT" low="0" high="4" type="uint"/>
2488         </reg32>
2489         <array offset="0xe593" name="SP_VS_OUT" stride="1" length="16">
2490                 <reg32 offset="0x0" name="REG">
2491                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2492                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2493                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2494                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2495                 </reg32>
2496         </array>
2497         <!--
2498         Starting with a5xx, position/psize outputs from shader end up in the
2499         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2500         the last entries too, except when gl_PointCoord is used, blob inserts
2501         an extra varying after, but with a lower OUTLOC position.  If present,
2502         psize is last, preceded by position.
2503          -->
2504         <array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8">
2505                 <reg32 offset="0x0" name="REG">
2506                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2507                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2508                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2509                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2510                 </reg32>
2511         </array>
2512         <reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
2513         <reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
2514         <reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
2515         <reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2516         <reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
2517         <reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
2518         <reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
2519         <reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
2520                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2521                 <bitfield name="UNK8" pos="8" type="boolean"/>
2522                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2523         </reg32>
2524         <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL">
2525                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2526                 <bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/>
2527                 <bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/>
2528         </reg32>
2529         <array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8">
2530                 <doc>per MRT</doc>
2531                 <reg32 offset="0x0" name="REG">
2532                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2533                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
2534                 </reg32>
2535         </array>
2536         <array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8">
2537                 <reg32 offset="0" name="REG">
2538                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2539                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2540                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2541                         <bitfield name="COLOR_SRGB" pos="10" type="boolean"/>
2542                 </reg32>
2543         </array>
2544         <!--
2545         e5db/e5dc seems to look related to some optimization to do sample from
2546         texture using varying value directly before shader thread starts?  I
2547         guess that could optimize common simple frag shaders..
2548          -->
2549         <reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
2550         <reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2551         <reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
2552         <reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
2553         <reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
2554         <!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes -->
2555
2556         <reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2557         <reg32 offset="0xe602" name="UNKNOWN_E602"/>
2558         <reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
2559         <reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
2560         <reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2561         <reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
2562         <reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
2563         <reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
2564         <reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2565         <reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
2566         <reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
2567         <reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
2568
2569         <reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL">
2570                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2571         </reg32>
2572         <reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL">
2573                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2574                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2575         </reg32>
2576         <!-- either blob is doing it wrong, or this is not per-stage anymore: -->
2577         <reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
2578         <reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
2579
2580         <!--
2581         so these have the same info that is normally in the CP_LOAD_STATE
2582         packets.. not sure if they are normally written by pm4/me or if the
2583         CP_LOAD_STATE mechanism is deprecated?
2584          -->
2585         <reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/>
2586         <reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/>
2587         <reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
2588         <reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
2589
2590         <reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
2591         <reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
2592         <reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
2593         <reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
2594         <reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
2595         <reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
2596         <reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
2597         <reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
2598
2599         <reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
2600         <reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
2601         <reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
2602         <reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
2603         <reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
2604         <reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
2605         <reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
2606         <reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
2607
2608         <reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
2609         <reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
2610
2611         <reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
2612         <reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
2613         <reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
2614         <reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
2615         <reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
2616         <reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
2617         <reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
2618         <reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
2619
2620         <reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
2621
2622         <reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG">
2623                 <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2624                 <bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/>
2625                 <bitfield name="CSTHREADSIZE" pos="2" type="a3xx_threadsize"/>
2626         </reg32>
2627         <reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG">
2628                 <!-- I guess.. not set exactly same as a4xx, but similar: -->
2629                 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/>
2630         </reg32>
2631         <reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG">
2632                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
2633                 <!-- SAMPLEID is loaded into a half-precision register: -->
2634                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
2635                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
2636         </reg32>
2637         <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
2638                 <!-- register loaded with position (bary.f) -->
2639                 <bitfield name="FRAGCOORDXYREGID" low="0" high="7" type="a3xx_regid"/>
2640         </reg32>
2641         <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
2642                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
2643                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
2644         </reg32>
2645         <!--
2646         0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state
2647         is enabled?  We could probably try disabling different bits and see
2648         what breaks to figure out which is what:
2649          -->
2650         <reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/>
2651         <reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/>
2652         <reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/>
2653         <reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/>
2654         <reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/>
2655         <reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/>
2656         <reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/>
2657         <reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/>
2658         <reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/>
2659         <reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/>
2660         <reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/>
2661         <reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/>
2662         <reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/>
2663         <reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/>
2664         <reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/>
2665         <reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/>
2666         <reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0">
2667                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2668                 <!-- localsize is value minus one: -->
2669                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
2670                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
2671                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
2672         </reg32>
2673         <reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1">
2674                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
2675         </reg32>
2676         <reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2">
2677                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
2678         </reg32>
2679         <reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3">
2680                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
2681         </reg32>
2682         <reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4">
2683                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
2684         </reg32>
2685         <reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5">
2686                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
2687         </reg32>
2688         <reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6">
2689                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
2690         </reg32>
2691         <reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0">
2692                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
2693                 <!-- possibly one of these is KERNELDIMCONSTID? -->
2694                 <!--
2695                 UNK0 appears to be NUMWGCONSTID.. but only works in certain
2696                 cases?  Blob doesn't appear to use it, but instead emits
2697                 these via const (uniform).  Which requires some shenanigans
2698                 for indirect draws when the offset is not strongly aligned
2699                 enough to use as EXT_SRC_ADDR in CP_LOAD_STATE
2700                  -->
2701                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
2702                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
2703                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
2704         </reg32>
2705         <reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/>
2706         <reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/>
2707         <reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/>
2708         <reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/>
2709         <reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/>
2710         <reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/>
2711         <reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/>
2712         <reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/>
2713         <reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/>
2714         <reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/>
2715         <reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/>
2716         <reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/>
2717         <reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/>
2718         <reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/>
2719         <reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/>
2720         <reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/>
2721         <reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/>
2722         <reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/>
2723         <reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/>
2724
2725         <!--
2726                 Separate blit/2d or dma engine?  Seems to get used sometimes for
2727                 texture uploads, where a4xx blob would use normal draws.  Used
2728                 in render-mode 0x5..
2729
2730                 Note seems mostly to be used for small blits, large blits seem
2731                 to use the CP_EVENT_WRITE:BLIT style of doing things.  See
2732                 cubemap-0003 (40x40) vs cubemap-0004 (256x256).
2733
2734                 see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17
2735
2736                 Other nearby registers are probably color formats, etc.  The
2737                 blit coords are in CP packet.  Play more w/ glTexSubImage2D()
2738                 to work it out.
2739
2740                 Separate this into a different domain??  Would that help to
2741                 restrict which registers we dump based on mode?
2742
2743                 regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
2744                 like 2nd source for blending?  Used in mipmap generation.. but
2745                 maybe layout is a bit different.  (Possibly used for reading
2746                 src via sampler, to enable scaling??)  0x2040 also used in this
2747                 case.
2748          -->
2749         <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/>  <!-- same as 0x2180 -->
2750         <reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/>
2751         <reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/>
2752         <reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/>
2753         <reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/>
2754         <reg32 offset="0x2107" name="RB_2D_SRC_INFO">
2755                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2756                 <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2757                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2758                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2759                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2760         </reg32>
2761         <reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
2762         <reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
2763         <reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
2764                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2765                 <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
2766         </reg32>
2767         <reg32 offset="0x2110" name="RB_2D_DST_INFO">
2768                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2769                 <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2770                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2771                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2772                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2773         </reg32>
2774         <reg32 offset="0x2111" name="RB_2D_DST_LO"/>
2775         <reg32 offset="0x2112" name="RB_2D_DST_HI"/>
2776         <reg32 offset="0x2113" name="RB_2D_DST_SIZE">
2777                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2778                 <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
2779         </reg32>
2780         <reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
2781         <reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
2782         <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
2783         <reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
2784         <reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
2785         <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
2786         <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
2787         <!-- looks same as 0x2107: -->
2788         <reg32 offset="0x2181" name="GRAS_2D_SRC_INFO">
2789                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2790                 <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2791                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2792                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2793                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2794         </reg32>
2795         <!-- looks same as 0x2110: -->
2796         <reg32 offset="0x2182" name="GRAS_2D_DST_INFO">
2797                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2798                 <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2799                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2800                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2801                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2802         </reg32>
2803 <!--
2804 0x2100 and 0x2180 look like same thing (RB and GRAS versions)..
2805    0x86000000 for copy, 0x00000000 for fill?
2806
2807 0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
2808  -->
2809         <reg32 offset="0x2100" name="UNKNOWN_2100"/>
2810         <reg32 offset="0x2180" name="UNKNOWN_2180"/>
2811         <reg32 offset="0x2184" name="UNKNOWN_2184"/>
2812 </domain>
2813
2814 <domain name="A5XX_TEX_SAMP" width="32">
2815         <doc>Texture sampler dwords</doc>
2816         <enum name="a5xx_tex_filter"> <!-- same as a4xx? -->
2817                 <value name="A5XX_TEX_NEAREST" value="0"/>
2818                 <value name="A5XX_TEX_LINEAR" value="1"/>
2819                 <value name="A5XX_TEX_ANISO" value="2"/>
2820         </enum>
2821         <enum name="a5xx_tex_clamp"> <!-- same as a4xx? -->
2822                 <value name="A5XX_TEX_REPEAT" value="0"/>
2823                 <value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/>
2824                 <value name="A5XX_TEX_MIRROR_REPEAT" value="2"/>
2825                 <value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/>
2826                 <value name="A5XX_TEX_MIRROR_CLAMP" value="4"/>
2827         </enum>
2828         <enum name="a5xx_tex_aniso"> <!-- same as a4xx? -->
2829                 <value name="A5XX_TEX_ANISO_1" value="0"/>
2830                 <value name="A5XX_TEX_ANISO_2" value="1"/>
2831                 <value name="A5XX_TEX_ANISO_4" value="2"/>
2832                 <value name="A5XX_TEX_ANISO_8" value="3"/>
2833                 <value name="A5XX_TEX_ANISO_16" value="4"/>
2834         </enum>
2835         <reg32 offset="0" name="0">
2836                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2837                 <bitfield name="XY_MAG" low="1" high="2" type="a5xx_tex_filter"/>
2838                 <bitfield name="XY_MIN" low="3" high="4" type="a5xx_tex_filter"/>
2839                 <bitfield name="WRAP_S" low="5" high="7" type="a5xx_tex_clamp"/>
2840                 <bitfield name="WRAP_T" low="8" high="10" type="a5xx_tex_clamp"/>
2841                 <bitfield name="WRAP_R" low="11" high="13" type="a5xx_tex_clamp"/>
2842                 <bitfield name="ANISO" low="14" high="16" type="a5xx_tex_aniso"/>
2843                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
2844         </reg32>
2845         <reg32 offset="1" name="1">
2846                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
2847                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
2848                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
2849                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
2850                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
2851                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
2852         </reg32>
2853         <reg32 offset="2" name="2">
2854                 <!--
2855                 offset into border-color buffer?  Blob always uses 0x80 for FS state
2856                 if both VS and FS have border-color.
2857 Seems like when both VS and FS have bcolor, one starts 0x300 after other..
2858 and 0x80 in TEX_SAMP.2 ..  blob doesn't seem to be able to cope w/ multiple
2859 different border-color states per texture..  Looks something like:
2860 0000: 3f000000 00000000 00000000 3f800000 00008000 ffff0000 00004000 7fff0000
2861 0020: 00003800 3c000000 80100010 0000f008 ff000080 7f000040 c0000200 00800000
2862 0040: 00003800 3c000000 00000000 00000000 00000000 00000000 00000000 00000000
2863 *
2864 0300: 3f800000 3f800000 3f800000 3f800000 ffffffff ffffffff 7fff7fff 7fff7fff
2865 0320: 3c003c00 3c003c00 ffffffff 0000ffff ffffffff 7f7f7f7f ffffffff 00ffffff
2866 0340: 3c003c00 3c003c00 00000000 00000000 00000000 00000000 00000000 00000000
2867
2868                  -->
2869                 <bitfield name="BCOLOR_OFFSET" low="4" high="31"/>
2870         </reg32>
2871         <reg32 offset="3" name="3"/>
2872 </domain>
2873
2874 <domain name="A5XX_TEX_CONST" width="32">
2875         <doc>Texture constant dwords</doc>
2876         <enum name="a5xx_tex_swiz"> <!-- same as a4xx? -->
2877                 <value name="A5XX_TEX_X" value="0"/>
2878                 <value name="A5XX_TEX_Y" value="1"/>
2879                 <value name="A5XX_TEX_Z" value="2"/>
2880                 <value name="A5XX_TEX_W" value="3"/>
2881                 <value name="A5XX_TEX_ZERO" value="4"/>
2882                 <value name="A5XX_TEX_ONE" value="5"/>
2883         </enum>
2884         <enum name="a5xx_tex_type"> <!-- same as a4xx? -->
2885                 <value name="A5XX_TEX_1D" value="0"/>
2886                 <value name="A5XX_TEX_2D" value="1"/>
2887                 <value name="A5XX_TEX_CUBE" value="2"/>
2888                 <value name="A5XX_TEX_3D" value="3"/>
2889         </enum>
2890         <reg32 offset="0" name="0">
2891                 <bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/>
2892                 <bitfield name="SRGB" pos="2" type="boolean"/>
2893                 <bitfield name="SWIZ_X" low="4" high="6" type="a5xx_tex_swiz"/>
2894                 <bitfield name="SWIZ_Y" low="7" high="9" type="a5xx_tex_swiz"/>
2895                 <bitfield name="SWIZ_Z" low="10" high="12" type="a5xx_tex_swiz"/>
2896                 <bitfield name="SWIZ_W" low="13" high="15" type="a5xx_tex_swiz"/>
2897                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
2898                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
2899                 <bitfield name="FMT" low="22" high="29" type="a5xx_tex_fmt"/>
2900                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
2901         </reg32>
2902         <reg32 offset="1" name="1">
2903                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
2904                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
2905         </reg32>
2906         <reg32 offset="2" name="2">
2907                 <bitfield name="FETCHSIZE" low="0" high="3" type="a5xx_tex_fetchsize"/>
2908                 <doc>Pitch in bytes (so actually stride)</doc>
2909                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
2910                 <bitfield name="TYPE" low="29" high="30" type="a5xx_tex_type"/>
2911         </reg32>
2912         <reg32 offset="3" name="3">
2913                 <!--
2914                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
2915                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
2916                 layer size at the point that it stops being reduced moving to
2917                 higher (smaller) mipmap levels
2918                  -->
2919                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
2920                 <!--
2921                 by default levels with w < 16 are linear
2922                 TILE_ALL makes all levels have tiling
2923                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
2924                  -->
2925                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
2926                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
2927                 <bitfield name="FLAG" pos="28" type="boolean"/>
2928         </reg32>
2929         <reg32 offset="4" name="4">
2930                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
2931         </reg32>
2932         <reg32 offset="5" name="5">
2933                 <bitfield name="BASE_HI" low="0" high="16"/>
2934                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
2935         </reg32>
2936         <reg32 offset="6" name="6"/>
2937         <reg32 offset="7" name="7"/>
2938         <reg32 offset="8" name="8"/>
2939         <reg32 offset="9" name="9"/>
2940         <reg32 offset="10" name="10"/>
2941         <reg32 offset="11" name="11"/>
2942 </domain>
2943
2944 <!--
2945 Note the "SSBO" state blocks are actually used for both images and SSBOs,
2946 naming is just because I r/e'd SSBOs first.  I should probably come up
2947 with a better name.
2948 -->
2949 <domain name="A5XX_SSBO_0" width="32">
2950         <reg32 offset="0" name="0">
2951                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
2952         </reg32>
2953         <reg32 offset="1" name="1">
2954                 <!-- no BASE_HI here?  Maybe this is only used for 32b mode? -->
2955                 <doc>Pitch in bytes (so actually stride)</doc>
2956                 <bitfield name="PITCH" low="0" high="21" type="uint"/>
2957         </reg32>
2958         <reg32 offset="2" name="2">
2959                 <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
2960         </reg32>
2961         <reg32 offset="3" name="3">
2962                 <!-- bytes per pixel: -->
2963                 <bitfield name="CPP" low="0" high="5" type="uint"/>
2964         </reg32>
2965 </domain>
2966
2967 <domain name="A5XX_SSBO_1" width="32">
2968         <reg32 offset="0" name="0">
2969                 <bitfield name="FMT" low="8" high="15" type="a5xx_tex_fmt"/>
2970                 <bitfield name="WIDTH" low="16" high="31" type="uint"/>
2971         </reg32>
2972         <reg32 offset="1" name="1">
2973                 <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
2974                 <bitfield name="DEPTH" low="16" high="31" type="uint"/>
2975         </reg32>
2976 </domain>
2977
2978 <domain name="A5XX_SSBO_2" width="32">
2979         <reg32 offset="0" name="0">
2980                 <bitfield name="BASE_LO" low="0" high="31"/>
2981         </reg32>
2982         <reg32 offset="1" name="1">
2983                 <bitfield name="BASE_HI" low="0" high="31"/>
2984         </reg32>
2985 </domain>
2986
2987 <domain name="A5XX_UBO" width="32">
2988         <reg32 offset="0" name="0">
2989                 <bitfield name="BASE_LO" low="0" high="31"/>
2990         </reg32>
2991         <reg32 offset="1" name="1">
2992                 <bitfield name="BASE_HI" low="0" high="16"/>
2993                 <!-- size probably in high bits -->
2994         </reg32>
2995 </domain>
2996
2997 </database>