src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  26
  27         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  28         <value value="0x10" name="FMT6_8_8_SNORM"/>
  29         <value value="0x11" name="FMT6_8_8_UINT"/>
  30         <value value="0x12" name="FMT6_8_8_SINT"/>
  31         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  32
  33         <value value="0x15" name="FMT6_16_UNORM"/>
  34         <value value="0x16" name="FMT6_16_SNORM"/>
  35         <value value="0x17" name="FMT6_16_FLOAT"/>
  36         <value value="0x18" name="FMT6_16_UINT"/>
  37         <value value="0x19" name="FMT6_16_SINT"/>
  38
  39         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  40         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  41         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  42         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  43
  44         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  45         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  46         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  47         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  48         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  49
  50         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  51
  52         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  53         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  54         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  55         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  56         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  57
  58         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  59
  60         <value value="0x43" name="FMT6_16_16_UNORM"/>
  61         <value value="0x44" name="FMT6_16_16_SNORM"/>
  62         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  63         <value value="0x46" name="FMT6_16_16_UINT"/>
  64         <value value="0x47" name="FMT6_16_16_SINT"/>
  65
  66         <value value="0x48" name="FMT6_32_UNORM"/>
  67         <value value="0x49" name="FMT6_32_SNORM"/>
  68         <value value="0x4a" name="FMT6_32_FLOAT"/>
  69         <value value="0x4b" name="FMT6_32_UINT"/>
  70         <value value="0x4c" name="FMT6_32_SINT"/>
  71         <value value="0x4d" name="FMT6_32_FIXED"/>
  72
  73         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  74         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  75         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  76         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  77         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  78
  79         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  80         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  81         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  82         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  83         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  84
  85         <value value="0x65" name="FMT6_32_32_UNORM"/>
  86         <value value="0x66" name="FMT6_32_32_SNORM"/>
  87         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  88         <value value="0x68" name="FMT6_32_32_UINT"/>
  89         <value value="0x69" name="FMT6_32_32_SINT"/>
  90         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  91
  92         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  93         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  94         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  95         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  96         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  97         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  98
  99         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 100         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 101         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 102         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 103         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 104         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 105
 106         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 107         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 108
 109         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 110         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 111         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 112         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 113         <value value="0xaf" name="FMT6_ETC1"/>
 114         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 115         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 116         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 117         <value value="0xb3" name="FMT6_DXT1"/>
 118         <value value="0xb4" name="FMT6_DXT3"/>
 119         <value value="0xb5" name="FMT6_DXT5"/>
 120         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 121         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 122         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 123         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 124         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 125         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 126         <value value="0xc0" name="FMT6_BPTC"/>
 127         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 128         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 129         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 130         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 131         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 132         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 133         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 134         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 135         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 136         <value value="0xca" name="FMT6_ASTC_10x6"/>
 137         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 138         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 139         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 140         <value value="0xce" name="FMT6_ASTC_12x12"/>
 141
 142         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 143         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 144 </enum>
 145
 146 <enum name="a6xx_tex_fetchsize">
 147         <value name="TFETCH6_1_BYTE"  value="0"/>
 148         <value name="TFETCH6_2_BYTE"  value="1"/>
 149         <value name="TFETCH6_4_BYTE"  value="2"/>
 150         <value name="TFETCH6_8_BYTE"  value="3"/>
 151         <value name="TFETCH6_16_BYTE" value="4"/>
 152 </enum>
 153
 154 <!-- probably same as a5xx -->
 155 <enum name="a6xx_depth_format">
 156         <value name="DEPTH6_NONE" value="0"/>
 157         <value name="DEPTH6_16" value="1"/>
 158         <value name="DEPTH6_24_8" value="2"/>
 159         <value name="DEPTH6_32" value="4"/>
 160 </enum>
 161
 162 <bitset name="a6x_cp_protect" inline="yes">
 163         <bitfield name="BASE_ADDR" low="0" high="17"/>
 164         <bitfield name="MASK_LEN" low="18" high="30"/>
 165         <bitfield name="READ" pos="31"/>
 166 </bitset>
 167
 168 <enum name="a6xx_shader_id">
 169         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 170         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 171         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 172         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 173         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 174         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 175         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 176         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 177         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 178         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 179         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 180         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 181         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 182         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 183         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 184         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 185         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 186         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 187         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 188         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 189         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 190         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 191         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 192         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 193         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 194         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 195         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 196         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 197         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 198         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 199         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 200         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 201         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 202         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 203         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 204         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 205         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 206         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 207         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 208         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 209         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 210         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 211         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 212 </enum>
 213
 214 <enum name="a6xx_debugbus_id">
 215         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 216         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 217         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 218         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 219         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 220         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 221         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 222         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 223         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 224         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 225         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 226         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 227         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 228         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 229         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 230         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 231         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 232         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 233         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 234         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 235         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 236         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 237         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 238         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 239         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 240         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 241         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 242         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 243         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 244         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 245         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 246         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 247         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 248         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 249         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 250         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 251         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 252         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 253         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 254         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 255         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 256         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 257         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 258 </enum>
 259
 260 <enum name="a6xx_cp_perfcounter_select">
 261         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 262         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 263         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 264         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 265         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 266         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 267         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 268         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 269         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 270         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 271         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 272         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 273         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 274         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 275         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 276         <value value="15" name="PERF_CP_SQE_IDLE"/>
 277         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 278         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 279         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 280         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 281         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 282         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 283         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 284         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 285         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 286         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 287         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 288         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 289         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 290         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 291         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 292         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 293         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 294         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 295         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 296         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 297         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 298         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 299         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 300         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 301         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 302         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 303         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 304         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 305         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 306         <value value="45" name="PERF_CP_PM4_DATA"/>
 307         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 308         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 309         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 310         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 311 </enum>
 312
 313 <enum name="a6xx_rbbm_perfcounter_select">
 314         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 315         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 316         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 317         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 318         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 319         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 320         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 321         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 322         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 323         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 324         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 325         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 326         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 327         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 328 </enum>
 329
 330 <enum name="a6xx_pc_perfcounter_select">
 331         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 332         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 333         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 334         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 335         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 336         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 337         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 338         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 339         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 340         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 341         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 342         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 343         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 344         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 345         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 346         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 347         <value value="16" name="PERF_PC_INSTANCES"/>
 348         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 349         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 350         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 351         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 352         <value value="21" name="PERF_PC_IA_VERTICES"/>
 353         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 354         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 355         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 356         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 357         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 358         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 359         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 360         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 361         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 362         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 363         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 364         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 365         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 366         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 367         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 368         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 369         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 370         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 371         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 372         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 373 </enum>
 374
 375 <enum name="a6xx_vfd_perfcounter_select">
 376         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 377         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 378         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 379         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 380         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 381         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 382         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 383         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 384         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 385         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 386         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 387         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 388         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 389         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 390         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 391         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 392         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 393         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 394         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 395         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 396         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 397         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 398         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 399 </enum>
 400
 401 <enum name="a6xx_hlsq_perfcounter_select">
 402         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 403         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 404         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 405         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 406         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 407         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 408         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 409         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 410         <value value="8" name="PERF_HLSQ_QUADS"/>
 411         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 412         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 413         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 414         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 415         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 416         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 417         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 418         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 419         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 420         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 421         <value value="19" name="PERF_HLSQ_PIXELS"/>
 422         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 423 </enum>
 424
 425 <enum name="a6xx_vpc_perfcounter_select">
 426         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 427         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 428         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 429         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 430         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 431         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 432         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 433         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 434         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 435         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 436         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 437         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 438         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 439         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 440         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 441         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 442         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 443         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 444         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 445         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 446         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 447         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 448         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 449         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 450         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 451         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 452         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 453         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 454 </enum>
 455
 456 <enum name="a6xx_tse_perfcounter_select">
 457         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 458         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 459         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 460         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 461         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 462         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 463         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 464         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 465         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 466         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 467         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 468         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 469         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 470         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 471         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 472         <value value="15" name="PERF_TSE_CINVOCATION"/>
 473         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 474         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 475         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 476         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 477 </enum>
 478
 479 <enum name="a6xx_ras_perfcounter_select">
 480         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 481         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 482         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 483         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 484         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 485         <value value="5" name="PERF_RAS_8X4_TILES"/>
 486         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 487         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 488         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 489         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 490         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 491         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 492         <value value="12" name="PERF_RAS_BLOCKS"/>
 493 </enum>
 494
 495 <enum name="a6xx_uche_perfcounter_select">
 496         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 497         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 498         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 499         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 500         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 501         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 502         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 503         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 504         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 505         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 506         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 507         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 508         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 509         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 510         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 511         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 512         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 513         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 514         <value value="18" name="PERF_UCHE_EVICTS"/>
 515         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 516         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 517         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 518         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 519         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 520         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 521         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 522         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 523         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 524         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 525         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 526         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 527         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 528         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 529         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 530         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 531         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 532         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 533         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 534         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 535         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 536 </enum>
 537
 538 <enum name="a6xx_tp_perfcounter_select">
 539         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 540         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 541         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 542         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 543         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 544         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 545         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 546         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 547         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 548         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 549         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 550         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 551         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 552         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 553         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 554         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 555         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 556         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 557         <value value="18" name="PERF_TP_QUADS_1D"/>
 558         <value value="19" name="PERF_TP_QUADS_2D"/>
 559         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 560         <value value="21" name="PERF_TP_QUADS_3D"/>
 561         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 562         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 563         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 564         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 565         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 566         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 567         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 568         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 569         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 570         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 571         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 572         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 573         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 574         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 575         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 576         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 577         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 578         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 579         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 580         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 581         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 582         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 583         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 584         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 585         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 586         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 587         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 588         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 589         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 590         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 591         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 592         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 593         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 594         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 595         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 596 </enum>
 597
 598 <enum name="a6xx_sp_perfcounter_select">
 599         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 600         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 601         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 602         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 603         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 604         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 605         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 606         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 607         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 608         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 609         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 610         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 611         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 612         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 613         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 614         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 615         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 616         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 617         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 618         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 619         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 620         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 621         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 622         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 623         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 624         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 625         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 626         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 627         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 628         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 629         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 630         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 631         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 632         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 633         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 634         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 635         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 636         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 637         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 638         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 639         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 640         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 641         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 642         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 643         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 644         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 645         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 646         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 647         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 648         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 649         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 650         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 651         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 652         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 653         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 654         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 655         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 656         <value value="57" name="PERF_SP_GPR_READ"/>
 657         <value value="58" name="PERF_SP_GPR_WRITE"/>
 658         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 659         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 660         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 661         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 662         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 663         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 664         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 665         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 666         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 667         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 668         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 669         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 670         <value value="71" name="PERF_SP_WORKING_EU"/>
 671         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 672         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 673         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 674         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 675         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 676         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 677         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 678         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 679         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 680         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 681         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 682         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 683         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 684 </enum>
 685
 686 <enum name="a6xx_rb_perfcounter_select">
 687         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 688         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 689         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 690         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 691         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 692         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 693         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 694         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 695         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 696         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 697         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 698         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 699         <value value="12" name="PERF_RB_Z_READ"/>
 700         <value value="13" name="PERF_RB_Z_WRITE"/>
 701         <value value="14" name="PERF_RB_C_READ"/>
 702         <value value="15" name="PERF_RB_C_WRITE"/>
 703         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 704         <value value="17" name="PERF_RB_Z_PASS"/>
 705         <value value="18" name="PERF_RB_Z_FAIL"/>
 706         <value value="19" name="PERF_RB_S_FAIL"/>
 707         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 708         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 709         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 710         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 711         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 712         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 713         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 714         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 715         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 716         <value value="29" name="PERF_RB_3D_PIXELS"/>
 717         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 718         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 719         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 720         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 721         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 722         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 723         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 724         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 725         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 726         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 727         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 728         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 729         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 730         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 731         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 732         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 733         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 734         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 735 </enum>
 736
 737 <enum name="a6xx_vsc_perfcounter_select">
 738         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 739         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 740         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 741         <value value="3" name="PERF_VSC_EOT_NUM"/>
 742         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 743 </enum>
 744
 745 <enum name="a6xx_ccu_perfcounter_select">
 746         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 747         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 748         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 749         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 750         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 751         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 752         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 753         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 754         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 755         <value value="9" name="PERF_CCU_GMEM_READ"/>
 756         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 757         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 758         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 759         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 760         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 761         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 762         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 763         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 764         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 765         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 766         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 767         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 768         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 769         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 770         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 771         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 772         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 773         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 774         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 775 </enum>
 776
 777 <enum name="a6xx_lrz_perfcounter_select">
 778         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 779         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 780         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 781         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 782         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 783         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 784         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 785         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 786         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 787         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 788         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 789         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 790         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 791         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 792         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 793         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 794         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 795         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 796         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 797         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 798         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 799         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 800         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 801         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 802         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 803         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 804         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 805         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 806 </enum>
 807
 808 <enum name="a6xx_cmp_perfcounter_select">
 809         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 810         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 811         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 812         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 813         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 814         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 815         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 816         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 817         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 818         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 819         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 820         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 821         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 822         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 823         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 824         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 825         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 826         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 827         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 828         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 829         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 830         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 831         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 832         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 833         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 834         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 835         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 836         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 837         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 838         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 839         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 840         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 841         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 842         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 843         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 844         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 845         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 846         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 847         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 848         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 849 </enum>
 850
 851 <!--
 852 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 853 component type/size, so I think it relates to internal format used for
 854 blending?  The one exception is that 16b unorm and 32b float use the
 855 same value... maybe 16b unorm is uncommon enough that it was just easier
 856 to upconvert to 32b float internally?
 857
 858  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 859 16b unorm:   4
 860
 861 32b int:     7
 862 16b int:     6
 863  8b int:     5
 864
 865 32b float:   4
 866 16b float:   3
 867  -->
 868 <enum name="a6xx_2d_ifmt">
 869         <value value="0x10" name="R2D_UNORM8"/>
 870         <value value="0x7"  name="R2D_INT32"/>
 871         <value value="0x6"  name="R2D_INT16"/>
 872         <value value="0x5"  name="R2D_INT8"/>
 873         <value value="0x4"  name="R2D_FLOAT32"/>
 874         <value value="0x3"  name="R2D_FLOAT16"/>
 875         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 876         <value value="0x0"  name="R2D_RAW"/>
 877 </enum>
 878
 879 <domain name="A6XX" width="32">
 880         <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
 881                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 882                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 883                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 884                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 885                 <bitfield name="CP_SW" pos="8"/>
 886                 <bitfield name="CP_HW_ERROR" pos="9"/>
 887                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 888                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 889                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 890                 <bitfield name="CP_IB2" pos="13"/>
 891                 <bitfield name="CP_IB1" pos="14"/>
 892                 <bitfield name="CP_RB" pos="15"/>
 893                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 894                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 895                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 896                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 897                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 898                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 899                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 900                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 901                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 902                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 903                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 904         </bitset>
 905
 906         <bitset name="A6XX_CP_INT">
 907                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 908                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 909                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 910                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 911                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 912                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 913                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 914         </bitset>
 915
 916         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 917         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 918         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 919         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 920         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 921         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 922         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 923         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 924         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 925                 <bitfield name="IFPC" pos="0" type="boolean"/>
 926         </reg32>
 927         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 928         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 929         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 930         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 931         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 932         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 933         <!-- all the threshold values seem to be in units of quad-dwords: -->
 934         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 935                 <doc>
 936                         b0..7 seems to contain the size of buffered by not yet processed
 937                         RB level cmdstream.. it's possible that it is a low threshold
 938                         and b8..15 is a high threshold?
 939
 940                         b16..23 identifies where IB1 data starts (and RB data ends?)
 941
 942                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 943                 </doc>
 944                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 945                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 946                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 947                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
 948         </reg32>
 949         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
 950                 <doc>
 951                         low bits identify where CP_SET_DRAW_STATE stateobj
 952                         processing starts (and IB2 data ends). I'm guessing
 953                         b8 is part of this since (from downstream kgsl):
 954
 955                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
 956                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
 957                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
 958                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
 959                                 } ...
 960                 </doc>
 961                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
 962                 <!-- total ROQ size: -->
 963                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
 964         </reg32>
 965         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
 966         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
 967         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
 968         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
 969         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
 970
 971         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
 972                 <reg32 offset="0x0" name="REG" type="uint"/>
 973         </array>
 974         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
 975                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
 976         </array>
 977
 978         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
 979         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
 980         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
 981         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
 982         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
 983         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
 984         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
 985         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
 986         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
 987         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
 988         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
 989         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
 990         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
 991         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
 992         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
 993         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
 994         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
 995         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
 996         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
 997         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
 998         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
 999         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1000         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1001         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1002         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1003         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1004         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1005         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1006         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1007         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1008         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1009         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1010         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1011         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1012         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1013         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1014         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1015         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1016         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1017         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1018         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1019         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1020         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1021         <!-- SDS == CP_SET_DRAW_STATE: -->
1022         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1023         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1024         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1025         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1026         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1027         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1028         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1029         <!--
1030         There are probably similar registers for RB and SDS, teasing out SDS will
1031         take a slightly better test case..
1032          -->
1033         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1034                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1035                 <bitfield name="REM" low="16" high="31"/>
1036         </reg32>
1037         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1038                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1039                 <bitfield name="REM" low="16" high="31"/>
1040         </reg32>
1041         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1042         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1043         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1044         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1045         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1046         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1047         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1048         <reg32 offset="0x0210" name="RBBM_STATUS">
1049                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1050                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1051                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1052                 <bitfield high="20" low="20" name="VSC_BUSY" />
1053                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1054                 <bitfield high="18" low="18" name="SP_BUSY" />
1055                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1056                 <bitfield high="16" low="16" name="VPC_BUSY" />
1057                 <bitfield high="15" low="15" name="VFD_BUSY" />
1058                 <bitfield high="14" low="14" name="TESS_BUSY" />
1059                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1060                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1061                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1062                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1063                 <bitfield high="9" low="9" name="A2D_BUSY" />
1064                 <bitfield high="8" low="8" name="CCU_BUSY" />
1065                 <bitfield high="7" low="7" name="RB_BUSY" />
1066                 <bitfield high="6" low="6" name="RAS_BUSY" />
1067                 <bitfield high="5" low="5" name="TSE_BUSY" />
1068                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1069                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1070                 <bitfield high="2" low="2" name="CP_BUSY" />
1071                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1072                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1073         </reg32>
1074         <reg32 offset="0x0213" name="RBBM_STATUS3"/>
1075         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1076         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1077         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1078         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1079         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1080         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1081         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1082         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1083         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1084         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1085         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1086         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1087         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1088         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1089         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1090         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1091         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1092         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1093         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1094         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1095         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1096         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1097         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1098         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1099         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1100         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1101         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1102         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1103         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1104         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1105         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1106         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1107         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1108         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1109         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1110         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1111         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1112         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1113         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1114         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1115         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1116         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1117         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1118         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1119         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1120         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1121         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1122         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1123         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1124         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1125         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1126         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1127         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1128         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1129         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1130         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1131         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1132         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1133         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1134         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1135         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1136         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1137         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1138         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1139         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1140         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1141         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1142         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1143         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1144         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1145         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1146         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1147         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1148         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1149         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1150         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1151         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1152         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1153         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1154         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1155         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1156         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1157         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1158         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1159         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1160         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1161         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1162         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1163         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1164         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1165         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1166         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1167         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1168         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1169         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1170         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1171         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1172         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1173         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1174         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1175         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1176         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1177         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1178         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1179         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1180         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1181         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1182         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1183         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1184         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1185         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1186         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1187         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1188         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1189         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1190         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1191         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1192         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1193         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1194         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1195         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1196         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1197         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1198         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1199         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1200         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1201         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1202         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1203         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1204         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1205         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1206         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1207         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1208         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1209         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1210         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1211         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1212         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1213         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1214         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1215         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1216         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1217         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1218         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1219         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1220         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1221         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1222         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1223         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1224         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1225         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1226         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1227         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1228         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1229         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1230         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1231         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1232         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1233         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1234         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1235         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1236         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1237         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1238         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1239         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1240         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1241         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1242         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1243         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1244         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1245         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1246         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1247         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1248         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1249         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1250         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1251         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1252         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1253         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1254         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1255         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1256         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1257         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1258         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1259         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1260         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1261         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1262         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1263         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1264         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1265         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1266         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1267         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1268         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1269         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1270         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1271         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1272         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1273         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1274         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1275         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1276         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1277         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1278         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1279         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1280         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1281         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1282         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1283         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1284         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1285         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1286         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1287         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1288         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1289         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1290         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1291         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1292         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1293         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1294         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1295         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1296         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1297         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1298         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1299         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1300         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1301         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1302         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1303         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1304         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1305         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1306         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1307         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1308         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1309         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1310         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1311         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1312         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1313         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1314         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1315         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1316         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1317         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1318         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1319         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1320         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1321         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1322         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1323         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1324         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1325         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1326         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1327         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1328         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1329         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1330         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1331         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1332         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1333         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1334         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1335         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1336         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1337         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1338         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1339
1340         <!---
1341             This block of registers aren't tied to perf counters. They
1342             count various geometry stats, for example number of
1343             vertices in, number of primnitives assembled etc.
1344         -->
1345
1346         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1347         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1348         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1349         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1350         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1351         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1352         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1353         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1354         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1355         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1356         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1357         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1358         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1359         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1360         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1361         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1362         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1363         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1364         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1365         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1366         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1367         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1368
1369         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1370         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1371         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1372         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1373         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1374         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1375         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1376         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1377         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1378         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1379         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1380         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1381         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1382         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1383         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1384         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1385         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1386         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1387         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1388         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1389         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1390         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1391         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1392         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1393         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1394         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1395         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1396         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1397         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1398         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1399         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1400         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1401         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1402         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1403         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1404         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1405         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1406         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1407         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1408         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1409         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1410         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1411         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1412         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1413         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1414         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1415         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1416         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1417         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1418         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1419         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1420         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1421         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1422         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1423         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1424         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1425         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1426         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1427         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1428         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1429         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1430         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1431         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1432         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1433         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1434         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1435         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1436         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1437         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1438         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1439         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1440         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1441         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1442         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1443         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1444         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1445         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1446         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1447         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1448         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1449         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1450         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1451         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1452         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1453         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1454         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1455         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1456         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1457         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1458         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1459         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1460         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1461         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1462         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1463         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1464         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1465         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1466         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1467         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1468         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1469         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1470         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1471         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1472         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1473         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1474         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1475         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1476         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1477         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1478         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1479         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1480         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1481         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1482         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1483         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1484         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1485         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1486         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1487         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1488         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1489         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1490         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1491         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1492         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1493         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1494                 <bitfield high="7" low="0" name="PING_INDEX"/>
1495                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1496         </reg32>
1497         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1498                 <bitfield high="5" low="0" name="TRACEEN"/>
1499                 <bitfield high="14" low="12" name="GRANU"/>
1500                 <bitfield high="31" low="28" name="SEGT"/>
1501         </reg32>
1502         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1503                 <bitfield high="27" low="24" name="ENABLE"/>
1504         </reg32>
1505         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1506         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1507         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1508         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1509         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1510         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1511         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1512         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1513         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1514                 <bitfield high="3" low="0" name="BYTEL0"/>
1515                 <bitfield high="7" low="4" name="BYTEL1"/>
1516                 <bitfield high="11" low="8" name="BYTEL2"/>
1517                 <bitfield high="15" low="12" name="BYTEL3"/>
1518                 <bitfield high="19" low="16" name="BYTEL4"/>
1519                 <bitfield high="23" low="20" name="BYTEL5"/>
1520                 <bitfield high="27" low="24" name="BYTEL6"/>
1521                 <bitfield high="31" low="28" name="BYTEL7"/>
1522         </reg32>
1523         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1524                 <bitfield high="3" low="0" name="BYTEL8"/>
1525                 <bitfield high="7" low="4" name="BYTEL9"/>
1526                 <bitfield high="11" low="8" name="BYTEL10"/>
1527                 <bitfield high="15" low="12" name="BYTEL11"/>
1528                 <bitfield high="19" low="16" name="BYTEL12"/>
1529                 <bitfield high="23" low="20" name="BYTEL13"/>
1530                 <bitfield high="27" low="24" name="BYTEL14"/>
1531                 <bitfield high="31" low="28" name="BYTEL15"/>
1532         </reg32>
1533         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1534         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1535         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1536         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1537         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1538         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1539         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1540         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1541         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1542         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1543         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1544         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1545         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1546         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1547         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1548         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1549         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1550         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1551         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1552         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1553         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1554         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1555         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1556         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1557         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1558         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1559         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1560         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1561         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1562         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1563         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1564         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1565         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1566         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1567         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1568         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1569         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1570         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1571         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1572         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1573         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1574         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1575         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1576         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1577         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1578         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1579         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1580         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1581         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1582         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1583         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1584         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1585         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1586         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1587         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1588         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1589         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1590         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1591         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1592         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1593         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1594         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1595         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1596         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1597         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1598         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1599         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1600         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1601         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1602         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1603         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1604         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1605         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1606         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1607         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1608         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1609         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1610         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1611         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1612         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1613         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1614         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1615         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1616         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1617         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1618         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1619         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1620         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1621                 <bitfield high="7" low="0" name="PERFSEL"/>
1622         </reg32>
1623         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1624         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1625         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1626         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1627         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1628         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1629         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1630         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1631         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1632         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1633         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1634         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1635         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1636         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1637         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1638         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1639         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1640         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1641         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1642         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1643         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1644         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1645         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1646         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1647         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1648         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1649         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1650         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1651         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1652         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1653         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1654         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1655         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1656         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1657         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1658         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1659         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1660         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1661         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1662         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1663         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1664         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1665         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1666         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1667         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1668         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1669         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1670         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1671         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1672         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1673         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1674         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1675         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1676         <reg32 offset="0x3001" name="VBIF_CLKON">
1677                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1678         </reg32>
1679         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1680         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1681         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1682         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1683         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1684         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1685                 <bitfield low="0" high="3" name="DATA_SEL"/>
1686         </reg32>
1687         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1688         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1689                 <bitfield low="0" high="8" name="DATA_SEL"/>
1690         </reg32>
1691         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1692         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1693         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1694         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1695         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1696         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1697         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1698         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1699         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1700         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1701         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1702         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1703         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1704         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1705         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1706         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1707         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1708         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1709         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1710         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1711         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1712         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1713
1714         <!-- move/rename these.. -->
1715
1716         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1717         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1718         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1719
1720         <!-- same as RB_BIN_CONTROL -->
1721         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1722                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1723                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1724                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1725                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1726         </reg32>
1727
1728         <!--
1729                 from offset it seems it should be RB, but weird to duplicate
1730                 other regs from same block??
1731          -->
1732         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1733                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1734                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1735         </reg32>
1736
1737         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1738                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1739                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1740         </reg32>
1741         <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
1742         <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
1743         <reg64 offset="0x0c03" name="VSC_SIZE_ADDRESS" type="waddress"/>
1744         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1745                 <bitfield name="NX" low="1" high="10" type="uint"/>
1746                 <bitfield name="NY" low="11" high="20" type="uint"/>
1747         </reg32>
1748         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1749                 <reg32 offset="0x0" name="REG">
1750                         <doc>
1751                                 Configures the mapping between VSC_PIPE buffer and
1752                                 bin, X/Y specify the bin index in the horiz/vert
1753                                 direction (0,0 is upper left, 0,1 is leftmost bin
1754                                 on second row, and so on).  W/H specify the number
1755                                 of bins assigned to this VSC_PIPE in the horiz/vert
1756                                 dimension.
1757                         </doc>
1758                         <bitfield name="X" low="0" high="9" type="uint"/>
1759                         <bitfield name="Y" low="10" high="19" type="uint"/>
1760                         <bitfield name="W" low="20" high="25" type="uint"/>
1761                         <bitfield name="H" low="26" high="31" type="uint"/>
1762                 </reg32>
1763         </array>
1764         <!--
1765         compared to a5xx and earlier, we just program the address of the first
1766         visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH)
1767
1768         TODO now there seem to be two buffers of VSC data (both referenced by
1769         CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
1770         to have the larger pitch.
1771
1772         The "DATA2" buffer is probably actually the main visibility stream; it
1773         is at least the larger of the two.
1774
1775         For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
1776         uses something somewhat larger) for many cases, although required value
1777         can ramp up somewhat higher.  Values less than 0x20 trigger GPU hangs
1778         even with small amount of geometry (so possibly 0x20 is minimum
1779         alignment or something like that).  So far I can't seem to find any-
1780         thing that needs values larger than 0x20
1781          -->
1782         <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
1783         <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
1784         <reg64 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS" type="waddress"/>
1785         <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
1786         <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
1787         <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
1788         <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
1789         <reg64 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS" type="waddress"/>
1790         <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
1791         <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
1792
1793         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1794                 <doc>
1795                         Seems to be a bitmap of which tiles mapped to the VSC
1796                         pipe contain geometry.
1797
1798                         I suppose we can connect a maximum of 32 tiles to a
1799                         single VSC pipe.
1800                 </doc>
1801                 <reg32 offset="0x0" name="REG"/>
1802         </array>
1803
1804         <array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
1805                 <doc>
1806                         Has the size of data written to corresponding VSC_DATA2
1807                         buffer.
1808                 </doc>
1809                 <reg32 offset="0x0" name="REG"/>
1810         </array>
1811
1812         <array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
1813                 <doc>
1814                         Has the size of data written to corresponding VSC pipe, ie.
1815                         same thing that is written out to VSC_SIZE_ADDRESS_LO/HI
1816                 </doc>
1817                 <reg32 offset="0x0" name="REG"/>
1818         </array>
1819
1820         <!-- always 0x03200000 ? -->
1821         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1822
1823         <reg32 offset="0x8000" name="GRAS_DISABLE_CNTL">
1824                  <!-- likely something clip-disable related -->
1825                 <bitfield name="UNK0" pos="0" type="boolean"/>
1826                 <!-- guess based on a3xx and meaning of bits 8 and 9
1827                      if the guess is right then this is related to point sprite clipping -->
1828                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1829                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1830                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1831         </reg32>
1832         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1833         <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
1834         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1835
1836         <enum name="a6xx_layer_type">
1837           <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
1838           <value value="0x1" name="LAYER_3D"/>
1839           <value value="0x2" name="LAYER_CUBEMAP"/>
1840           <value value="0x3" name="LAYER_2D_ARRAY"/>
1841         </enum>
1842
1843         <reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
1844                 <bitfield name="LAYERED" pos="0" type="boolean"/>
1845                 <bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
1846         </reg32>
1847
1848         <reg32 offset="0x8005" name="GRAS_CNTL">
1849                 <!-- see also RB_RENDER_CONTROL0 -->
1850                 <bitfield name="VARYING" pos="0" type="boolean"/>
1851                 <!-- b1 set for interpolateAtCentroid() -->
1852                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1853                 <!-- b2 set instead of b0 when running in per-sample mode -->
1854                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1855                 <!--
1856                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1857                 mode, and frag_face
1858                  -->
1859                 <bitfield name="SIZE" pos="3" type="boolean"/>
1860                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1861                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1862                 <bitfield name="XCOORD" pos="6" type="boolean"/>
1863                 <bitfield name="YCOORD" pos="7" type="boolean"/>
1864                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
1865                 <bitfield name="WCOORD" pos="9" type="boolean"/>
1866         </reg32>
1867         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1868                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1869                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1870         </reg32>
1871         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1872         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1873         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1874         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1875         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1876         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1877
1878         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1879                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1880                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1881                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1882                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1883                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1884                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1885                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1886         </reg32>
1887         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1888                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1889                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1890         </reg32>
1891         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1892
1893         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1894                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1895         </reg32>
1896         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1897         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1898         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1899         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1900         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1901                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1902         </reg32>
1903
1904         <!-- always 0x0 -->
1905         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1906
1907         <!-- always 0x0 ? -->
1908         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1909
1910         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1911                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1912         </reg32>
1913
1914         <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
1915
1916         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1917
1918         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1919                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1920         </reg32>
1921         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1922                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1923                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1924         </reg32>
1925
1926         <!-- always 0x0 -->
1927         <reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/>
1928         <!-- always 0x0 -->
1929         <reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/>
1930         <!-- always 0x0 -->
1931         <reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/>
1932         <!-- always 0x0 -->
1933         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1934
1935         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1936         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1937         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1938         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1939         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1940         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1941
1942         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1943                 <!--
1944                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1945                 look when we get around to enabling lrz
1946                  -->
1947                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1948                 <doc>LRZ write also disabled for blend/etc.</doc>
1949                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1950                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1951                 <bitfield name="GREATER" pos="2" type="boolean"/>
1952                 <bitfield name="UNK3" pos="3" type="boolean"/>
1953                 <!-- set when depth-test + depth-write enabled -->
1954                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
1955         </reg32>
1956         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
1957         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1958                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1959         </reg32>
1960         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1961         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1962         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
1963         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1964                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
1965                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
1966         </reg32>
1967         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1968         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1969         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
1970
1971         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1972                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1973         </reg32>
1974
1975         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
1976
1977         <enum name="a6xx_rotation">
1978           <value value="0x0" name="ROTATE_0"/>
1979           <value value="0x1" name="ROTATE_90"/>
1980           <value value="0x2" name="ROTATE_180"/>
1981           <value value="0x3" name="ROTATE_270"/>
1982           <value value="0x4" name="ROTATE_HFLIP"/>
1983           <value value="0x5" name="ROTATE_VFLIP"/>
1984         </enum>
1985
1986         <bitset name="a6xx_2d_blit_cntl" inline="yes">
1987                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
1988                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
1989                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
1990                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
1991
1992                 <bitfield name="UNK" low="17" high="18" type="uint"/>
1993
1994                 <!-- required when blitting D24S8/D24X8 -->
1995                 <bitfield name="D24S8" pos="19" type="boolean"/>
1996                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
1997                 <bitfield name="MASK" low="20" high="23"/>
1998                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
1999         </bitset>
2000
2001         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2002
2003         <!-- could be the src coords are fixed point? -->
2004         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2005                 <bitfield name="X" low="8" high="31" type="int"/>
2006         </reg32>
2007         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2008                 <bitfield name="X" low="8" high="31" type="int"/>
2009         </reg32>
2010         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2011                 <bitfield name="Y" low="8" high="31" type="int"/>
2012         </reg32>
2013         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2014                 <bitfield name="Y" low="8" high="31" type="int"/>
2015         </reg32>
2016
2017         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2018         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2019
2020         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2021         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2022
2023         <!-- always 0x880 ? -->
2024         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2025
2026         <!-- same as GRAS_BIN_CONTROL: -->
2027         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2028                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2029                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2030                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2031                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2032         </reg32>
2033         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2034                 <!-- always set: ?? -->
2035                 <bitfield name="UNK4" pos="4" type="boolean"/>
2036                 <!-- set during binning pass: -->
2037                 <bitfield name="BINNING" pos="7" type="boolean"/>
2038                 <!-- bit seems to be set whenever depth buffer enabled: -->
2039                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2040                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2041                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2042         </reg32>
2043         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2044                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2045         </reg32>
2046         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2047                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2048                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2049         </reg32>
2050
2051         <!-- always 0x0 ? -->
2052         <reg32 offset="0x8804" name="RB_UNKNOWN_8804"/>
2053         <!-- always 0x0 ? -->
2054         <reg32 offset="0x8805" name="RB_UNKNOWN_8805"/>
2055         <!-- always 0x0 ? -->
2056         <reg32 offset="0x8806" name="RB_UNKNOWN_8806"/>
2057
2058         <!--
2059         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2060         name comes from kernel and is probably right)
2061          -->
2062         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2063                 <!-- see also GRAS_CNTL -->
2064                 <bitfield name="VARYING" pos="0" type="boolean"/>
2065                 <!-- b1 set for interpolateAtCentroid() -->
2066                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2067                 <!-- b2 set instead of b0 when running in per-sample mode -->
2068                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2069                 <!--
2070                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2071                 mode, and frag_face
2072                  -->
2073                 <bitfield name="SIZE" pos="3" type="boolean"/>
2074                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2075                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2076                 <bitfield name="XCOORD" pos="6" type="boolean"/>
2077                 <bitfield name="YCOORD" pos="7" type="boolean"/>
2078                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
2079                 <bitfield name="WCOORD" pos="9" type="boolean"/>
2080                 <bitfield name="UNK10" pos="10" type="boolean"/>
2081         </reg32>
2082         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2083                 <!-- enable bits for various FS sysvalue regs: -->
2084                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2085                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2086                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2087                 <!-- b4 and b5 set in per-sample mode: -->
2088                 <bitfield name="UNK4" pos="4" type="boolean"/>
2089                 <bitfield name="UNK5" pos="5" type="boolean"/>
2090                 <bitfield name="SIZE" pos="6" type="boolean"/>
2091         </reg32>
2092
2093         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2094                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2095                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2096         </reg32>
2097         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2098                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2099         </reg32>
2100         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2101                 <bitfield name="RT0" low="0" high="3"/>
2102                 <bitfield name="RT1" low="4" high="7"/>
2103                 <bitfield name="RT2" low="8" high="11"/>
2104                 <bitfield name="RT3" low="12" high="15"/>
2105                 <bitfield name="RT4" low="16" high="19"/>
2106                 <bitfield name="RT5" low="20" high="23"/>
2107                 <bitfield name="RT6" low="24" high="27"/>
2108                 <bitfield name="RT7" low="28" high="31"/>
2109         </reg32>
2110         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2111                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2112                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2113                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2114                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2115                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2116                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2117                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2118                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2119         </reg32>
2120         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2121                 <!-- Same as SP_SRGB_CNTL -->
2122                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2123                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2124                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2125                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2126                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2127                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2128                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2129                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2130         </reg32>
2131
2132         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2133                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2134         </reg32>
2135         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2136
2137         <!-- always 0x0 ? -->
2138         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2139         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2140         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2141         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2142         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2143         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2144         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2145
2146         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2147                 <reg32 offset="0x0" name="CONTROL">
2148                         <bitfield name="BLEND" pos="0" type="boolean"/>
2149                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2150                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2151                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2152                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2153                 </reg32>
2154                 <reg32 offset="0x1" name="BLEND_CONTROL">
2155                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2156                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2157                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2158                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2159                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2160                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2161                 </reg32>
2162                 <reg32 offset="0x2" name="BUF_INFO">
2163                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2164                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2165                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2166                 </reg32>
2167                 <!--
2168                 at least in gmem, things seem to be aligned to pitch of 64..
2169                 maybe an artifact of tiled format used in gmem?
2170                  -->
2171                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2172                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2173                 <!--
2174                 Compared to a5xx and before, we configure both a GMEM base and
2175                 external base.  Not sure if this is to facilitate GMEM save/
2176                 restore for context switch, or just to simplify state setup to
2177                 not have to care about GMEM vs BYPASS mode.
2178                  -->
2179                 <reg32 offset="0x5" name="BASE_LO"/>
2180                 <reg32 offset="0x6" name="BASE_HI"/>
2181
2182                 <reg64 offset="0x5" name="BASE" type="waddress"/>
2183
2184                 <reg32 offset="0x7" name="BASE_GMEM"/>
2185         </array>
2186
2187         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2188         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2189         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2190         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2191         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2192                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2193                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2194                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2195         </reg32>
2196         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2197                 <!-- per-mrt enable bit -->
2198                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2199                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2200                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2201                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2202         </reg32>
2203         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2204                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2205         </reg32>
2206
2207         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2208                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2209                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2210                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2211                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2212                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2213         </reg32>
2214         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2215         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2216                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2217         </reg32>
2218 <!-- probably: -->
2219         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2220                 <doc>stride of depth/stencil buffer</doc>
2221         </reg32>
2222         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2223                 <doc>size of layer</doc>
2224         </reg32>
2225         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2226         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2227         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
2228         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2229
2230         <!-- always 0x0 ? -->
2231         <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
2232         <!-- always 0x0 ? -->
2233         <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
2234
2235         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2236                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2237                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2238                 <!--
2239                         set for stencil operations that require read from stencil
2240                         buffer, but not for example for stencil clear (which does
2241                         not require read).. so guessing this is analogous to
2242                         READ_DEST_ENABLE for color buffer..
2243                  -->
2244                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2245                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2246                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2247                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2248                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2249                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2250                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2251                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2252                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2253         </reg32>
2254         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2255                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2256         </reg32>
2257         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2258                 <doc>stride of stencil buffer</doc>
2259         </reg32>
2260         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2261                 <doc>size of layer</doc>
2262         </reg32>
2263         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2264         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2265         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
2266         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2267         <reg32 offset="0x8887" name="RB_STENCILREF">
2268                 <bitfield name="REF" low="0" high="7"/>
2269                 <bitfield name="BFREF" low="8" high="15"/>
2270         </reg32>
2271         <reg32 offset="0x8888" name="RB_STENCILMASK">
2272                 <bitfield name="MASK" low="0" high="7"/>
2273                 <bitfield name="BFMASK" low="8" high="15"/>
2274         </reg32>
2275         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2276                 <bitfield name="WRMASK" low="0" high="7"/>
2277                 <bitfield name="BFWRMASK" low="8" high="15"/>
2278         </reg32>
2279         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2280         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2281                 <bitfield name="COPY" pos="1" type="boolean"/>
2282         </reg32>
2283
2284         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2285                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2286         </reg32>
2287
2288         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2289         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2290         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2291
2292         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2293                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2294         </reg32>
2295         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2296         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2297         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2298                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2299                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2300                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2301                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2302                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2303         </reg32>
2304         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
2305         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2306         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2307         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2308         <!-- array-pitch is size of layer -->
2309         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2310         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
2311         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2312         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2313         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2314                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2315                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2316         </reg32>
2317
2318         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2319         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2320         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2321         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2322
2323         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2324         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2325                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2326                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2327                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2328                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2329                 <doc>
2330                         For clearing depth/stencil
2331                                 1 - depth
2332                                 2 - stencil
2333                                 3 - depth+stencil
2334                         For clearing color buffer:
2335                                 then probably a component mask, I always see 0xf
2336                 </doc>
2337                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2338         </reg32>
2339
2340         <!-- always 0x0 ? -->
2341         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2342
2343         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2344         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2345         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
2346         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2347                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2348                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2349         </reg32>
2350         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2351                 <reg32 offset="0" name="ADDR_LO"/>
2352                 <reg32 offset="1" name="ADDR_HI"/>
2353                 <reg64 offset="0" name="ADDR" type="waddress"/>
2354                 <reg32 offset="2" name="PITCH">
2355                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2356                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2357                 </reg32>
2358         </array>
2359         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2360         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2361
2362         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2363         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2364
2365         <bitset name="a6xx_2d_surf_info" inline="yes">
2366                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2367                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2368                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2369                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2370                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2371                 <bitfield name="SRGB" pos="13" type="boolean"/>
2372                 <!-- the rest is only for src -->
2373                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2374                 <bitfield name="FILTER" pos="16" type="boolean"/>
2375                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2376         </bitset>
2377
2378         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2379         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2380         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2381         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2382                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2383         </reg32>
2384
2385         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2386         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2387         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2388                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2389                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2390         </reg32>
2391
2392         <!-- unlike a5xx, these are per channel values rather than packed -->
2393         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2394         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2395         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2396         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2397
2398         <!-- always 0x1 ? -->
2399         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2400
2401         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2402
2403         <reg32 offset="0x8e07" name="RB_CCU_CNTL"/>  <!-- always 7c400004 or 10000000 -->
2404
2405         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2406
2407         <!-- always 0x00ffff00 ? */ -->
2408         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2409         <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
2410         <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
2411
2412         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2413
2414         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2415                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2416         </reg32>
2417
2418         <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
2419         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2420         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2421
2422         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2423                 <reg32 offset="0x0" name="MODE"/>
2424         </array>
2425         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2426                 <reg32 offset="0x0" name="MODE"/>
2427         </array>
2428
2429         <!-- always 0x0 -->
2430         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2431         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2432
2433         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2434                 <!-- one bit per varying component: -->
2435                 <reg32 offset="0" name="DISABLE"/>
2436         </array>
2437
2438         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2439                 <!-- always 0x10000 when SO enabled.. -->
2440                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2441         </reg32>
2442         <reg32 offset="0x9217" name="VPC_SO_PROG">
2443                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2444                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2445                 <bitfield name="A_EN" pos="11" type="boolean"/>
2446                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2447                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2448                 <bitfield name="B_EN" pos="23" type="boolean"/>
2449         </reg32>
2450
2451         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2452         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2453
2454         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2455                 <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
2456                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2457                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2458                 <reg32 offset="2" name="BUFFER_SIZE"/>
2459                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2460                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2461                 <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
2462                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2463                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2464         </array>
2465
2466         <!-- always 0x0 ? -->
2467         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2468                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2469         </reg32>
2470
2471         <!-- always 0x0 ? -->
2472         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2473
2474         <reg32 offset="0x9301" name="VPC_PACK">
2475                 <doc>
2476                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2477                         plus # of transform-feedback (streamout) varyings if using the
2478                         hw streamout (rather than stg instructions in shader)
2479                 </doc>
2480                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2481                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2482                 <!--
2483                 This seems to be the OUTLOC for the psize output.  It could possibly
2484                 be the max-OUTLOC position, but it is only set when VS writes psize
2485                 (and blob always puts psize at highest OUTLOC)
2486                  -->
2487                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2488         </reg32>
2489
2490         <reg32 offset="0x9302" name="VPC_PACK_GS">
2491                 <doc>
2492                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2493                         plus # of transform-feedback (streamout) varyings if using the
2494                         hw streamout (rather than stg instructions in shader)
2495                 </doc>
2496                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2497                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2498                 <!--
2499                 This seems to be the OUTLOC for the psize output.  It could possibly
2500                 be the max-OUTLOC position, but it is only set when VS writes psize
2501                 (and blob always puts psize at highest OUTLOC)
2502                  -->
2503                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2504         </reg32>
2505
2506         <reg32 offset="0x9303" name="VPC_PACK_3">
2507                 <doc>
2508                         domain shader version of VPC_PACK
2509                 </doc>
2510                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2511                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2512                 <!--
2513                 This seems to be the OUTLOC for the psize output.  It could possibly
2514                 be the max-OUTLOC position, but it is only set when VS writes psize
2515                 (and blob always puts psize at highest OUTLOC)
2516                  -->
2517                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2518         </reg32>
2519
2520         <reg32 offset="0x9304" name="VPC_CNTL_0">
2521                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2522                 <bitfield name="VARYING" pos="16" type="boolean"/>
2523         </reg32>
2524
2525         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2526                 <bitfield name="BUF0" pos="0" type="boolean"/>
2527                 <bitfield name="BUF1" pos="3" type="boolean"/>
2528                 <bitfield name="BUF2" pos="6" type="boolean"/>
2529                 <bitfield name="BUF3" pos="9" type="boolean"/>
2530                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2531         </reg32>
2532         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2533                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2534         </reg32>
2535
2536         <!-- always 0x0 ? -->
2537         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2538         <!-- always 0x0 ? -->
2539         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2540
2541         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2542
2543         <!-- always 0x0 ? -->
2544         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2545
2546         <enum name="a6xx_tess_spacing">
2547           <value value="0x0" name="TESS_EQUAL"/>
2548           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2549           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2550         </enum>
2551
2552         <enum name="a6xx_tess_output">
2553           <value value="0x0" name="TESS_POINTS"/>
2554           <value value="0x1" name="TESS_LINES"/>
2555           <value value="0x2" name="TESS_CW_TRIS"/>
2556           <value value="0x3" name="TESS_CCW_TRIS"/>
2557         </enum>
2558
2559         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2560           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2561           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2562         </reg32>
2563
2564         <!-- probably: -->
2565         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2566         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2567
2568         <!-- always 0x1 ? -->
2569         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2570         <reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>
2571
2572         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2573         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2574
2575         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2576
2577         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2578                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2579                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2580                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2581         </reg32>
2582         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2583                 <doc>
2584                         vertex shader
2585
2586                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2587                         plus # of transform-feedback (streamout) varyings if using the
2588                         hw streamout (rather than stg instructions in shader)
2589                 </doc>
2590                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2591                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2592         </reg32>
2593
2594         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2595                 <doc>
2596                   geometry shader
2597                 </doc>
2598                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2599                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2600                 <bitfield name="LAYER" pos="9" type="boolean"/>
2601                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2602         </reg32>
2603
2604         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2605                 <doc>
2606                         hull shader?
2607
2608                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2609                         plus # of transform-feedback (streamout) varyings if using the
2610                         hw streamout (rather than stg instructions in shader)
2611                 </doc>
2612                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2613                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2614         </reg32>
2615         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2616                 <doc>
2617                         domain shader
2618                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2619                         plus # of transform-feedback (streamout) varyings if using the
2620                         hw streamout (rather than stg instructions in shader)
2621                 </doc>
2622                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2623                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2624         </reg32>
2625
2626         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2627                 <doc>
2628                   geometry shader
2629                 </doc>
2630                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2631                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2632                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2633         </reg32>
2634
2635         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2636                 <doc>
2637                   size in vec4s of per-primitive storage for gs
2638                 </doc>
2639                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2640         </reg32>
2641
2642         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2643
2644         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2645         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2646
2647         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2648         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2649                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2650                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2651         </reg32>
2652         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
2653         <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
2654         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
2655         <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
2656
2657         <!-- always 0x0 -->
2658         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2659
2660         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2661                 <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2662         </reg32>
2663         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2664                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2665                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2666                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2667         </reg32>
2668         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2669                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2670                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2671         </reg32>
2672         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2673                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2674                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2675                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2676         </reg32>
2677         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2678         </reg32>
2679         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2680                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2681         </reg32>
2682         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2683         </reg32>
2684
2685         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2686                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2687         </reg32>
2688
2689         <!-- always 0x0 ? -->
2690         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2691         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2692                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2693                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2694                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2695                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2696         </reg32>
2697
2698         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2699         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2700         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2701                 <reg64 offset="0x0" name="BASE" type="address"/>
2702                 <reg32 offset="0x0" name="BASE_LO"/>
2703                 <reg32 offset="0x1" name="BASE_HI"/>
2704                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2705                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2706         </array>
2707         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2708                 <reg32 offset="0x0" name="INSTR">
2709                         <!-- IDX appears to index into VFD_FETCH[] -->
2710                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2711                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2712                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2713                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2714                         <bitfield name="UNK30" pos="30" type="boolean"/>
2715                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2716                 </reg32>
2717                 <reg32 offset="0x1" name="STEP_RATE"/>
2718         </array>
2719         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2720                 <reg32 offset="0x0" name="INSTR">
2721                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2722                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2723                 </reg32>
2724         </array>
2725
2726         <!-- always 0x1 ? -->
2727         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2728
2729         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2730                 <!--
2731                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2732                 used registers is a bit odd too:
2733                         - used (half): 0-15 68-179 (cnt=128, max=179)
2734                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2735                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2736                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2737                 then:
2738                         - used (merged): 0-191 (cnt=192, max=191)
2739                 So I think if b31 is set, then the half precision registers overlap
2740                 the full precision registers.  (Which seems like a pretty sensible
2741                 feature, actually I'm not sure when you *wouldn't* want to use that,
2742                 since it gives register allocation more flexibility)
2743                  -->
2744                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2745                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2746                 <!-- seems to be nesting level for flow control:.. -->
2747                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2748                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2749                 <bitfield name="VARYING" pos="22" type="boolean"/>
2750                 <!-- set when dFdxFine/dFdyFine is used -->
2751                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2752                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2753                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2754         </bitset>
2755
2756         <bitset name="a6xx_sp_xs_config" inline="yes">
2757                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2758                 <!--
2759                 number of textures and samplers.. these might be swapped, with GL I
2760                 always see the same value for both.
2761                  -->
2762                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2763                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2764                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2765         </bitset>
2766
2767         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2768         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2769                 <!-- # of VS outputs including pos/psize -->
2770                 <bitfield name="VSOUT" low="0" high="4" type="uint"/>
2771         </reg32>
2772         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2773                 <reg32 offset="0x0" name="REG">
2774                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2775                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2776                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2777                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2778                 </reg32>
2779         </array>
2780         <!--
2781         Starting with a5xx, position/psize outputs from shader end up in the
2782         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2783         the last entries too, except when gl_PointCoord is used, blob inserts
2784         an extra varying after, but with a lower OUTLOC position.  If present,
2785         psize is last, preceded by position.
2786          -->
2787         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2788                 <reg32 offset="0x0" name="REG">
2789                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2790                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2791                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2792                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2793                 </reg32>
2794         </array>
2795
2796         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2797         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2798         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2799         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2800         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2801         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2802
2803         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2804         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2805         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2806         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2807         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2808         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2809         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2810         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2811
2812         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2813         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2814                 <!-- # of DS outputs including pos/psize -->
2815                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2816         </reg32>
2817         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2818                 <reg32 offset="0x0" name="REG">
2819                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2820                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2821                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2822                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2823                 </reg32>
2824         </array>
2825         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2826                 <reg32 offset="0x0" name="REG">
2827                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2828                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2829                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2830                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2831                 </reg32>
2832         </array>
2833
2834         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2835         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2836         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2837         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2838         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2839         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2840
2841         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2842         <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
2843
2844         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
2845                 <!-- # of VS outputs including pos/psize -->
2846                 <bitfield name="GSOUT" low="0" high="4" type="uint"/>
2847                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2848         </reg32>
2849
2850         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
2851                 <reg32 offset="0x0" name="REG">
2852                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2853                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2854                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2855                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2856                 </reg32>
2857         </array>
2858
2859         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
2860                 <reg32 offset="0x0" name="REG">
2861                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2862                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2863                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2864                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2865                 </reg32>
2866         </array>
2867
2868         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
2869         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
2870         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
2871         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2872         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
2873
2874         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
2875         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
2876         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
2877         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
2878         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
2879         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
2880         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
2881         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
2882         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
2883         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
2884         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
2885         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
2886         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
2887         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
2888         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
2889         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
2890
2891         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2892         <reg32 offset="0xa981" name="SP_UNKNOWN_A981">
2893                 <bitfield name="FACE0" pos="0" type="boolean"/>
2894                 <bitfield name="FACE1" pos="1" type="boolean"/>
2895                 <bitfield name="FACE2" pos="2" type="boolean"/>
2896                 <bitfield name="FACE3" pos="3" type="boolean"/>
2897                 <bitfield name="FACE4" pos="4" type="boolean"/>
2898                 <bitfield name="FACE5" pos="5" type="boolean"/>
2899         </reg32>
2900         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
2901         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
2902         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
2903
2904         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
2905                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2906                 <bitfield name="UNK8" pos="8" type="boolean"/>
2907                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2908         </reg32>
2909         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
2910                 <!-- Same as RB_SRGB_CNTL -->
2911                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2912                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2913                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2914                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2915                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2916                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2917                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2918                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2919         </reg32>
2920         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
2921                 <bitfield name="RT0" low="0" high="3"/>
2922                 <bitfield name="RT1" low="4" high="7"/>
2923                 <bitfield name="RT2" low="8" high="11"/>
2924                 <bitfield name="RT3" low="12" high="15"/>
2925                 <bitfield name="RT4" low="16" high="19"/>
2926                 <bitfield name="RT5" low="20" high="23"/>
2927                 <bitfield name="RT6" low="24" high="27"/>
2928                 <bitfield name="RT7" low="28" high="31"/>
2929         </reg32>
2930         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
2931                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
2932                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
2933         </reg32>
2934         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
2935                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2936         </reg32>
2937
2938         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
2939                 <reg32 offset="0" name="REG">
2940                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2941                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2942                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2943                 </reg32>
2944         </array>
2945
2946         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
2947                 <!-- unknown bits 0x7fc0 always set -->
2948                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
2949                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
2950                 <bitfield name="UNK3" pos="3" type="boolean"/>
2951                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
2952         </reg32>
2953         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
2954                 <reg32 offset="0" name="CMD">
2955                         <bitfield name="SRC" low="0" high="6" type="uint"/>
2956                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
2957                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
2958                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
2959                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
2960                         <bitfield name="HALF" pos="26" type="boolean"/>
2961                         <!--
2962                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
2963                         skip pre-fetch.. TODO test texelFetch
2964                          -->
2965                         <bitfield name="CMD" low="27" high="31"/>
2966                 </reg32>
2967         </array>
2968
2969         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
2970
2971         <!-- always 0x0 ? -->
2972         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
2973
2974         <!-- set for compute shaders, always 0x41 -->
2975         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
2976
2977         <!-- set for compute shaders, always 0x0 -->
2978         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
2979
2980         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
2981
2982         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
2983         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
2984         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
2985         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
2986         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
2987         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
2988         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
2989         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
2990
2991         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
2992                 <doc>per MRT</doc>
2993                 <reg32 offset="0x0" name="REG">
2994                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2995                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
2996                 </reg32>
2997         </array>
2998
2999         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3000         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3001         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3002         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3003         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3004
3005         <!--
3006         IBO state for compute shader:
3007          -->
3008         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3009         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3010         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3011
3012         <!-- always 0x5 ? -->
3013         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3014
3015         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3016         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3017
3018         <!--
3019         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3020         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3021          -->
3022         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3023         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3024         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3025
3026         <!--
3027         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
3028          -->
3029         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3030                 <bitfield name="NORM" pos="0" type="boolean"/>
3031                 <bitfield name="SINT" pos="1" type="boolean"/>
3032                 <bitfield name="UINT" pos="2" type="boolean"/>
3033                 <!-- looks like HW only cares about the base type of this format,
3034                      which matches the ifmt? -->
3035                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3036                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3037                 <bitfield name="SRGB" pos="11" type="boolean"/>
3038                 <!-- some sort of channel mask, not sure what it is for -->
3039                 <bitfield name="MASK" low="12" high="15"/>
3040         </reg32>
3041
3042         <!-- always 0x0 -->
3043         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3044
3045         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3046         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3047
3048         <!-- always 0x3f ? -->
3049         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3050
3051         <!-- always 0x0 ? -->
3052         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3053         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3054
3055         <!-- could be all the stuff below here is actually TPL1?? -->
3056
3057         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3058                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3059         </reg32>
3060         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3061                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3062                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3063         </reg32>
3064
3065         <!-- looks to work in the same way as a5xx: -->
3066         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3067         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3068         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3069         <!-- always 0x0 ? -->
3070         <reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/>
3071
3072         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3073
3074         <!--
3075         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3076         badly named or the functionality moved in a6xx.  But downstream kernel
3077         calls this "a6xx_sp_ps_tp_2d_cluster"
3078          -->
3079         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3080         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3081                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3082                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3083         </reg32>
3084         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3085         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3086         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3087            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3088         </reg32>
3089
3090         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3091         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3092         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3093                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3094                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3095         </reg32>
3096
3097         <!-- always 0x00100000 ? -->
3098         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3099
3100         <!-- always 0x44 ? -->
3101         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3102
3103         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3104                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3105                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3106         </bitset>
3107
3108         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3109         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3110         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3111         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3112
3113         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3114
3115         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3116                 <!-- always 0x7 ? -->
3117         </reg32>
3118         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3119                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3120                 <!-- SAMPLEID is loaded into a half-precision register: -->
3121                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3122                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3123                 <!--
3124                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3125                 to be divided by to scale to a single fragment.  It is probably
3126                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3127                  -->
3128                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3129         </reg32>
3130         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3131                 <!-- register loaded with position (bary.f) -->
3132                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3133                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3134         </reg32>
3135         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3136                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3137                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3138                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3139         </reg32>
3140         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3141                 <!-- unknown regid in low 8b -->
3142         </reg32>
3143         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3144
3145         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3146                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3147                 <!-- localsize is value minus one: -->
3148                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3149                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3150                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3151         </reg32>
3152         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3153                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3154         </reg32>
3155         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3156                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3157         </reg32>
3158         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3159                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3160         </reg32>
3161         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3162                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3163         </reg32>
3164         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3165                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3166         </reg32>
3167         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3168                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3169         </reg32>
3170         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3171                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3172                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3173                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3174                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3175         </reg32>
3176         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3177         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3178         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3179         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3180
3181         <!-- probably: -->
3182         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3183
3184         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3185
3186         <!-- always 0x0 ? -->
3187         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3188
3189         <!-- always 0x80 ? -->
3190         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3191         <!-- always 0x0 ? -->
3192         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3193         <!-- always 0x0 ? -->
3194         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3195
3196 </domain>
3197
3198 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3199 <domain name="A6XX_TEX_SAMP" width="32">
3200         <doc>Texture sampler dwords</doc>
3201         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3202                 <value name="A6XX_TEX_NEAREST" value="0"/>
3203                 <value name="A6XX_TEX_LINEAR" value="1"/>
3204                 <value name="A6XX_TEX_ANISO" value="2"/>
3205         </enum>
3206         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3207                 <value name="A6XX_TEX_REPEAT" value="0"/>
3208                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3209                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3210                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3211                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3212         </enum>
3213         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3214                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3215                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3216                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3217                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3218                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3219         </enum>
3220         <reg32 offset="0" name="0">
3221                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3222                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3223                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3224                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3225                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3226                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3227                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3228                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3229         </reg32>
3230         <reg32 offset="1" name="1">
3231                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3232                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3233                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3234                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3235                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3236                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3237         </reg32>
3238         <reg32 offset="2" name="2">
3239                 <bitfield name="BCOLOR_OFFSET" low="0" high="31"/>
3240         </reg32>
3241         <reg32 offset="3" name="3"/>
3242 </domain>
3243
3244 <domain name="A6XX_TEX_CONST" width="32">
3245         <doc>Texture constant dwords</doc>
3246         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3247                 <value name="A6XX_TEX_X" value="0"/>
3248                 <value name="A6XX_TEX_Y" value="1"/>
3249                 <value name="A6XX_TEX_Z" value="2"/>
3250                 <value name="A6XX_TEX_W" value="3"/>
3251                 <value name="A6XX_TEX_ZERO" value="4"/>
3252                 <value name="A6XX_TEX_ONE" value="5"/>
3253         </enum>
3254         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3255                 <value name="A6XX_TEX_1D" value="0"/>
3256                 <value name="A6XX_TEX_2D" value="1"/>
3257                 <value name="A6XX_TEX_CUBE" value="2"/>
3258                 <value name="A6XX_TEX_3D" value="3"/>
3259         </enum>
3260         <reg32 offset="0" name="0">
3261                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3262                 <bitfield name="SRGB" pos="2" type="boolean"/>
3263                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3264                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3265                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3266                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3267                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3268                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3269                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3270                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3271         </reg32>
3272         <reg32 offset="1" name="1">
3273                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3274                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3275         </reg32>
3276         <reg32 offset="2" name="2">
3277                 <!--
3278                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3279                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3280
3281                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3282                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3283                  -->
3284                 <bitfield name="UNK4" pos="4" type="boolean"/>
3285                 <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
3286                 <doc>Pitch in bytes (so actually stride)</doc>
3287                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3288                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3289                 <bitfield name="UNK31" pos="31" type="boolean"/>
3290         </reg32>
3291         <reg32 offset="3" name="3">
3292                 <!--
3293                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3294                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3295                 layer size at the point that it stops being reduced moving to
3296                 higher (smaller) mipmap levels
3297                  -->
3298                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3299                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3300                 <!--
3301                 by default levels with w < 16 are linear
3302                 TILE_ALL makes all levels have tiling
3303                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3304                  -->
3305                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3306                 <bitfield name="FLAG" pos="28" type="boolean"/>
3307         </reg32>
3308         <reg32 offset="4" name="4">
3309                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3310         </reg32>
3311         <reg32 offset="5" name="5">
3312                 <bitfield name="BASE_HI" low="0" high="16"/>
3313                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3314         </reg32>
3315         <reg32 offset="6" name="6"/>
3316         <reg32 offset="7" name="7">
3317                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3318         </reg32>
3319         <reg32 offset="8" name="8">
3320                 <bitfield name="FLAG_HI" low="0" high="16"/>
3321         </reg32>
3322         <reg32 offset="9" name="9">
3323                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3324         </reg32>
3325         <reg32 offset="10" name="10">
3326                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3327                 <!-- log2 size of the first level, required for mipmapping -->
3328                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3329                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3330         </reg32>
3331         <reg32 offset="11" name="11"/>
3332         <reg32 offset="12" name="12"/>
3333         <reg32 offset="13" name="13"/>
3334         <reg32 offset="14" name="14"/>
3335         <reg32 offset="15" name="15"/>
3336 </domain>
3337
3338 <!--
3339 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3340 naming is just because I r/e'd SSBOs first.  I should probably come up
3341 with a better name.
3342 -->
3343 <domain name="A6XX_IBO" width="32">
3344         <reg32 offset="0" name="0">
3345                 <!--
3346                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3347                 used but if they are good chance position is same as TEX_CONST
3348                  -->
3349                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3350                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3351         </reg32>
3352         <reg32 offset="1" name="1">
3353                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3354                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3355         </reg32>
3356         <reg32 offset="2" name="2">
3357                 <!--
3358                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3359                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3360                  -->
3361                 <bitfield name="UNK4" pos="4" type="boolean"/>
3362                 <doc>Pitch in bytes (so actually stride)</doc>
3363                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3364                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3365                 <bitfield name="UNK31" pos="31" type="boolean"/>
3366         </reg32>
3367         <reg32 offset="3" name="3">
3368                 <!--
3369                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3370                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3371                 layer size at the point that it stops being reduced moving to
3372                 higher (smaller) mipmap levels
3373                  -->
3374                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3375                 <bitfield name="UNK27" pos="27" type="boolean"/>
3376                 <bitfield name="FLAG" pos="28" type="boolean"/>
3377         </reg32>
3378         <reg32 offset="4" name="4">
3379                 <bitfield name="BASE_LO" low="0" high="31"/>
3380         </reg32>
3381         <reg32 offset="5" name="5">
3382                 <bitfield name="BASE_HI" low="0" high="16"/>
3383                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3384         </reg32>
3385         <reg32 offset="6" name="6">
3386         </reg32>
3387         <reg32 offset="7" name="7">
3388         </reg32>
3389         <reg32 offset="8" name="8">
3390         </reg32>
3391         <reg32 offset="9" name="9">
3392                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3393         </reg32>
3394         <reg32 offset="10" name="10">
3395                 <!--
3396                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3397                 don't seem to be particularly sensible... or needed for UBWC to work
3398                  -->
3399                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3400         </reg32>
3401 </domain>
3402
3403 <domain name="A6XX_UBO" width="32">
3404         <reg32 offset="0" name="0">
3405                 <bitfield name="BASE_LO" low="0" high="31"/>
3406         </reg32>
3407         <reg32 offset="1" name="1">
3408                 <bitfield name="BASE_HI" low="0" high="16"/>
3409                 <!-- size probably in high bits -->
3410         </reg32>
3411 </domain>
3412
3413 <domain name="A6XX_PDC" width="32">
3414         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3415         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3416         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3417         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3418         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3419         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3420         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3421         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3422         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3423         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3424         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3425         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3426         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3427         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3428         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3429         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3430         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3431         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3432         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3433         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3434         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3435         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3436         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3437         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3438         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3439         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3440 </domain>
3441
3442 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3443         <reg32 offset="0x0" name="MEM_0"/>
3444 </domain>
3445
3446 <domain name="A6XX_CX_DBGC" width="32">
3447         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3448                 <bitfield high="7" low="0" name="PING_INDEX"/>
3449                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3450         </reg32>
3451         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3452         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3453         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3454         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3455                 <bitfield high="5" low="0" name="TRACEEN"/>
3456                 <bitfield high="14" low="12" name="GRANU"/>
3457                 <bitfield high="31" low="28" name="SEGT"/>
3458         </reg32>
3459         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3460                 <bitfield high="27" low="24" name="ENABLE"/>
3461         </reg32>
3462         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3463         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3464         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3465         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3466         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3467         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3468         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3469         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3470         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3471                 <bitfield high="3" low="0" name="BYTEL0"/>
3472                 <bitfield high="7" low="4" name="BYTEL1"/>
3473                 <bitfield high="11" low="8" name="BYTEL2"/>
3474                 <bitfield high="15" low="12" name="BYTEL3"/>
3475                 <bitfield high="19" low="16" name="BYTEL4"/>
3476                 <bitfield high="23" low="20" name="BYTEL5"/>
3477                 <bitfield high="27" low="24" name="BYTEL6"/>
3478                 <bitfield high="31" low="28" name="BYTEL7"/>
3479         </reg32>
3480         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3481                 <bitfield high="3" low="0" name="BYTEL8"/>
3482                 <bitfield high="7" low="4" name="BYTEL9"/>
3483                 <bitfield high="11" low="8" name="BYTEL10"/>
3484                 <bitfield high="15" low="12" name="BYTEL11"/>
3485                 <bitfield high="19" low="16" name="BYTEL12"/>
3486                 <bitfield high="23" low="20" name="BYTEL13"/>
3487                 <bitfield high="27" low="24" name="BYTEL14"/>
3488                 <bitfield high="31" low="28" name="BYTEL15"/>
3489         </reg32>
3490
3491         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3492         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3493 </domain>
3494
3495 <domain name="A6XX_CX_MISC" width="32">
3496         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3497         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3498 </domain>
3499
3500 </database>