src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
  26         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  27
  28         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  29         <value value="0x10" name="FMT6_8_8_SNORM"/>
  30         <value value="0x11" name="FMT6_8_8_UINT"/>
  31         <value value="0x12" name="FMT6_8_8_SINT"/>
  32         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  33
  34         <value value="0x15" name="FMT6_16_UNORM"/>
  35         <value value="0x16" name="FMT6_16_SNORM"/>
  36         <value value="0x17" name="FMT6_16_FLOAT"/>
  37         <value value="0x18" name="FMT6_16_UINT"/>
  38         <value value="0x19" name="FMT6_16_SINT"/>
  39
  40         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  41         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  42         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  43         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  44
  45         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  46         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  47         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  48         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  49         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  50
  51         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  52
  53         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  54         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  55         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  56         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  57         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  58
  59         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  60
  61         <value value="0x43" name="FMT6_16_16_UNORM"/>
  62         <value value="0x44" name="FMT6_16_16_SNORM"/>
  63         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  64         <value value="0x46" name="FMT6_16_16_UINT"/>
  65         <value value="0x47" name="FMT6_16_16_SINT"/>
  66
  67         <value value="0x48" name="FMT6_32_UNORM"/>
  68         <value value="0x49" name="FMT6_32_SNORM"/>
  69         <value value="0x4a" name="FMT6_32_FLOAT"/>
  70         <value value="0x4b" name="FMT6_32_UINT"/>
  71         <value value="0x4c" name="FMT6_32_SINT"/>
  72         <value value="0x4d" name="FMT6_32_FIXED"/>
  73
  74         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  75         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  76         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  77         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  78         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  79
  80         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  81         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  82         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  83         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  84         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  85
  86         <value value="0x65" name="FMT6_32_32_UNORM"/>
  87         <value value="0x66" name="FMT6_32_32_SNORM"/>
  88         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  89         <value value="0x68" name="FMT6_32_32_UINT"/>
  90         <value value="0x69" name="FMT6_32_32_SINT"/>
  91         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  92
  93         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  94         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  95         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  96         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  97         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  98         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  99
 100         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 101         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 102         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 103         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 104         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 105         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 106
 107         <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/>
 108         <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/>
 109         <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/>
 110         <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/>
 111
 112         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 113
 114         <!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
 115              which has different UBWC compression from regular 8_UNORM format -->
 116         <value value="0x94" name="FMT6_8_PLANE_UNORM"/>
 117
 118         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 119
 120         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 121         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 122         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 123         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 124         <value value="0xaf" name="FMT6_ETC1"/>
 125         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 126         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 127         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 128         <value value="0xb3" name="FMT6_DXT1"/>
 129         <value value="0xb4" name="FMT6_DXT3"/>
 130         <value value="0xb5" name="FMT6_DXT5"/>
 131         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 132         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 133         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 134         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 135         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 136         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 137         <value value="0xc0" name="FMT6_BPTC"/>
 138         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 139         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 140         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 141         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 142         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 143         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 144         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 145         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 146         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 147         <value value="0xca" name="FMT6_ASTC_10x6"/>
 148         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 149         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 150         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 151         <value value="0xce" name="FMT6_ASTC_12x12"/>
 152
 153         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 154         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 155
 156         <!-- Not a hw enum, used internally in driver -->
 157         <value value="0xff" name="FMT6_NONE"/>
 158
 159 </enum>
 160
 161 <!-- probably same as a5xx -->
 162 <enum name="a6xx_polygon_mode">
 163         <value name="POLYMODE6_POINTS" value="1"/>
 164         <value name="POLYMODE6_LINES" value="2"/>
 165         <value name="POLYMODE6_TRIANGLES" value="3"/>
 166 </enum>
 167
 168 <enum name="a6xx_depth_format">
 169         <value name="DEPTH6_NONE" value="0"/>
 170         <value name="DEPTH6_16" value="1"/>
 171         <value name="DEPTH6_24_8" value="2"/>
 172         <value name="DEPTH6_32" value="4"/>
 173 </enum>
 174
 175 <bitset name="a6x_cp_protect" inline="yes">
 176         <bitfield name="BASE_ADDR" low="0" high="17"/>
 177         <bitfield name="MASK_LEN" low="18" high="30"/>
 178         <bitfield name="READ" pos="31"/>
 179 </bitset>
 180
 181 <enum name="a6xx_shader_id">
 182         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 183         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 184         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 185         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 186         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 187         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 188         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 189         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 190         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 191         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 192         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 193         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 194         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 195         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 196         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 197         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 198         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 199         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 200         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 201         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 202         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 203         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 204         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 205         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 206         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 207         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 208         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 209         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 210         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 211         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 212         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 213         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 214         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 215         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 216         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 217         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 218         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 219         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 220         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 221         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 222         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 223         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 224         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 225 </enum>
 226
 227 <enum name="a6xx_debugbus_id">
 228         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 229         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 230         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 231         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 232         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 233         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 234         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 235         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 236         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 237         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 238         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 239         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 240         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 241         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 242         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 243         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 244         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 245         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 246         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 247         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 248         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 249         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 250         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 251         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 252         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 253         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 254         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 255         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 256         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 257         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 258         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 259         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 260         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 261         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 262         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 263         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 264         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 265         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 266         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 267         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 268         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 269         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 270         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 271 </enum>
 272
 273 <enum name="a6xx_cp_perfcounter_select">
 274         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 275         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 276         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 277         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 278         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 279         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 280         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 281         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 282         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 283         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 284         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 285         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 286         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 287         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 288         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 289         <value value="15" name="PERF_CP_SQE_IDLE"/>
 290         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 291         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 292         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 293         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 294         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 295         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 296         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 297         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 298         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 299         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 300         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 301         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 302         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 303         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 304         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 305         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 306         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 307         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 308         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 309         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 310         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 311         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 312         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 313         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 314         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 315         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 316         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 317         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 318         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 319         <value value="45" name="PERF_CP_PM4_DATA"/>
 320         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 321         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 322         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 323         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 324 </enum>
 325
 326 <enum name="a6xx_rbbm_perfcounter_select">
 327         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 328         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 329         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 330         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 331         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 332         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 333         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 334         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 335         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 336         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 337         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 338         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 339         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 340         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 341 </enum>
 342
 343 <enum name="a6xx_pc_perfcounter_select">
 344         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 345         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 346         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 347         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 348         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 349         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 350         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 351         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 352         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 353         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 354         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 355         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 356         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 357         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 358         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 359         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 360         <value value="16" name="PERF_PC_INSTANCES"/>
 361         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 362         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 363         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 364         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 365         <value value="21" name="PERF_PC_IA_VERTICES"/>
 366         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 367         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 368         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 369         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 370         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 371         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 372         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 373         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 374         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 375         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 376         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 377         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 378         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 379         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 380         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 381         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 382         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 383         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 384         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 385         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 386 </enum>
 387
 388 <enum name="a6xx_vfd_perfcounter_select">
 389         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 390         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 391         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 392         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 393         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 394         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 395         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 396         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 397         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 398         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 399         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 400         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 401         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 402         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 403         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 404         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 405         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 406         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 407         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 408         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 409         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 410         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 411         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 412 </enum>
 413
 414 <enum name="a6xx_hlsq_perfcounter_select">
 415         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 416         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 417         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 418         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 419         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 420         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 421         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 422         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 423         <value value="8" name="PERF_HLSQ_QUADS"/>
 424         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 425         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 426         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 427         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 428         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 429         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 430         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 431         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 432         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 433         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 434         <value value="19" name="PERF_HLSQ_PIXELS"/>
 435         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 436 </enum>
 437
 438 <enum name="a6xx_vpc_perfcounter_select">
 439         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 440         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 441         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 442         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 443         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 444         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 445         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 446         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 447         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 448         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 449         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 450         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 451         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 452         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 453         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 454         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 455         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 456         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 457         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 458         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 459         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 460         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 461         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 462         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 463         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 464         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 465         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 466         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 467 </enum>
 468
 469 <enum name="a6xx_tse_perfcounter_select">
 470         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 471         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 472         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 473         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 474         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 475         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 476         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 477         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 478         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 479         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 480         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 481         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 482         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 483         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 484         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 485         <value value="15" name="PERF_TSE_CINVOCATION"/>
 486         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 487         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 488         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 489         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 490 </enum>
 491
 492 <enum name="a6xx_ras_perfcounter_select">
 493         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 494         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 495         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 496         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 497         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 498         <value value="5" name="PERF_RAS_8X4_TILES"/>
 499         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 500         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 501         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 502         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 503         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 504         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 505         <value value="12" name="PERF_RAS_BLOCKS"/>
 506 </enum>
 507
 508 <enum name="a6xx_uche_perfcounter_select">
 509         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 510         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 511         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 512         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 513         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 514         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 515         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 516         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 517         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 518         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 519         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 520         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 521         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 522         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 523         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 524         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 525         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 526         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 527         <value value="18" name="PERF_UCHE_EVICTS"/>
 528         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 529         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 530         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 531         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 532         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 533         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 534         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 535         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 536         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 537         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 538         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 539         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 540         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 541         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 542         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 543         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 544         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 545         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 546         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 547         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 548         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 549 </enum>
 550
 551 <enum name="a6xx_tp_perfcounter_select">
 552         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 553         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 554         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 555         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 556         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 557         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 558         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 559         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 560         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 561         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 562         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 563         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 564         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 565         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 566         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 567         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 568         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 569         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 570         <value value="18" name="PERF_TP_QUADS_1D"/>
 571         <value value="19" name="PERF_TP_QUADS_2D"/>
 572         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 573         <value value="21" name="PERF_TP_QUADS_3D"/>
 574         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 575         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 576         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 577         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 578         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 579         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 580         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 581         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 582         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 583         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 584         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 585         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 586         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 587         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 588         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 589         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 590         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 591         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 592         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 593         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 594         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 595         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 596         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 597         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 598         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 599         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 600         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 601         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 602         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 603         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 604         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 605         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 606         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 607         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 608         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 609 </enum>
 610
 611 <enum name="a6xx_sp_perfcounter_select">
 612         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 613         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 614         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 615         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 616         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 617         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 618         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 619         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 620         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 621         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 622         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 623         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 624         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 625         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 626         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 627         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 628         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 629         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 630         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 631         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 632         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 633         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 634         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 635         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 636         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 637         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 638         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 639         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 640         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 641         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 642         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 643         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 644         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 645         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 646         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 647         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 648         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 649         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 650         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 651         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 652         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 653         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 654         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 655         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 656         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 657         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 658         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 659         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 660         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 661         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 662         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 663         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 664         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 665         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 666         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 667         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 668         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 669         <value value="57" name="PERF_SP_GPR_READ"/>
 670         <value value="58" name="PERF_SP_GPR_WRITE"/>
 671         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 672         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 673         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 674         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 675         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 676         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 677         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 678         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 679         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 680         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 681         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 682         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 683         <value value="71" name="PERF_SP_WORKING_EU"/>
 684         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 685         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 686         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 687         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 688         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 689         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 690         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 691         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 692         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 693         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 694         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 695         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 696         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 697 </enum>
 698
 699 <enum name="a6xx_rb_perfcounter_select">
 700         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 701         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 702         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 703         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 704         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 705         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 706         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 707         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 708         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 709         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 710         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 711         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 712         <value value="12" name="PERF_RB_Z_READ"/>
 713         <value value="13" name="PERF_RB_Z_WRITE"/>
 714         <value value="14" name="PERF_RB_C_READ"/>
 715         <value value="15" name="PERF_RB_C_WRITE"/>
 716         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 717         <value value="17" name="PERF_RB_Z_PASS"/>
 718         <value value="18" name="PERF_RB_Z_FAIL"/>
 719         <value value="19" name="PERF_RB_S_FAIL"/>
 720         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 721         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 722         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 723         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 724         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 725         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 726         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 727         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 728         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 729         <value value="29" name="PERF_RB_3D_PIXELS"/>
 730         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 731         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 732         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 733         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 734         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 735         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 736         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 737         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 738         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 739         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 740         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 741         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 742         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 743         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 744         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 745         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 746         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 747         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 748 </enum>
 749
 750 <enum name="a6xx_vsc_perfcounter_select">
 751         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 752         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 753         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 754         <value value="3" name="PERF_VSC_EOT_NUM"/>
 755         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 756 </enum>
 757
 758 <enum name="a6xx_ccu_perfcounter_select">
 759         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 760         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 761         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 762         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 763         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 764         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 765         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 766         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 767         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 768         <value value="9" name="PERF_CCU_GMEM_READ"/>
 769         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 770         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 771         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 772         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 773         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 774         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 775         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 776         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 777         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 778         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 779         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 780         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 781         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 782         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 783         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 784         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 785         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 786         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 787         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 788 </enum>
 789
 790 <enum name="a6xx_lrz_perfcounter_select">
 791         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 792         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 793         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 794         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 795         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 796         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 797         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 798         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 799         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 800         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 801         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 802         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 803         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 804         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 805         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 806         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 807         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 808         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 809         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 810         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 811         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 812         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 813         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 814         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 815         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 816         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 817         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 818         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 819 </enum>
 820
 821 <enum name="a6xx_cmp_perfcounter_select">
 822         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 823         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 824         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 825         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 826         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 827         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 828         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 829         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 830         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 831         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 832         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 833         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 834         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 835         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 836         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 837         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 838         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 839         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 840         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 841         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 842         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 843         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 844         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 845         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 846         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 847         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 848         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 849         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 850         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 851         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 852         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 853         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 854         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 855         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 856         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 857         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 858         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 859         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 860         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 861         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 862 </enum>
 863
 864 <!--
 865 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 866 component type/size, so I think it relates to internal format used for
 867 blending?  The one exception is that 16b unorm and 32b float use the
 868 same value... maybe 16b unorm is uncommon enough that it was just easier
 869 to upconvert to 32b float internally?
 870
 871  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 872 16b unorm:   4
 873
 874 32b int:     7
 875 16b int:     6
 876  8b int:     5
 877
 878 32b float:   4
 879 16b float:   3
 880  -->
 881 <enum name="a6xx_2d_ifmt">
 882         <value value="0x10" name="R2D_UNORM8"/>
 883         <value value="0x7"  name="R2D_INT32"/>
 884         <value value="0x6"  name="R2D_INT16"/>
 885         <value value="0x5"  name="R2D_INT8"/>
 886         <value value="0x4"  name="R2D_FLOAT32"/>
 887         <value value="0x3"  name="R2D_FLOAT16"/>
 888         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 889         <value value="0x0"  name="R2D_RAW"/>
 890 </enum>
 891
 892 <enum name="a6xx_ztest_mode">
 893         <doc>Allow early z-test and early-lrz (if applicable)</doc>
 894         <value value="0x0" name="A6XX_EARLY_Z"/>
 895         <doc>Disable early z-test and early-lrz test (if applicable)</doc>
 896         <value value="0x1" name="A6XX_LATE_Z"/>
 897         <doc>
 898                 A special mode that allows early-lrz test but disables
 899                 early-z test.  Which might sound a bit funny, since
 900                 lrz-test happens before z-test.  But as long as a couple
 901                 conditions are maintained this allows using lrz-test in
 902                 cases where fragment shader has kill/discard:
 903
 904                 1) Disable lrz-write in cases where it is uncertain during
 905                    binning pass that a fragment will pass.  Ie.  if frag
 906                    shader has-kill, writes-z, or alpha/stencil test is
 907                    enabled.  (For correctness, lrz-write must be disabled
 908                    when blend is enabled.)  This is analogous to how a
 909                    z-prepass works.
 910
 911                 2) Disable lrz-write and test if a depth-test direction
 912                    reversal is detected.  Due to condition (1), the contents
 913                    of the lrz buffer are a conservative estimation of the
 914                    depth buffer during the draw pass.  Meaning that geometry
 915                    that we know for certain will not be visible will not pass
 916                    lrz-test.  But geometry which may be (or contributes to
 917                    blend) will pass the lrz-test.
 918
 919                 This allows us to keep early-lrz-test in cases where the frag
 920                 shader does not write-z (ie. we know the z-value before FS)
 921                 and does not have side-effects (image/ssbo writes, etc), but
 922                 does have kill/discard.  Which turns out to be a common
 923                 enough case that it is useful to keep early-lrz test against
 924                 the conservative lrz buffer to discard fragments that we
 925                 know will definitely not be visible.
 926         </doc>
 927         <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
 928 </enum>
 929
 930 <domain name="A6XX" width="32">
 931         <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
 932                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 933                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 934                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 935                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 936                 <bitfield name="CP_SW" pos="8"/>
 937                 <bitfield name="CP_HW_ERROR" pos="9"/>
 938                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 939                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 940                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 941                 <bitfield name="CP_IB2" pos="13"/>
 942                 <bitfield name="CP_IB1" pos="14"/>
 943                 <bitfield name="CP_RB" pos="15"/>
 944                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 945                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 946                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 947                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 948                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 949                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 950                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 951                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 952                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 953                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 954                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 955         </bitset>
 956
 957         <bitset name="A6XX_CP_INT">
 958                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 959                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 960                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 961                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 962                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 963                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 964                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 965         </bitset>
 966
 967         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 968         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 969         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 970         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 971         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 972         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 973         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 974         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 975         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 976                 <bitfield name="IFPC" pos="0" type="boolean"/>
 977         </reg32>
 978         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 979         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 980         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 981         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 982         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 983         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 984         <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
 985         <!-- all the threshold values seem to be in units of quad-dwords: -->
 986         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 987                 <doc>
 988                         b0..7 seems to contain the size of buffered by not yet processed
 989                         RB level cmdstream.. it's possible that it is a low threshold
 990                         and b8..15 is a high threshold?
 991
 992                         b16..23 identifies where IB1 data starts (and RB data ends?)
 993
 994                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 995                 </doc>
 996                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 997                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 998                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 999                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
1000         </reg32>
1001         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1002                 <doc>
1003                         low bits identify where CP_SET_DRAW_STATE stateobj
1004                         processing starts (and IB2 data ends). I'm guessing
1005                         b8 is part of this since (from downstream kgsl):
1006
1007                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
1008                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1009                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1010                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1011                                 } ...
1012                 </doc>
1013                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
1014                 <!-- total ROQ size: -->
1015                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1016         </reg32>
1017         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1018         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1019         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
1020         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1021         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1022
1023         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1024                 <reg32 offset="0x0" name="REG" type="uint"/>
1025         </array>
1026         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1027                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1028         </array>
1029
1030         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1031         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1032         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1033         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1034         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1035         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1036         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1037         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1038         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1039         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1040         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1041         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1042         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1043         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1044         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1045         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1046         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1047         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1048         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1049         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1050         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1051         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1052         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1053         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1054         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1055         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1056         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1057         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1058         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1059         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1060         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1061         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1062         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1063         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1064         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1065         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1066         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1067         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1068         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1069         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1070         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1071         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1072         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1073         <!-- SDS == CP_SET_DRAW_STATE: -->
1074         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1075         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1076         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1077         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1078         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1079         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1080         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1081         <!--
1082         There are probably similar registers for RB and SDS, teasing out SDS will
1083         take a slightly better test case..
1084          -->
1085         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1086                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1087                 <bitfield name="REM" low="16" high="31"/>
1088         </reg32>
1089         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1090                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1091                 <bitfield name="REM" low="16" high="31"/>
1092         </reg32>
1093         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1094         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1095         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1096         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1097         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1098         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1099         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1100         <reg32 offset="0x0210" name="RBBM_STATUS">
1101                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1102                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1103                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1104                 <bitfield high="20" low="20" name="VSC_BUSY" />
1105                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1106                 <bitfield high="18" low="18" name="SP_BUSY" />
1107                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1108                 <bitfield high="16" low="16" name="VPC_BUSY" />
1109                 <bitfield high="15" low="15" name="VFD_BUSY" />
1110                 <bitfield high="14" low="14" name="TESS_BUSY" />
1111                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1112                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1113                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1114                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1115                 <bitfield high="9" low="9" name="A2D_BUSY" />
1116                 <bitfield high="8" low="8" name="CCU_BUSY" />
1117                 <bitfield high="7" low="7" name="RB_BUSY" />
1118                 <bitfield high="6" low="6" name="RAS_BUSY" />
1119                 <bitfield high="5" low="5" name="TSE_BUSY" />
1120                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1121                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1122                 <bitfield high="2" low="2" name="CP_BUSY" />
1123                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1124                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1125         </reg32>
1126         <reg32 offset="0x0213" name="RBBM_STATUS3">
1127                 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1128         </reg32>
1129         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1130         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1131         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1132         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1133         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1134         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1135         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1136         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1137         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1138         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1139         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1140         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1141         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1142         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1143         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1144         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1145         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1146         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1147         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1148         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1149         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1150         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1151         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1152         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1153         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1154         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1155         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1156         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1157         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1158         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1159         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1160         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1161         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1162         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1163         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1164         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1165         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1166         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1167         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1168         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1169         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1170         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1171         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1172         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1173         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1174         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1175         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1176         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1177         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1178         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1179         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1180         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1181         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1182         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1183         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1184         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1185         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1186         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1187         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1188         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1189         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1190         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1191         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1192         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1193         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1194         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1195         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1196         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1197         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1198         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1199         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1200         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1201         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1202         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1203         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1204         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1205         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1206         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1207         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1208         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1209         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1210         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1211         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1212         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1213         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1214         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1215         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1216         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1217         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1218         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1219         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1220         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1221         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1222         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1223         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1224         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1225         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1226         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1227         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1228         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1229         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1230         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1231         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1232         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1233         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1234         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1235         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1236         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1237         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1238         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1239         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1240         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1241         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1242         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1243         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1244         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1245         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1246         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1247         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1248         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1249         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1250         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1251         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1252         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1253         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1254         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1255         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1256         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1257         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1258         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1259         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1260         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1261         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1262         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1263         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1264         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1265         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1266         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1267         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1268         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1269         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1270         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1271         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1272         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1273         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1274         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1275         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1276         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1277         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1278         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1279         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1280         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1281         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1282         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1283         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1284         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1285         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1286         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1287         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1288         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1289         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1290         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1291         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1292         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1293         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1294         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1295         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1296         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1297         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1298         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1299         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1300         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1301         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1302         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1303         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1304         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1305         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1306         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1307         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1308         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1309         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1310         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1311         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1312         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1313         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1314         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1315         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1316         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1317         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1318         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1319         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1320         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1321         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1322         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1323         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1324         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1325         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1326         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1327         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1328         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1329         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1330         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1331         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1332         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1333         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1334         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1335         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1336         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1337         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1338         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1339         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1340         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1341         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1342         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1343         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1344         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1345         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1346         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1347         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1348         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1349         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1350         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1351         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1352         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1353         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1354         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1355         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1356         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1357         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1358         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1359         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1360         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1361         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1362         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1363         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1364         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1365         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1366         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1367         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1368         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1369         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1370         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1371         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1372         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1373         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1374         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1375         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1376         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1377         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1378         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1379         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1380         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1381         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1382         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1383         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1384         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1385         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1386         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1387         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1388         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1389         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1390         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1391         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1392         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1393
1394         <!---
1395             This block of registers aren't tied to perf counters. They
1396             count various geometry stats, for example number of
1397             vertices in, number of primnitives assembled etc.
1398         -->
1399
1400         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1401         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1402         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1403         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1404         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1405         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1406         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1407         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1408         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1409         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1410         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1411         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1412         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1413         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1414         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1415         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1416         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1417         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1418         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1419         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1420         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1421         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1422
1423         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1424         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1425         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1426         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1427         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1428         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1429         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1430         <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1431         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1432         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1433         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1434         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1435         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1436         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1437         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1438         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1439         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1440         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1441         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1442         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1443         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1444         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1445         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1446         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1447         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1448         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1449         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1450         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1451         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1452         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1453         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1454         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1455         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1456         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1457         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1458         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1459         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1460         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1461         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1462         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1463         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1464         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1465         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1466         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1467         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1468         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1469         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1470         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1471         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1472         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1473         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1474         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1475         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1476         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1477         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1478         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1479         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1480         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1481         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1482         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1483         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1484         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1485         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1486         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1487         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1488         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1489         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1490         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1491         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1492         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1493         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1494         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1495         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1496         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1497         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1498         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1499         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1500         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1501         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1502         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1503         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1504         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1505         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1506         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1507         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1508         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1509         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1510         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1511         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1512         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1513         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1514         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1515         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1516         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1517         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1518         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1519         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1520         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1521         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1522         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1523         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1524         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1525         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1526         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1527         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1528         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1529         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1530         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1531         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1532         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1533         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1534         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1535         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1536         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1537         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1538         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1539         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1540         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1541         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1542         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1543         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1544         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1545         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1546         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1547         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1548         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1549                 <bitfield high="7" low="0" name="PING_INDEX"/>
1550                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1551         </reg32>
1552         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1553                 <bitfield high="5" low="0" name="TRACEEN"/>
1554                 <bitfield high="14" low="12" name="GRANU"/>
1555                 <bitfield high="31" low="28" name="SEGT"/>
1556         </reg32>
1557         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1558                 <bitfield high="27" low="24" name="ENABLE"/>
1559         </reg32>
1560         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1561         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1562         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1563         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1564         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1565         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1566         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1567         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1568         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1569                 <bitfield high="3" low="0" name="BYTEL0"/>
1570                 <bitfield high="7" low="4" name="BYTEL1"/>
1571                 <bitfield high="11" low="8" name="BYTEL2"/>
1572                 <bitfield high="15" low="12" name="BYTEL3"/>
1573                 <bitfield high="19" low="16" name="BYTEL4"/>
1574                 <bitfield high="23" low="20" name="BYTEL5"/>
1575                 <bitfield high="27" low="24" name="BYTEL6"/>
1576                 <bitfield high="31" low="28" name="BYTEL7"/>
1577         </reg32>
1578         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1579                 <bitfield high="3" low="0" name="BYTEL8"/>
1580                 <bitfield high="7" low="4" name="BYTEL9"/>
1581                 <bitfield high="11" low="8" name="BYTEL10"/>
1582                 <bitfield high="15" low="12" name="BYTEL11"/>
1583                 <bitfield high="19" low="16" name="BYTEL12"/>
1584                 <bitfield high="23" low="20" name="BYTEL13"/>
1585                 <bitfield high="27" low="24" name="BYTEL14"/>
1586                 <bitfield high="31" low="28" name="BYTEL15"/>
1587         </reg32>
1588         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1589         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1590         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1591         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1592         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1593         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1594         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1595         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1596         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1597         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1598         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1599         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1600         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1601         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1602         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1603         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1604         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1605         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1606         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1607         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1608         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1609         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1610         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1611         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1612         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1613         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1614         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1615         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1616         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1617         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1618         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1619         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1620         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1621         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1622         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1623         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1624         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1625         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1626         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1627         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1628         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1629         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1630         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1631         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1632         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1633         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1634         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1635         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1636         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1637         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1638         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1639         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1640         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1641         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1642         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1643         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1644         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1645         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1646         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1647         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1648         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1649         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1650         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1651         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1652         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1653         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1654         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1655         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1656         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1657         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1658         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1659         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1660         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1661         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1662         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1663         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1664         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1665         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1666         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1667         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1668         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1669         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1670         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1671         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1672         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1673         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1674         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1675         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1676                 <bitfield high="7" low="0" name="PERFSEL"/>
1677         </reg32>
1678         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1679         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1680         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1681         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1682         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1683         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1684         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1685         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1686         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1687         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1688         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1689         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1690         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1691         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1692         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1693         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1694         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1695         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1696         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1697         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1698         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1699         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1700         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1701         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1702         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1703         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1704         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1705         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1706         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1707         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1708         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1709         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1710         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1711         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1712         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1713         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1714         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1715         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1716         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1717         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1718         <reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
1719         <reg32 offset="0xB609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1"/>
1720         <reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
1721         <reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
1722         <reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
1723         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1724         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1725         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1726         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1727         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1728         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1729         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1730         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1731         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1732         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1733         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1734         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1735         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1736         <reg32 offset="0x3001" name="VBIF_CLKON">
1737                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1738         </reg32>
1739         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1740         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1741         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1742         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1743         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1744         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1745                 <bitfield low="0" high="3" name="DATA_SEL"/>
1746         </reg32>
1747         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1748         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1749                 <bitfield low="0" high="8" name="DATA_SEL"/>
1750         </reg32>
1751         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1752         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1753         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1754         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1755         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1756         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1757         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1758         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1759         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1760         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1761         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1762         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1763         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1764         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1765         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1766         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1767         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1768         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1769         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1770         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1771         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1772         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1773
1774         <!-- move/rename these.. -->
1775
1776         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1777         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1778         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1779
1780         <!-- same as RB_BIN_CONTROL -->
1781         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1782                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1783                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1784                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1785                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1786         </reg32>
1787
1788         <!--
1789                 from offset it seems it should be RB, but weird to duplicate
1790                 other regs from same block??
1791          -->
1792         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1793                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1794                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1795         </reg32>
1796
1797         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1798                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1799                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1800         </reg32>
1801         <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1802         <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1803         <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1804         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1805                 <bitfield name="NX" low="1" high="10" type="uint"/>
1806                 <bitfield name="NY" low="11" high="20" type="uint"/>
1807         </reg32>
1808         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1809                 <reg32 offset="0x0" name="REG">
1810                         <doc>
1811                                 Configures the mapping between VSC_PIPE buffer and
1812                                 bin, X/Y specify the bin index in the horiz/vert
1813                                 direction (0,0 is upper left, 0,1 is leftmost bin
1814                                 on second row, and so on).  W/H specify the number
1815                                 of bins assigned to this VSC_PIPE in the horiz/vert
1816                                 dimension.
1817                         </doc>
1818                         <bitfield name="X" low="0" high="9" type="uint"/>
1819                         <bitfield name="Y" low="10" high="19" type="uint"/>
1820                         <bitfield name="W" low="20" high="25" type="uint"/>
1821                         <bitfield name="H" low="26" high="31" type="uint"/>
1822                 </reg32>
1823         </array>
1824         <!--
1825         HW binning primitive & draw streams, which enable draws and primitives
1826         within a draw to be skipped in the main tile pass.  See:
1827         https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1828
1829         Compared to a5xx and earlier, we just program the address of the first
1830         stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1831
1832         LIMIT is set to PITCH - 64, to make room for a bit of overflow
1833          -->
1834         <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1835         <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1836         <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1837         <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1838         <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1839         <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1840         <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1841         <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1842         <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1843         <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1844
1845         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1846                 <doc>
1847                         Seems to be a bitmap of which tiles mapped to the VSC
1848                         pipe contain geometry.
1849
1850                         I suppose we can connect a maximum of 32 tiles to a
1851                         single VSC pipe.
1852                 </doc>
1853                 <reg32 offset="0x0" name="REG"/>
1854         </array>
1855
1856         <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1857                 <doc>
1858                         Has the size of data written to corresponding VSC_PRIM_STRM
1859                         buffer.
1860                 </doc>
1861                 <reg32 offset="0x0" name="REG"/>
1862         </array>
1863
1864         <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1865                 <doc>
1866                         Has the size of data written to corresponding VSC pipe, ie.
1867                         same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1868                 </doc>
1869                 <reg32 offset="0x0" name="REG"/>
1870         </array>
1871
1872         <!-- always 0x03200000 ? -->
1873         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1874
1875         <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1876                 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1877                 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1878                 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1879                 <!-- set with depthClampEnable, not clear what it does -->
1880                 <bitfield name="UNK5" pos="5" type="boolean"/>
1881                 <!-- controls near z clip behavior (set for vulkan) -->
1882                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1883                 <!-- guess based on a3xx and meaning of bits 8 and 9
1884                      if the guess is right then this is related to point sprite clipping -->
1885                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1886                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1887                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1888         </reg32>
1889         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1890         <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
1891         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1892
1893         <enum name="a6xx_layer_type">
1894           <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
1895           <value value="0x1" name="LAYER_3D"/>
1896           <value value="0x2" name="LAYER_CUBEMAP"/>
1897           <value value="0x3" name="LAYER_2D_ARRAY"/>
1898         </enum>
1899
1900         <!-- index of highest layer that can be written to via gl_Layer -->
1901         <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
1902
1903         <reg32 offset="0x8005" name="GRAS_CNTL">
1904                 <!-- see also RB_RENDER_CONTROL0 -->
1905                 <bitfield name="VARYING" pos="0" type="boolean"/>
1906                 <!-- b1 set for interpolateAtCentroid() -->
1907                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1908                 <!-- b2 set instead of b0 when running in per-sample mode -->
1909                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1910                 <!--
1911                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1912                 mode, and frag_face
1913                  -->
1914                 <bitfield name="SIZE" pos="3" type="boolean"/>
1915                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1916                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1917                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1918         </reg32>
1919         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1920                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1921                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1922         </reg32>
1923         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1924         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1925         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1926         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1927         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1928         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1929
1930         <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
1931         <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
1932         <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
1933
1934         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1935                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1936                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1937                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1938                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1939                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1940                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1941                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1942         </reg32>
1943         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1944                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1945                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1946         </reg32>
1947         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1948
1949         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1950                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1951         </reg32>
1952         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1953         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1954         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1955         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1956         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1957                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1958         </reg32>
1959
1960         <!-- always 0x0 -->
1961         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1962
1963         <!-- always 0x0 ? -->
1964         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1965
1966         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1967                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1968         </reg32>
1969
1970         <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
1971
1972         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1973
1974         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1975                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1976         </reg32>
1977         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1978                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1979                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1980         </reg32>
1981
1982         <bitset name="a6xx_sample_config" inline="yes">
1983                 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1984         </bitset>
1985
1986         <bitset name="a6xx_sample_locations" inline="yes">
1987                 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1988                 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1989                 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1990                 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1991                 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1992                 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1993                 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1994                 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1995         </bitset>
1996
1997         <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1998         <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1999         <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2000
2001         <!-- always 0x0 -->
2002         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
2003
2004         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
2005         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
2006         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
2007         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
2008         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
2009         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
2010
2011         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
2012                 <!--
2013                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
2014                 look when we get around to enabling lrz
2015                  -->
2016                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2017                 <doc>LRZ write also disabled for blend/etc.</doc>
2018                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
2019                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2020                 <bitfield name="GREATER" pos="2" type="boolean"/>
2021                 <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
2022                 <!-- set when depth-test + depth-write enabled -->
2023                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
2024         </reg32>
2025         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
2026         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
2027                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2028         </reg32>
2029         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
2030         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
2031         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
2032         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
2033                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
2034                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
2035         </reg32>
2036
2037         <!--
2038         The LRZ "fast clear" buffer is initialized to zero's by blob, and
2039         read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears
2040         to store 1b/block.  It appears that '0' means block has original
2041         depth clear value, and '1' means that the corresponding block in
2042         LRZ has been modified.  Ignoring alignment/padding, the size is
2043         given by the formula:
2044
2045                 // calculate LRZ size from depth size:
2046                 if (nr_samples == 4) {
2047                         width *= 2;
2048                         height *= 2;
2049                 } else if (nr_samples == 2) {
2050                         height *= 2;
2051                 }
2052
2053                 lrz_width = div_round_up(width, 8);
2054                 lrz_heigh = div_round_up(height, 8);
2055
2056                 // calculate # of blocks:
2057                 nblocksx = div_round_up(lrz_width, 16);
2058                 nblocksy = div_round_up(lrz_height, 4);
2059
2060                 // fast-clear buffer is 1bit/block:
2061                 fc_sz = div_round_up(nblocksx * nblocksy, 8);
2062
2063         In practice the blob seems to switch off FC_ENABLE once the size
2064         increases beyond 1 page.  Not sure if that is an actual limit or
2065         not.
2066          -->
2067         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
2068         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
2069         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
2070
2071         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
2072                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2073         </reg32>
2074
2075         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
2076
2077         <enum name="a6xx_rotation">
2078           <value value="0x0" name="ROTATE_0"/>
2079           <value value="0x1" name="ROTATE_90"/>
2080           <value value="0x2" name="ROTATE_180"/>
2081           <value value="0x3" name="ROTATE_270"/>
2082           <value value="0x4" name="ROTATE_HFLIP"/>
2083           <value value="0x5" name="ROTATE_VFLIP"/>
2084         </enum>
2085
2086         <bitset name="a6xx_2d_blit_cntl" inline="yes">
2087                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2088                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2089                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2090                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2091
2092                 <bitfield name="UNK" low="17" high="18" type="uint"/>
2093
2094                 <!-- required when blitting D24S8/D24X8 -->
2095                 <bitfield name="D24S8" pos="19" type="boolean"/>
2096                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2097                 <bitfield name="MASK" low="20" high="23"/>
2098                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2099         </bitset>
2100
2101         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2102
2103         <!-- could be the src coords are fixed point? -->
2104         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2105                 <bitfield name="X" low="8" high="31" type="int"/>
2106         </reg32>
2107         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2108                 <bitfield name="X" low="8" high="31" type="int"/>
2109         </reg32>
2110         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2111                 <bitfield name="Y" low="8" high="31" type="int"/>
2112         </reg32>
2113         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2114                 <bitfield name="Y" low="8" high="31" type="int"/>
2115         </reg32>
2116
2117         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2118         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2119
2120         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2121         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2122
2123         <!-- always 0x880 ? -->
2124         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2125
2126         <!-- same as GRAS_BIN_CONTROL: -->
2127         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2128                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2129                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2130                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2131                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2132         </reg32>
2133         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2134                 <!-- always set: ?? -->
2135                 <bitfield name="UNK4" pos="4" type="boolean"/>
2136                 <!-- set during binning pass: -->
2137                 <bitfield name="BINNING" pos="7" type="boolean"/>
2138                 <!-- bit seems to be set whenever depth buffer enabled: -->
2139                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2140                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2141                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2142         </reg32>
2143         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2144                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2145         </reg32>
2146         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2147                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2148                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2149         </reg32>
2150
2151         <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2152         <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2153         <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2154
2155         <!--
2156         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2157         name comes from kernel and is probably right)
2158          -->
2159         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2160                 <!-- see also GRAS_CNTL -->
2161                 <bitfield name="VARYING" pos="0" type="boolean"/>
2162                 <!-- b1 set for interpolateAtCentroid() -->
2163                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2164                 <!-- b2 set instead of b0 when running in per-sample mode -->
2165                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2166                 <!--
2167                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2168                 mode, and frag_face
2169                  -->
2170                 <bitfield name="SIZE" pos="3" type="boolean"/>
2171                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2172                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2173                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2174                 <bitfield name="UNK10" pos="10" type="boolean"/>
2175         </reg32>
2176         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2177                 <!-- enable bits for various FS sysvalue regs: -->
2178                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2179                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2180                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2181                 <!-- b4 and b5 set in per-sample mode: -->
2182                 <bitfield name="UNK4" pos="4" type="boolean"/>
2183                 <bitfield name="UNK5" pos="5" type="boolean"/>
2184                 <bitfield name="SIZE" pos="6" type="boolean"/>
2185         </reg32>
2186
2187         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2188                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2189                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2190                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2191         </reg32>
2192         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2193                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2194         </reg32>
2195         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2196                 <bitfield name="RT0" low="0" high="3"/>
2197                 <bitfield name="RT1" low="4" high="7"/>
2198                 <bitfield name="RT2" low="8" high="11"/>
2199                 <bitfield name="RT3" low="12" high="15"/>
2200                 <bitfield name="RT4" low="16" high="19"/>
2201                 <bitfield name="RT5" low="20" high="23"/>
2202                 <bitfield name="RT6" low="24" high="27"/>
2203                 <bitfield name="RT7" low="28" high="31"/>
2204         </reg32>
2205         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2206                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2207                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2208                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2209                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2210                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2211                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2212                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2213                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2214         </reg32>
2215         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2216                 <!-- Same as SP_SRGB_CNTL -->
2217                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2218                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2219                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2220                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2221                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2222                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2223                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2224                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2225         </reg32>
2226
2227         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2228                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2229         </reg32>
2230         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2231
2232         <!-- always 0x0 ? -->
2233         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2234         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2235         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2236         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2237         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2238         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2239         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2240
2241         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2242                 <reg32 offset="0x0" name="CONTROL">
2243                         <bitfield name="BLEND" pos="0" type="boolean"/>
2244                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2245                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2246                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2247                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2248                 </reg32>
2249                 <reg32 offset="0x1" name="BLEND_CONTROL">
2250                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2251                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2252                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2253                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2254                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2255                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2256                 </reg32>
2257                 <reg32 offset="0x2" name="BUF_INFO">
2258                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2259                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2260                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2261                 </reg32>
2262                 <!--
2263                 at least in gmem, things seem to be aligned to pitch of 64..
2264                 maybe an artifact of tiled format used in gmem?
2265                  -->
2266                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2267                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2268                 <!--
2269                 Compared to a5xx and before, we configure both a GMEM base and
2270                 external base.  Not sure if this is to facilitate GMEM save/
2271                 restore for context switch, or just to simplify state setup to
2272                 not have to care about GMEM vs BYPASS mode.
2273                  -->
2274                 <reg32 offset="0x5" name="BASE_LO"/>
2275                 <reg32 offset="0x6" name="BASE_HI"/>
2276
2277                 <reg64 offset="0x5" name="BASE" type="waddress"/>
2278
2279                 <reg32 offset="0x7" name="BASE_GMEM"/>
2280         </array>
2281
2282         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2283         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2284         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2285         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2286         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2287                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2288                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2289                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2290         </reg32>
2291         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2292                 <!-- per-mrt enable bit -->
2293                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2294                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2295                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2296                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2297                 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2298                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2299         </reg32>
2300         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2301                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2302         </reg32>
2303
2304         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2305                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2306                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2307                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2308                 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2309                 <doc>
2310                 Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2311                 also set when Z_BOUNDS_ENABLE is set
2312                 </doc>
2313                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2314                 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2315         </reg32>
2316         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2317         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2318                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2319         </reg32>
2320 <!-- probably: -->
2321         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2322                 <doc>stride of depth/stencil buffer</doc>
2323         </reg32>
2324         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2325                 <doc>size of layer</doc>
2326         </reg32>
2327         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2328         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2329         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
2330         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2331
2332         <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2333         <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2334
2335         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2336                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2337                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2338                 <!--
2339                         set for stencil operations that require read from stencil
2340                         buffer, but not for example for stencil clear (which does
2341                         not require read).. so guessing this is analogous to
2342                         READ_DEST_ENABLE for color buffer..
2343                  -->
2344                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2345                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2346                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2347                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2348                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2349                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2350                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2351                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2352                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2353         </reg32>
2354         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2355                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2356         </reg32>
2357         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2358                 <doc>stride of stencil buffer</doc>
2359         </reg32>
2360         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2361                 <doc>size of layer</doc>
2362         </reg32>
2363         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2364         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2365         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
2366         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2367         <reg32 offset="0x8887" name="RB_STENCILREF">
2368                 <bitfield name="REF" low="0" high="7"/>
2369                 <bitfield name="BFREF" low="8" high="15"/>
2370         </reg32>
2371         <reg32 offset="0x8888" name="RB_STENCILMASK">
2372                 <bitfield name="MASK" low="0" high="7"/>
2373                 <bitfield name="BFMASK" low="8" high="15"/>
2374         </reg32>
2375         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2376                 <bitfield name="WRMASK" low="0" high="7"/>
2377                 <bitfield name="BFWRMASK" low="8" high="15"/>
2378         </reg32>
2379         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2380         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2381                 <bitfield name="COPY" pos="1" type="boolean"/>
2382         </reg32>
2383
2384         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2385                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2386         </reg32>
2387
2388         <!-- clamps depth value for depth test/write -->
2389         <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2390         <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2391
2392         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2393         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2394         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2395
2396         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2397                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2398         </reg32>
2399         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2400         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2401         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2402                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2403                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2404                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2405                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2406                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2407         </reg32>
2408         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
2409         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2410         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2411         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2412         <!-- array-pitch is size of layer -->
2413         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2414         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
2415         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2416         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2417         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2418                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2419                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2420         </reg32>
2421
2422         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2423         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2424         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2425         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2426
2427         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2428         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2429                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2430                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2431                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2432                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2433                 <doc>
2434                         For clearing depth/stencil
2435                                 1 - depth
2436                                 2 - stencil
2437                                 3 - depth+stencil
2438                         For clearing color buffer:
2439                                 then probably a component mask, I always see 0xf
2440                 </doc>
2441                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2442         </reg32>
2443
2444         <!-- always 0x0 ? -->
2445         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2446
2447         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2448         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2449         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
2450         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2451                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2452                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2453         </reg32>
2454         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2455                 <reg32 offset="0" name="ADDR_LO"/>
2456                 <reg32 offset="1" name="ADDR_HI"/>
2457                 <reg64 offset="0" name="ADDR" type="waddress"/>
2458                 <reg32 offset="2" name="PITCH">
2459                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2460                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2461                 </reg32>
2462         </array>
2463         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2464         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2465
2466         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2467         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2468
2469         <bitset name="a6xx_2d_surf_info" inline="yes">
2470                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2471                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2472                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2473                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2474                 <bitfield name="SRGB" pos="13" type="boolean"/>
2475                 <!-- the rest is only for src -->
2476                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2477                 <bitfield name="FILTER" pos="16" type="boolean"/>
2478                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2479                 <bitfield name="UNK20" pos="20" type="boolean"/>
2480                 <bitfield name="UNK22" pos="22" type="boolean"/>
2481         </bitset>
2482
2483         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2484         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2485         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2486         <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
2487         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2488                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2489         </reg32>
2490
2491         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2492         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2493         <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
2494         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2495                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2496                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2497         </reg32>
2498
2499         <!-- unlike a5xx, these are per channel values rather than packed -->
2500         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2501         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2502         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2503         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2504
2505         <!-- always 0x1 ? -->
2506         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2507
2508         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2509
2510         <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2511                 <!-- offset into GMEM for something.
2512                         important for sysmem path
2513                         BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2514                         blob values for GMEM path (note: close to GMEM size):
2515                         a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
2516                         SYSMEM path values:
2517                         a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
2518                 -->
2519                 <bitfield name="OFFSET" low="23" high="31" shr="12" type="hex"/>
2520                 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2521                 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2522         </reg32>
2523
2524         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2525
2526         <!-- always 0x00ffff00 ? */ -->
2527         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2528         <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
2529         <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
2530
2531         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2532
2533         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2534                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2535         </reg32>
2536
2537         <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
2538         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2539         <reg32 offset="0x9108" name="VPC_POLYGON_MODE">
2540                 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2541         </reg32>
2542
2543         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2544                 <reg32 offset="0x0" name="MODE"/>
2545         </array>
2546         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2547                 <reg32 offset="0x0" name="MODE"/>
2548         </array>
2549
2550         <!-- always 0x0 -->
2551         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2552         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2553
2554         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2555                 <!-- one bit per varying component: -->
2556                 <reg32 offset="0" name="DISABLE"/>
2557         </array>
2558
2559         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2560                 <!-- always 0x10000 when SO enabled.. -->
2561                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2562         </reg32>
2563         <reg32 offset="0x9217" name="VPC_SO_PROG">
2564                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2565                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2566                 <bitfield name="A_EN" pos="11" type="boolean"/>
2567                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2568                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2569                 <bitfield name="B_EN" pos="23" type="boolean"/>
2570         </reg32>
2571
2572         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2573         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2574
2575         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2576                 <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
2577                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2578                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2579                 <reg32 offset="2" name="BUFFER_SIZE"/>
2580                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2581                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2582                 <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
2583                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2584                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2585         </array>
2586
2587         <!-- always 0x0 ? -->
2588         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2589                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2590         </reg32>
2591
2592         <!-- always 0x0 ? -->
2593         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2594
2595         <reg32 offset="0x9301" name="VPC_PACK">
2596                 <doc>
2597                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2598                         plus # of transform-feedback (streamout) varyings if using the
2599                         hw streamout (rather than stg instructions in shader)
2600                 </doc>
2601                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2602                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2603                 <!--
2604                 This seems to be the OUTLOC for the psize output.  It could possibly
2605                 be the max-OUTLOC position, but it is only set when VS writes psize
2606                 (and blob always puts psize at highest OUTLOC)
2607                  -->
2608                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2609         </reg32>
2610
2611         <reg32 offset="0x9302" name="VPC_PACK_GS">
2612                 <doc>
2613                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2614                         plus # of transform-feedback (streamout) varyings if using the
2615                         hw streamout (rather than stg instructions in shader)
2616                 </doc>
2617                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2618                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2619                 <!--
2620                 This seems to be the OUTLOC for the psize output.  It could possibly
2621                 be the max-OUTLOC position, but it is only set when VS writes psize
2622                 (and blob always puts psize at highest OUTLOC)
2623                  -->
2624                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2625         </reg32>
2626
2627         <reg32 offset="0x9303" name="VPC_PACK_3">
2628                 <doc>
2629                         domain shader version of VPC_PACK
2630                 </doc>
2631                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2632                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2633                 <!--
2634                 This seems to be the OUTLOC for the psize output.  It could possibly
2635                 be the max-OUTLOC position, but it is only set when VS writes psize
2636                 (and blob always puts psize at highest OUTLOC)
2637                  -->
2638                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2639         </reg32>
2640
2641         <reg32 offset="0x9304" name="VPC_CNTL_0">
2642                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2643                 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2644                 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2645                 <bitfield name="VARYING" pos="16" type="boolean"/>
2646                 <bitfield name="UNKLOC" low="24" high="31" type="uint"/>
2647         </reg32>
2648
2649         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2650                 <bitfield name="BUF0" pos="0" type="boolean"/>
2651                 <bitfield name="BUF1" pos="3" type="boolean"/>
2652                 <bitfield name="BUF2" pos="6" type="boolean"/>
2653                 <bitfield name="BUF3" pos="9" type="boolean"/>
2654                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2655         </reg32>
2656         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2657                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2658         </reg32>
2659
2660         <!-- always 0x0 ? -->
2661         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2662         <!-- always 0x0 ? -->
2663         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2664
2665         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2666
2667         <!-- always 0x0 ? -->
2668         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2669
2670         <enum name="a6xx_tess_spacing">
2671           <value value="0x0" name="TESS_EQUAL"/>
2672           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2673           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2674         </enum>
2675
2676         <enum name="a6xx_tess_output">
2677           <value value="0x0" name="TESS_POINTS"/>
2678           <value value="0x1" name="TESS_LINES"/>
2679           <value value="0x2" name="TESS_CW_TRIS"/>
2680           <value value="0x3" name="TESS_CCW_TRIS"/>
2681         </enum>
2682
2683         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2684           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2685           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2686         </reg32>
2687
2688         <!-- probably: -->
2689         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2690         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2691
2692         <!-- always 0x1 ? -->
2693         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2694
2695         <!-- probably a mirror of VFD_CONTROL_6 -->
2696         <reg32 offset="0x9806" name="PC_PRIMID_CNTL">
2697                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2698         </reg32>
2699
2700         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2701
2702         <reg32 offset="0x9981" name="PC_POLYGON_MODE">
2703                 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2704         </reg32>
2705
2706         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2707
2708         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2709                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2710                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2711                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2712                 <bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
2713         </reg32>
2714         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2715                 <doc>
2716                         vertex shader
2717
2718                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2719                         plus # of transform-feedback (streamout) varyings if using the
2720                         hw streamout (rather than stg instructions in shader)
2721                 </doc>
2722                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2723                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2724         </reg32>
2725
2726         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2727                 <doc>
2728                   geometry shader
2729                 </doc>
2730                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2731                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2732                 <bitfield name="LAYER" pos="9" type="boolean"/>
2733                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2734         </reg32>
2735
2736         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2737                 <doc>
2738                         hull shader?
2739
2740                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2741                         plus # of transform-feedback (streamout) varyings if using the
2742                         hw streamout (rather than stg instructions in shader)
2743                 </doc>
2744                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2745                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2746         </reg32>
2747         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2748                 <doc>
2749                         domain shader
2750                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2751                         plus # of transform-feedback (streamout) varyings if using the
2752                         hw streamout (rather than stg instructions in shader)
2753                 </doc>
2754                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2755                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2756         </reg32>
2757
2758         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2759                 <doc>
2760                   geometry shader
2761                 </doc>
2762                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2763                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2764                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2765         </reg32>
2766
2767         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2768                 <doc>
2769                   size in vec4s of per-primitive storage for gs
2770                 </doc>
2771                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2772         </reg32>
2773
2774         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2775
2776         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2777         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2778
2779         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2780         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2781                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2782                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2783         </reg32>
2784         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
2785         <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
2786         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
2787         <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
2788
2789         <!-- always 0x0 -->
2790         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2791
2792         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2793                 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2794                 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2795         </reg32>
2796         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2797                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2798                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2799                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2800         </reg32>
2801         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2802                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2803                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2804         </reg32>
2805         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2806                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2807                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2808                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2809         </reg32>
2810         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2811         </reg32>
2812         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2813                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2814         </reg32>
2815         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2816                 <!--
2817                         True if gl_PrimitiveID is read via the FS and there is
2818                         no matching write from the GS, and therefore it needs to
2819                         be passed through via fixed-function logic.
2820                 -->
2821                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2822         </reg32>
2823
2824         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2825                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2826         </reg32>
2827
2828         <!-- always 0x0 ? -->
2829         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2830         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2831                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2832                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2833                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2834                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2835         </reg32>
2836
2837         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2838         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2839         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2840                 <reg64 offset="0x0" name="BASE" type="address"/>
2841                 <reg32 offset="0x0" name="BASE_LO"/>
2842                 <reg32 offset="0x1" name="BASE_HI"/>
2843                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2844                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2845         </array>
2846         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2847                 <reg32 offset="0x0" name="INSTR">
2848                         <!-- IDX and byte OFFSET into VFD_FETCH -->
2849                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2850                         <bitfield name="OFFSET" low="5" high="16"/>
2851                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2852                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2853                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2854                         <bitfield name="UNK30" pos="30" type="boolean"/>
2855                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2856                 </reg32>
2857                 <reg32 offset="0x1" name="STEP_RATE"/>
2858         </array>
2859         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2860                 <reg32 offset="0x0" name="INSTR">
2861                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2862                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2863                 </reg32>
2864         </array>
2865
2866         <!-- always 0x1 ? -->
2867         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2868
2869         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2870                 <!--
2871                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2872                 used registers is a bit odd too:
2873                         - used (half): 0-15 68-179 (cnt=128, max=179)
2874                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2875                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2876                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2877                 then:
2878                         - used (merged): 0-191 (cnt=192, max=191)
2879                 So I think if b31 is set, then the half precision registers overlap
2880                 the full precision registers.  (Which seems like a pretty sensible
2881                 feature, actually I'm not sure when you *wouldn't* want to use that,
2882                 since it gives register allocation more flexibility)
2883                  -->
2884                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2885                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2886                 <!-- seems to be nesting level for flow control:.. -->
2887                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2888                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2889                 <bitfield name="VARYING" pos="22" type="boolean"/>
2890                 <!-- set when dFdxFine/dFdyFine is used -->
2891                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2892                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2893                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2894         </bitset>
2895
2896         <bitset name="a6xx_sp_xs_config" inline="yes">
2897                 <!--
2898                 Each of these are set if the given resource type is used
2899                 with the Vulkan/bindless binding model.
2900                 -->
2901                 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2902                 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2903                 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2904                 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2905
2906                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2907                 <!--
2908                 number of textures and samplers.. these might be swapped, with GL I
2909                 always see the same value for both.
2910                  -->
2911                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2912                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2913                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2914         </bitset>
2915
2916         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2917         <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex">
2918                 <!--
2919                 bitmask of true/false conditions for VS brac.N instructions,
2920                 bit N corresponds to brac.N
2921                  -->
2922         </reg32>
2923         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2924                 <!-- # of VS outputs including pos/psize -->
2925                 <bitfield name="VSOUT" low="0" high="5" type="uint"/>
2926         </reg32>
2927         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2928                 <reg32 offset="0x0" name="REG">
2929                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2930                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2931                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2932                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2933                 </reg32>
2934         </array>
2935         <!--
2936         Starting with a5xx, position/psize outputs from shader end up in the
2937         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2938         the last entries too, except when gl_PointCoord is used, blob inserts
2939         an extra varying after, but with a lower OUTLOC position.  If present,
2940         psize is last, preceded by position.
2941          -->
2942         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2943                 <reg32 offset="0x0" name="REG">
2944                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2945                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2946                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2947                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2948                 </reg32>
2949         </array>
2950
2951         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2952         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2953         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2954         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2955         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2956         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2957
2958         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2959         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2960         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2961         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2962         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2963         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2964         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2965         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2966
2967         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2968         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2969                 <!-- # of DS outputs including pos/psize -->
2970                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2971         </reg32>
2972         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2973                 <reg32 offset="0x0" name="REG">
2974                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2975                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2976                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2977                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2978                 </reg32>
2979         </array>
2980         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2981                 <reg32 offset="0x0" name="REG">
2982                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2983                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2984                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2985                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2986                 </reg32>
2987         </array>
2988
2989         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2990         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2991         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2992         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2993         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2994         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2995
2996         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2997         <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE">
2998                 <!-- size of output of previous stage -->
2999         </reg32>
3000         <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex">
3001                 <!--
3002                 bitmask of true/false conditions for FS brac.N instructions,
3003                 bit N corresponds to brac.N
3004                  -->
3005         </reg32>
3006
3007         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
3008                 <!-- # of VS outputs including pos/psize -->
3009                 <bitfield name="GSOUT" low="0" high="5" type="uint"/>
3010                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
3011         </reg32>
3012
3013         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
3014                 <reg32 offset="0x0" name="REG">
3015                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3016                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3017                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3018                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3019                 </reg32>
3020         </array>
3021
3022         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
3023                 <reg32 offset="0x0" name="REG">
3024                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3025                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3026                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3027                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3028                 </reg32>
3029         </array>
3030
3031         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
3032         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
3033         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
3034         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
3035         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
3036
3037         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
3038         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
3039         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
3040         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
3041         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
3042         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
3043         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
3044         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
3045         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
3046         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
3047         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
3048         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
3049         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
3050         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
3051         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
3052         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
3053
3054         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3055         <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
3056                 <!--
3057                 bitmask of true/false conditions for FS brac.N instructions,
3058                 bit N corresponds to brac.N
3059                  -->
3060         </reg32>
3061         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
3062         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
3063         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
3064
3065         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
3066                 <bitfield name="ENABLED" pos="0" type="boolean"/>
3067                 <bitfield name="UNK8" pos="8" type="boolean"/>
3068                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3069                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3070         </reg32>
3071         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3072                 <!-- Same as RB_SRGB_CNTL -->
3073                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3074                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3075                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3076                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3077                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3078                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3079                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3080                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3081         </reg32>
3082         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3083                 <bitfield name="RT0" low="0" high="3"/>
3084                 <bitfield name="RT1" low="4" high="7"/>
3085                 <bitfield name="RT2" low="8" high="11"/>
3086                 <bitfield name="RT3" low="12" high="15"/>
3087                 <bitfield name="RT4" low="16" high="19"/>
3088                 <bitfield name="RT5" low="20" high="23"/>
3089                 <bitfield name="RT6" low="24" high="27"/>
3090                 <bitfield name="RT7" low="28" high="31"/>
3091         </reg32>
3092         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3093                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3094                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3095                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3096         </reg32>
3097         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3098                 <bitfield name="MRT" low="0" high="3" type="uint"/>
3099         </reg32>
3100
3101         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3102                 <reg32 offset="0" name="REG">
3103                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3104                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3105                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3106                 </reg32>
3107         </array>
3108
3109         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3110                 <!-- unknown bits 0x7fc0 always set -->
3111                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
3112                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3113                 <bitfield name="UNK3" pos="3" type="boolean"/>
3114                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3115         </reg32>
3116         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3117                 <reg32 offset="0" name="CMD">
3118                         <bitfield name="SRC" low="0" high="6" type="uint"/>
3119                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3120                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3121                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3122                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
3123                         <bitfield name="HALF" pos="26" type="boolean"/>
3124                         <!--
3125                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
3126                         skip pre-fetch.. TODO test texelFetch
3127                         CMD is 0x6 when the Vulkan mode is enabled, and
3128                         TEX_ID/SAMP_ID refer to the descriptor sets while the
3129                         indices come from SP_FS_BINDLESS_PREFETCH[n]
3130                          -->
3131                         <bitfield name="CMD" low="27" high="31"/>
3132                 </reg32>
3133         </array>
3134
3135         <!-- TODO confirm that this is actually an array -->
3136         <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3137                 <reg32 offset="0" name="CMD">
3138                         <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
3139                         <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
3140                 </reg32>
3141         </array>
3142
3143         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3144
3145         <!-- always 0x0 ? -->
3146         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3147
3148         <!-- set for compute shaders, always 0x41 -->
3149         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
3150
3151         <!-- set for compute shaders, always 0x0 -->
3152         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3153
3154         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3155
3156         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3157         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3158         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3159         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3160         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3161         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3162         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3163         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3164
3165         <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3166                 <reg64 offset="0" name="ADDR" type="waddress"/>
3167         </array>
3168
3169         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3170                 <doc>per MRT</doc>
3171                 <reg32 offset="0x0" name="REG">
3172                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3173                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3174                 </reg32>
3175         </array>
3176
3177         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3178         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3179         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3180         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3181         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3182
3183         <!--
3184         IBO state for compute shader:
3185          -->
3186         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3187         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3188         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3189
3190         <!-- always 0x5 ? -->
3191         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3192
3193         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3194         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3195
3196         <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3197                 <reg64 offset="0" name="ADDR" type="waddress"/>
3198         </array>
3199
3200         <!--
3201         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3202         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3203          -->
3204         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3205         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3206         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3207
3208         <!--
3209         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
3210          -->
3211         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3212                 <bitfield name="NORM" pos="0" type="boolean"/>
3213                 <bitfield name="SINT" pos="1" type="boolean"/>
3214                 <bitfield name="UINT" pos="2" type="boolean"/>
3215                 <!-- looks like HW only cares about the base type of this format,
3216                      which matches the ifmt? -->
3217                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3218                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3219                 <bitfield name="SRGB" pos="11" type="boolean"/>
3220                 <!-- some sort of channel mask, not sure what it is for -->
3221                 <bitfield name="MASK" low="12" high="15"/>
3222         </reg32>
3223
3224         <!-- always 0x0 -->
3225         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3226
3227         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3228         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3229
3230         <!-- always 0x3f ? -->
3231         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3232
3233         <!--
3234         The downstream kernel calls the debug cluster of registers
3235         "a6xx_sp_ps_tp_cluster" but this actually specifies the border
3236         color base for compute shaders.
3237         -->
3238         <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3239         <!-- always 0x0 ? -->
3240         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3241         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3242
3243         <!-- could be all the stuff below here is actually TPL1?? -->
3244
3245         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3246                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3247         </reg32>
3248         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3249                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3250                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3251         </reg32>
3252
3253         <!-- looks to work in the same way as a5xx: -->
3254         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3255         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3256         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3257         <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3258         <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3259         <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3260
3261         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3262
3263         <!--
3264         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3265         badly named or the functionality moved in a6xx.  But downstream kernel
3266         calls this "a6xx_sp_ps_tp_2d_cluster"
3267          -->
3268         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3269         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3270                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3271                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3272         </reg32>
3273         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3274         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3275         <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3276         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3277            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3278         </reg32>
3279
3280         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3281         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3282         <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3283         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3284                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3285                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3286         </reg32>
3287
3288         <!-- always 0x00100000 ? -->
3289         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3290
3291         <!-- always 0x44 ? -->
3292         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3293
3294         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3295                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3296                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3297         </bitset>
3298
3299         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3300         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3301         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3302         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3303
3304         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3305
3306         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3307                 <!-- always 0x7 ? -->
3308         </reg32>
3309         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3310                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3311                 <!-- SAMPLEID is loaded into a half-precision register: -->
3312                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3313                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3314                 <!--
3315                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3316                 to be divided by to scale to a single fragment.  It is probably
3317                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3318                  -->
3319                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3320         </reg32>
3321         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3322                 <!-- register loaded with position (bary.f) -->
3323                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3324                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3325         </reg32>
3326         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3327                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3328                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3329                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3330         </reg32>
3331         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3332                 <!-- unknown regid in low 8b -->
3333         </reg32>
3334         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3335
3336         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3337                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3338                 <!-- localsize is value minus one: -->
3339                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3340                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3341                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3342         </reg32>
3343         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3344                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3345         </reg32>
3346         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3347                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3348         </reg32>
3349         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3350                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3351         </reg32>
3352         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3353                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3354         </reg32>
3355         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3356                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3357         </reg32>
3358         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3359                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3360         </reg32>
3361         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3362                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3363                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3364                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3365                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3366         </reg32>
3367         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3368         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3369         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3370         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3371
3372         <!-- mirror of SP_CS_BINDLESS_BASE -->
3373         <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3374                 <reg64 offset="0" name="ADDR" type="waddress"/>
3375         </array>
3376
3377         <!-- probably: -->
3378         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3379
3380         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3381
3382         <!-- always 0x0 ? -->
3383         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3384
3385         <!-- mirror of SP_BINDLESS_BASE -->
3386         <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3387                 <reg64 offset="0" name="ADDR" type="waddress"/>
3388         </array>
3389
3390         <!-- always 0x80 ? -->
3391         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3392         <!-- always 0x0 ? -->
3393         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3394         <!-- always 0x0 ? -->
3395         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3396
3397 </domain>
3398
3399 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3400 <domain name="A6XX_TEX_SAMP" width="32">
3401         <doc>Texture sampler dwords</doc>
3402         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3403                 <value name="A6XX_TEX_NEAREST" value="0"/>
3404                 <value name="A6XX_TEX_LINEAR" value="1"/>
3405                 <value name="A6XX_TEX_ANISO" value="2"/>
3406                 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3407         </enum>
3408         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3409                 <value name="A6XX_TEX_REPEAT" value="0"/>
3410                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3411                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3412                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3413                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3414         </enum>
3415         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3416                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3417                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3418                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3419                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3420                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3421         </enum>
3422         <enum name="a6xx_reduction_mode">
3423                 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3424                 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3425                 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3426         </enum>
3427
3428         <reg32 offset="0" name="0">
3429                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3430                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3431                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3432                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3433                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3434                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3435                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3436                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3437         </reg32>
3438         <reg32 offset="1" name="1">
3439                 <!-- bit 0 always set with vulkan? -->
3440                 <bitfield name="UNK0" pos="0" type="boolean"/>
3441                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3442                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3443                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3444                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3445                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3446                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3447         </reg32>
3448         <reg32 offset="2" name="2">
3449                 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3450                 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
3451                 <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
3452         </reg32>
3453         <reg32 offset="3" name="3"/>
3454 </domain>
3455
3456 <domain name="A6XX_TEX_CONST" width="32">
3457         <doc>Texture constant dwords</doc>
3458         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3459                 <value name="A6XX_TEX_X" value="0"/>
3460                 <value name="A6XX_TEX_Y" value="1"/>
3461                 <value name="A6XX_TEX_Z" value="2"/>
3462                 <value name="A6XX_TEX_W" value="3"/>
3463                 <value name="A6XX_TEX_ZERO" value="4"/>
3464                 <value name="A6XX_TEX_ONE" value="5"/>
3465         </enum>
3466         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3467                 <value name="A6XX_TEX_1D" value="0"/>
3468                 <value name="A6XX_TEX_2D" value="1"/>
3469                 <value name="A6XX_TEX_CUBE" value="2"/>
3470                 <value name="A6XX_TEX_3D" value="3"/>
3471         </enum>
3472         <reg32 offset="0" name="0">
3473                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3474                 <bitfield name="SRGB" pos="2" type="boolean"/>
3475                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3476                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3477                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3478                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3479                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3480                 <!-- overlaps with MIPLVLS -->
3481                 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
3482                 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
3483                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3484                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3485                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3486         </reg32>
3487         <reg32 offset="1" name="1">
3488                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3489                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3490         </reg32>
3491         <reg32 offset="2" name="2">
3492                 <!--
3493                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3494                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3495
3496                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3497                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3498                  -->
3499                 <bitfield name="UNK4" pos="4" type="boolean"/>
3500                 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3501                 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
3502                 <doc>Pitch in bytes (so actually stride)</doc>
3503                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3504                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3505                 <bitfield name="UNK31" pos="31" type="boolean"/>
3506         </reg32>
3507         <reg32 offset="3" name="3">
3508                 <!--
3509                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3510                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3511                 layer size at the point that it stops being reduced moving to
3512                 higher (smaller) mipmap levels
3513                  -->
3514                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3515                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3516                 <!--
3517                 by default levels with w < 16 are linear
3518                 TILE_ALL makes all levels have tiling
3519                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3520                  -->
3521                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3522                 <bitfield name="FLAG" pos="28" type="boolean"/>
3523         </reg32>
3524         <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3525              the address of the non-flag base buffer is determined automatically,
3526              and must follow the flag buffer
3527          -->
3528         <reg32 offset="4" name="4">
3529                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3530         </reg32>
3531         <reg32 offset="5" name="5">
3532                 <bitfield name="BASE_HI" low="0" high="16"/>
3533                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3534         </reg32>
3535         <reg32 offset="6" name="6">
3536                 <!-- pitch for plane 2 / plane 3 -->
3537                 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
3538         </reg32>
3539         <!-- 7/8 is plane 2 address for planar formats -->
3540         <reg32 offset="7" name="7">
3541                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3542         </reg32>
3543         <reg32 offset="8" name="8">
3544                 <bitfield name="FLAG_HI" low="0" high="16"/>
3545         </reg32>
3546         <!-- 9/10 is plane 3 address for planar formats -->
3547         <reg32 offset="9" name="9">
3548                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3549         </reg32>
3550         <reg32 offset="10" name="10">
3551                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3552                 <!-- log2 size of the first level, required for mipmapping -->
3553                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3554                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3555         </reg32>
3556         <reg32 offset="11" name="11"/>
3557         <reg32 offset="12" name="12"/>
3558         <reg32 offset="13" name="13"/>
3559         <reg32 offset="14" name="14"/>
3560         <reg32 offset="15" name="15"/>
3561 </domain>
3562
3563 <!--
3564 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3565 naming is just because I r/e'd SSBOs first.  I should probably come up
3566 with a better name.
3567 -->
3568 <domain name="A6XX_IBO" width="32">
3569         <reg32 offset="0" name="0">
3570                 <!--
3571                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3572                 used but if they are good chance position is same as TEX_CONST
3573                  -->
3574                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3575                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3576         </reg32>
3577         <reg32 offset="1" name="1">
3578                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3579                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3580         </reg32>
3581         <reg32 offset="2" name="2">
3582                 <!--
3583                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3584                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3585                  -->
3586                 <bitfield name="UNK4" pos="4" type="boolean"/>
3587                 <doc>Pitch in bytes (so actually stride)</doc>
3588                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3589                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3590                 <bitfield name="UNK31" pos="31" type="boolean"/>
3591         </reg32>
3592         <reg32 offset="3" name="3">
3593                 <!--
3594                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3595                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3596                 layer size at the point that it stops being reduced moving to
3597                 higher (smaller) mipmap levels
3598                  -->
3599                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3600                 <bitfield name="UNK27" pos="27" type="boolean"/>
3601                 <bitfield name="FLAG" pos="28" type="boolean"/>
3602         </reg32>
3603         <reg32 offset="4" name="4">
3604                 <bitfield name="BASE_LO" low="0" high="31"/>
3605         </reg32>
3606         <reg32 offset="5" name="5">
3607                 <bitfield name="BASE_HI" low="0" high="16"/>
3608                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3609         </reg32>
3610         <reg32 offset="6" name="6">
3611         </reg32>
3612         <reg32 offset="7" name="7">
3613         </reg32>
3614         <reg32 offset="8" name="8">
3615         </reg32>
3616         <reg32 offset="9" name="9">
3617                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3618         </reg32>
3619         <reg32 offset="10" name="10">
3620                 <!--
3621                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3622                 don't seem to be particularly sensible... or needed for UBWC to work
3623                  -->
3624                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3625         </reg32>
3626 </domain>
3627
3628 <domain name="A6XX_UBO" width="32">
3629         <reg32 offset="0" name="0">
3630                 <bitfield name="BASE_LO" low="0" high="31"/>
3631         </reg32>
3632         <reg32 offset="1" name="1">
3633                 <bitfield name="BASE_HI" low="0" high="16"/>
3634                 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3635         </reg32>
3636 </domain>
3637
3638 <domain name="A6XX_PDC" width="32">
3639         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3640         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3641         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3642         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3643         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3644         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3645         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3646         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3647         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3648         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3649         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3650         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3651         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3652         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3653         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3654         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3655         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3656         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3657         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3658         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3659         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3660         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3661         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3662         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3663         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3664         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3665 </domain>
3666
3667 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3668         <reg32 offset="0x0" name="MEM_0"/>
3669 </domain>
3670
3671 <domain name="A6XX_CX_DBGC" width="32">
3672         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3673                 <bitfield high="7" low="0" name="PING_INDEX"/>
3674                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3675         </reg32>
3676         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3677         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3678         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3679         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3680                 <bitfield high="5" low="0" name="TRACEEN"/>
3681                 <bitfield high="14" low="12" name="GRANU"/>
3682                 <bitfield high="31" low="28" name="SEGT"/>
3683         </reg32>
3684         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3685                 <bitfield high="27" low="24" name="ENABLE"/>
3686         </reg32>
3687         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3688         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3689         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3690         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3691         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3692         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3693         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3694         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3695         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3696                 <bitfield high="3" low="0" name="BYTEL0"/>
3697                 <bitfield high="7" low="4" name="BYTEL1"/>
3698                 <bitfield high="11" low="8" name="BYTEL2"/>
3699                 <bitfield high="15" low="12" name="BYTEL3"/>
3700                 <bitfield high="19" low="16" name="BYTEL4"/>
3701                 <bitfield high="23" low="20" name="BYTEL5"/>
3702                 <bitfield high="27" low="24" name="BYTEL6"/>
3703                 <bitfield high="31" low="28" name="BYTEL7"/>
3704         </reg32>
3705         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3706                 <bitfield high="3" low="0" name="BYTEL8"/>
3707                 <bitfield high="7" low="4" name="BYTEL9"/>
3708                 <bitfield high="11" low="8" name="BYTEL10"/>
3709                 <bitfield high="15" low="12" name="BYTEL11"/>
3710                 <bitfield high="19" low="16" name="BYTEL12"/>
3711                 <bitfield high="23" low="20" name="BYTEL13"/>
3712                 <bitfield high="27" low="24" name="BYTEL14"/>
3713                 <bitfield high="31" low="28" name="BYTEL15"/>
3714         </reg32>
3715
3716         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3717         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3718 </domain>
3719
3720 <domain name="A6XX_CX_MISC" width="32">
3721         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3722         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3723 </domain>
3724
3725 </database>