src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
  26         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  27
  28         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  29         <value value="0x10" name="FMT6_8_8_SNORM"/>
  30         <value value="0x11" name="FMT6_8_8_UINT"/>
  31         <value value="0x12" name="FMT6_8_8_SINT"/>
  32         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  33
  34         <value value="0x15" name="FMT6_16_UNORM"/>
  35         <value value="0x16" name="FMT6_16_SNORM"/>
  36         <value value="0x17" name="FMT6_16_FLOAT"/>
  37         <value value="0x18" name="FMT6_16_UINT"/>
  38         <value value="0x19" name="FMT6_16_SINT"/>
  39
  40         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  41         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  42         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  43         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  44
  45         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  46         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  47         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  48         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  49         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  50
  51         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  52
  53         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  54         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  55         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  56         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  57         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  58
  59         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  60
  61         <value value="0x43" name="FMT6_16_16_UNORM"/>
  62         <value value="0x44" name="FMT6_16_16_SNORM"/>
  63         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  64         <value value="0x46" name="FMT6_16_16_UINT"/>
  65         <value value="0x47" name="FMT6_16_16_SINT"/>
  66
  67         <value value="0x48" name="FMT6_32_UNORM"/>
  68         <value value="0x49" name="FMT6_32_SNORM"/>
  69         <value value="0x4a" name="FMT6_32_FLOAT"/>
  70         <value value="0x4b" name="FMT6_32_UINT"/>
  71         <value value="0x4c" name="FMT6_32_SINT"/>
  72         <value value="0x4d" name="FMT6_32_FIXED"/>
  73
  74         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  75         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  76         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  77         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  78         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  79
  80         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  81         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  82         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  83         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  84         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  85
  86         <value value="0x65" name="FMT6_32_32_UNORM"/>
  87         <value value="0x66" name="FMT6_32_32_SNORM"/>
  88         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  89         <value value="0x68" name="FMT6_32_32_UINT"/>
  90         <value value="0x69" name="FMT6_32_32_SINT"/>
  91         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  92
  93         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  94         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  95         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  96         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  97         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  98         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  99
 100         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 101         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 102         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 103         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 104         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 105         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 106
 107         <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/>
 108         <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/>
 109         <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/>
 110         <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/>
 111
 112         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 113
 114         <!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
 115              which has different UBWC compression from regular 8_UNORM format -->
 116         <value value="0x94" name="FMT6_8_PLANE_UNORM"/>
 117
 118         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 119
 120         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 121         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 122         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 123         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 124         <value value="0xaf" name="FMT6_ETC1"/>
 125         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 126         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 127         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 128         <value value="0xb3" name="FMT6_DXT1"/>
 129         <value value="0xb4" name="FMT6_DXT3"/>
 130         <value value="0xb5" name="FMT6_DXT5"/>
 131         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 132         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 133         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 134         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 135         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 136         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 137         <value value="0xc0" name="FMT6_BPTC"/>
 138         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 139         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 140         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 141         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 142         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 143         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 144         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 145         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 146         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 147         <value value="0xca" name="FMT6_ASTC_10x6"/>
 148         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 149         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 150         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 151         <value value="0xce" name="FMT6_ASTC_12x12"/>
 152
 153         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 154         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 155
 156         <!-- Not a hw enum, used internally in driver -->
 157         <value value="0xff" name="FMT6_NONE"/>
 158
 159 </enum>
 160
 161 <!-- probably same as a5xx -->
 162 <enum name="a6xx_depth_format">
 163         <value name="DEPTH6_NONE" value="0"/>
 164         <value name="DEPTH6_16" value="1"/>
 165         <value name="DEPTH6_24_8" value="2"/>
 166         <value name="DEPTH6_32" value="4"/>
 167 </enum>
 168
 169 <bitset name="a6x_cp_protect" inline="yes">
 170         <bitfield name="BASE_ADDR" low="0" high="17"/>
 171         <bitfield name="MASK_LEN" low="18" high="30"/>
 172         <bitfield name="READ" pos="31"/>
 173 </bitset>
 174
 175 <enum name="a6xx_shader_id">
 176         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 177         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 178         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 179         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 180         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 181         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 182         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 183         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 184         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 185         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 186         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 187         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 188         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 189         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 190         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 191         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 192         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 193         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 194         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 195         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 196         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 197         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 198         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 199         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 200         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 201         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 202         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 203         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 204         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 205         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 206         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 207         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 208         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 209         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 210         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 211         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 212         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 213         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 214         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 215         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 216         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 217         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 218         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 219 </enum>
 220
 221 <enum name="a6xx_debugbus_id">
 222         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 223         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 224         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 225         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 226         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 227         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 228         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 229         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 230         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 231         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 232         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 233         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 234         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 235         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 236         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 237         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 238         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 239         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 240         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 241         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 242         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 243         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 244         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 245         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 246         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 247         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 248         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 249         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 250         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 251         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 252         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 253         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 254         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 255         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 256         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 257         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 258         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 259         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 260         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 261         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 262         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 263         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 264         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 265 </enum>
 266
 267 <enum name="a6xx_cp_perfcounter_select">
 268         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 269         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 270         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 271         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 272         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 273         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 274         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 275         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 276         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 277         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 278         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 279         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 280         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 281         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 282         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 283         <value value="15" name="PERF_CP_SQE_IDLE"/>
 284         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 285         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 286         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 287         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 288         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 289         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 290         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 291         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 292         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 293         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 294         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 295         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 296         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 297         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 298         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 299         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 300         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 301         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 302         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 303         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 304         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 305         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 306         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 307         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 308         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 309         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 310         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 311         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 312         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 313         <value value="45" name="PERF_CP_PM4_DATA"/>
 314         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 315         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 316         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 317         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 318 </enum>
 319
 320 <enum name="a6xx_rbbm_perfcounter_select">
 321         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 322         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 323         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 324         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 325         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 326         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 327         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 328         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 329         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 330         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 331         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 332         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 333         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 334         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 335 </enum>
 336
 337 <enum name="a6xx_pc_perfcounter_select">
 338         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 339         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 340         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 341         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 342         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 343         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 344         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 345         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 346         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 347         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 348         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 349         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 350         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 351         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 352         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 353         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 354         <value value="16" name="PERF_PC_INSTANCES"/>
 355         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 356         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 357         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 358         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 359         <value value="21" name="PERF_PC_IA_VERTICES"/>
 360         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 361         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 362         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 363         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 364         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 365         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 366         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 367         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 368         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 369         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 370         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 371         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 372         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 373         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 374         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 375         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 376         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 377         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 378         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 379         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 380 </enum>
 381
 382 <enum name="a6xx_vfd_perfcounter_select">
 383         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 384         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 385         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 386         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 387         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 388         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 389         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 390         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 391         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 392         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 393         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 394         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 395         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 396         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 397         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 398         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 399         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 400         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 401         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 402         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 403         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 404         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 405         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 406 </enum>
 407
 408 <enum name="a6xx_hlsq_perfcounter_select">
 409         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 410         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 411         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 412         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 413         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 414         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 415         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 416         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 417         <value value="8" name="PERF_HLSQ_QUADS"/>
 418         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 419         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 420         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 421         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 422         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 423         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 424         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 425         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 426         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 427         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 428         <value value="19" name="PERF_HLSQ_PIXELS"/>
 429         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 430 </enum>
 431
 432 <enum name="a6xx_vpc_perfcounter_select">
 433         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 434         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 435         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 436         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 437         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 438         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 439         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 440         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 441         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 442         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 443         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 444         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 445         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 446         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 447         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 448         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 449         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 450         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 451         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 452         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 453         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 454         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 455         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 456         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 457         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 458         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 459         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 460         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 461 </enum>
 462
 463 <enum name="a6xx_tse_perfcounter_select">
 464         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 465         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 466         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 467         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 468         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 469         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 470         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 471         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 472         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 473         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 474         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 475         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 476         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 477         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 478         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 479         <value value="15" name="PERF_TSE_CINVOCATION"/>
 480         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 481         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 482         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 483         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 484 </enum>
 485
 486 <enum name="a6xx_ras_perfcounter_select">
 487         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 488         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 489         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 490         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 491         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 492         <value value="5" name="PERF_RAS_8X4_TILES"/>
 493         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 494         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 495         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 496         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 497         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 498         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 499         <value value="12" name="PERF_RAS_BLOCKS"/>
 500 </enum>
 501
 502 <enum name="a6xx_uche_perfcounter_select">
 503         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 504         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 505         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 506         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 507         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 508         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 509         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 510         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 511         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 512         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 513         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 514         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 515         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 516         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 517         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 518         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 519         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 520         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 521         <value value="18" name="PERF_UCHE_EVICTS"/>
 522         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 523         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 524         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 525         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 526         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 527         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 528         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 529         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 530         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 531         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 532         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 533         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 534         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 535         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 536         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 537         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 538         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 539         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 540         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 541         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 542         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 543 </enum>
 544
 545 <enum name="a6xx_tp_perfcounter_select">
 546         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 547         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 548         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 549         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 550         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 551         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 552         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 553         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 554         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 555         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 556         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 557         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 558         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 559         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 560         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 561         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 562         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 563         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 564         <value value="18" name="PERF_TP_QUADS_1D"/>
 565         <value value="19" name="PERF_TP_QUADS_2D"/>
 566         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 567         <value value="21" name="PERF_TP_QUADS_3D"/>
 568         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 569         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 570         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 571         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 572         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 573         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 574         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 575         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 576         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 577         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 578         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 579         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 580         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 581         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 582         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 583         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 584         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 585         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 586         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 587         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 588         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 589         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 590         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 591         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 592         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 593         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 594         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 595         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 596         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 597         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 598         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 599         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 600         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 601         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 602         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 603 </enum>
 604
 605 <enum name="a6xx_sp_perfcounter_select">
 606         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 607         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 608         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 609         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 610         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 611         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 612         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 613         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 614         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 615         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 616         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 617         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 618         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 619         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 620         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 621         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 622         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 623         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 624         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 625         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 626         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 627         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 628         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 629         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 630         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 631         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 632         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 633         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 634         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 635         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 636         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 637         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 638         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 639         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 640         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 641         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 642         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 643         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 644         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 645         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 646         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 647         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 648         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 649         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 650         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 651         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 652         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 653         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 654         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 655         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 656         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 657         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 658         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 659         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 660         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 661         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 662         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 663         <value value="57" name="PERF_SP_GPR_READ"/>
 664         <value value="58" name="PERF_SP_GPR_WRITE"/>
 665         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 666         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 667         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 668         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 669         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 670         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 671         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 672         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 673         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 674         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 675         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 676         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 677         <value value="71" name="PERF_SP_WORKING_EU"/>
 678         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 679         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 680         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 681         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 682         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 683         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 684         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 685         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 686         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 687         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 688         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 689         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 690         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 691 </enum>
 692
 693 <enum name="a6xx_rb_perfcounter_select">
 694         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 695         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 696         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 697         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 698         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 699         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 700         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 701         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 702         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 703         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 704         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 705         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 706         <value value="12" name="PERF_RB_Z_READ"/>
 707         <value value="13" name="PERF_RB_Z_WRITE"/>
 708         <value value="14" name="PERF_RB_C_READ"/>
 709         <value value="15" name="PERF_RB_C_WRITE"/>
 710         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 711         <value value="17" name="PERF_RB_Z_PASS"/>
 712         <value value="18" name="PERF_RB_Z_FAIL"/>
 713         <value value="19" name="PERF_RB_S_FAIL"/>
 714         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 715         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 716         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 717         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 718         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 719         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 720         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 721         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 722         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 723         <value value="29" name="PERF_RB_3D_PIXELS"/>
 724         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 725         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 726         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 727         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 728         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 729         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 730         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 731         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 732         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 733         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 734         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 735         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 736         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 737         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 738         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 739         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 740         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 741         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 742 </enum>
 743
 744 <enum name="a6xx_vsc_perfcounter_select">
 745         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 746         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 747         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 748         <value value="3" name="PERF_VSC_EOT_NUM"/>
 749         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 750 </enum>
 751
 752 <enum name="a6xx_ccu_perfcounter_select">
 753         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 754         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 755         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 756         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 757         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 758         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 759         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 760         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 761         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 762         <value value="9" name="PERF_CCU_GMEM_READ"/>
 763         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 764         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 765         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 766         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 767         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 768         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 769         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 770         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 771         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 772         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 773         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 774         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 775         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 776         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 777         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 778         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 779         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 780         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 781         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 782 </enum>
 783
 784 <enum name="a6xx_lrz_perfcounter_select">
 785         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 786         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 787         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 788         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 789         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 790         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 791         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 792         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 793         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 794         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 795         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 796         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 797         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 798         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 799         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 800         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 801         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 802         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 803         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 804         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 805         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 806         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 807         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 808         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 809         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 810         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 811         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 812         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 813 </enum>
 814
 815 <enum name="a6xx_cmp_perfcounter_select">
 816         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 817         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 818         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 819         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 820         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 821         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 822         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 823         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 824         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 825         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 826         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 827         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 828         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 829         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 830         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 831         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 832         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 833         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 834         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 835         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 836         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 837         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 838         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 839         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 840         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 841         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 842         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 843         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 844         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 845         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 846         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 847         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 848         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 849         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 850         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 851         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 852         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 853         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 854         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 855         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 856 </enum>
 857
 858 <!--
 859 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 860 component type/size, so I think it relates to internal format used for
 861 blending?  The one exception is that 16b unorm and 32b float use the
 862 same value... maybe 16b unorm is uncommon enough that it was just easier
 863 to upconvert to 32b float internally?
 864
 865  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 866 16b unorm:   4
 867
 868 32b int:     7
 869 16b int:     6
 870  8b int:     5
 871
 872 32b float:   4
 873 16b float:   3
 874  -->
 875 <enum name="a6xx_2d_ifmt">
 876         <value value="0x10" name="R2D_UNORM8"/>
 877         <value value="0x7"  name="R2D_INT32"/>
 878         <value value="0x6"  name="R2D_INT16"/>
 879         <value value="0x5"  name="R2D_INT8"/>
 880         <value value="0x4"  name="R2D_FLOAT32"/>
 881         <value value="0x3"  name="R2D_FLOAT16"/>
 882         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 883         <value value="0x0"  name="R2D_RAW"/>
 884 </enum>
 885
 886 <enum name="a6xx_ztest_mode">
 887         <doc>Allow early z-test and early-lrz (if applicable)</doc>
 888         <value value="0x0" name="A6XX_EARLY_Z"/>
 889         <doc>Disable early z-test and early-lrz test (if applicable)</doc>
 890         <value value="0x1" name="A6XX_LATE_Z"/>
 891         <doc>
 892                 A special mode that allows early-lrz test but disables
 893                 early-z test.  Which might sound a bit funny, since
 894                 lrz-test happens before z-test.  But as long as a couple
 895                 conditions are maintained this allows using lrz-test in
 896                 cases where fragment shader has kill/discard:
 897
 898                 1) Disable lrz-write in cases where it is uncertain during
 899                    binning pass that a fragment will pass.  Ie.  if frag
 900                    shader has-kill, writes-z, or alpha/stencil test is
 901                    enabled.  (For correctness, lrz-write must be disabled
 902                    when blend is enabled.)  This is analogous to how a
 903                    z-prepass works.
 904
 905                 2) Disable lrz-write and test if a depth-test direction
 906                    reversal is detected.  Due to condition (1), the contents
 907                    of the lrz buffer are a conservative estimation of the
 908                    depth buffer during the draw pass.  Meaning that geometry
 909                    that we know for certain will not be visible will not pass
 910                    lrz-test.  But geometry which may be (or contributes to
 911                    blend) will pass the lrz-test.
 912
 913                 This allows us to keep early-lrz-test in cases where the frag
 914                 shader does not write-z (ie. we know the z-value before FS)
 915                 and does not have side-effects (image/ssbo writes, etc), but
 916                 does have kill/discard.  Which turns out to be a common
 917                 enough case that it is useful to keep early-lrz test against
 918                 the conservative lrz buffer to discard fragments that we
 919                 know will definitely not be visible.
 920         </doc>
 921         <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
 922 </enum>
 923
 924 <domain name="A6XX" width="32">
 925         <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
 926                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 927                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 928                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 929                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 930                 <bitfield name="CP_SW" pos="8"/>
 931                 <bitfield name="CP_HW_ERROR" pos="9"/>
 932                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 933                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 934                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 935                 <bitfield name="CP_IB2" pos="13"/>
 936                 <bitfield name="CP_IB1" pos="14"/>
 937                 <bitfield name="CP_RB" pos="15"/>
 938                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 939                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 940                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 941                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 942                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 943                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 944                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 945                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 946                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 947                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 948                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 949         </bitset>
 950
 951         <bitset name="A6XX_CP_INT">
 952                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 953                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 954                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 955                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 956                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 957                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 958                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 959         </bitset>
 960
 961         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 962         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 963         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 964         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 965         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 966         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 967         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 968         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 969         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 970                 <bitfield name="IFPC" pos="0" type="boolean"/>
 971         </reg32>
 972         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 973         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 974         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 975         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 976         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 977         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 978         <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
 979         <!-- all the threshold values seem to be in units of quad-dwords: -->
 980         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 981                 <doc>
 982                         b0..7 seems to contain the size of buffered by not yet processed
 983                         RB level cmdstream.. it's possible that it is a low threshold
 984                         and b8..15 is a high threshold?
 985
 986                         b16..23 identifies where IB1 data starts (and RB data ends?)
 987
 988                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 989                 </doc>
 990                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 991                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 992                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 993                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
 994         </reg32>
 995         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
 996                 <doc>
 997                         low bits identify where CP_SET_DRAW_STATE stateobj
 998                         processing starts (and IB2 data ends). I'm guessing
 999                         b8 is part of this since (from downstream kgsl):
1000
1001                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
1002                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1003                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1004                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1005                                 } ...
1006                 </doc>
1007                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
1008                 <!-- total ROQ size: -->
1009                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1010         </reg32>
1011         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1012         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1013         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
1014         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1015         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1016
1017         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1018                 <reg32 offset="0x0" name="REG" type="uint"/>
1019         </array>
1020         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1021                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1022         </array>
1023
1024         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1025         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1026         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1027         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1028         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1029         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1030         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1031         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1032         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1033         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1034         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1035         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1036         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1037         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1038         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1039         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1040         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1041         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1042         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1043         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1044         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1045         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1046         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1047         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1048         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1049         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1050         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1051         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1052         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1053         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1054         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1055         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1056         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1057         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1058         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1059         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1060         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1061         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1062         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1063         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1064         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1065         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1066         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1067         <!-- SDS == CP_SET_DRAW_STATE: -->
1068         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1069         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1070         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1071         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1072         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1073         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1074         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1075         <!--
1076         There are probably similar registers for RB and SDS, teasing out SDS will
1077         take a slightly better test case..
1078          -->
1079         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1080                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1081                 <bitfield name="REM" low="16" high="31"/>
1082         </reg32>
1083         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1084                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1085                 <bitfield name="REM" low="16" high="31"/>
1086         </reg32>
1087         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1088         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1089         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1090         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1091         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1092         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1093         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1094         <reg32 offset="0x0210" name="RBBM_STATUS">
1095                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1096                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1097                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1098                 <bitfield high="20" low="20" name="VSC_BUSY" />
1099                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1100                 <bitfield high="18" low="18" name="SP_BUSY" />
1101                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1102                 <bitfield high="16" low="16" name="VPC_BUSY" />
1103                 <bitfield high="15" low="15" name="VFD_BUSY" />
1104                 <bitfield high="14" low="14" name="TESS_BUSY" />
1105                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1106                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1107                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1108                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1109                 <bitfield high="9" low="9" name="A2D_BUSY" />
1110                 <bitfield high="8" low="8" name="CCU_BUSY" />
1111                 <bitfield high="7" low="7" name="RB_BUSY" />
1112                 <bitfield high="6" low="6" name="RAS_BUSY" />
1113                 <bitfield high="5" low="5" name="TSE_BUSY" />
1114                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1115                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1116                 <bitfield high="2" low="2" name="CP_BUSY" />
1117                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1118                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1119         </reg32>
1120         <reg32 offset="0x0213" name="RBBM_STATUS3">
1121                 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1122         </reg32>
1123         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1124         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1125         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1126         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1127         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1128         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1129         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1130         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1131         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1132         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1133         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1134         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1135         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1136         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1137         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1138         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1139         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1140         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1141         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1142         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1143         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1144         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1145         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1146         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1147         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1148         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1149         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1150         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1151         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1152         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1153         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1154         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1155         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1156         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1157         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1158         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1159         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1160         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1161         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1162         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1163         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1164         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1165         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1166         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1167         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1168         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1169         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1170         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1171         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1172         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1173         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1174         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1175         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1176         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1177         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1178         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1179         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1180         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1181         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1182         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1183         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1184         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1185         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1186         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1187         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1188         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1189         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1190         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1191         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1192         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1193         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1194         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1195         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1196         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1197         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1198         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1199         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1200         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1201         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1202         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1203         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1204         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1205         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1206         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1207         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1208         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1209         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1210         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1211         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1212         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1213         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1214         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1215         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1216         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1217         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1218         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1219         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1220         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1221         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1222         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1223         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1224         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1225         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1226         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1227         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1228         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1229         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1230         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1231         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1232         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1233         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1234         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1235         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1236         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1237         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1238         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1239         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1240         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1241         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1242         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1243         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1244         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1245         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1246         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1247         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1248         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1249         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1250         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1251         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1252         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1253         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1254         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1255         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1256         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1257         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1258         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1259         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1260         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1261         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1262         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1263         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1264         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1265         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1266         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1267         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1268         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1269         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1270         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1271         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1272         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1273         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1274         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1275         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1276         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1277         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1278         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1279         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1280         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1281         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1282         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1283         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1284         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1285         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1286         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1287         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1288         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1289         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1290         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1291         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1292         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1293         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1294         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1295         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1296         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1297         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1298         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1299         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1300         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1301         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1302         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1303         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1304         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1305         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1306         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1307         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1308         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1309         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1310         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1311         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1312         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1313         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1314         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1315         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1316         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1317         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1318         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1319         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1320         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1321         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1322         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1323         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1324         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1325         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1326         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1327         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1328         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1329         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1330         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1331         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1332         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1333         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1334         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1335         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1336         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1337         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1338         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1339         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1340         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1341         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1342         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1343         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1344         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1345         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1346         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1347         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1348         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1349         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1350         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1351         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1352         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1353         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1354         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1355         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1356         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1357         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1358         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1359         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1360         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1361         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1362         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1363         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1364         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1365         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1366         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1367         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1368         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1369         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1370         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1371         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1372         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1373         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1374         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1375         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1376         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1377         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1378         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1379         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1380         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1381         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1382         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1383         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1384         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1385         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1386         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1387
1388         <!---
1389             This block of registers aren't tied to perf counters. They
1390             count various geometry stats, for example number of
1391             vertices in, number of primnitives assembled etc.
1392         -->
1393
1394         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1395         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1396         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1397         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1398         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1399         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1400         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1401         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1402         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1403         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1404         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1405         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1406         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1407         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1408         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1409         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1410         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1411         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1412         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1413         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1414         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1415         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1416
1417         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1418         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1419         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1420         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1421         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1422         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1423         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1424         <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1425         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1426         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1427         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1428         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1429         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1430         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1431         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1432         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1433         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1434         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1435         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1436         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1437         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1438         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1439         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1440         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1441         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1442         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1443         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1444         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1445         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1446         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1447         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1448         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1449         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1450         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1451         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1452         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1453         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1454         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1455         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1456         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1457         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1458         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1459         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1460         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1461         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1462         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1463         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1464         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1465         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1466         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1467         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1468         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1469         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1470         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1471         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1472         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1473         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1474         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1475         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1476         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1477         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1478         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1479         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1480         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1481         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1482         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1483         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1484         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1485         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1486         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1487         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1488         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1489         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1490         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1491         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1492         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1493         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1494         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1495         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1496         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1497         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1498         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1499         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1500         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1501         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1502         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1503         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1504         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1505         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1506         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1507         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1508         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1509         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1510         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1511         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1512         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1513         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1514         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1515         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1516         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1517         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1518         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1519         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1520         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1521         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1522         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1523         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1524         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1525         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1526         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1527         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1528         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1529         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1530         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1531         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1532         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1533         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1534         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1535         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1536         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1537         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1538         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1539         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1540         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1541         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1542         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1543                 <bitfield high="7" low="0" name="PING_INDEX"/>
1544                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1545         </reg32>
1546         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1547                 <bitfield high="5" low="0" name="TRACEEN"/>
1548                 <bitfield high="14" low="12" name="GRANU"/>
1549                 <bitfield high="31" low="28" name="SEGT"/>
1550         </reg32>
1551         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1552                 <bitfield high="27" low="24" name="ENABLE"/>
1553         </reg32>
1554         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1555         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1556         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1557         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1558         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1559         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1560         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1561         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1562         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1563                 <bitfield high="3" low="0" name="BYTEL0"/>
1564                 <bitfield high="7" low="4" name="BYTEL1"/>
1565                 <bitfield high="11" low="8" name="BYTEL2"/>
1566                 <bitfield high="15" low="12" name="BYTEL3"/>
1567                 <bitfield high="19" low="16" name="BYTEL4"/>
1568                 <bitfield high="23" low="20" name="BYTEL5"/>
1569                 <bitfield high="27" low="24" name="BYTEL6"/>
1570                 <bitfield high="31" low="28" name="BYTEL7"/>
1571         </reg32>
1572         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1573                 <bitfield high="3" low="0" name="BYTEL8"/>
1574                 <bitfield high="7" low="4" name="BYTEL9"/>
1575                 <bitfield high="11" low="8" name="BYTEL10"/>
1576                 <bitfield high="15" low="12" name="BYTEL11"/>
1577                 <bitfield high="19" low="16" name="BYTEL12"/>
1578                 <bitfield high="23" low="20" name="BYTEL13"/>
1579                 <bitfield high="27" low="24" name="BYTEL14"/>
1580                 <bitfield high="31" low="28" name="BYTEL15"/>
1581         </reg32>
1582         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1583         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1584         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1585         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1586         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1587         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1588         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1589         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1590         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1591         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1592         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1593         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1594         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1595         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1596         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1597         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1598         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1599         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1600         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1601         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1602         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1603         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1604         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1605         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1606         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1607         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1608         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1609         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1610         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1611         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1612         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1613         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1614         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1615         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1616         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1617         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1618         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1619         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1620         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1621         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1622         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1623         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1624         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1625         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1626         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1627         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1628         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1629         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1630         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1631         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1632         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1633         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1634         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1635         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1636         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1637         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1638         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1639         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1640         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1641         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1642         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1643         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1644         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1645         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1646         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1647         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1648         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1649         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1650         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1651         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1652         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1653         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1654         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1655         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1656         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1657         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1658         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1659         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1660         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1661         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1662         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1663         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1664         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1665         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1666         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1667         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1668         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1669         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1670                 <bitfield high="7" low="0" name="PERFSEL"/>
1671         </reg32>
1672         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1673         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1674         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1675         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1676         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1677         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1678         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1679         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1680         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1681         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1682         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1683         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1684         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1685         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1686         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1687         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1688         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1689         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1690         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1691         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1692         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1693         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1694         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1695         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1696         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1697         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1698         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1699         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1700         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1701         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1702         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1703         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1704         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1705         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1706         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1707         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1708         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1709         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1710         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1711         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1712         <reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
1713         <reg32 offset="0xB609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1"/>
1714         <reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
1715         <reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
1716         <reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
1717         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1718         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1719         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1720         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1721         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1722         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1723         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1724         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1725         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1726         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1727         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1728         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1729         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1730         <reg32 offset="0x3001" name="VBIF_CLKON">
1731                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1732         </reg32>
1733         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1734         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1735         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1736         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1737         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1738         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1739                 <bitfield low="0" high="3" name="DATA_SEL"/>
1740         </reg32>
1741         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1742         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1743                 <bitfield low="0" high="8" name="DATA_SEL"/>
1744         </reg32>
1745         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1746         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1747         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1748         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1749         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1750         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1751         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1752         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1753         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1754         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1755         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1756         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1757         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1758         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1759         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1760         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1761         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1762         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1763         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1764         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1765         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1766         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1767
1768         <!-- move/rename these.. -->
1769
1770         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1771         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1772         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1773
1774         <!-- same as RB_BIN_CONTROL -->
1775         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1776                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1777                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1778                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1779                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1780         </reg32>
1781
1782         <!--
1783                 from offset it seems it should be RB, but weird to duplicate
1784                 other regs from same block??
1785          -->
1786         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1787                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1788                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1789         </reg32>
1790
1791         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1792                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1793                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1794         </reg32>
1795         <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1796         <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1797         <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1798         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1799                 <bitfield name="NX" low="1" high="10" type="uint"/>
1800                 <bitfield name="NY" low="11" high="20" type="uint"/>
1801         </reg32>
1802         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1803                 <reg32 offset="0x0" name="REG">
1804                         <doc>
1805                                 Configures the mapping between VSC_PIPE buffer and
1806                                 bin, X/Y specify the bin index in the horiz/vert
1807                                 direction (0,0 is upper left, 0,1 is leftmost bin
1808                                 on second row, and so on).  W/H specify the number
1809                                 of bins assigned to this VSC_PIPE in the horiz/vert
1810                                 dimension.
1811                         </doc>
1812                         <bitfield name="X" low="0" high="9" type="uint"/>
1813                         <bitfield name="Y" low="10" high="19" type="uint"/>
1814                         <bitfield name="W" low="20" high="25" type="uint"/>
1815                         <bitfield name="H" low="26" high="31" type="uint"/>
1816                 </reg32>
1817         </array>
1818         <!--
1819         HW binning primitive & draw streams, which enable draws and primitives
1820         within a draw to be skipped in the main tile pass.  See:
1821         https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1822
1823         Compared to a5xx and earlier, we just program the address of the first
1824         stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1825
1826         LIMIT is set to PITCH - 64, to make room for a bit of overflow
1827          -->
1828         <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1829         <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1830         <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1831         <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1832         <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1833         <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1834         <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1835         <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1836         <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1837         <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1838
1839         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1840                 <doc>
1841                         Seems to be a bitmap of which tiles mapped to the VSC
1842                         pipe contain geometry.
1843
1844                         I suppose we can connect a maximum of 32 tiles to a
1845                         single VSC pipe.
1846                 </doc>
1847                 <reg32 offset="0x0" name="REG"/>
1848         </array>
1849
1850         <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1851                 <doc>
1852                         Has the size of data written to corresponding VSC_PRIM_STRM
1853                         buffer.
1854                 </doc>
1855                 <reg32 offset="0x0" name="REG"/>
1856         </array>
1857
1858         <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1859                 <doc>
1860                         Has the size of data written to corresponding VSC pipe, ie.
1861                         same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1862                 </doc>
1863                 <reg32 offset="0x0" name="REG"/>
1864         </array>
1865
1866         <!-- always 0x03200000 ? -->
1867         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1868
1869         <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1870                 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1871                 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1872                 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1873                 <!-- set with depthClampEnable, not clear what it does -->
1874                 <bitfield name="UNK5" pos="5" type="boolean"/>
1875                 <!-- controls near z clip behavior (set for vulkan) -->
1876                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1877                 <!-- guess based on a3xx and meaning of bits 8 and 9
1878                      if the guess is right then this is related to point sprite clipping -->
1879                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1880                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1881                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1882         </reg32>
1883         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1884         <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
1885         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1886
1887         <enum name="a6xx_layer_type">
1888           <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
1889           <value value="0x1" name="LAYER_3D"/>
1890           <value value="0x2" name="LAYER_CUBEMAP"/>
1891           <value value="0x3" name="LAYER_2D_ARRAY"/>
1892         </enum>
1893
1894         <!-- index of highest layer that can be written to via gl_Layer -->
1895         <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
1896
1897         <reg32 offset="0x8005" name="GRAS_CNTL">
1898                 <!-- see also RB_RENDER_CONTROL0 -->
1899                 <bitfield name="VARYING" pos="0" type="boolean"/>
1900                 <!-- b1 set for interpolateAtCentroid() -->
1901                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1902                 <!-- b2 set instead of b0 when running in per-sample mode -->
1903                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1904                 <!--
1905                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1906                 mode, and frag_face
1907                  -->
1908                 <bitfield name="SIZE" pos="3" type="boolean"/>
1909                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1910                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1911                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1912         </reg32>
1913         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1914                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1915                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1916         </reg32>
1917         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1918         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1919         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1920         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1921         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1922         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1923
1924         <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
1925         <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
1926         <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
1927
1928         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1929                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1930                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1931                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1932                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1933                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1934                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1935                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1936         </reg32>
1937         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1938                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1939                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1940         </reg32>
1941         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1942
1943         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1944                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1945         </reg32>
1946         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1947         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1948         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1949         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1950         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1951                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1952         </reg32>
1953
1954         <!-- always 0x0 -->
1955         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1956
1957         <!-- always 0x0 ? -->
1958         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1959
1960         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1961                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1962         </reg32>
1963
1964         <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
1965
1966         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1967
1968         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1969                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1970         </reg32>
1971         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1972                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1973                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1974         </reg32>
1975
1976         <bitset name="a6xx_sample_config" inline="yes">
1977                 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1978         </bitset>
1979
1980         <bitset name="a6xx_sample_locations" inline="yes">
1981                 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1982                 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1983                 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1984                 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1985                 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1986                 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1987                 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1988                 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1989         </bitset>
1990
1991         <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1992         <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1993         <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1994
1995         <!-- always 0x0 -->
1996         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1997
1998         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1999         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
2000         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
2001         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
2002         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
2003         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
2004
2005         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
2006                 <!--
2007                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
2008                 look when we get around to enabling lrz
2009                  -->
2010                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2011                 <doc>LRZ write also disabled for blend/etc.</doc>
2012                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
2013                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2014                 <bitfield name="GREATER" pos="2" type="boolean"/>
2015                 <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
2016                 <!-- set when depth-test + depth-write enabled -->
2017                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
2018         </reg32>
2019         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
2020         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
2021                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2022         </reg32>
2023         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
2024         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
2025         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
2026         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
2027                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
2028                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
2029         </reg32>
2030
2031         <!--
2032         The LRZ "fast clear" buffer is initialized to zero's by blob, and
2033         read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears
2034         to store 1b/block.  It appears that '0' means block has original
2035         depth clear value, and '1' means that the corresponding block in
2036         LRZ has been modified.  Ignoring alignment/padding, the size is
2037         given by the formula:
2038
2039                 // calculate LRZ size from depth size:
2040                 if (nr_samples == 4) {
2041                         width *= 2;
2042                         height *= 2;
2043                 } else if (nr_samples == 2) {
2044                         height *= 2;
2045                 }
2046
2047                 lrz_width = div_round_up(width, 8);
2048                 lrz_heigh = div_round_up(height, 8);
2049
2050                 // calculate # of blocks:
2051                 nblocksx = div_round_up(lrz_width, 16);
2052                 nblocksy = div_round_up(lrz_height, 4);
2053
2054                 // fast-clear buffer is 1bit/block:
2055                 fc_sz = div_round_up(nblocksx * nblocksy, 8);
2056
2057         In practice the blob seems to switch off FC_ENABLE once the size
2058         increases beyond 1 page.  Not sure if that is an actual limit or
2059         not.
2060          -->
2061         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
2062         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
2063         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
2064
2065         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
2066                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2067         </reg32>
2068
2069         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
2070
2071         <enum name="a6xx_rotation">
2072           <value value="0x0" name="ROTATE_0"/>
2073           <value value="0x1" name="ROTATE_90"/>
2074           <value value="0x2" name="ROTATE_180"/>
2075           <value value="0x3" name="ROTATE_270"/>
2076           <value value="0x4" name="ROTATE_HFLIP"/>
2077           <value value="0x5" name="ROTATE_VFLIP"/>
2078         </enum>
2079
2080         <bitset name="a6xx_2d_blit_cntl" inline="yes">
2081                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2082                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2083                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2084                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2085
2086                 <bitfield name="UNK" low="17" high="18" type="uint"/>
2087
2088                 <!-- required when blitting D24S8/D24X8 -->
2089                 <bitfield name="D24S8" pos="19" type="boolean"/>
2090                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2091                 <bitfield name="MASK" low="20" high="23"/>
2092                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2093         </bitset>
2094
2095         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2096
2097         <!-- could be the src coords are fixed point? -->
2098         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2099                 <bitfield name="X" low="8" high="31" type="int"/>
2100         </reg32>
2101         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2102                 <bitfield name="X" low="8" high="31" type="int"/>
2103         </reg32>
2104         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2105                 <bitfield name="Y" low="8" high="31" type="int"/>
2106         </reg32>
2107         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2108                 <bitfield name="Y" low="8" high="31" type="int"/>
2109         </reg32>
2110
2111         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2112         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2113
2114         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2115         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2116
2117         <!-- always 0x880 ? -->
2118         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2119
2120         <!-- same as GRAS_BIN_CONTROL: -->
2121         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2122                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2123                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2124                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2125                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2126         </reg32>
2127         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2128                 <!-- always set: ?? -->
2129                 <bitfield name="UNK4" pos="4" type="boolean"/>
2130                 <!-- set during binning pass: -->
2131                 <bitfield name="BINNING" pos="7" type="boolean"/>
2132                 <!-- bit seems to be set whenever depth buffer enabled: -->
2133                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2134                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2135                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2136         </reg32>
2137         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2138                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2139         </reg32>
2140         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2141                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2142                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2143         </reg32>
2144
2145         <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2146         <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2147         <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2148
2149         <!--
2150         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2151         name comes from kernel and is probably right)
2152          -->
2153         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2154                 <!-- see also GRAS_CNTL -->
2155                 <bitfield name="VARYING" pos="0" type="boolean"/>
2156                 <!-- b1 set for interpolateAtCentroid() -->
2157                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2158                 <!-- b2 set instead of b0 when running in per-sample mode -->
2159                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2160                 <!--
2161                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2162                 mode, and frag_face
2163                  -->
2164                 <bitfield name="SIZE" pos="3" type="boolean"/>
2165                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2166                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2167                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2168                 <bitfield name="UNK10" pos="10" type="boolean"/>
2169         </reg32>
2170         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2171                 <!-- enable bits for various FS sysvalue regs: -->
2172                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2173                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2174                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2175                 <!-- b4 and b5 set in per-sample mode: -->
2176                 <bitfield name="UNK4" pos="4" type="boolean"/>
2177                 <bitfield name="UNK5" pos="5" type="boolean"/>
2178                 <bitfield name="SIZE" pos="6" type="boolean"/>
2179         </reg32>
2180
2181         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2182                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2183                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2184                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2185         </reg32>
2186         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2187                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2188         </reg32>
2189         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2190                 <bitfield name="RT0" low="0" high="3"/>
2191                 <bitfield name="RT1" low="4" high="7"/>
2192                 <bitfield name="RT2" low="8" high="11"/>
2193                 <bitfield name="RT3" low="12" high="15"/>
2194                 <bitfield name="RT4" low="16" high="19"/>
2195                 <bitfield name="RT5" low="20" high="23"/>
2196                 <bitfield name="RT6" low="24" high="27"/>
2197                 <bitfield name="RT7" low="28" high="31"/>
2198         </reg32>
2199         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2200                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2201                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2202                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2203                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2204                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2205                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2206                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2207                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2208         </reg32>
2209         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2210                 <!-- Same as SP_SRGB_CNTL -->
2211                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2212                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2213                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2214                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2215                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2216                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2217                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2218                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2219         </reg32>
2220
2221         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2222                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2223         </reg32>
2224         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2225
2226         <!-- always 0x0 ? -->
2227         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2228         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2229         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2230         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2231         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2232         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2233         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2234
2235         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2236                 <reg32 offset="0x0" name="CONTROL">
2237                         <bitfield name="BLEND" pos="0" type="boolean"/>
2238                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2239                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2240                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2241                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2242                 </reg32>
2243                 <reg32 offset="0x1" name="BLEND_CONTROL">
2244                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2245                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2246                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2247                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2248                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2249                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2250                 </reg32>
2251                 <reg32 offset="0x2" name="BUF_INFO">
2252                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2253                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2254                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2255                 </reg32>
2256                 <!--
2257                 at least in gmem, things seem to be aligned to pitch of 64..
2258                 maybe an artifact of tiled format used in gmem?
2259                  -->
2260                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2261                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2262                 <!--
2263                 Compared to a5xx and before, we configure both a GMEM base and
2264                 external base.  Not sure if this is to facilitate GMEM save/
2265                 restore for context switch, or just to simplify state setup to
2266                 not have to care about GMEM vs BYPASS mode.
2267                  -->
2268                 <reg32 offset="0x5" name="BASE_LO"/>
2269                 <reg32 offset="0x6" name="BASE_HI"/>
2270
2271                 <reg64 offset="0x5" name="BASE" type="waddress"/>
2272
2273                 <reg32 offset="0x7" name="BASE_GMEM"/>
2274         </array>
2275
2276         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2277         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2278         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2279         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2280         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2281                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2282                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2283                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2284         </reg32>
2285         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2286                 <!-- per-mrt enable bit -->
2287                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2288                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2289                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2290                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2291                 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2292                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2293         </reg32>
2294         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2295                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2296         </reg32>
2297
2298         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2299                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2300                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2301                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2302                 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2303                 <doc>
2304                 Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2305                 also set when Z_BOUNDS_ENABLE is set
2306                 </doc>
2307                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2308                 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2309         </reg32>
2310         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2311         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2312                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2313         </reg32>
2314 <!-- probably: -->
2315         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2316                 <doc>stride of depth/stencil buffer</doc>
2317         </reg32>
2318         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2319                 <doc>size of layer</doc>
2320         </reg32>
2321         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2322         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2323         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
2324         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2325
2326         <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2327         <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2328
2329         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2330                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2331                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2332                 <!--
2333                         set for stencil operations that require read from stencil
2334                         buffer, but not for example for stencil clear (which does
2335                         not require read).. so guessing this is analogous to
2336                         READ_DEST_ENABLE for color buffer..
2337                  -->
2338                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2339                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2340                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2341                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2342                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2343                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2344                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2345                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2346                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2347         </reg32>
2348         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2349                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2350         </reg32>
2351         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2352                 <doc>stride of stencil buffer</doc>
2353         </reg32>
2354         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2355                 <doc>size of layer</doc>
2356         </reg32>
2357         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2358         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2359         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
2360         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2361         <reg32 offset="0x8887" name="RB_STENCILREF">
2362                 <bitfield name="REF" low="0" high="7"/>
2363                 <bitfield name="BFREF" low="8" high="15"/>
2364         </reg32>
2365         <reg32 offset="0x8888" name="RB_STENCILMASK">
2366                 <bitfield name="MASK" low="0" high="7"/>
2367                 <bitfield name="BFMASK" low="8" high="15"/>
2368         </reg32>
2369         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2370                 <bitfield name="WRMASK" low="0" high="7"/>
2371                 <bitfield name="BFWRMASK" low="8" high="15"/>
2372         </reg32>
2373         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2374         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2375                 <bitfield name="COPY" pos="1" type="boolean"/>
2376         </reg32>
2377
2378         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2379                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2380         </reg32>
2381
2382         <!-- clamps depth value for depth test/write -->
2383         <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2384         <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2385
2386         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2387         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2388         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2389
2390         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2391                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2392         </reg32>
2393         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2394         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2395         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2396                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2397                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2398                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2399                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2400                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2401         </reg32>
2402         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
2403         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2404         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2405         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2406         <!-- array-pitch is size of layer -->
2407         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2408         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
2409         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2410         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2411         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2412                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2413                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2414         </reg32>
2415
2416         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2417         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2418         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2419         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2420
2421         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2422         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2423                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2424                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2425                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2426                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2427                 <doc>
2428                         For clearing depth/stencil
2429                                 1 - depth
2430                                 2 - stencil
2431                                 3 - depth+stencil
2432                         For clearing color buffer:
2433                                 then probably a component mask, I always see 0xf
2434                 </doc>
2435                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2436         </reg32>
2437
2438         <!-- always 0x0 ? -->
2439         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2440
2441         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2442         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2443         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
2444         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2445                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2446                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2447         </reg32>
2448         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2449                 <reg32 offset="0" name="ADDR_LO"/>
2450                 <reg32 offset="1" name="ADDR_HI"/>
2451                 <reg64 offset="0" name="ADDR" type="waddress"/>
2452                 <reg32 offset="2" name="PITCH">
2453                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2454                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2455                 </reg32>
2456         </array>
2457         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2458         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2459
2460         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2461         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2462
2463         <bitset name="a6xx_2d_surf_info" inline="yes">
2464                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2465                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2466                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2467                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2468                 <bitfield name="SRGB" pos="13" type="boolean"/>
2469                 <!-- the rest is only for src -->
2470                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2471                 <bitfield name="FILTER" pos="16" type="boolean"/>
2472                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2473                 <bitfield name="UNK20" pos="20" type="boolean"/>
2474                 <bitfield name="UNK22" pos="22" type="boolean"/>
2475         </bitset>
2476
2477         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2478         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2479         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2480         <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
2481         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2482                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2483         </reg32>
2484
2485         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2486         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2487         <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
2488         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2489                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2490                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2491         </reg32>
2492
2493         <!-- unlike a5xx, these are per channel values rather than packed -->
2494         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2495         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2496         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2497         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2498
2499         <!-- always 0x1 ? -->
2500         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2501
2502         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2503
2504         <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2505                 <!-- offset into GMEM for something.
2506                         important for sysmem path
2507                         BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2508                         blob values for GMEM path (note: close to GMEM size):
2509                         a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
2510                         SYSMEM path values:
2511                         a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
2512                 -->
2513                 <bitfield name="OFFSET" low="23" high="31" shr="12" type="hex"/>
2514                 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2515                 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2516         </reg32>
2517
2518         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2519
2520         <!-- always 0x00ffff00 ? */ -->
2521         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2522         <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
2523         <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
2524
2525         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2526
2527         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2528                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2529         </reg32>
2530
2531         <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
2532         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2533         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2534
2535         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2536                 <reg32 offset="0x0" name="MODE"/>
2537         </array>
2538         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2539                 <reg32 offset="0x0" name="MODE"/>
2540         </array>
2541
2542         <!-- always 0x0 -->
2543         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2544         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2545
2546         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2547                 <!-- one bit per varying component: -->
2548                 <reg32 offset="0" name="DISABLE"/>
2549         </array>
2550
2551         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2552                 <!-- always 0x10000 when SO enabled.. -->
2553                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2554         </reg32>
2555         <reg32 offset="0x9217" name="VPC_SO_PROG">
2556                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2557                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2558                 <bitfield name="A_EN" pos="11" type="boolean"/>
2559                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2560                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2561                 <bitfield name="B_EN" pos="23" type="boolean"/>
2562         </reg32>
2563
2564         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2565         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2566
2567         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2568                 <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
2569                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2570                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2571                 <reg32 offset="2" name="BUFFER_SIZE"/>
2572                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2573                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2574                 <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
2575                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2576                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2577         </array>
2578
2579         <!-- always 0x0 ? -->
2580         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2581                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2582         </reg32>
2583
2584         <!-- always 0x0 ? -->
2585         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2586
2587         <reg32 offset="0x9301" name="VPC_PACK">
2588                 <doc>
2589                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2590                         plus # of transform-feedback (streamout) varyings if using the
2591                         hw streamout (rather than stg instructions in shader)
2592                 </doc>
2593                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2594                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2595                 <!--
2596                 This seems to be the OUTLOC for the psize output.  It could possibly
2597                 be the max-OUTLOC position, but it is only set when VS writes psize
2598                 (and blob always puts psize at highest OUTLOC)
2599                  -->
2600                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2601         </reg32>
2602
2603         <reg32 offset="0x9302" name="VPC_PACK_GS">
2604                 <doc>
2605                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2606                         plus # of transform-feedback (streamout) varyings if using the
2607                         hw streamout (rather than stg instructions in shader)
2608                 </doc>
2609                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2610                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2611                 <!--
2612                 This seems to be the OUTLOC for the psize output.  It could possibly
2613                 be the max-OUTLOC position, but it is only set when VS writes psize
2614                 (and blob always puts psize at highest OUTLOC)
2615                  -->
2616                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2617         </reg32>
2618
2619         <reg32 offset="0x9303" name="VPC_PACK_3">
2620                 <doc>
2621                         domain shader version of VPC_PACK
2622                 </doc>
2623                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2624                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2625                 <!--
2626                 This seems to be the OUTLOC for the psize output.  It could possibly
2627                 be the max-OUTLOC position, but it is only set when VS writes psize
2628                 (and blob always puts psize at highest OUTLOC)
2629                  -->
2630                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2631         </reg32>
2632
2633         <reg32 offset="0x9304" name="VPC_CNTL_0">
2634                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2635                 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2636                 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2637                 <bitfield name="VARYING" pos="16" type="boolean"/>
2638                 <bitfield name="UNKLOC" low="24" high="31" type="uint"/>
2639         </reg32>
2640
2641         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2642                 <bitfield name="BUF0" pos="0" type="boolean"/>
2643                 <bitfield name="BUF1" pos="3" type="boolean"/>
2644                 <bitfield name="BUF2" pos="6" type="boolean"/>
2645                 <bitfield name="BUF3" pos="9" type="boolean"/>
2646                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2647         </reg32>
2648         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2649                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2650         </reg32>
2651
2652         <!-- always 0x0 ? -->
2653         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2654         <!-- always 0x0 ? -->
2655         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2656
2657         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2658
2659         <!-- always 0x0 ? -->
2660         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2661
2662         <enum name="a6xx_tess_spacing">
2663           <value value="0x0" name="TESS_EQUAL"/>
2664           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2665           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2666         </enum>
2667
2668         <enum name="a6xx_tess_output">
2669           <value value="0x0" name="TESS_POINTS"/>
2670           <value value="0x1" name="TESS_LINES"/>
2671           <value value="0x2" name="TESS_CW_TRIS"/>
2672           <value value="0x3" name="TESS_CCW_TRIS"/>
2673         </enum>
2674
2675         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2676           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2677           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2678         </reg32>
2679
2680         <!-- probably: -->
2681         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2682         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2683
2684         <!-- always 0x1 ? -->
2685         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2686
2687         <!-- probably a mirror of VFD_CONTROL_6 -->
2688         <reg32 offset="0x9806" name="PC_PRIMID_CNTL">
2689                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2690         </reg32>
2691
2692         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2693         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2694
2695         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2696
2697         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2698                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2699                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2700                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2701                 <bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
2702         </reg32>
2703         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2704                 <doc>
2705                         vertex shader
2706
2707                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2708                         plus # of transform-feedback (streamout) varyings if using the
2709                         hw streamout (rather than stg instructions in shader)
2710                 </doc>
2711                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2712                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2713         </reg32>
2714
2715         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2716                 <doc>
2717                   geometry shader
2718                 </doc>
2719                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2720                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2721                 <bitfield name="LAYER" pos="9" type="boolean"/>
2722                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2723         </reg32>
2724
2725         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2726                 <doc>
2727                         hull shader?
2728
2729                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2730                         plus # of transform-feedback (streamout) varyings if using the
2731                         hw streamout (rather than stg instructions in shader)
2732                 </doc>
2733                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2734                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2735         </reg32>
2736         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2737                 <doc>
2738                         domain shader
2739                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2740                         plus # of transform-feedback (streamout) varyings if using the
2741                         hw streamout (rather than stg instructions in shader)
2742                 </doc>
2743                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2744                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2745         </reg32>
2746
2747         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2748                 <doc>
2749                   geometry shader
2750                 </doc>
2751                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2752                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2753                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2754         </reg32>
2755
2756         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2757                 <doc>
2758                   size in vec4s of per-primitive storage for gs
2759                 </doc>
2760                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2761         </reg32>
2762
2763         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2764
2765         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2766         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2767
2768         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2769         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2770                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2771                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2772         </reg32>
2773         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
2774         <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
2775         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
2776         <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
2777
2778         <!-- always 0x0 -->
2779         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2780
2781         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2782                 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2783                 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2784         </reg32>
2785         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2786                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2787                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2788                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2789         </reg32>
2790         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2791                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2792                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2793         </reg32>
2794         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2795                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2796                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2797                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2798         </reg32>
2799         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2800         </reg32>
2801         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2802                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2803         </reg32>
2804         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2805                 <!--
2806                         True if gl_PrimitiveID is read via the FS and there is
2807                         no matching write from the GS, and therefore it needs to
2808                         be passed through via fixed-function logic.
2809                 -->
2810                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2811         </reg32>
2812
2813         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2814                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2815         </reg32>
2816
2817         <!-- always 0x0 ? -->
2818         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2819         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2820                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2821                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2822                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2823                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2824         </reg32>
2825
2826         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2827         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2828         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2829                 <reg64 offset="0x0" name="BASE" type="address"/>
2830                 <reg32 offset="0x0" name="BASE_LO"/>
2831                 <reg32 offset="0x1" name="BASE_HI"/>
2832                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2833                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2834         </array>
2835         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2836                 <reg32 offset="0x0" name="INSTR">
2837                         <!-- IDX and byte OFFSET into VFD_FETCH -->
2838                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2839                         <bitfield name="OFFSET" low="5" high="16"/>
2840                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2841                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2842                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2843                         <bitfield name="UNK30" pos="30" type="boolean"/>
2844                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2845                 </reg32>
2846                 <reg32 offset="0x1" name="STEP_RATE"/>
2847         </array>
2848         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2849                 <reg32 offset="0x0" name="INSTR">
2850                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2851                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2852                 </reg32>
2853         </array>
2854
2855         <!-- always 0x1 ? -->
2856         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2857
2858         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2859                 <!--
2860                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2861                 used registers is a bit odd too:
2862                         - used (half): 0-15 68-179 (cnt=128, max=179)
2863                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2864                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2865                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2866                 then:
2867                         - used (merged): 0-191 (cnt=192, max=191)
2868                 So I think if b31 is set, then the half precision registers overlap
2869                 the full precision registers.  (Which seems like a pretty sensible
2870                 feature, actually I'm not sure when you *wouldn't* want to use that,
2871                 since it gives register allocation more flexibility)
2872                  -->
2873                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2874                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2875                 <!-- seems to be nesting level for flow control:.. -->
2876                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2877                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2878                 <bitfield name="VARYING" pos="22" type="boolean"/>
2879                 <!-- set when dFdxFine/dFdyFine is used -->
2880                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2881                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2882                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2883         </bitset>
2884
2885         <bitset name="a6xx_sp_xs_config" inline="yes">
2886                 <!--
2887                 Each of these are set if the given resource type is used
2888                 with the Vulkan/bindless binding model.
2889                 -->
2890                 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2891                 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2892                 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2893                 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2894
2895                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2896                 <!--
2897                 number of textures and samplers.. these might be swapped, with GL I
2898                 always see the same value for both.
2899                  -->
2900                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2901                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2902                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2903         </bitset>
2904
2905         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2906         <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex">
2907                 <!--
2908                 bitmask of true/false conditions for VS brac.N instructions,
2909                 bit N corresponds to brac.N
2910                  -->
2911         </reg32>
2912         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2913                 <!-- # of VS outputs including pos/psize -->
2914                 <bitfield name="VSOUT" low="0" high="5" type="uint"/>
2915         </reg32>
2916         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2917                 <reg32 offset="0x0" name="REG">
2918                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2919                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2920                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2921                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2922                 </reg32>
2923         </array>
2924         <!--
2925         Starting with a5xx, position/psize outputs from shader end up in the
2926         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2927         the last entries too, except when gl_PointCoord is used, blob inserts
2928         an extra varying after, but with a lower OUTLOC position.  If present,
2929         psize is last, preceded by position.
2930          -->
2931         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2932                 <reg32 offset="0x0" name="REG">
2933                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2934                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2935                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2936                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2937                 </reg32>
2938         </array>
2939
2940         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2941         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2942         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2943         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2944         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2945         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2946
2947         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2948         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2949         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2950         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2951         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2952         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2953         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2954         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2955
2956         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2957         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2958                 <!-- # of DS outputs including pos/psize -->
2959                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2960         </reg32>
2961         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2962                 <reg32 offset="0x0" name="REG">
2963                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2964                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2965                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2966                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2967                 </reg32>
2968         </array>
2969         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2970                 <reg32 offset="0x0" name="REG">
2971                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2972                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2973                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2974                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2975                 </reg32>
2976         </array>
2977
2978         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2979         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2980         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2981         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2982         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2983         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2984
2985         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2986         <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE">
2987                 <!-- size of output of previous stage -->
2988         </reg32>
2989         <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex">
2990                 <!--
2991                 bitmask of true/false conditions for FS brac.N instructions,
2992                 bit N corresponds to brac.N
2993                  -->
2994         </reg32>
2995
2996         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
2997                 <!-- # of VS outputs including pos/psize -->
2998                 <bitfield name="GSOUT" low="0" high="5" type="uint"/>
2999                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
3000         </reg32>
3001
3002         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
3003                 <reg32 offset="0x0" name="REG">
3004                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3005                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3006                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3007                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3008                 </reg32>
3009         </array>
3010
3011         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
3012                 <reg32 offset="0x0" name="REG">
3013                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3014                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3015                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3016                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3017                 </reg32>
3018         </array>
3019
3020         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
3021         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
3022         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
3023         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
3024         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
3025
3026         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
3027         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
3028         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
3029         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
3030         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
3031         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
3032         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
3033         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
3034         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
3035         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
3036         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
3037         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
3038         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
3039         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
3040         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
3041         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
3042
3043         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3044         <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
3045                 <!--
3046                 bitmask of true/false conditions for FS brac.N instructions,
3047                 bit N corresponds to brac.N
3048                  -->
3049         </reg32>
3050         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
3051         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
3052         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
3053
3054         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
3055                 <bitfield name="ENABLED" pos="0" type="boolean"/>
3056                 <bitfield name="UNK8" pos="8" type="boolean"/>
3057                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3058                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3059         </reg32>
3060         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3061                 <!-- Same as RB_SRGB_CNTL -->
3062                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3063                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3064                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3065                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3066                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3067                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3068                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3069                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3070         </reg32>
3071         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3072                 <bitfield name="RT0" low="0" high="3"/>
3073                 <bitfield name="RT1" low="4" high="7"/>
3074                 <bitfield name="RT2" low="8" high="11"/>
3075                 <bitfield name="RT3" low="12" high="15"/>
3076                 <bitfield name="RT4" low="16" high="19"/>
3077                 <bitfield name="RT5" low="20" high="23"/>
3078                 <bitfield name="RT6" low="24" high="27"/>
3079                 <bitfield name="RT7" low="28" high="31"/>
3080         </reg32>
3081         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3082                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3083                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3084                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3085         </reg32>
3086         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3087                 <bitfield name="MRT" low="0" high="3" type="uint"/>
3088         </reg32>
3089
3090         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3091                 <reg32 offset="0" name="REG">
3092                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3093                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3094                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3095                 </reg32>
3096         </array>
3097
3098         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3099                 <!-- unknown bits 0x7fc0 always set -->
3100                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
3101                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3102                 <bitfield name="UNK3" pos="3" type="boolean"/>
3103                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3104         </reg32>
3105         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3106                 <reg32 offset="0" name="CMD">
3107                         <bitfield name="SRC" low="0" high="6" type="uint"/>
3108                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3109                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3110                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3111                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
3112                         <bitfield name="HALF" pos="26" type="boolean"/>
3113                         <!--
3114                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
3115                         skip pre-fetch.. TODO test texelFetch
3116                         CMD is 0x6 when the Vulkan mode is enabled, and
3117                         TEX_ID/SAMP_ID refer to the descriptor sets while the
3118                         indices come from SP_FS_BINDLESS_PREFETCH[n]
3119                          -->
3120                         <bitfield name="CMD" low="27" high="31"/>
3121                 </reg32>
3122         </array>
3123
3124         <!-- TODO confirm that this is actually an array -->
3125         <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3126                 <reg32 offset="0" name="CMD">
3127                         <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
3128                         <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
3129                 </reg32>
3130         </array>
3131
3132         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3133
3134         <!-- always 0x0 ? -->
3135         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3136
3137         <!-- set for compute shaders, always 0x41 -->
3138         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
3139
3140         <!-- set for compute shaders, always 0x0 -->
3141         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3142
3143         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3144
3145         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3146         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3147         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3148         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3149         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3150         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3151         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3152         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3153
3154         <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3155                 <reg64 offset="0" name="ADDR" type="waddress"/>
3156         </array>
3157
3158         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3159                 <doc>per MRT</doc>
3160                 <reg32 offset="0x0" name="REG">
3161                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3162                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3163                 </reg32>
3164         </array>
3165
3166         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3167         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3168         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3169         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3170         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3171
3172         <!--
3173         IBO state for compute shader:
3174          -->
3175         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3176         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3177         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3178
3179         <!-- always 0x5 ? -->
3180         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3181
3182         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3183         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3184
3185         <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3186                 <reg64 offset="0" name="ADDR" type="waddress"/>
3187         </array>
3188
3189         <!--
3190         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3191         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3192          -->
3193         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3194         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3195         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3196
3197         <!--
3198         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
3199          -->
3200         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3201                 <bitfield name="NORM" pos="0" type="boolean"/>
3202                 <bitfield name="SINT" pos="1" type="boolean"/>
3203                 <bitfield name="UINT" pos="2" type="boolean"/>
3204                 <!-- looks like HW only cares about the base type of this format,
3205                      which matches the ifmt? -->
3206                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3207                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3208                 <bitfield name="SRGB" pos="11" type="boolean"/>
3209                 <!-- some sort of channel mask, not sure what it is for -->
3210                 <bitfield name="MASK" low="12" high="15"/>
3211         </reg32>
3212
3213         <!-- always 0x0 -->
3214         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3215
3216         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3217         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3218
3219         <!-- always 0x3f ? -->
3220         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3221
3222         <!--
3223         The downstream kernel calls the debug cluster of registers
3224         "a6xx_sp_ps_tp_cluster" but this actually specifies the border
3225         color base for compute shaders.
3226         -->
3227         <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3228         <!-- always 0x0 ? -->
3229         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3230         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3231
3232         <!-- could be all the stuff below here is actually TPL1?? -->
3233
3234         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3235                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3236         </reg32>
3237         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3238                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3239                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3240         </reg32>
3241
3242         <!-- looks to work in the same way as a5xx: -->
3243         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3244         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3245         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3246         <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3247         <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3248         <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3249
3250         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3251
3252         <!--
3253         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3254         badly named or the functionality moved in a6xx.  But downstream kernel
3255         calls this "a6xx_sp_ps_tp_2d_cluster"
3256          -->
3257         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3258         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3259                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3260                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3261         </reg32>
3262         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3263         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3264         <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3265         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3266            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3267         </reg32>
3268
3269         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3270         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3271         <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3272         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3273                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3274                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3275         </reg32>
3276
3277         <!-- always 0x00100000 ? -->
3278         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3279
3280         <!-- always 0x44 ? -->
3281         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3282
3283         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3284                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3285                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3286         </bitset>
3287
3288         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3289         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3290         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3291         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3292
3293         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3294
3295         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3296                 <!-- always 0x7 ? -->
3297         </reg32>
3298         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3299                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3300                 <!-- SAMPLEID is loaded into a half-precision register: -->
3301                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3302                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3303                 <!--
3304                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3305                 to be divided by to scale to a single fragment.  It is probably
3306                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3307                  -->
3308                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3309         </reg32>
3310         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3311                 <!-- register loaded with position (bary.f) -->
3312                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3313                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3314         </reg32>
3315         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3316                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3317                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3318                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3319         </reg32>
3320         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3321                 <!-- unknown regid in low 8b -->
3322         </reg32>
3323         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3324
3325         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3326                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3327                 <!-- localsize is value minus one: -->
3328                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3329                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3330                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3331         </reg32>
3332         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3333                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3334         </reg32>
3335         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3336                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3337         </reg32>
3338         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3339                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3340         </reg32>
3341         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3342                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3343         </reg32>
3344         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3345                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3346         </reg32>
3347         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3348                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3349         </reg32>
3350         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3351                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3352                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3353                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3354                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3355         </reg32>
3356         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3357         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3358         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3359         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3360
3361         <!-- mirror of SP_CS_BINDLESS_BASE -->
3362         <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3363                 <reg64 offset="0" name="ADDR" type="waddress"/>
3364         </array>
3365
3366         <!-- probably: -->
3367         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3368
3369         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3370
3371         <!-- always 0x0 ? -->
3372         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3373
3374         <!-- mirror of SP_BINDLESS_BASE -->
3375         <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3376                 <reg64 offset="0" name="ADDR" type="waddress"/>
3377         </array>
3378
3379         <!-- always 0x80 ? -->
3380         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3381         <!-- always 0x0 ? -->
3382         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3383         <!-- always 0x0 ? -->
3384         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3385
3386 </domain>
3387
3388 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3389 <domain name="A6XX_TEX_SAMP" width="32">
3390         <doc>Texture sampler dwords</doc>
3391         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3392                 <value name="A6XX_TEX_NEAREST" value="0"/>
3393                 <value name="A6XX_TEX_LINEAR" value="1"/>
3394                 <value name="A6XX_TEX_ANISO" value="2"/>
3395                 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3396         </enum>
3397         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3398                 <value name="A6XX_TEX_REPEAT" value="0"/>
3399                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3400                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3401                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3402                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3403         </enum>
3404         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3405                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3406                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3407                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3408                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3409                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3410         </enum>
3411         <enum name="a6xx_reduction_mode">
3412                 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3413                 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3414                 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3415         </enum>
3416
3417         <reg32 offset="0" name="0">
3418                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3419                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3420                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3421                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3422                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3423                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3424                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3425                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3426         </reg32>
3427         <reg32 offset="1" name="1">
3428                 <!-- bit 0 always set with vulkan? -->
3429                 <bitfield name="UNK0" pos="0" type="boolean"/>
3430                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3431                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3432                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3433                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3434                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3435                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3436         </reg32>
3437         <reg32 offset="2" name="2">
3438                 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3439                 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
3440                 <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
3441         </reg32>
3442         <reg32 offset="3" name="3"/>
3443 </domain>
3444
3445 <domain name="A6XX_TEX_CONST" width="32">
3446         <doc>Texture constant dwords</doc>
3447         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3448                 <value name="A6XX_TEX_X" value="0"/>
3449                 <value name="A6XX_TEX_Y" value="1"/>
3450                 <value name="A6XX_TEX_Z" value="2"/>
3451                 <value name="A6XX_TEX_W" value="3"/>
3452                 <value name="A6XX_TEX_ZERO" value="4"/>
3453                 <value name="A6XX_TEX_ONE" value="5"/>
3454         </enum>
3455         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3456                 <value name="A6XX_TEX_1D" value="0"/>
3457                 <value name="A6XX_TEX_2D" value="1"/>
3458                 <value name="A6XX_TEX_CUBE" value="2"/>
3459                 <value name="A6XX_TEX_3D" value="3"/>
3460         </enum>
3461         <reg32 offset="0" name="0">
3462                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3463                 <bitfield name="SRGB" pos="2" type="boolean"/>
3464                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3465                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3466                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3467                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3468                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3469                 <!-- overlaps with MIPLVLS -->
3470                 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
3471                 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
3472                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3473                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3474                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3475         </reg32>
3476         <reg32 offset="1" name="1">
3477                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3478                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3479         </reg32>
3480         <reg32 offset="2" name="2">
3481                 <!--
3482                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3483                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3484
3485                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3486                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3487                  -->
3488                 <bitfield name="UNK4" pos="4" type="boolean"/>
3489                 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3490                 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
3491                 <doc>Pitch in bytes (so actually stride)</doc>
3492                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3493                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3494                 <bitfield name="UNK31" pos="31" type="boolean"/>
3495         </reg32>
3496         <reg32 offset="3" name="3">
3497                 <!--
3498                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3499                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3500                 layer size at the point that it stops being reduced moving to
3501                 higher (smaller) mipmap levels
3502                  -->
3503                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3504                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3505                 <!--
3506                 by default levels with w < 16 are linear
3507                 TILE_ALL makes all levels have tiling
3508                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3509                  -->
3510                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3511                 <bitfield name="FLAG" pos="28" type="boolean"/>
3512         </reg32>
3513         <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3514              the address of the non-flag base buffer is determined automatically,
3515              and must follow the flag buffer
3516          -->
3517         <reg32 offset="4" name="4">
3518                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3519         </reg32>
3520         <reg32 offset="5" name="5">
3521                 <bitfield name="BASE_HI" low="0" high="16"/>
3522                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3523         </reg32>
3524         <reg32 offset="6" name="6">
3525                 <!-- pitch for plane 2 / plane 3 -->
3526                 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
3527         </reg32>
3528         <!-- 7/8 is plane 2 address for planar formats -->
3529         <reg32 offset="7" name="7">
3530                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3531         </reg32>
3532         <reg32 offset="8" name="8">
3533                 <bitfield name="FLAG_HI" low="0" high="16"/>
3534         </reg32>
3535         <!-- 9/10 is plane 3 address for planar formats -->
3536         <reg32 offset="9" name="9">
3537                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3538         </reg32>
3539         <reg32 offset="10" name="10">
3540                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3541                 <!-- log2 size of the first level, required for mipmapping -->
3542                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3543                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3544         </reg32>
3545         <reg32 offset="11" name="11"/>
3546         <reg32 offset="12" name="12"/>
3547         <reg32 offset="13" name="13"/>
3548         <reg32 offset="14" name="14"/>
3549         <reg32 offset="15" name="15"/>
3550 </domain>
3551
3552 <!--
3553 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3554 naming is just because I r/e'd SSBOs first.  I should probably come up
3555 with a better name.
3556 -->
3557 <domain name="A6XX_IBO" width="32">
3558         <reg32 offset="0" name="0">
3559                 <!--
3560                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3561                 used but if they are good chance position is same as TEX_CONST
3562                  -->
3563                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3564                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3565         </reg32>
3566         <reg32 offset="1" name="1">
3567                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3568                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3569         </reg32>
3570         <reg32 offset="2" name="2">
3571                 <!--
3572                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3573                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3574                  -->
3575                 <bitfield name="UNK4" pos="4" type="boolean"/>
3576                 <doc>Pitch in bytes (so actually stride)</doc>
3577                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3578                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3579                 <bitfield name="UNK31" pos="31" type="boolean"/>
3580         </reg32>
3581         <reg32 offset="3" name="3">
3582                 <!--
3583                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3584                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3585                 layer size at the point that it stops being reduced moving to
3586                 higher (smaller) mipmap levels
3587                  -->
3588                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3589                 <bitfield name="UNK27" pos="27" type="boolean"/>
3590                 <bitfield name="FLAG" pos="28" type="boolean"/>
3591         </reg32>
3592         <reg32 offset="4" name="4">
3593                 <bitfield name="BASE_LO" low="0" high="31"/>
3594         </reg32>
3595         <reg32 offset="5" name="5">
3596                 <bitfield name="BASE_HI" low="0" high="16"/>
3597                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3598         </reg32>
3599         <reg32 offset="6" name="6">
3600         </reg32>
3601         <reg32 offset="7" name="7">
3602         </reg32>
3603         <reg32 offset="8" name="8">
3604         </reg32>
3605         <reg32 offset="9" name="9">
3606                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3607         </reg32>
3608         <reg32 offset="10" name="10">
3609                 <!--
3610                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3611                 don't seem to be particularly sensible... or needed for UBWC to work
3612                  -->
3613                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3614         </reg32>
3615 </domain>
3616
3617 <domain name="A6XX_UBO" width="32">
3618         <reg32 offset="0" name="0">
3619                 <bitfield name="BASE_LO" low="0" high="31"/>
3620         </reg32>
3621         <reg32 offset="1" name="1">
3622                 <bitfield name="BASE_HI" low="0" high="16"/>
3623                 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3624         </reg32>
3625 </domain>
3626
3627 <domain name="A6XX_PDC" width="32">
3628         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3629         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3630         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3631         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3632         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3633         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3634         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3635         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3636         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3637         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3638         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3639         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3640         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3641         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3642         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3643         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3644         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3645         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3646         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3647         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3648         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3649         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3650         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3651         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3652         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3653         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3654 </domain>
3655
3656 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3657         <reg32 offset="0x0" name="MEM_0"/>
3658 </domain>
3659
3660 <domain name="A6XX_CX_DBGC" width="32">
3661         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3662                 <bitfield high="7" low="0" name="PING_INDEX"/>
3663                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3664         </reg32>
3665         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3666         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3667         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3668         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3669                 <bitfield high="5" low="0" name="TRACEEN"/>
3670                 <bitfield high="14" low="12" name="GRANU"/>
3671                 <bitfield high="31" low="28" name="SEGT"/>
3672         </reg32>
3673         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3674                 <bitfield high="27" low="24" name="ENABLE"/>
3675         </reg32>
3676         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3677         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3678         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3679         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3680         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3681         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3682         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3683         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3684         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3685                 <bitfield high="3" low="0" name="BYTEL0"/>
3686                 <bitfield high="7" low="4" name="BYTEL1"/>
3687                 <bitfield high="11" low="8" name="BYTEL2"/>
3688                 <bitfield high="15" low="12" name="BYTEL3"/>
3689                 <bitfield high="19" low="16" name="BYTEL4"/>
3690                 <bitfield high="23" low="20" name="BYTEL5"/>
3691                 <bitfield high="27" low="24" name="BYTEL6"/>
3692                 <bitfield high="31" low="28" name="BYTEL7"/>
3693         </reg32>
3694         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3695                 <bitfield high="3" low="0" name="BYTEL8"/>
3696                 <bitfield high="7" low="4" name="BYTEL9"/>
3697                 <bitfield high="11" low="8" name="BYTEL10"/>
3698                 <bitfield high="15" low="12" name="BYTEL11"/>
3699                 <bitfield high="19" low="16" name="BYTEL12"/>
3700                 <bitfield high="23" low="20" name="BYTEL13"/>
3701                 <bitfield high="27" low="24" name="BYTEL14"/>
3702                 <bitfield high="31" low="28" name="BYTEL15"/>
3703         </reg32>
3704
3705         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3706         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3707 </domain>
3708
3709 <domain name="A6XX_CX_MISC" width="32">
3710         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3711         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3712 </domain>
3713
3714 </database>