src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
  26         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  27
  28         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  29         <value value="0x10" name="FMT6_8_8_SNORM"/>
  30         <value value="0x11" name="FMT6_8_8_UINT"/>
  31         <value value="0x12" name="FMT6_8_8_SINT"/>
  32         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  33
  34         <value value="0x15" name="FMT6_16_UNORM"/>
  35         <value value="0x16" name="FMT6_16_SNORM"/>
  36         <value value="0x17" name="FMT6_16_FLOAT"/>
  37         <value value="0x18" name="FMT6_16_UINT"/>
  38         <value value="0x19" name="FMT6_16_SINT"/>
  39
  40         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  41         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  42         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  43         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  44
  45         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  46         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  47         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  48         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  49         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  50
  51         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  52
  53         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  54         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  55         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  56         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  57         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  58
  59         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  60
  61         <value value="0x43" name="FMT6_16_16_UNORM"/>
  62         <value value="0x44" name="FMT6_16_16_SNORM"/>
  63         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  64         <value value="0x46" name="FMT6_16_16_UINT"/>
  65         <value value="0x47" name="FMT6_16_16_SINT"/>
  66
  67         <value value="0x48" name="FMT6_32_UNORM"/>
  68         <value value="0x49" name="FMT6_32_SNORM"/>
  69         <value value="0x4a" name="FMT6_32_FLOAT"/>
  70         <value value="0x4b" name="FMT6_32_UINT"/>
  71         <value value="0x4c" name="FMT6_32_SINT"/>
  72         <value value="0x4d" name="FMT6_32_FIXED"/>
  73
  74         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  75         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  76         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  77         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  78         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  79
  80         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  81         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  82         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  83         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  84         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  85
  86         <value value="0x65" name="FMT6_32_32_UNORM"/>
  87         <value value="0x66" name="FMT6_32_32_SNORM"/>
  88         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  89         <value value="0x68" name="FMT6_32_32_UINT"/>
  90         <value value="0x69" name="FMT6_32_32_SINT"/>
  91         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  92
  93         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  94         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  95         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  96         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  97         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  98         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  99
 100         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 101         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 102         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 103         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 104         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 105         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 106
 107         <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/>
 108         <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/>
 109         <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/>
 110         <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/>
 111
 112         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 113
 114         <!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
 115              which has different UBWC compression from regular 8_UNORM format -->
 116         <value value="0x94" name="FMT6_8_PLANE_UNORM"/>
 117
 118         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 119
 120         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 121         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 122         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 123         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 124         <value value="0xaf" name="FMT6_ETC1"/>
 125         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 126         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 127         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 128         <value value="0xb3" name="FMT6_DXT1"/>
 129         <value value="0xb4" name="FMT6_DXT3"/>
 130         <value value="0xb5" name="FMT6_DXT5"/>
 131         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 132         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 133         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 134         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 135         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 136         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 137         <value value="0xc0" name="FMT6_BPTC"/>
 138         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 139         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 140         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 141         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 142         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 143         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 144         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 145         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 146         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 147         <value value="0xca" name="FMT6_ASTC_10x6"/>
 148         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 149         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 150         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 151         <value value="0xce" name="FMT6_ASTC_12x12"/>
 152
 153         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 154         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 155
 156         <!-- Not a hw enum, used internally in driver -->
 157         <value value="0xff" name="FMT6_NONE"/>
 158
 159 </enum>
 160
 161 <!-- probably same as a5xx -->
 162 <enum name="a6xx_polygon_mode">
 163         <value name="POLYMODE6_POINTS" value="1"/>
 164         <value name="POLYMODE6_LINES" value="2"/>
 165         <value name="POLYMODE6_TRIANGLES" value="3"/>
 166 </enum>
 167
 168 <enum name="a6xx_depth_format">
 169         <value name="DEPTH6_NONE" value="0"/>
 170         <value name="DEPTH6_16" value="1"/>
 171         <value name="DEPTH6_24_8" value="2"/>
 172         <value name="DEPTH6_32" value="4"/>
 173 </enum>
 174
 175 <bitset name="a6x_cp_protect" inline="yes">
 176         <bitfield name="BASE_ADDR" low="0" high="17"/>
 177         <bitfield name="MASK_LEN" low="18" high="30"/>
 178         <bitfield name="READ" pos="31"/>
 179 </bitset>
 180
 181 <enum name="a6xx_shader_id">
 182         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 183         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 184         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 185         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 186         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 187         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 188         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 189         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 190         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 191         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 192         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 193         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 194         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 195         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 196         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 197         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 198         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 199         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 200         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 201         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 202         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 203         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 204         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 205         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 206         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 207         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 208         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 209         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 210         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 211         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 212         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 213         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 214         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 215         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 216         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 217         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 218         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 219         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 220         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 221         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 222         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 223         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 224         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 225 </enum>
 226
 227 <enum name="a6xx_debugbus_id">
 228         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 229         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 230         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 231         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 232         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 233         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 234         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 235         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 236         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 237         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 238         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 239         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 240         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 241         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 242         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 243         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 244         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 245         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 246         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 247         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 248         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 249         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 250         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 251         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 252         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 253         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 254         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 255         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 256         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 257         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 258         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 259         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 260         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 261         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 262         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 263         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 264         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 265         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 266         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 267         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 268         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 269         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 270         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 271 </enum>
 272
 273 <enum name="a6xx_cp_perfcounter_select">
 274         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 275         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 276         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 277         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 278         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 279         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 280         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 281         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 282         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 283         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 284         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 285         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 286         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 287         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 288         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 289         <value value="15" name="PERF_CP_SQE_IDLE"/>
 290         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 291         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 292         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 293         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 294         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 295         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 296         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 297         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 298         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 299         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 300         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 301         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 302         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 303         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 304         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 305         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 306         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 307         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 308         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 309         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 310         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 311         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 312         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 313         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 314         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 315         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 316         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 317         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 318         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 319         <value value="45" name="PERF_CP_PM4_DATA"/>
 320         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 321         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 322         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 323         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 324 </enum>
 325
 326 <enum name="a6xx_rbbm_perfcounter_select">
 327         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 328         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 329         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 330         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 331         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 332         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 333         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 334         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 335         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 336         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 337         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 338         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 339         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 340         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 341 </enum>
 342
 343 <enum name="a6xx_pc_perfcounter_select">
 344         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 345         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 346         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 347         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 348         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 349         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 350         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 351         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 352         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 353         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 354         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 355         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 356         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 357         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 358         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 359         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 360         <value value="16" name="PERF_PC_INSTANCES"/>
 361         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 362         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 363         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 364         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 365         <value value="21" name="PERF_PC_IA_VERTICES"/>
 366         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 367         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 368         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 369         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 370         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 371         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 372         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 373         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 374         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 375         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 376         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 377         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 378         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 379         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 380         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 381         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 382         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 383         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 384         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 385         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 386 </enum>
 387
 388 <enum name="a6xx_vfd_perfcounter_select">
 389         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 390         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 391         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 392         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 393         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 394         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 395         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 396         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 397         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 398         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 399         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 400         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 401         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 402         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 403         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 404         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 405         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 406         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 407         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 408         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 409         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 410         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 411         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 412 </enum>
 413
 414 <enum name="a6xx_hlsq_perfcounter_select">
 415         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 416         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 417         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 418         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 419         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 420         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 421         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 422         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 423         <value value="8" name="PERF_HLSQ_QUADS"/>
 424         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 425         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 426         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 427         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 428         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 429         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 430         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 431         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 432         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 433         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 434         <value value="19" name="PERF_HLSQ_PIXELS"/>
 435         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 436 </enum>
 437
 438 <enum name="a6xx_vpc_perfcounter_select">
 439         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 440         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 441         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 442         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 443         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 444         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 445         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 446         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 447         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 448         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 449         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 450         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 451         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 452         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 453         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 454         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 455         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 456         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 457         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 458         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 459         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 460         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 461         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 462         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 463         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 464         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 465         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 466         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 467 </enum>
 468
 469 <enum name="a6xx_tse_perfcounter_select">
 470         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 471         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 472         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 473         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 474         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 475         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 476         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 477         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 478         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 479         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 480         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 481         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 482         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 483         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 484         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 485         <value value="15" name="PERF_TSE_CINVOCATION"/>
 486         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 487         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 488         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 489         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 490 </enum>
 491
 492 <enum name="a6xx_ras_perfcounter_select">
 493         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 494         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 495         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 496         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 497         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 498         <value value="5" name="PERF_RAS_8X4_TILES"/>
 499         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 500         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 501         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 502         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 503         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 504         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 505         <value value="12" name="PERF_RAS_BLOCKS"/>
 506 </enum>
 507
 508 <enum name="a6xx_uche_perfcounter_select">
 509         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 510         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 511         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 512         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 513         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 514         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 515         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 516         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 517         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 518         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 519         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 520         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 521         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 522         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 523         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 524         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 525         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 526         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 527         <value value="18" name="PERF_UCHE_EVICTS"/>
 528         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 529         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 530         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 531         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 532         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 533         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 534         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 535         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 536         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 537         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 538         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 539         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 540         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 541         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 542         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 543         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 544         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 545         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 546         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 547         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 548         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 549 </enum>
 550
 551 <enum name="a6xx_tp_perfcounter_select">
 552         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 553         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 554         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 555         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 556         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 557         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 558         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 559         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 560         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 561         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 562         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 563         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 564         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 565         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 566         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 567         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 568         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 569         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 570         <value value="18" name="PERF_TP_QUADS_1D"/>
 571         <value value="19" name="PERF_TP_QUADS_2D"/>
 572         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 573         <value value="21" name="PERF_TP_QUADS_3D"/>
 574         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 575         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 576         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 577         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 578         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 579         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 580         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 581         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 582         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 583         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 584         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 585         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 586         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 587         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 588         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 589         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 590         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 591         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 592         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 593         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 594         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 595         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 596         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 597         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 598         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 599         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 600         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 601         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 602         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 603         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 604         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 605         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 606         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 607         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 608         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 609 </enum>
 610
 611 <enum name="a6xx_sp_perfcounter_select">
 612         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 613         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 614         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 615         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 616         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 617         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 618         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 619         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 620         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 621         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 622         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 623         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 624         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 625         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 626         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 627         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 628         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 629         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 630         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 631         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 632         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 633         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 634         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 635         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 636         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 637         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 638         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 639         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 640         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 641         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 642         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 643         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 644         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 645         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 646         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 647         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 648         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 649         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 650         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 651         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 652         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 653         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 654         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 655         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 656         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 657         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 658         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 659         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 660         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 661         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 662         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 663         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 664         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 665         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 666         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 667         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 668         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 669         <value value="57" name="PERF_SP_GPR_READ"/>
 670         <value value="58" name="PERF_SP_GPR_WRITE"/>
 671         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 672         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 673         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 674         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 675         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 676         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 677         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 678         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 679         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 680         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 681         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 682         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 683         <value value="71" name="PERF_SP_WORKING_EU"/>
 684         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 685         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 686         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 687         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 688         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 689         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 690         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 691         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 692         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 693         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 694         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 695         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 696         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 697 </enum>
 698
 699 <enum name="a6xx_rb_perfcounter_select">
 700         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 701         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 702         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 703         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 704         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 705         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 706         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 707         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 708         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 709         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 710         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 711         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 712         <value value="12" name="PERF_RB_Z_READ"/>
 713         <value value="13" name="PERF_RB_Z_WRITE"/>
 714         <value value="14" name="PERF_RB_C_READ"/>
 715         <value value="15" name="PERF_RB_C_WRITE"/>
 716         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 717         <value value="17" name="PERF_RB_Z_PASS"/>
 718         <value value="18" name="PERF_RB_Z_FAIL"/>
 719         <value value="19" name="PERF_RB_S_FAIL"/>
 720         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 721         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 722         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 723         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 724         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 725         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 726         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 727         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 728         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 729         <value value="29" name="PERF_RB_3D_PIXELS"/>
 730         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 731         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 732         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 733         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 734         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 735         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 736         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 737         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 738         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 739         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 740         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 741         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 742         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 743         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 744         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 745         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 746         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 747         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 748 </enum>
 749
 750 <enum name="a6xx_vsc_perfcounter_select">
 751         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 752         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 753         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 754         <value value="3" name="PERF_VSC_EOT_NUM"/>
 755         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 756 </enum>
 757
 758 <enum name="a6xx_ccu_perfcounter_select">
 759         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 760         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 761         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 762         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 763         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 764         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 765         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 766         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 767         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 768         <value value="9" name="PERF_CCU_GMEM_READ"/>
 769         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 770         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 771         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 772         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 773         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 774         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 775         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 776         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 777         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 778         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 779         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 780         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 781         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 782         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 783         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 784         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 785         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 786         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 787         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 788 </enum>
 789
 790 <enum name="a6xx_lrz_perfcounter_select">
 791         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 792         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 793         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 794         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 795         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 796         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 797         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 798         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 799         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 800         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 801         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 802         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 803         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 804         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 805         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 806         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 807         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 808         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 809         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 810         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 811         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 812         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 813         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 814         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 815         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 816         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 817         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 818         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 819 </enum>
 820
 821 <enum name="a6xx_cmp_perfcounter_select">
 822         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 823         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 824         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 825         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 826         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 827         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 828         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 829         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 830         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 831         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 832         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 833         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 834         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 835         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 836         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 837         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 838         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 839         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 840         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 841         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 842         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 843         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 844         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 845         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 846         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 847         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 848         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 849         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 850         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 851         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 852         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 853         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 854         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 855         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 856         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 857         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 858         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 859         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 860         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 861         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 862 </enum>
 863
 864 <!--
 865 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 866 component type/size, so I think it relates to internal format used for
 867 blending?  The one exception is that 16b unorm and 32b float use the
 868 same value... maybe 16b unorm is uncommon enough that it was just easier
 869 to upconvert to 32b float internally?
 870
 871  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 872 16b unorm:   4
 873
 874 32b int:     7
 875 16b int:     6
 876  8b int:     5
 877
 878 32b float:   4
 879 16b float:   3
 880  -->
 881 <enum name="a6xx_2d_ifmt">
 882         <value value="0x10" name="R2D_UNORM8"/>
 883         <value value="0x7"  name="R2D_INT32"/>
 884         <value value="0x6"  name="R2D_INT16"/>
 885         <value value="0x5"  name="R2D_INT8"/>
 886         <value value="0x4"  name="R2D_FLOAT32"/>
 887         <value value="0x3"  name="R2D_FLOAT16"/>
 888         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 889         <value value="0x0"  name="R2D_RAW"/>
 890 </enum>
 891
 892 <enum name="a6xx_ztest_mode">
 893         <doc>Allow early z-test and early-lrz (if applicable)</doc>
 894         <value value="0x0" name="A6XX_EARLY_Z"/>
 895         <doc>Disable early z-test and early-lrz test (if applicable)</doc>
 896         <value value="0x1" name="A6XX_LATE_Z"/>
 897         <doc>
 898                 A special mode that allows early-lrz test but disables
 899                 early-z test.  Which might sound a bit funny, since
 900                 lrz-test happens before z-test.  But as long as a couple
 901                 conditions are maintained this allows using lrz-test in
 902                 cases where fragment shader has kill/discard:
 903
 904                 1) Disable lrz-write in cases where it is uncertain during
 905                    binning pass that a fragment will pass.  Ie.  if frag
 906                    shader has-kill, writes-z, or alpha/stencil test is
 907                    enabled.  (For correctness, lrz-write must be disabled
 908                    when blend is enabled.)  This is analogous to how a
 909                    z-prepass works.
 910
 911                 2) Disable lrz-write and test if a depth-test direction
 912                    reversal is detected.  Due to condition (1), the contents
 913                    of the lrz buffer are a conservative estimation of the
 914                    depth buffer during the draw pass.  Meaning that geometry
 915                    that we know for certain will not be visible will not pass
 916                    lrz-test.  But geometry which may be (or contributes to
 917                    blend) will pass the lrz-test.
 918
 919                 This allows us to keep early-lrz-test in cases where the frag
 920                 shader does not write-z (ie. we know the z-value before FS)
 921                 and does not have side-effects (image/ssbo writes, etc), but
 922                 does have kill/discard.  Which turns out to be a common
 923                 enough case that it is useful to keep early-lrz test against
 924                 the conservative lrz buffer to discard fragments that we
 925                 know will definitely not be visible.
 926         </doc>
 927         <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
 928 </enum>
 929
 930 <domain name="A6XX" width="32">
 931         <bitset name="A6XX_RBBM_INT_0_MASK" inline="no">
 932                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 933                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 934                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 935                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 936                 <bitfield name="CP_SW" pos="8"/>
 937                 <bitfield name="CP_HW_ERROR" pos="9"/>
 938                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 939                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 940                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 941                 <bitfield name="CP_IB2" pos="13"/>
 942                 <bitfield name="CP_IB1" pos="14"/>
 943                 <bitfield name="CP_RB" pos="15"/>
 944                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 945                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 946                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 947                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 948                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 949                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 950                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 951                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 952                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 953                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 954                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 955         </bitset>
 956
 957         <bitset name="A6XX_CP_INT">
 958                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 959                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 960                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 961                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 962                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 963                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 964                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 965         </bitset>
 966
 967         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 968         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 969         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 970         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 971         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 972         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 973         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 974         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 975         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 976                 <bitfield name="IFPC" pos="0" type="boolean"/>
 977         </reg32>
 978         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 979         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 980         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 981         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 982         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 983         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 984         <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
 985         <!-- all the threshold values seem to be in units of quad-dwords: -->
 986         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 987                 <doc>
 988                         b0..7 seems to contain the size of buffered by not yet processed
 989                         RB level cmdstream.. it's possible that it is a low threshold
 990                         and b8..15 is a high threshold?
 991
 992                         b16..23 identifies where IB1 data starts (and RB data ends?)
 993
 994                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 995                 </doc>
 996                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 997                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 998                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 999                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
1000         </reg32>
1001         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1002                 <doc>
1003                         low bits identify where CP_SET_DRAW_STATE stateobj
1004                         processing starts (and IB2 data ends). I'm guessing
1005                         b8 is part of this since (from downstream kgsl):
1006
1007                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
1008                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1009                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1010                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1011                                 } ...
1012                 </doc>
1013                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
1014                 <!-- total ROQ size: -->
1015                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1016         </reg32>
1017         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1018         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1019         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
1020         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1021         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1022
1023         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1024                 <reg32 offset="0x0" name="REG" type="uint"/>
1025         </array>
1026         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1027                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1028         </array>
1029
1030         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1031         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1032         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1033         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1034         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1035         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1036         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1037         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1038         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1039         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1040         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1041         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1042         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1043         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1044         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1045         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1046         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1047         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1048         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1049         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1050         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1051         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1052         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1053         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1054         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1055         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1056         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1057         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1058         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1059         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1060         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1061         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1062         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1063         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1064         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1065         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1066         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1067         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1068         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1069         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1070         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1071         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1072         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1073         <!-- SDS == CP_SET_DRAW_STATE: -->
1074         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1075         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1076         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1077         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1078         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1079         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1080         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1081         <!--
1082         There are probably similar registers for RB and SDS, teasing out SDS will
1083         take a slightly better test case..
1084          -->
1085         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1086                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1087                 <bitfield name="REM" low="16" high="31"/>
1088         </reg32>
1089         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1090                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1091                 <bitfield name="REM" low="16" high="31"/>
1092         </reg32>
1093         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1094         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1095         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1096         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1097         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1098         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1099         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1100         <reg32 offset="0x0210" name="RBBM_STATUS">
1101                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1102                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1103                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1104                 <bitfield high="20" low="20" name="VSC_BUSY" />
1105                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1106                 <bitfield high="18" low="18" name="SP_BUSY" />
1107                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1108                 <bitfield high="16" low="16" name="VPC_BUSY" />
1109                 <bitfield high="15" low="15" name="VFD_BUSY" />
1110                 <bitfield high="14" low="14" name="TESS_BUSY" />
1111                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1112                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1113                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1114                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1115                 <bitfield high="9" low="9" name="A2D_BUSY" />
1116                 <bitfield high="8" low="8" name="CCU_BUSY" />
1117                 <bitfield high="7" low="7" name="RB_BUSY" />
1118                 <bitfield high="6" low="6" name="RAS_BUSY" />
1119                 <bitfield high="5" low="5" name="TSE_BUSY" />
1120                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1121                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1122                 <bitfield high="2" low="2" name="CP_BUSY" />
1123                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1124                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1125         </reg32>
1126         <reg32 offset="0x0213" name="RBBM_STATUS3">
1127                 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1128         </reg32>
1129         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1130         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1131         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1132         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1133         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1134         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1135         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1136         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1137         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1138         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1139         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1140         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1141         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1142         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1143         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1144         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1145         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1146         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1147         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1148         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1149         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1150         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1151         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1152         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1153         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1154         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1155         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1156         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1157         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1158         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1159         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1160         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1161         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1162         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1163         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1164         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1165         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1166         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1167         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1168         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1169         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1170         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1171         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1172         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1173         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1174         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1175         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1176         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1177         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1178         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1179         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1180         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1181         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1182         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1183         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1184         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1185         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1186         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1187         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1188         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1189         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1190         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1191         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1192         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1193         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1194         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1195         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1196         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1197         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1198         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1199         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1200         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1201         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1202         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1203         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1204         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1205         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1206         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1207         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1208         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1209         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1210         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1211         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1212         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1213         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1214         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1215         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1216         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1217         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1218         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1219         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1220         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1221         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1222         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1223         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1224         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1225         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1226         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1227         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1228         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1229         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1230         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1231         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1232         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1233         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1234         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1235         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1236         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1237         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1238         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1239         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1240         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1241         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1242         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1243         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1244         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1245         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1246         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1247         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1248         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1249         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1250         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1251         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1252         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1253         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1254         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1255         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1256         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1257         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1258         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1259         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1260         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1261         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1262         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1263         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1264         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1265         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1266         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1267         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1268         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1269         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1270         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1271         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1272         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1273         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1274         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1275         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1276         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1277         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1278         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1279         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1280         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1281         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1282         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1283         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1284         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1285         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1286         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1287         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1288         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1289         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1290         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1291         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1292         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1293         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1294         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1295         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1296         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1297         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1298         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1299         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1300         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1301         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1302         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1303         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1304         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1305         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1306         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1307         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1308         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1309         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1310         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1311         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1312         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1313         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1314         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1315         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1316         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1317         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1318         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1319         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1320         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1321         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1322         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1323         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1324         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1325         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1326         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1327         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1328         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1329         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1330         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1331         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1332         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1333         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1334         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1335         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1336         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1337         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1338         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1339         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1340         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1341         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1342         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1343         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1344         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1345         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1346         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1347         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1348         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1349         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1350         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1351         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1352         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1353         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1354         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1355         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1356         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1357         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1358         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1359         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1360         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1361         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1362         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1363         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1364         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1365         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1366         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1367         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1368         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1369         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1370         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1371         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1372         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1373         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1374         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1375         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1376         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1377         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1378         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1379         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1380         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1381         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1382         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1383         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1384         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1385         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1386         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1387         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1388         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1389         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1390         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1391         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1392         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1393
1394         <!---
1395             This block of registers aren't tied to perf counters. They
1396             count various geometry stats, for example number of
1397             vertices in, number of primnitives assembled etc.
1398         -->
1399
1400         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1401         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1402         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1403         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1404         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1405         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1406         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1407         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1408         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1409         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1410         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1411         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1412         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1413         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1414         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1415         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1416         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1417         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1418         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1419         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1420         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1421         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1422
1423         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1424         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1425         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1426         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1427         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1428         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1429         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1430         <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1431         <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1432                 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
1433         </reg32>
1434         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1435         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1436         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1437         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1438         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1439         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1440         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1441         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1442         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1443         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1444         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1445         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1446         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1447         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1448         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1449         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1450         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1451         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1452         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1453         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1454         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1455         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1456         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1457         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1458         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1459         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1460         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1461         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1462         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1463         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1464         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1465         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1466         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1467         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1468         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1469         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1470         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1471         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1472         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1473         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1474         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1475         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1476         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1477         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1478         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1479         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1480         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1481         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1482         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1483         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1484         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1485         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1486         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1487         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1488         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1489         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1490         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1491         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1492         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1493         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1494         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1495         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1496         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1497         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1498         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1499         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1500         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1501         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1502         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1503         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1504         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1505         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1506         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1507         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1508         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1509         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1510         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1511         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1512         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1513         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1514         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1515         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1516         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1517         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1518         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1519         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1520         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1521         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1522         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1523         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1524         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1525         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1526         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1527         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1528         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1529         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1530         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1531         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1532         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1533         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1534         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1535         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1536         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1537         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1538         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1539         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1540         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1541         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1542         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1543         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1544         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1545         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1546         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1547         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1548         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1549         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1550         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1551         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1552                 <bitfield high="7" low="0" name="PING_INDEX"/>
1553                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1554         </reg32>
1555         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1556                 <bitfield high="5" low="0" name="TRACEEN"/>
1557                 <bitfield high="14" low="12" name="GRANU"/>
1558                 <bitfield high="31" low="28" name="SEGT"/>
1559         </reg32>
1560         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1561                 <bitfield high="27" low="24" name="ENABLE"/>
1562         </reg32>
1563         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1564         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1565         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1566         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1567         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1568         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1569         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1570         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1571         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1572                 <bitfield high="3" low="0" name="BYTEL0"/>
1573                 <bitfield high="7" low="4" name="BYTEL1"/>
1574                 <bitfield high="11" low="8" name="BYTEL2"/>
1575                 <bitfield high="15" low="12" name="BYTEL3"/>
1576                 <bitfield high="19" low="16" name="BYTEL4"/>
1577                 <bitfield high="23" low="20" name="BYTEL5"/>
1578                 <bitfield high="27" low="24" name="BYTEL6"/>
1579                 <bitfield high="31" low="28" name="BYTEL7"/>
1580         </reg32>
1581         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1582                 <bitfield high="3" low="0" name="BYTEL8"/>
1583                 <bitfield high="7" low="4" name="BYTEL9"/>
1584                 <bitfield high="11" low="8" name="BYTEL10"/>
1585                 <bitfield high="15" low="12" name="BYTEL11"/>
1586                 <bitfield high="19" low="16" name="BYTEL12"/>
1587                 <bitfield high="23" low="20" name="BYTEL13"/>
1588                 <bitfield high="27" low="24" name="BYTEL14"/>
1589                 <bitfield high="31" low="28" name="BYTEL15"/>
1590         </reg32>
1591         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1592         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1593         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1594         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1595         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1596         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1597         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1598         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1599         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1600         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1601         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1602         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1603         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1604         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1605         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1606         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1607         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1608         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1609         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1610         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1611         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1612         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1613         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1614         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1615         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1616         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1617         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1618         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1619         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1620         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1621         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1622         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1623         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1624         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1625         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1626         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1627         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1628                 <bitfield high="7" low="0" name="PERFSEL"/>
1629         </reg32>
1630         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1631         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1632         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1633         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1634         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1635         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1636         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1637         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1638         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1639         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1640         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1641         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1642         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1643         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1644         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1645         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1646         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1647         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1648         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1649         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1650         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1651         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1652         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1653         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1654         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1655         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1656         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1657         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1658         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1659         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1660         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1661         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1662         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1663         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1664         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1665         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1666         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1667         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1668         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1669         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1670         <reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
1671         <reg32 offset="0xB609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1"/>
1672         <reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
1673         <reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
1674         <reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
1675         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1676         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1677         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1678         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1679         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1680         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1681         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1682         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1683         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1684         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1685         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1686         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1687         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1688         <reg32 offset="0x3001" name="VBIF_CLKON">
1689                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1690         </reg32>
1691         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1692         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1693         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1694         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1695         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1696         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1697                 <bitfield low="0" high="3" name="DATA_SEL"/>
1698         </reg32>
1699         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1700         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1701                 <bitfield low="0" high="8" name="DATA_SEL"/>
1702         </reg32>
1703         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1704         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1705         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1706         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1707         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1708         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1709         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1710         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1711         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1712         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1713         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1714         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1715         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1716         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1717         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1718         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1719         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1720         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1721         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1722         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1723         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1724         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1725
1726         <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1727         <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1728         <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1729         <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1730         <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1731         <reg32 offset="0x3c45" name="GBIF_HALT"/>
1732         <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1733         <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1734         <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1735         <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1736         <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1737         <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1738         <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1739         <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1740         <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1741         <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1742         <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1743         <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1744         <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1745         <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1746         <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1747         <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1748         <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1749         <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1750
1751         <!-- move/rename these.. -->
1752
1753         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1754         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1755
1756         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1757                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1758                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1759         </reg32>
1760         <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1761         <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1762         <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1763         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1764                 <bitfield name="NX" low="1" high="10" type="uint"/>
1765                 <bitfield name="NY" low="11" high="20" type="uint"/>
1766         </reg32>
1767         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1768                 <reg32 offset="0x0" name="REG">
1769                         <doc>
1770                                 Configures the mapping between VSC_PIPE buffer and
1771                                 bin, X/Y specify the bin index in the horiz/vert
1772                                 direction (0,0 is upper left, 0,1 is leftmost bin
1773                                 on second row, and so on).  W/H specify the number
1774                                 of bins assigned to this VSC_PIPE in the horiz/vert
1775                                 dimension.
1776                         </doc>
1777                         <bitfield name="X" low="0" high="9" type="uint"/>
1778                         <bitfield name="Y" low="10" high="19" type="uint"/>
1779                         <bitfield name="W" low="20" high="25" type="uint"/>
1780                         <bitfield name="H" low="26" high="31" type="uint"/>
1781                 </reg32>
1782         </array>
1783         <!--
1784         HW binning primitive & draw streams, which enable draws and primitives
1785         within a draw to be skipped in the main tile pass.  See:
1786         https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1787
1788         Compared to a5xx and earlier, we just program the address of the first
1789         stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1790
1791         LIMIT is set to PITCH - 64, to make room for a bit of overflow
1792          -->
1793         <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1794         <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1795         <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1796         <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1797         <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1798         <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1799         <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1800         <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1801         <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1802         <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1803
1804         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1805                 <doc>
1806                         Seems to be a bitmap of which tiles mapped to the VSC
1807                         pipe contain geometry.
1808
1809                         I suppose we can connect a maximum of 32 tiles to a
1810                         single VSC pipe.
1811                 </doc>
1812                 <reg32 offset="0x0" name="REG"/>
1813         </array>
1814
1815         <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1816                 <doc>
1817                         Has the size of data written to corresponding VSC_PRIM_STRM
1818                         buffer.
1819                 </doc>
1820                 <reg32 offset="0x0" name="REG"/>
1821         </array>
1822
1823         <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1824                 <doc>
1825                         Has the size of data written to corresponding VSC pipe, ie.
1826                         same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1827                 </doc>
1828                 <reg32 offset="0x0" name="REG"/>
1829         </array>
1830
1831         <!-- always 0x03200000 ? -->
1832         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1833
1834         <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1835         <bitset name="a6xx_reg_xy" inline="yes">
1836                 <bitfield name="X" low="0" high="13" type="uint"/>
1837                 <bitfield name="Y" low="16" high="29" type="uint"/>
1838         </bitset>
1839
1840         <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1841                 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1842                 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1843                 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1844                 <!-- set with depthClampEnable, not clear what it does -->
1845                 <bitfield name="UNK5" pos="5" type="boolean"/>
1846                 <!-- controls near z clip behavior (set for vulkan) -->
1847                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1848                 <!-- guess based on a3xx and meaning of bits 8 and 9
1849                      if the guess is right then this is related to point sprite clipping -->
1850                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1851                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1852                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1853         </reg32>
1854
1855         <bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
1856                 <bitfield name="CLIP_MASK" low="0" high="7"/>
1857                 <bitfield name="CULL_MASK" low="8" high="15"/>
1858         </bitset>
1859         <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1860         <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1861         <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1862         <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
1863
1864         <reg32 offset="0x8005" name="GRAS_CNTL">
1865                 <!-- see also RB_RENDER_CONTROL0 -->
1866                 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1867                 <!-- b1 set for interpolateAtCentroid() -->
1868                 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1869                 <!-- b2 set instead of b0 when running in per-sample mode -->
1870                 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1871                 <!--
1872                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1873                 mode, and frag_face
1874                  -->
1875                 <bitfield name="SIZE" pos="3" type="boolean"/>
1876                 <bitfield name="UNK4" pos="4" type="boolean"/>
1877                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1878                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1879                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1880         </reg32>
1881         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1882                 <bitfield name="HORZ" low="0" high="8" type="uint"/>
1883                 <bitfield name="VERT" low="10" high="18" type="uint"/>
1884         </reg32>
1885         <!-- 0x8006-0x800f invalid -->
1886         <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
1887                 <reg32 offset="0" name="XOFFSET" type="float"/>
1888                 <reg32 offset="1" name="XSCALE" type="float"/>
1889                 <reg32 offset="2" name="YOFFSET" type="float"/>
1890                 <reg32 offset="3" name="YSCALE" type="float"/>
1891                 <reg32 offset="4" name="ZOFFSET" type="float"/>
1892                 <reg32 offset="5" name="ZSCALE" type="float"/>
1893         </array>
1894         <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
1895                 <reg32 offset="0" name="MIN" type="float"/>
1896                 <reg32 offset="1" name="MAX" type="float"/>
1897         </array>
1898
1899         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1900                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1901                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1902                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1903                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1904                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1905                 <bitfield name="UNK12" pos="12"/>
1906                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1907                 <bitfield name="UNK15" low="15" high="22"/>
1908         </reg32>
1909         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1910                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1911                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1912         </reg32>
1913         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
1914         <!-- 0x8093 invalid -->
1915         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1916                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1917         </reg32>
1918         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1919         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1920         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1921         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1922         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1923                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1924                 <bitfield name="UNK3" pos="3"/>
1925         </reg32>
1926
1927         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
1928         <reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
1929
1930         <bitset name="a6xx_gras_layer_cntl" inline="yes">
1931                 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
1932                 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
1933         </bitset>
1934         <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1935         <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1936         <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1937         <!-- 0x809e/0x809f invalid -->
1938         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
1939         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1940                 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1941                 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1942                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1943                 <bitfield name="UNK19" pos="19"/>
1944                 <bitfield name="UNK20" pos="20"/>
1945                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1946                 <bitfield name="UNK22" low="22" high="27"/>
1947         </reg32>
1948
1949         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1950                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1951                 <bitfield name="UNK2" pos="2"/>
1952                 <bitfield name="UNK3" pos="3"/>
1953         </reg32>
1954         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1955                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1956                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1957         </reg32>
1958
1959         <bitset name="a6xx_sample_config" inline="yes">
1960                 <bitfield name="UNK0" pos="0"/>
1961                 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1962         </bitset>
1963
1964         <bitset name="a6xx_sample_locations" inline="yes">
1965                 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1966                 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1967                 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1968                 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1969                 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1970                 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1971                 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1972                 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1973         </bitset>
1974
1975         <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1976         <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1977         <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1978         <!-- 0x80a7-0x80ae invalid -->
1979         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
1980
1981         <bitset name="a6xx_scissor_xy" inline="yes">
1982                 <bitfield name="X" low="0" high="15" type="uint"/>
1983                 <bitfield name="Y" low="16" high="31" type="uint"/>
1984         </bitset>
1985         <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
1986                 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1987                 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1988         </array>
1989         <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
1990                 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1991                 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1992         </array>
1993
1994         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
1995         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
1996         <!-- 0x80f2-0x80ff invalid -->
1997
1998         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1999                 <!--
2000                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
2001                 look when we get around to enabling lrz
2002                  -->
2003                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2004                 <doc>LRZ write also disabled for blend/etc.</doc>
2005                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
2006                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2007                 <bitfield name="GREATER" pos="2" type="boolean"/>
2008                 <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
2009                 <!-- set when depth-test + depth-write enabled -->
2010                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
2011                 <bitfield name="UNK5" low="5" high="9"/>
2012         </reg32>
2013         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
2014         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
2015                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2016         </reg32>
2017         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
2018         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
2019         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
2020         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
2021                 <!-- TODO: fix the shr fields -->
2022                 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
2023                 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
2024         </reg32>
2025
2026         <!--
2027         The LRZ "fast clear" buffer is initialized to zero's by blob, and
2028         read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears
2029         to store 1b/block.  It appears that '0' means block has original
2030         depth clear value, and '1' means that the corresponding block in
2031         LRZ has been modified.  Ignoring alignment/padding, the size is
2032         given by the formula:
2033
2034                 // calculate LRZ size from depth size:
2035                 if (nr_samples == 4) {
2036                         width *= 2;
2037                         height *= 2;
2038                 } else if (nr_samples == 2) {
2039                         height *= 2;
2040                 }
2041
2042                 lrz_width = div_round_up(width, 8);
2043                 lrz_heigh = div_round_up(height, 8);
2044
2045                 // calculate # of blocks:
2046                 nblocksx = div_round_up(lrz_width, 16);
2047                 nblocksy = div_round_up(lrz_height, 4);
2048
2049                 // fast-clear buffer is 1bit/block:
2050                 fc_sz = div_round_up(nblocksx * nblocksy, 8);
2051
2052         In practice the blob seems to switch off FC_ENABLE once the size
2053         increases beyond 1 page.  Not sure if that is an actual limit or
2054         not.
2055          -->
2056         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
2057         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
2058         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
2059         <!-- 0x8108 invalid -->
2060         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
2061                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2062         </reg32>
2063         <reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
2064                 <bitfield name="UNK0" low="0" high="10" type="uint"/>
2065                 <bitfield name="UNK16" low="16" high="26" type="uint"/>
2066                 <bitfield name="UNK28" low="28" high="31" type="uint"/>
2067         </reg32>
2068
2069         <!-- 0x810b-0x810f invalid -->
2070
2071         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
2072
2073         <!-- 0x8111-0x83ff invalid -->
2074
2075         <enum name="a6xx_rotation">
2076                 <value value="0x0" name="ROTATE_0"/>
2077                 <value value="0x1" name="ROTATE_90"/>
2078                 <value value="0x2" name="ROTATE_180"/>
2079                 <value value="0x3" name="ROTATE_270"/>
2080                 <value value="0x4" name="ROTATE_HFLIP"/>
2081                 <value value="0x5" name="ROTATE_VFLIP"/>
2082         </enum>
2083
2084         <bitset name="a6xx_2d_blit_cntl" inline="yes">
2085                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2086                 <bitfield name="UNK3" low="3" high="6"/>
2087                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2088                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2089                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2090                 <bitfield name="UNK17" low="17" high="18"/>
2091                 <!-- required when blitting D24S8/D24X8 -->
2092                 <bitfield name="D24S8" pos="19" type="boolean"/>
2093                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2094                 <bitfield name="MASK" low="20" high="23"/>
2095                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2096                 <bitfield name="UNK29" pos="29"/>
2097         </bitset>
2098
2099         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2100         <!-- note: the low 8 bits for src coords are valid, probably fixed point
2101              it would be a bit weird though, since we subtract 1 from BR coords
2102              apparently signed, gallium driver uses negative coords and it works?
2103          -->
2104         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
2105         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
2106         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
2107         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
2108         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
2109         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
2110         <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
2111         <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
2112         <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
2113         <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
2114         <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
2115         <!-- 0x840c-0x85ff invalid -->
2116
2117         <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
2118         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
2119         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="boolean"/>
2120         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
2121         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
2122         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
2123         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
2124         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
2125         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
2126         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
2127         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
2128         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
2129         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
2130         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
2131         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
2132
2133         <!-- note 0x8620-0x87ff are not all invalid
2134         (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
2135         -->
2136
2137         <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
2138         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2139                 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2140                 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2141                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2142                 <bitfield name="UNK19" pos="19"/>
2143                 <bitfield name="UNK20" pos="20"/>
2144                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2145                 <bitfield name="UNK22" low="22" high="26"/>
2146         </reg32>
2147         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2148                 <bitfield name="UNK3" pos="3" type="boolean"/>
2149                 <!-- always set: ?? -->
2150                 <bitfield name="UNK4" pos="4" type="boolean"/>
2151                 <bitfield name="UNK5" low="5" high="6"/>
2152                 <!-- set during binning pass: -->
2153                 <bitfield name="BINNING" pos="7" type="boolean"/>
2154                 <bitfield name="UNK8" low="8" high="12"/>
2155                 <!-- bit seems to be set whenever depth buffer enabled: -->
2156                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2157                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2158                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2159         </reg32>
2160         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2161                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2162                 <bitfield name="UNK2" pos="2"/>
2163                 <bitfield name="UNK3" pos="3"/>
2164         </reg32>
2165         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2166                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2167                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2168         </reg32>
2169
2170         <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2171         <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2172         <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2173         <!-- 0x8807-0x8808 invalid -->
2174         <!--
2175         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2176         name comes from kernel and is probably right)
2177          -->
2178         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2179                 <!-- see also GRAS_CNTL -->
2180                 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
2181                 <!-- b1 set for interpolateAtCentroid() -->
2182                 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
2183                 <!-- b2 set instead of b0 when running in per-sample mode -->
2184                 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
2185                 <!--
2186                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2187                 mode, and frag_face
2188                  -->
2189                 <bitfield name="SIZE" pos="3" type="boolean"/>
2190                 <bitfield name="UNK4" pos="4" type="boolean"/>
2191                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2192                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2193                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2194                 <bitfield name="UNK10" pos="10" type="boolean"/>
2195         </reg32>
2196         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2197                 <!-- enable bits for various FS sysvalue regs: -->
2198                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2199                 <bitfield name="UNK1" pos="1" type="boolean"/>
2200                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2201                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2202                 <!-- b4 and b5 set in per-sample mode: -->
2203                 <bitfield name="UNK4" pos="4" type="boolean"/>
2204                 <bitfield name="UNK5" pos="5" type="boolean"/>
2205                 <bitfield name="SIZE" pos="6" type="boolean"/>
2206                 <bitfield name="UNK7" pos="7" type="boolean"/>
2207                 <bitfield name="UNK8" pos="8" type="boolean"/>
2208         </reg32>
2209
2210         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2211                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2212                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2213                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2214                 <bitfield name="UNK3" pos="3" type="boolean"/>
2215         </reg32>
2216         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2217                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2218         </reg32>
2219         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2220                 <bitfield name="RT0" low="0" high="3"/>
2221                 <bitfield name="RT1" low="4" high="7"/>
2222                 <bitfield name="RT2" low="8" high="11"/>
2223                 <bitfield name="RT3" low="12" high="15"/>
2224                 <bitfield name="RT4" low="16" high="19"/>
2225                 <bitfield name="RT5" low="20" high="23"/>
2226                 <bitfield name="RT6" low="24" high="27"/>
2227                 <bitfield name="RT7" low="28" high="31"/>
2228         </reg32>
2229         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2230                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2231                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2232                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2233                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2234                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2235                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2236                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2237                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2238         </reg32>
2239         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2240                 <!-- Same as SP_SRGB_CNTL -->
2241                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2242                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2243                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2244                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2245                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2246                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2247                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2248                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2249         </reg32>
2250
2251         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2252                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2253         </reg32>
2254         <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
2255         <!-- 0x8812-0x8817 invalid -->
2256         <!-- always 0x0 ? -->
2257         <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
2258         <!-- 0x8819-0x881e all 32 bits -->
2259         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2260         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2261         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2262         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2263         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2264         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2265         <!-- 0x881f invalid -->
2266         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2267                 <reg32 offset="0x0" name="CONTROL">
2268                         <bitfield name="BLEND" pos="0" type="boolean"/>
2269                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2270                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2271                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2272                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2273                 </reg32>
2274                 <reg32 offset="0x1" name="BLEND_CONTROL">
2275                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2276                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2277                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2278                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2279                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2280                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2281                 </reg32>
2282                 <reg32 offset="0x2" name="BUF_INFO">
2283                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2284                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2285                         <bitfield name="UNK10" pos="10"/>
2286                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2287                 </reg32>
2288                 <!--
2289                 at least in gmem, things seem to be aligned to pitch of 64..
2290                 maybe an artifact of tiled format used in gmem?
2291                  -->
2292                 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
2293                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
2294                 <!--
2295                 Compared to a5xx and before, we configure both a GMEM base and
2296                 external base.  Not sure if this is to facilitate GMEM save/
2297                 restore for context switch, or just to simplify state setup to
2298                 not have to care about GMEM vs BYPASS mode.
2299                  -->
2300                 <reg32 offset="0x5" name="BASE_LO"/>
2301                 <reg32 offset="0x6" name="BASE_HI"/>
2302
2303                 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2304                 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
2305
2306                 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
2307         </array>
2308
2309         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2310         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2311         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2312         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2313         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2314                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2315                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2316                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2317         </reg32>
2318         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2319                 <!-- per-mrt enable bit -->
2320                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2321                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2322                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2323                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2324                 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2325                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2326         </reg32>
2327         <!-- 0x8866-0x886f invalid -->
2328         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2329                 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2330         </reg32>
2331
2332         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2333                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2334                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2335                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2336                 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2337                 <doc>
2338                 Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2339                 also set when Z_BOUNDS_ENABLE is set
2340                 </doc>
2341                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2342                 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2343         </reg32>
2344         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2345         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2346                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2347                 <bitfield name="UNK3" low="3" high="4"/>
2348         </reg32>
2349         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
2350         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
2351         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2352         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2353         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
2354         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2355
2356         <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2357         <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2358         <!-- 0x887a-0x887f invalid -->
2359         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2360                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2361                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2362                 <!--
2363                         set for stencil operations that require read from stencil
2364                         buffer, but not for example for stencil clear (which does
2365                         not require read).. so guessing this is analogous to
2366                         READ_DEST_ENABLE for color buffer..
2367                  -->
2368                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2369                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2370                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2371                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2372                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2373                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2374                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2375                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2376                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2377         </reg32>
2378         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2379                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2380                 <bitfield name="UNK1" pos="1" type="boolean"/>
2381         </reg32>
2382         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
2383         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
2384         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2385         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2386         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
2387         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2388         <reg32 offset="0x8887" name="RB_STENCILREF">
2389                 <bitfield name="REF" low="0" high="7"/>
2390                 <bitfield name="BFREF" low="8" high="15"/>
2391         </reg32>
2392         <reg32 offset="0x8888" name="RB_STENCILMASK">
2393                 <bitfield name="MASK" low="0" high="7"/>
2394                 <bitfield name="BFMASK" low="8" high="15"/>
2395         </reg32>
2396         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2397                 <bitfield name="WRMASK" low="0" high="7"/>
2398                 <bitfield name="BFWRMASK" low="8" high="15"/>
2399         </reg32>
2400         <!-- 0x888a-0x888f invalid -->
2401         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
2402         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2403                 <bitfield name="UNK0" pos="0" type="boolean"/>
2404                 <bitfield name="COPY" pos="1" type="boolean"/>
2405         </reg32>
2406         <!-- 0x8892-0x8897 invalid -->
2407         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2408                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2409         </reg32>
2410         <!-- 0x8899-0x88bf invalid -->
2411         <!-- clamps depth value for depth test/write -->
2412         <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2413         <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2414         <!-- 0x88c2-0x88cf invalid-->
2415         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
2416                 <bitfield name="UNK0" low="0" high="12"/>
2417                 <bitfield name="UNK16" low="16" high="26"/>
2418         </reg32>
2419         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
2420         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
2421         <!-- weird to duplicate other regs from same block?? -->
2422         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
2423                 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2424                 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2425         </reg32>
2426         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
2427         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2428                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2429         </reg32>
2430         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
2431         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2432         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2433                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2434                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2435                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2436                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2437                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2438                 <bitfield name="UNK15" pos="15" type="boolean"/>
2439         </reg32>
2440         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
2441         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2442         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2443         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2444         <!-- array-pitch is size of layer -->
2445         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
2446         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
2447         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2448         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2449         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2450                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2451                 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2452         </reg32>
2453
2454         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2455         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2456         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2457         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2458
2459         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2460         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2461                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2462                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2463                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2464                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2465                 <doc>
2466                         For clearing depth/stencil
2467                                 1 - depth
2468                                 2 - stencil
2469                                 3 - depth+stencil
2470                         For clearing color buffer:
2471                                 then probably a component mask, I always see 0xf
2472                 </doc>
2473                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2474                 <bitfield name="UNK8" low="8" high="9"/>
2475                 <bitfield name="UNK12" low="12" high="15"/>
2476         </reg32>
2477         <!-- 0x88e4-0x88ef invalid -->
2478         <!-- always 0x0 ? -->
2479         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
2480         <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2481         <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2482         <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2483                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2484                 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
2485         </reg32>
2486         <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2487         <!-- 0x88f5-0x88ff invalid -->
2488         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2489         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2490         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2491         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2492                 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
2493                 <!-- TODO: actually part of array pitch -->
2494                 <bitfield name="UNK8" low="8" high="10"/>
2495                 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2496         </reg32>
2497         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2498                 <reg32 offset="0" name="ADDR_LO"/>
2499                 <reg32 offset="1" name="ADDR_HI"/>
2500                 <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2501                 <reg32 offset="2" name="PITCH">
2502                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2503                         <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
2504                 </reg32>
2505         </array>
2506         <!-- 0x891b-0x8926 invalid -->
2507         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2508         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2509         <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
2510         <!-- 0x8929-0x89ff invalid -->
2511
2512         <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2513
2514         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2515         <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
2516
2517         <bitset name="a6xx_2d_surf_info" inline="yes">
2518                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2519                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2520                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2521                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2522                 <bitfield name="SRGB" pos="13" type="boolean"/>
2523                 <!-- the rest is only for src -->
2524                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2525                 <bitfield name="FILTER" pos="16" type="boolean"/>
2526                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2527                 <bitfield name="UNK20" pos="20" type="boolean"/>
2528                 <bitfield name="UNK22" pos="22" type="boolean"/>
2529         </bitset>
2530
2531         <!-- 0x8c02-0x8c16 invalid -->
2532         <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2533         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2534         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2535         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2536         <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
2537         <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2538         <!-- this is a guess but seems likely (for NV12/IYUV): -->
2539         <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/>
2540         <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
2541         <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
2542
2543         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2544         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2545         <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
2546         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
2547         <!-- this is a guess but seems likely (for NV12 with UBWC): -->
2548         <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/>
2549         <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/>
2550
2551         <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2552         <!-- unlike a5xx, these are per channel values rather than packed -->
2553         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2554         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2555         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2556         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2557         <!-- 0x8c34-0x8dff invalid -->
2558
2559         <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2560         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2561         <!-- 0x8e00-0x8e03 invalid -->
2562         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2563         <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="boolean"/>
2564         <!-- 0x8e06 invalid -->
2565         <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2566                 <!-- offset into GMEM for something.
2567                         important for sysmem path
2568                         BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2569                         blob values for GMEM path (note: close to GMEM size):
2570                         a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
2571                         SYSMEM path values:
2572                         a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
2573                         TODO: valid mask 0xfffffc1f
2574                 -->
2575                 <bitfield name="OFFSET" low="23" high="31" shr="12" type="hex"/>
2576                 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2577                 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2578         </reg32>
2579         <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
2580                 <bitfield name="MODE" pos="0" type="boolean"/>
2581                 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
2582                 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2583                 <bitfield name="AMSBC" pos="4" type="boolean"/>
2584                 <bitfield name="UPPER_BIT" pos="10" type="uint"/>
2585                 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
2586                 <bitfield name="UNK12" low="12" high="13"/>
2587         </reg32>
2588         <!-- 0x8e09-0x8e0f invalid -->
2589         <reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL_0"/>
2590         <reg32 offset="0x8e11" name="RB_PERFCTR_RB_SEL_1"/>
2591         <reg32 offset="0x8e12" name="RB_PERFCTR_RB_SEL_2"/>
2592         <reg32 offset="0x8e13" name="RB_PERFCTR_RB_SEL_3"/>
2593         <reg32 offset="0x8e14" name="RB_PERFCTR_RB_SEL_4"/>
2594         <reg32 offset="0x8e15" name="RB_PERFCTR_RB_SEL_5"/>
2595         <reg32 offset="0x8e16" name="RB_PERFCTR_RB_SEL_6"/>
2596         <reg32 offset="0x8e17" name="RB_PERFCTR_RB_SEL_7"/>
2597         <reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL_0"/>
2598         <reg32 offset="0x8e19" name="RB_PERFCTR_CCU_SEL_1"/>
2599         <reg32 offset="0x8e1a" name="RB_PERFCTR_CCU_SEL_2"/>
2600         <reg32 offset="0x8e1b" name="RB_PERFCTR_CCU_SEL_3"/>
2601         <reg32 offset="0x8e1c" name="RB_PERFCTR_CCU_SEL_4"/>
2602         <!-- 0x8e1d-0x8e1f invalid -->
2603         <!-- 0x8e20-0x8e25 more perfcntr sel? -->
2604         <!-- 0x8e26-0x8e27 invalid -->
2605         <reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
2606         <!-- 0x8e29-0x8e2b invalid -->
2607         <reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL_0"/>
2608         <reg32 offset="0x8e2d" name="RB_PERFCTR_CMP_SEL_1"/>
2609         <reg32 offset="0x8e2e" name="RB_PERFCTR_CMP_SEL_2"/>
2610         <reg32 offset="0x8e2f" name="RB_PERFCTR_CMP_SEL_3"/>
2611         <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2612         <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
2613         <!-- 0x8e3e-0x8e4f invalid -->
2614         <!-- GMEM save/restore for preemption: -->
2615         <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
2616         <!-- address for GMEM save/restore? -->
2617         <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
2618         <!-- 0x8e53-0x8e7f invalid -->
2619         <!-- 0x8e80-0x8e83 are valid -->
2620         <!-- 0x8e84-0x90ff invalid -->
2621
2622         <!-- 0x9000-0x90ff invalid -->
2623
2624         <!-- something to do with geometry shader: -->
2625         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100" low="0" high="7"/>
2626
2627         <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
2628                 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
2629                 <!-- there can be up to 8 total clip/cull distance outputs,
2630                      but apparenly VPC can only deal with vec4, so when there are
2631                      more than 4 outputs a second location needs to be programmed
2632                 -->
2633                 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
2634                 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
2635         </bitset>
2636         <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2637         <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2638         <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2639
2640         <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
2641                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2642                 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
2643         </bitset>
2644
2645         <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2646         <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2647         <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2648
2649         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" pos="2"/>
2650         <reg32 offset="0x9108" name="VPC_POLYGON_MODE">
2651                 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2652         </reg32>
2653         <!-- 0x9109-0x91ff invalid -->
2654         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2655                 <reg32 offset="0x0" name="MODE"/>
2656         </array>
2657         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2658                 <reg32 offset="0x0" name="MODE"/>
2659         </array>
2660
2661         <!-- always 0x0 -->
2662         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/>
2663         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/>
2664
2665         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2666                 <!-- one bit per varying component: -->
2667                 <reg32 offset="0" name="DISABLE"/>
2668         </array>
2669
2670         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2671                 <bitfield name="UNK0" low="0" high="7"/>
2672                 <!-- always 0x10000 when SO enabled.. -->
2673                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2674         </reg32>
2675         <!-- special register, write multiple times to load SO program (not readable) -->
2676         <reg32 offset="0x9217" name="VPC_SO_PROG">
2677                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2678                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2679                 <bitfield name="A_EN" pos="11" type="boolean"/>
2680                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2681                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2682                 <bitfield name="B_EN" pos="23" type="boolean"/>
2683         </reg32>
2684
2685         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2686         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2687         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
2688
2689         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2690                 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
2691                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2692                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2693                 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
2694                 <reg32 offset="3" name="NCOMP" low="0" high="9"/>  <!-- component count -->
2695                 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
2696                 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
2697                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2698                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2699         </array>
2700
2701         <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
2702                 <bitfield name="INVERT" pos="0" type="boolean"/>
2703         </reg32>
2704         <!-- 0x9237-0x92ff invalid -->
2705         <!-- always 0x0 ? -->
2706         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/>
2707
2708         <bitset name="a6xx_vpc_xs_pack" inline="yes">
2709                 <doc>
2710                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2711                         plus # of transform-feedback (streamout) varyings if using the
2712                         hw streamout (rather than stg instructions in shader)
2713                 </doc>
2714                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2715                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2716                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2717                 <bitfield name="UNK24" low="24" high="27"/>
2718         </bitset>
2719         <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
2720         <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
2721         <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/>
2722
2723         <reg32 offset="0x9304" name="VPC_CNTL_0">
2724                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2725                 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2726                 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2727                 <bitfield name="VARYING" pos="16" type="boolean"/>
2728                 <bitfield name="UNKLOC" low="24" high="31" type="uint"/>
2729         </reg32>
2730
2731         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2732                 <!-- TODO: the first 12 bits are valid, likely 3-bit enum instead of bools -->
2733                 <bitfield name="BUF0" pos="0" type="boolean"/>
2734                 <bitfield name="BUF1" pos="3" type="boolean"/>
2735                 <bitfield name="BUF2" pos="6" type="boolean"/>
2736                 <bitfield name="BUF3" pos="9" type="boolean"/>
2737                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2738                 <bitfield name="UNK16" low="16" high="19"/>
2739         </reg32>
2740         <reg32 offset="0x9306" name="VPC_SO_DISABLE">
2741                 <bitfield name="DISABLE" pos="0" type="boolean"/>
2742         </reg32>
2743         <!-- 0x9307-0x95ff invalid -->
2744
2745         <!-- TODO: 0x9600-0x97ff range -->
2746         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2747         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="boolean"/>
2748         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2749         <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
2750         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
2751         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
2752         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
2753         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
2754         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
2755         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
2756         <!-- 0x960a-0x9623 invalid -->
2757         <!-- TODO: regs from 0x9624-0x963a -->
2758         <!-- 0x963b-0x97ff invalid -->
2759
2760         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
2761
2762         <!-- always 0x0 ? -->
2763         <reg32 offset="0x9801" name="PC_UNKNOWN_9801">
2764                 <bitfield name="UNK0" low="0" high="10"/>
2765                 <bitfield name="UNK13" pos="13"/>
2766         </reg32>
2767
2768         <enum name="a6xx_tess_spacing">
2769                 <value value="0x0" name="TESS_EQUAL"/>
2770                 <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2771                 <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2772         </enum>
2773         <enum name="a6xx_tess_output">
2774                 <value value="0x0" name="TESS_POINTS"/>
2775                 <value value="0x1" name="TESS_LINES"/>
2776                 <value value="0x2" name="TESS_CW_TRIS"/>
2777                 <value value="0x3" name="TESS_CCW_TRIS"/>
2778         </enum>
2779         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2780                 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2781                 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2782         </reg32>
2783
2784         <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
2785         <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
2786
2787         <!-- always 0x1 ? -->
2788         <reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
2789
2790         <!-- probably a mirror of VFD_CONTROL_6 -->
2791         <reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
2792         <!-- 0x980b-0x983f invalid -->
2793
2794         <!-- 0x9840 - 0x9842 are not readable -->
2795         <reg32 offset="0x9840" name="PC_DRAW_CMD">
2796                 <bitfield name="STATE_ID" low="0" high="7"/>
2797         </reg32>
2798
2799         <reg32 offset="0x9841" name="PC_DISPATCH_CMD">
2800                 <bitfield name="STATE_ID" low="0" high="7"/>
2801         </reg32>
2802
2803         <reg32 offset="0x9842" name="PC_EVENT_CMD">
2804                 <!-- I think only the low bit is actually used? -->
2805                 <bitfield name="STATE_ID" low="16" high="23"/>
2806                 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2807         </reg32>
2808
2809         <!-- 0x9843-0x997f invalid -->
2810
2811         <reg32 offset="0x9981" name="PC_POLYGON_MODE">
2812                 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2813         </reg32>
2814         <reg32 offset="0x9980" name="PC_UNKNOWN_9980" low="0" high="2"/>
2815
2816         <!-- 0x9982-0x9aff invalid -->
2817
2818         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2819                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2820                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2821                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2822                 <bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
2823                 <bitfield name="UNK3" pos="3" type="boolean"/>
2824         </reg32>
2825
2826         <bitset name="a6xx_xs_out_cntl" inline="yes">
2827                 <doc>
2828                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2829                         plus # of transform-feedback (streamout) varyings if using the
2830                         hw streamout (rather than stg instructions in shader)
2831                 </doc>
2832                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2833                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2834                 <bitfield name="LAYER" pos="9" type="boolean"/>
2835                 <bitfield name="VIEW" pos="10" type="boolean"/>
2836                 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
2837                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2838                 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
2839         </bitset>
2840
2841         <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2842         <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2843         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3" pos="11"/>
2844         <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2845
2846         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2847                 <doc>
2848                   geometry shader
2849                 </doc>
2850                 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
2851                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2852                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2853                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2854                 <bitfield name="UNK18" pos="18"/>
2855         </reg32>
2856
2857         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2858                 <doc>
2859                   size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
2860                 </doc>
2861                 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
2862         </reg32>
2863         <!-- something gs related: -->
2864         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07" low="0" high="6"/>
2865
2866         <reg32 offset="0x9b08" name="PC_UNKNOWN_9B08" low="0" high="15"/>
2867         <!-- 0x9b09-0x9bff invalid -->
2868         <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
2869                 <!-- special register (but note first 8 bits can be written/read) -->
2870                 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2871                 <bitfield name="STATE_ID" low="8" high="15"/>
2872         </reg32>
2873         <!-- 0x9c01-0x9dff invalid -->
2874         <!-- TODO: 0x9e00-0xa000 range incomplete -->
2875         <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
2876         <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL"/>
2877         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2878         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2879         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
2880
2881         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2882         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2883                 <bitfield name="UNK0" low="0" high="15"/>
2884                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2885                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2886         </reg32>
2887         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2" type="waddress" align="32"/>
2888         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR" type="waddress" align="32"/>
2889
2890         <reg32 offset="0x9e34" name="PC_PERFCTR_PC_SEL_0"/>
2891         <reg32 offset="0x9e35" name="PC_PERFCTR_PC_SEL_1"/>
2892         <reg32 offset="0x9e36" name="PC_PERFCTR_PC_SEL_2"/>
2893         <reg32 offset="0x9e37" name="PC_PERFCTR_PC_SEL_3"/>
2894         <reg32 offset="0x9e38" name="PC_PERFCTR_PC_SEL_4"/>
2895         <reg32 offset="0x9e39" name="PC_PERFCTR_PC_SEL_5"/>
2896         <reg32 offset="0x9e3a" name="PC_PERFCTR_PC_SEL_6"/>
2897         <reg32 offset="0x9e3b" name="PC_PERFCTR_PC_SEL_7"/>
2898
2899         <!-- always 0x0 -->
2900         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2901
2902         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2903                 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2904                 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2905         </reg32>
2906         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2907                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2908                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2909                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2910         </reg32>
2911         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2912                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2913                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2914         </reg32>
2915         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2916                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2917                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2918                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2919         </reg32>
2920         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2921         </reg32>
2922         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2923                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2924         </reg32>
2925         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2926                 <!--
2927                         True if gl_PrimitiveID is read via the FS and there is
2928                         no matching write from the GS, and therefore it needs to
2929                         be passed through via fixed-function logic.
2930                 -->
2931                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2932         </reg32>
2933
2934         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2935                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2936         </reg32>
2937
2938         <!-- always 0x0 ? -->
2939         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2940         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2941                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2942                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2943                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2944                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2945         </reg32>
2946
2947         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2948         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2949         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2950                 <reg64 offset="0x0" name="BASE" type="address"/>
2951                 <reg32 offset="0x0" name="BASE_LO"/>
2952                 <reg32 offset="0x1" name="BASE_HI"/>
2953                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2954                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2955         </array>
2956         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2957                 <reg32 offset="0x0" name="INSTR">
2958                         <!-- IDX and byte OFFSET into VFD_FETCH -->
2959                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2960                         <bitfield name="OFFSET" low="5" high="16"/>
2961                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2962                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2963                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2964                         <bitfield name="UNK30" pos="30" type="boolean"/>
2965                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2966                 </reg32>
2967                 <reg32 offset="0x1" name="STEP_RATE"/>
2968         </array>
2969         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2970                 <reg32 offset="0x0" name="INSTR">
2971                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2972                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2973                 </reg32>
2974         </array>
2975
2976         <!-- always 0x1 ? -->
2977         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2978
2979         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2980                 <!--
2981                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2982                 used registers is a bit odd too:
2983                         - used (half): 0-15 68-179 (cnt=128, max=179)
2984                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2985                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2986                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2987                 then:
2988                         - used (merged): 0-191 (cnt=192, max=191)
2989                 So I think if b31 is set, then the half precision registers overlap
2990                 the full precision registers.  (Which seems like a pretty sensible
2991                 feature, actually I'm not sure when you *wouldn't* want to use that,
2992                 since it gives register allocation more flexibility)
2993                  -->
2994                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2995                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2996                 <!-- seems to be nesting level for flow control:.. -->
2997                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2998                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2999                 <bitfield name="VARYING" pos="22" type="boolean"/>
3000                 <!-- set when dFdxFine/dFdyFine is used -->
3001                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
3002                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
3003                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3004         </bitset>
3005
3006         <bitset name="a6xx_sp_xs_config" inline="yes">
3007                 <!--
3008                 Each of these are set if the given resource type is used
3009                 with the Vulkan/bindless binding model.
3010                 -->
3011                 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
3012                 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
3013                 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
3014                 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
3015
3016                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3017                 <!--
3018                 number of textures and samplers.. these might be swapped, with GL I
3019                 always see the same value for both.
3020                  -->
3021                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
3022                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
3023                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
3024         </bitset>
3025
3026         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3027         <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex">
3028                 <!--
3029                 bitmask of true/false conditions for VS brac.N instructions,
3030                 bit N corresponds to brac.N
3031                  -->
3032         </reg32>
3033         <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL">
3034                 <!-- # of VS outputs including pos/psize -->
3035                 <bitfield name="OUT" low="0" high="5" type="uint"/>
3036         </reg32>
3037         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
3038                 <reg32 offset="0x0" name="REG">
3039                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3040                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3041                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3042                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3043                 </reg32>
3044         </array>
3045         <!--
3046         Starting with a5xx, position/psize outputs from shader end up in the
3047         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
3048         the last entries too, except when gl_PointCoord is used, blob inserts
3049         an extra varying after, but with a lower OUTLOC position.  If present,
3050         psize is last, preceded by position.
3051          -->
3052         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
3053                 <reg32 offset="0x0" name="REG">
3054                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3055                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3056                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3057                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3058                 </reg32>
3059         </array>
3060
3061         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
3062         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
3063         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
3064         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
3065         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
3066         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
3067
3068         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3069         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
3070         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
3071         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
3072         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
3073         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
3074         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
3075         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
3076
3077         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3078         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
3079                 <!-- # of DS outputs including pos/psize -->
3080                 <bitfield name="OUT" low="0" high="5" type="uint"/>
3081         </reg32>
3082         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
3083                 <reg32 offset="0x0" name="REG">
3084                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3085                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3086                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3087                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3088                 </reg32>
3089         </array>
3090         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
3091                 <reg32 offset="0x0" name="REG">
3092                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3093                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3094                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3095                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3096                 </reg32>
3097         </array>
3098
3099         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
3100         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
3101         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
3102         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
3103         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
3104         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
3105
3106         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3107         <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE">
3108                 <!-- size of output of previous stage -->
3109         </reg32>
3110         <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex">
3111                 <!--
3112                 bitmask of true/false conditions for FS brac.N instructions,
3113                 bit N corresponds to brac.N
3114                  -->
3115         </reg32>
3116
3117         <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL">
3118                 <!-- # of VS outputs including pos/psize -->
3119                 <bitfield name="OUT" low="0" high="5" type="uint"/>
3120                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
3121         </reg32>
3122
3123         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
3124                 <reg32 offset="0x0" name="REG">
3125                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3126                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3127                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3128                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3129                 </reg32>
3130         </array>
3131
3132         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
3133                 <reg32 offset="0x0" name="REG">
3134                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3135                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3136                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3137                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3138                 </reg32>
3139         </array>
3140
3141         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
3142         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
3143         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
3144         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
3145         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
3146
3147         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
3148         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
3149         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
3150         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
3151         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
3152         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
3153         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
3154         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
3155         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
3156         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
3157         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
3158         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
3159         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
3160         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
3161         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
3162         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
3163
3164         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3165         <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
3166                 <!--
3167                 bitmask of true/false conditions for FS brac.N instructions,
3168                 bit N corresponds to brac.N
3169                  -->
3170         </reg32>
3171         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
3172         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
3173         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
3174
3175         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
3176                 <bitfield name="ENABLED" pos="0" type="boolean"/>
3177                 <bitfield name="UNK8" pos="8" type="boolean"/>
3178                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3179                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3180         </reg32>
3181         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3182                 <!-- Same as RB_SRGB_CNTL -->
3183                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3184                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3185                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3186                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3187                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3188                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3189                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3190                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3191         </reg32>
3192         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3193                 <bitfield name="RT0" low="0" high="3"/>
3194                 <bitfield name="RT1" low="4" high="7"/>
3195                 <bitfield name="RT2" low="8" high="11"/>
3196                 <bitfield name="RT3" low="12" high="15"/>
3197                 <bitfield name="RT4" low="16" high="19"/>
3198                 <bitfield name="RT5" low="20" high="23"/>
3199                 <bitfield name="RT6" low="24" high="27"/>
3200                 <bitfield name="RT7" low="28" high="31"/>
3201         </reg32>
3202         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3203                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3204                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3205                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3206         </reg32>
3207         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3208                 <bitfield name="MRT" low="0" high="3" type="uint"/>
3209         </reg32>
3210
3211         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3212                 <reg32 offset="0" name="REG">
3213                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3214                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3215                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3216                 </reg32>
3217         </array>
3218
3219         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3220                 <!-- unknown bits 0x7fc0 always set -->
3221                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
3222                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3223                 <bitfield name="UNK3" pos="3" type="boolean"/>
3224                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3225         </reg32>
3226         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3227                 <reg32 offset="0" name="CMD">
3228                         <bitfield name="SRC" low="0" high="6" type="uint"/>
3229                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3230                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3231                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3232                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
3233                         <bitfield name="HALF" pos="26" type="boolean"/>
3234                         <!--
3235                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
3236                         skip pre-fetch.. TODO test texelFetch
3237                         CMD is 0x6 when the Vulkan mode is enabled, and
3238                         TEX_ID/SAMP_ID refer to the descriptor sets while the
3239                         indices come from SP_FS_BINDLESS_PREFETCH[n]
3240                          -->
3241                         <bitfield name="CMD" low="27" high="31"/>
3242                 </reg32>
3243         </array>
3244
3245         <!-- TODO confirm that this is actually an array -->
3246         <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3247                 <reg32 offset="0" name="CMD">
3248                         <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
3249                         <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
3250                 </reg32>
3251         </array>
3252
3253         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3254
3255         <!-- always 0x0 ? -->
3256         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3257
3258         <!-- set for compute shaders, always 0x41 -->
3259         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint">
3260                 <doc>
3261                         bit 0 seems to toggle between 2k and 32k of shared storage
3262                         the ldl/stl offset seems to be rewritten to 0 when it is beyond
3263                         this limit. This is different from ldlw/stlw, which wraps at
3264                         64k (and has 36k of storage on A640 - reads between 36k-64k
3265                         always return 0)
3266                 </doc>
3267                 <bitfield name="SHARED_SIZE_2K" pos="0" type="uint"/>
3268         </reg32>
3269
3270         <!-- set for compute shaders, always 0x0 -->
3271         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3272
3273         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3274
3275         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3276         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3277         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3278         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3279         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3280         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3281         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3282         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3283
3284         <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3285                 <reg64 offset="0" name="ADDR" type="waddress"/>
3286         </array>
3287
3288         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3289                 <doc>per MRT</doc>
3290                 <reg32 offset="0x0" name="REG">
3291                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3292                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3293                 </reg32>
3294         </array>
3295
3296         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3297         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3298         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3299         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3300         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3301
3302         <!--
3303         IBO state for compute shader:
3304          -->
3305         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3306         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3307         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3308
3309         <!-- always 0x5 ? -->
3310         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3311
3312         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3313         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3314
3315         <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3316                 <reg64 offset="0" name="ADDR" type="waddress"/>
3317         </array>
3318
3319         <!--
3320         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3321         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3322          -->
3323         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3324         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3325         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3326
3327         <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
3328                 <bitfield name="NORM" pos="0" type="boolean"/>
3329                 <bitfield name="SINT" pos="1" type="boolean"/>
3330                 <bitfield name="UINT" pos="2" type="boolean"/>
3331                 <!-- looks like HW only cares about the base type of this format,
3332                      which matches the ifmt? -->
3333                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3334                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3335                 <bitfield name="SRGB" pos="11" type="boolean"/>
3336                 <!-- some sort of channel mask, not sure what it is for -->
3337                 <bitfield name="MASK" low="12" high="15"/>
3338         </reg32>
3339
3340         <!-- always 0x0 -->
3341         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3342
3343         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3344         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3345
3346         <!-- always 0x3f ? -->
3347         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3348
3349         <!--
3350         The downstream kernel calls the debug cluster of registers
3351         "a6xx_sp_ps_tp_cluster" but this actually specifies the border
3352         color base for compute shaders.
3353         -->
3354         <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3355         <!-- always 0x0 ? -->
3356         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3357         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3358
3359         <!-- could be all the stuff below here is actually TPL1?? -->
3360
3361         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3362                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3363         </reg32>
3364         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3365                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3366                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3367         </reg32>
3368
3369         <!-- looks to work in the same way as a5xx: -->
3370         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3371         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3372         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3373         <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3374         <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3375         <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3376
3377         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3378
3379         <!--
3380         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3381         badly named or the functionality moved in a6xx.  But downstream kernel
3382         calls this "a6xx_sp_ps_tp_2d_cluster"
3383          -->
3384         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3385         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3386                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3387                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3388         </reg32>
3389         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3390         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3391         <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3392         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3393            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3394         </reg32>
3395
3396         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3397         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3398         <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3399         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3400                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3401                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3402         </reg32>
3403
3404         <!-- always 0x00100000 ? -->
3405         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3406
3407         <!-- always 0x44 ? -->
3408         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3409
3410         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3411                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3412                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3413         </bitset>
3414
3415         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3416         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3417         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3418         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3419
3420         <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
3421         <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR"/>
3422         <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
3423
3424         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3425
3426         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3427                 <!-- always 0x7 ? -->
3428         </reg32>
3429         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3430                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3431                 <!-- SAMPLEID is loaded into a half-precision register: -->
3432                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3433                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3434                 <!--
3435                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3436                 to be divided by to scale to a single fragment.  It is probably
3437                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3438                  -->
3439                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3440         </reg32>
3441         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3442                 <!-- register loaded with position (bary.f) -->
3443                 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
3444                 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
3445                 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
3446                 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
3447         </reg32>
3448         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3449                 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
3450                 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
3451                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3452                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3453         </reg32>
3454         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3455                 <!-- unknown regid in low 8b -->
3456         </reg32>
3457         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3458
3459         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3460                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3461                 <!-- localsize is value minus one: -->
3462                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3463                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3464                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3465         </reg32>
3466         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3467                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3468         </reg32>
3469         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3470                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3471         </reg32>
3472         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3473                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3474         </reg32>
3475         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3476                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3477         </reg32>
3478         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3479                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3480         </reg32>
3481         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3482                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3483         </reg32>
3484         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3485                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3486                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3487                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3488                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3489         </reg32>
3490         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3491         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3492         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3493         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3494
3495         <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
3496         <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR"/>
3497         <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
3498
3499         <!-- mirror of SP_CS_BINDLESS_BASE -->
3500         <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3501                 <reg64 offset="0" name="ADDR" type="waddress"/>
3502         </array>
3503
3504         <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
3505                 <bitfield name="STATE_ID" low="0" high="7"/>
3506         </reg32>
3507
3508         <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
3509                 <bitfield name="STATE_ID" low="0" high="7"/>
3510         </reg32>
3511
3512         <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
3513                 <!-- I think only the low bit is actually used? -->
3514                 <bitfield name="STATE_ID" low="16" high="23"/>
3515                 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3516         </reg32>
3517
3518         <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD">
3519                 <doc>
3520                         This register clears pending loads queued up by
3521                         CP_LOAD_STATE6. Each bit resets a particular kind(s) of
3522                         CP_LOAD_STATE6.
3523                 </doc>
3524
3525                 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3526                 <bitfield name="VS_STATE" pos="0" type="boolean"/>
3527                 <bitfield name="HS_STATE" pos="1" type="boolean"/>
3528                 <bitfield name="DS_STATE" pos="2" type="boolean"/>
3529                 <bitfield name="GS_STATE" pos="3" type="boolean"/>
3530                 <bitfield name="FS_STATE" pos="4" type="boolean"/>
3531                 <bitfield name="CS_STATE" pos="5" type="boolean"/>
3532
3533                 <bitfield name="CS_IBO" pos="6" type="boolean"/>
3534                 <bitfield name="GFX_IBO" pos="7" type="boolean"/>
3535
3536                 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
3537                 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
3538                 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
3539
3540                 <!-- SS6_BINDLESS: one bit per bindless base -->
3541                 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
3542                 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
3543         </reg32>
3544
3545         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3546
3547         <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS">
3548                 <doc>
3549                         Shared constants are intended to be used for Vulkan push
3550                         constants. When enabled, 8 vec4's are reserved in the FS
3551                         const pool and 16 in the geometry const pool although
3552                         only 8 are actually used (why?) and they are mapped to
3553                         c504-c511 in each stage. Both VS and FS shared consts
3554                         are written using ST6_CONSTANTS/SB6_IBO, so that both
3555                         the geometry and FS shared consts can be written at once
3556                         by using CP_LOAD_STATE6 rather than
3557                         CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
3558                         DST_OFF and NUM_UNIT are in units of dwords instead of
3559                         vec4's.
3560
3561                         There is also a separate shared constant pool for CS,
3562                         which is loaded through CP_LOAD_STATE6_FRAG with
3563                         ST6_UBO/ST6_IBO. However the only real difference for CS
3564                         is the dword units.
3565                 </doc>
3566                 <bitfield name="ENABLE" pos="0" type="boolean"/>
3567         </reg32>
3568
3569         <!-- mirror of SP_BINDLESS_BASE -->
3570         <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3571                 <reg64 offset="0" name="ADDR" type="waddress"/>
3572         </array>
3573
3574         <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
3575                 <bitfield name="STATE_ID" low="8" high="15"/>
3576                 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3577         </reg32>
3578
3579         <!-- always 0x80 ? -->
3580         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3581         <!-- always 0x0 ? -->
3582         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3583         <!-- always 0x0 ? -->
3584         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3585
3586         <!--
3587                 These special registers signal the beginning/end of an event
3588                 sequence. The sequence used internally for an event looks like:
3589                 - write EVENT_CMD pipe register
3590                 - write CP_EVENT_START
3591                 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
3592                 - write PC_EVENT_CMD with event or PC_DRAW_CMD
3593                 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
3594                 - write PC_EVENT_CMD(CONTEXT_DONE)
3595                 - write CP_EVENT_END
3596                 Writing to CP_EVENT_END seems to actually trigger the context roll
3597         -->
3598         <reg32 offset="0xd600" name="CP_EVENT_START">
3599                 <bitfield name="STATE_ID" low="0" high="7"/>
3600         </reg32>
3601         <reg32 offset="0xd601" name="CP_EVENT_END">
3602                 <bitfield name="STATE_ID" low="0" high="7"/>
3603         </reg32>
3604         <reg32 offset="0xd700" name="CP_2D_EVENT_START">
3605                 <bitfield name="STATE_ID" low="0" high="7"/>
3606         </reg32>
3607         <reg32 offset="0xd701" name="CP_2D_EVENT_END">
3608                 <bitfield name="STATE_ID" low="0" high="7"/>
3609         </reg32>
3610 </domain>
3611
3612 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3613 <domain name="A6XX_TEX_SAMP" width="32">
3614         <doc>Texture sampler dwords</doc>
3615         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3616                 <value name="A6XX_TEX_NEAREST" value="0"/>
3617                 <value name="A6XX_TEX_LINEAR" value="1"/>
3618                 <value name="A6XX_TEX_ANISO" value="2"/>
3619                 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3620         </enum>
3621         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3622                 <value name="A6XX_TEX_REPEAT" value="0"/>
3623                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3624                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3625                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3626                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3627         </enum>
3628         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3629                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3630                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3631                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3632                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3633                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3634         </enum>
3635         <enum name="a6xx_reduction_mode">
3636                 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3637                 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3638                 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3639         </enum>
3640
3641         <reg32 offset="0" name="0">
3642                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3643                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3644                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3645                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3646                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3647                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3648                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3649                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3650         </reg32>
3651         <reg32 offset="1" name="1">
3652                 <!-- bit 0 always set with vulkan? -->
3653                 <bitfield name="UNK0" pos="0" type="boolean"/>
3654                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3655                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3656                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3657                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3658                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3659                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3660         </reg32>
3661         <reg32 offset="2" name="2">
3662                 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3663                 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
3664                 <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
3665         </reg32>
3666         <reg32 offset="3" name="3"/>
3667 </domain>
3668
3669 <domain name="A6XX_TEX_CONST" width="32">
3670         <doc>Texture constant dwords</doc>
3671         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3672                 <value name="A6XX_TEX_X" value="0"/>
3673                 <value name="A6XX_TEX_Y" value="1"/>
3674                 <value name="A6XX_TEX_Z" value="2"/>
3675                 <value name="A6XX_TEX_W" value="3"/>
3676                 <value name="A6XX_TEX_ZERO" value="4"/>
3677                 <value name="A6XX_TEX_ONE" value="5"/>
3678         </enum>
3679         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3680                 <value name="A6XX_TEX_1D" value="0"/>
3681                 <value name="A6XX_TEX_2D" value="1"/>
3682                 <value name="A6XX_TEX_CUBE" value="2"/>
3683                 <value name="A6XX_TEX_3D" value="3"/>
3684         </enum>
3685         <reg32 offset="0" name="0">
3686                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3687                 <bitfield name="SRGB" pos="2" type="boolean"/>
3688                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3689                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3690                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3691                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3692                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3693                 <!-- overlaps with MIPLVLS -->
3694                 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
3695                 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
3696                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3697                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3698                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3699         </reg32>
3700         <reg32 offset="1" name="1">
3701                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3702                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3703         </reg32>
3704         <reg32 offset="2" name="2">
3705                 <!--
3706                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3707                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3708
3709                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3710                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3711                  -->
3712                 <bitfield name="UNK4" pos="4" type="boolean"/>
3713                 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3714                 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
3715                 <doc>Pitch in bytes (so actually stride)</doc>
3716                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3717                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3718                 <bitfield name="UNK31" pos="31" type="boolean"/>
3719         </reg32>
3720         <reg32 offset="3" name="3">
3721                 <!--
3722                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3723                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3724                 layer size at the point that it stops being reduced moving to
3725                 higher (smaller) mipmap levels
3726                  -->
3727                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3728                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3729                 <!--
3730                 by default levels with w < 16 are linear
3731                 TILE_ALL makes all levels have tiling
3732                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3733                  -->
3734                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3735                 <bitfield name="FLAG" pos="28" type="boolean"/>
3736         </reg32>
3737         <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3738              the address of the non-flag base buffer is determined automatically,
3739              and must follow the flag buffer
3740          -->
3741         <reg32 offset="4" name="4">
3742                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3743         </reg32>
3744         <reg32 offset="5" name="5">
3745                 <bitfield name="BASE_HI" low="0" high="16"/>
3746                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3747         </reg32>
3748         <reg32 offset="6" name="6">
3749                 <!-- pitch for plane 2 / plane 3 -->
3750                 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
3751         </reg32>
3752         <!-- 7/8 is plane 2 address for planar formats -->
3753         <reg32 offset="7" name="7">
3754                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3755         </reg32>
3756         <reg32 offset="8" name="8">
3757                 <bitfield name="FLAG_HI" low="0" high="16"/>
3758         </reg32>
3759         <!-- 9/10 is plane 3 address for planar formats -->
3760         <reg32 offset="9" name="9">
3761                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3762         </reg32>
3763         <reg32 offset="10" name="10">
3764                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3765                 <!-- log2 size of the first level, required for mipmapping -->
3766                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3767                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3768         </reg32>
3769         <reg32 offset="11" name="11"/>
3770         <reg32 offset="12" name="12"/>
3771         <reg32 offset="13" name="13"/>
3772         <reg32 offset="14" name="14"/>
3773         <reg32 offset="15" name="15"/>
3774 </domain>
3775
3776 <!--
3777 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3778 naming is just because I r/e'd SSBOs first.  I should probably come up
3779 with a better name.
3780 -->
3781 <domain name="A6XX_IBO" width="32">
3782         <reg32 offset="0" name="0">
3783                 <!--
3784                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3785                 used but if they are good chance position is same as TEX_CONST
3786                  -->
3787                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3788                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3789         </reg32>
3790         <reg32 offset="1" name="1">
3791                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3792                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3793         </reg32>
3794         <reg32 offset="2" name="2">
3795                 <!--
3796                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3797                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3798                  -->
3799                 <bitfield name="UNK4" pos="4" type="boolean"/>
3800                 <doc>Pitch in bytes (so actually stride)</doc>
3801                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3802                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3803                 <bitfield name="UNK31" pos="31" type="boolean"/>
3804         </reg32>
3805         <reg32 offset="3" name="3">
3806                 <!--
3807                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3808                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3809                 layer size at the point that it stops being reduced moving to
3810                 higher (smaller) mipmap levels
3811                  -->
3812                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3813                 <bitfield name="UNK27" pos="27" type="boolean"/>
3814                 <bitfield name="FLAG" pos="28" type="boolean"/>
3815         </reg32>
3816         <reg32 offset="4" name="4">
3817                 <bitfield name="BASE_LO" low="0" high="31"/>
3818         </reg32>
3819         <reg32 offset="5" name="5">
3820                 <bitfield name="BASE_HI" low="0" high="16"/>
3821                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3822         </reg32>
3823         <reg32 offset="6" name="6">
3824         </reg32>
3825         <reg32 offset="7" name="7">
3826         </reg32>
3827         <reg32 offset="8" name="8">
3828         </reg32>
3829         <reg32 offset="9" name="9">
3830                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3831         </reg32>
3832         <reg32 offset="10" name="10">
3833                 <!--
3834                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3835                 don't seem to be particularly sensible... or needed for UBWC to work
3836                  -->
3837                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3838         </reg32>
3839 </domain>
3840
3841 <domain name="A6XX_UBO" width="32">
3842         <reg32 offset="0" name="0">
3843                 <bitfield name="BASE_LO" low="0" high="31"/>
3844         </reg32>
3845         <reg32 offset="1" name="1">
3846                 <bitfield name="BASE_HI" low="0" high="16"/>
3847                 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3848         </reg32>
3849 </domain>
3850
3851 <domain name="A6XX_PDC" width="32">
3852         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3853         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3854         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3855         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3856         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3857         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3858         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3859         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3860         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3861         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3862         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3863         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3864         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3865         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3866         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3867         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3868         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3869         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3870         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3871         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3872         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3873         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3874         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3875         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3876         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3877         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3878 </domain>
3879
3880 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3881         <reg32 offset="0x0" name="MEM_0"/>
3882 </domain>
3883
3884 <domain name="A6XX_CX_DBGC" width="32">
3885         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3886                 <bitfield high="7" low="0" name="PING_INDEX"/>
3887                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3888         </reg32>
3889         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3890         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3891         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3892         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3893                 <bitfield high="5" low="0" name="TRACEEN"/>
3894                 <bitfield high="14" low="12" name="GRANU"/>
3895                 <bitfield high="31" low="28" name="SEGT"/>
3896         </reg32>
3897         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3898                 <bitfield high="27" low="24" name="ENABLE"/>
3899         </reg32>
3900         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3901         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3902         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3903         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3904         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3905         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3906         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3907         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3908         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3909                 <bitfield high="3" low="0" name="BYTEL0"/>
3910                 <bitfield high="7" low="4" name="BYTEL1"/>
3911                 <bitfield high="11" low="8" name="BYTEL2"/>
3912                 <bitfield high="15" low="12" name="BYTEL3"/>
3913                 <bitfield high="19" low="16" name="BYTEL4"/>
3914                 <bitfield high="23" low="20" name="BYTEL5"/>
3915                 <bitfield high="27" low="24" name="BYTEL6"/>
3916                 <bitfield high="31" low="28" name="BYTEL7"/>
3917         </reg32>
3918         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3919                 <bitfield high="3" low="0" name="BYTEL8"/>
3920                 <bitfield high="7" low="4" name="BYTEL9"/>
3921                 <bitfield high="11" low="8" name="BYTEL10"/>
3922                 <bitfield high="15" low="12" name="BYTEL11"/>
3923                 <bitfield high="19" low="16" name="BYTEL12"/>
3924                 <bitfield high="23" low="20" name="BYTEL13"/>
3925                 <bitfield high="27" low="24" name="BYTEL14"/>
3926                 <bitfield high="31" low="28" name="BYTEL15"/>
3927         </reg32>
3928
3929         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3930         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3931 </domain>
3932
3933 <domain name="A6XX_CX_MISC" width="32">
3934         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3935         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3936 </domain>
3937
3938 </database>