src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_tile_mode">
  11         <value name="TILE6_LINEAR" value="0"/>
  12         <value name="TILE6_2" value="2"/>
  13         <value name="TILE6_3" value="3"/>
  14 </enum>
  15
  16 <enum name="a6xx_format">
  17         <value value="0x02" name="FMT6_A8_UNORM"/>
  18         <value value="0x03" name="FMT6_8_UNORM"/>
  19         <value value="0x04" name="FMT6_8_SNORM"/>
  20         <value value="0x05" name="FMT6_8_UINT"/>
  21         <value value="0x06" name="FMT6_8_SINT"/>
  22
  23         <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
  24         <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
  25         <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
  26         <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
  27
  28         <value value="0x0f" name="FMT6_8_8_UNORM"/>
  29         <value value="0x10" name="FMT6_8_8_SNORM"/>
  30         <value value="0x11" name="FMT6_8_8_UINT"/>
  31         <value value="0x12" name="FMT6_8_8_SINT"/>
  32         <value value="0x13" name="FMT6_L8_A8_UNORM"/>
  33
  34         <value value="0x15" name="FMT6_16_UNORM"/>
  35         <value value="0x16" name="FMT6_16_SNORM"/>
  36         <value value="0x17" name="FMT6_16_FLOAT"/>
  37         <value value="0x18" name="FMT6_16_UINT"/>
  38         <value value="0x19" name="FMT6_16_SINT"/>
  39
  40         <value value="0x21" name="FMT6_8_8_8_UNORM"/>
  41         <value value="0x22" name="FMT6_8_8_8_SNORM"/>
  42         <value value="0x23" name="FMT6_8_8_8_UINT"/>
  43         <value value="0x24" name="FMT6_8_8_8_SINT"/>
  44
  45         <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
  46         <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
  47         <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
  48         <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
  49         <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
  50
  51         <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
  52
  53         <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
  54         <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
  55         <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
  56         <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
  57         <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
  58
  59         <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
  60
  61         <value value="0x43" name="FMT6_16_16_UNORM"/>
  62         <value value="0x44" name="FMT6_16_16_SNORM"/>
  63         <value value="0x45" name="FMT6_16_16_FLOAT"/>
  64         <value value="0x46" name="FMT6_16_16_UINT"/>
  65         <value value="0x47" name="FMT6_16_16_SINT"/>
  66
  67         <value value="0x48" name="FMT6_32_UNORM"/>
  68         <value value="0x49" name="FMT6_32_SNORM"/>
  69         <value value="0x4a" name="FMT6_32_FLOAT"/>
  70         <value value="0x4b" name="FMT6_32_UINT"/>
  71         <value value="0x4c" name="FMT6_32_SINT"/>
  72         <value value="0x4d" name="FMT6_32_FIXED"/>
  73
  74         <value value="0x58" name="FMT6_16_16_16_UNORM"/>
  75         <value value="0x59" name="FMT6_16_16_16_SNORM"/>
  76         <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
  77         <value value="0x5b" name="FMT6_16_16_16_UINT"/>
  78         <value value="0x5c" name="FMT6_16_16_16_SINT"/>
  79
  80         <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
  81         <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
  82         <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
  83         <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
  84         <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
  85
  86         <value value="0x65" name="FMT6_32_32_UNORM"/>
  87         <value value="0x66" name="FMT6_32_32_SNORM"/>
  88         <value value="0x67" name="FMT6_32_32_FLOAT"/>
  89         <value value="0x68" name="FMT6_32_32_UINT"/>
  90         <value value="0x69" name="FMT6_32_32_SINT"/>
  91         <value value="0x6a" name="FMT6_32_32_FIXED"/>
  92
  93         <value value="0x70" name="FMT6_32_32_32_UNORM"/>
  94         <value value="0x71" name="FMT6_32_32_32_SNORM"/>
  95         <value value="0x72" name="FMT6_32_32_32_UINT"/>
  96         <value value="0x73" name="FMT6_32_32_32_SINT"/>
  97         <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
  98         <value value="0x75" name="FMT6_32_32_32_FIXED"/>
  99
 100         <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
 101         <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
 102         <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
 103         <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
 104         <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
 105         <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
 106
 107         <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
 108         <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
 109
 110         <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
 111         <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
 112         <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
 113         <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
 114         <value value="0xaf" name="FMT6_ETC1"/>
 115         <value value="0xb0" name="FMT6_ETC2_RGB8"/>
 116         <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
 117         <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
 118         <value value="0xb3" name="FMT6_DXT1"/>
 119         <value value="0xb4" name="FMT6_DXT3"/>
 120         <value value="0xb5" name="FMT6_DXT5"/>
 121         <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
 122         <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
 123         <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
 124         <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
 125         <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
 126         <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
 127         <value value="0xc0" name="FMT6_BPTC"/>
 128         <value value="0xc1" name="FMT6_ASTC_4x4"/>
 129         <value value="0xc2" name="FMT6_ASTC_5x4"/>
 130         <value value="0xc3" name="FMT6_ASTC_5x5"/>
 131         <value value="0xc4" name="FMT6_ASTC_6x5"/>
 132         <value value="0xc5" name="FMT6_ASTC_6x6"/>
 133         <value value="0xc6" name="FMT6_ASTC_8x5"/>
 134         <value value="0xc7" name="FMT6_ASTC_8x6"/>
 135         <value value="0xc8" name="FMT6_ASTC_8x8"/>
 136         <value value="0xc9" name="FMT6_ASTC_10x5"/>
 137         <value value="0xca" name="FMT6_ASTC_10x6"/>
 138         <value value="0xcb" name="FMT6_ASTC_10x8"/>
 139         <value value="0xcc" name="FMT6_ASTC_10x10"/>
 140         <value value="0xcd" name="FMT6_ASTC_12x10"/>
 141         <value value="0xce" name="FMT6_ASTC_12x12"/>
 142
 143         <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
 144         <value value="0xea" name="FMT6_S8Z24_UINT"/>
 145 </enum>
 146
 147 <enum name="a6xx_tex_fetchsize">
 148         <value name="TFETCH6_1_BYTE"  value="0"/>
 149         <value name="TFETCH6_2_BYTE"  value="1"/>
 150         <value name="TFETCH6_4_BYTE"  value="2"/>
 151         <value name="TFETCH6_8_BYTE"  value="3"/>
 152         <value name="TFETCH6_16_BYTE" value="4"/>
 153 </enum>
 154
 155 <!-- probably same as a5xx -->
 156 <enum name="a6xx_depth_format">
 157         <value name="DEPTH6_NONE" value="0"/>
 158         <value name="DEPTH6_16" value="1"/>
 159         <value name="DEPTH6_24_8" value="2"/>
 160         <value name="DEPTH6_32" value="4"/>
 161 </enum>
 162
 163 <bitset name="a6x_cp_protect" inline="yes">
 164         <bitfield name="BASE_ADDR" low="0" high="17"/>
 165         <bitfield name="MASK_LEN" low="18" high="30"/>
 166         <bitfield name="READ" pos="31"/>
 167 </bitset>
 168
 169 <enum name="a6xx_shader_id">
 170         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 171         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 172         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 173         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 174         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 175         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 176         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 177         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 178         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 179         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 180         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 181         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 182         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 183         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 184         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 185         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 186         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 187         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 188         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 189         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 190         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 191         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 192         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 193         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 194         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 195         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 196         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 197         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 198         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 199         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 200         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 201         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 202         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 203         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 204         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 205         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 206         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 207         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 208         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 209         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 210         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 211         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 212         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 213 </enum>
 214
 215 <enum name="a6xx_debugbus_id">
 216         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 217         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 218         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 219         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 220         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 221         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 222         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 223         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 224         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 225         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 226         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 227         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 228         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 229         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 230         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 231         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 232         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 233         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 234         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 235         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 236         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 237         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 238         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 239         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 240         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 241         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 242         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 243         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 244         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 245         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 246         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 247         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 248         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 249         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 250         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 251         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 252         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 253         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 254         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 255         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 256         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 257         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 258         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 259 </enum>
 260
 261 <enum name="a6xx_cp_perfcounter_select">
 262         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 263         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 264         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 265         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 266         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 267         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 268         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 269         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 270         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 271         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 272         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 273         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 274         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 275         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 276         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 277         <value value="15" name="PERF_CP_SQE_IDLE"/>
 278         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 279         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 280         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 281         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 282         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 283         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 284         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 285         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 286         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 287         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 288         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 289         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 290         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 291         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 292         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 293         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 294         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 295         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 296         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 297         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 298         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 299         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 300         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 301         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 302         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 303         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 304         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 305         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 306         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 307         <value value="45" name="PERF_CP_PM4_DATA"/>
 308         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 309         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 310         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 311         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 312 </enum>
 313
 314 <enum name="a6xx_rbbm_perfcounter_select">
 315         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 316         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 317         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 318         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 319         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 320         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 321         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 322         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 323         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 324         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 325         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 326         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 327         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 328         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 329 </enum>
 330
 331 <enum name="a6xx_pc_perfcounter_select">
 332         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 333         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 334         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 335         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 336         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 337         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 338         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 339         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 340         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 341         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 342         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 343         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 344         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 345         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 346         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 347         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 348         <value value="16" name="PERF_PC_INSTANCES"/>
 349         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 350         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 351         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 352         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 353         <value value="21" name="PERF_PC_IA_VERTICES"/>
 354         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 355         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 356         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 357         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 358         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 359         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 360         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 361         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 362         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 363         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 364         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 365         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 366         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 367         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 368         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 369         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 370         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 371         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 372         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 373         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 374 </enum>
 375
 376 <enum name="a6xx_vfd_perfcounter_select">
 377         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 378         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 379         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 380         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 381         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 382         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 383         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 384         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 385         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 386         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 387         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 388         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 389         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 390         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 391         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 392         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 393         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 394         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 395         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 396         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 397         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 398         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 399         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 400 </enum>
 401
 402 <enum name="a6xx_hlsq_perfcounter_select">
 403         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 404         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 405         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 406         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 407         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 408         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 409         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 410         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 411         <value value="8" name="PERF_HLSQ_QUADS"/>
 412         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 413         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 414         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 415         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 416         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 417         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 418         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 419         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 420         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 421         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 422         <value value="19" name="PERF_HLSQ_PIXELS"/>
 423         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 424 </enum>
 425
 426 <enum name="a6xx_vpc_perfcounter_select">
 427         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 428         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 429         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 430         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 431         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 432         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 433         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 434         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 435         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 436         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 437         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 438         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 439         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 440         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 441         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 442         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 443         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 444         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 445         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 446         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 447         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 448         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 449         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 450         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 451         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 452         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 453         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 454         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 455 </enum>
 456
 457 <enum name="a6xx_tse_perfcounter_select">
 458         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 459         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 460         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 461         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 462         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 463         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 464         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 465         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 466         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 467         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 468         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 469         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 470         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 471         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 472         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 473         <value value="15" name="PERF_TSE_CINVOCATION"/>
 474         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 475         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 476         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 477         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 478 </enum>
 479
 480 <enum name="a6xx_ras_perfcounter_select">
 481         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 482         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 483         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 484         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 485         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 486         <value value="5" name="PERF_RAS_8X4_TILES"/>
 487         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 488         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 489         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 490         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 491         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 492         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 493         <value value="12" name="PERF_RAS_BLOCKS"/>
 494 </enum>
 495
 496 <enum name="a6xx_uche_perfcounter_select">
 497         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 498         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 499         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 500         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 501         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 502         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 503         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 504         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 505         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 506         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 507         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 508         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 509         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 510         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 511         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 512         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 513         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 514         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 515         <value value="18" name="PERF_UCHE_EVICTS"/>
 516         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 517         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 518         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 519         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 520         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 521         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 522         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 523         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 524         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 525         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 526         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 527         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 528         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 529         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 530         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 531         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 532         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 533         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 534         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 535         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 536         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 537 </enum>
 538
 539 <enum name="a6xx_tp_perfcounter_select">
 540         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 541         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 542         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 543         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 544         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 545         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 546         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 547         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 548         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 549         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 550         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 551         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 552         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 553         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 554         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 555         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 556         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 557         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 558         <value value="18" name="PERF_TP_QUADS_1D"/>
 559         <value value="19" name="PERF_TP_QUADS_2D"/>
 560         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 561         <value value="21" name="PERF_TP_QUADS_3D"/>
 562         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 563         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 564         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 565         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 566         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 567         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 568         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 569         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 570         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 571         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 572         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 573         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 574         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 575         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 576         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 577         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 578         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 579         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 580         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 581         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 582         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 583         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 584         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 585         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 586         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 587         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 588         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 589         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 590         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 591         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 592         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 593         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 594         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 595         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 596         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 597 </enum>
 598
 599 <enum name="a6xx_sp_perfcounter_select">
 600         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 601         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 602         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 603         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 604         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 605         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 606         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 607         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 608         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 609         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 610         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 611         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 612         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 613         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 614         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 615         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 616         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 617         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 618         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 619         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 620         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 621         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 622         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 623         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 624         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 625         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 626         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 627         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 628         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 629         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 630         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 631         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 632         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 633         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 634         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 635         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 636         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 637         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 638         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 639         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 640         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 641         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 642         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 643         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 644         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 645         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 646         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 647         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 648         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 649         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 650         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 651         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 652         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 653         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 654         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 655         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 656         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 657         <value value="57" name="PERF_SP_GPR_READ"/>
 658         <value value="58" name="PERF_SP_GPR_WRITE"/>
 659         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 660         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 661         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 662         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 663         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 664         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 665         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 666         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 667         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 668         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 669         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 670         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 671         <value value="71" name="PERF_SP_WORKING_EU"/>
 672         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 673         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 674         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 675         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 676         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 677         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 678         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 679         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 680         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 681         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 682         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 683         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 684         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 685 </enum>
 686
 687 <enum name="a6xx_rb_perfcounter_select">
 688         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 689         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 690         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 691         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 692         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 693         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 694         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 695         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 696         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 697         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 698         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 699         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 700         <value value="12" name="PERF_RB_Z_READ"/>
 701         <value value="13" name="PERF_RB_Z_WRITE"/>
 702         <value value="14" name="PERF_RB_C_READ"/>
 703         <value value="15" name="PERF_RB_C_WRITE"/>
 704         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 705         <value value="17" name="PERF_RB_Z_PASS"/>
 706         <value value="18" name="PERF_RB_Z_FAIL"/>
 707         <value value="19" name="PERF_RB_S_FAIL"/>
 708         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 709         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 710         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 711         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 712         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 713         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 714         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 715         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 716         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 717         <value value="29" name="PERF_RB_3D_PIXELS"/>
 718         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 719         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 720         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 721         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 722         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 723         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 724         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 725         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 726         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 727         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 728         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 729         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 730         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 731         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 732         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 733         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 734         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 735         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 736 </enum>
 737
 738 <enum name="a6xx_vsc_perfcounter_select">
 739         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 740         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 741         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 742         <value value="3" name="PERF_VSC_EOT_NUM"/>
 743         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 744 </enum>
 745
 746 <enum name="a6xx_ccu_perfcounter_select">
 747         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 748         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 749         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 750         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 751         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 752         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 753         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 754         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 755         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 756         <value value="9" name="PERF_CCU_GMEM_READ"/>
 757         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 758         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 759         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 760         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 761         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 762         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 763         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 764         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 765         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 766         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 767         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 768         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 769         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 770         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 771         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 772         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 773         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 774         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 775         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 776 </enum>
 777
 778 <enum name="a6xx_lrz_perfcounter_select">
 779         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 780         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 781         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 782         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 783         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 784         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 785         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 786         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 787         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 788         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 789         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 790         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 791         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 792         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 793         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 794         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 795         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 796         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 797         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 798         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 799         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 800         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 801         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 802         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 803         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 804         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 805         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 806         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 807 </enum>
 808
 809 <enum name="a6xx_cmp_perfcounter_select">
 810         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 811         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 812         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 813         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 814         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 815         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 816         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 817         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 818         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 819         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 820         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 821         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 822         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 823         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 824         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 825         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 826         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 827         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 828         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 829         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 830         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 831         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 832         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 833         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 834         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 835         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 836         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 837         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 838         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 839         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 840         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 841         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 842         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 843         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 844         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 845         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 846         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 847         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 848         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 849         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 850 </enum>
 851
 852 <!--
 853 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 854 component type/size, so I think it relates to internal format used for
 855 blending?  The one exception is that 16b unorm and 32b float use the
 856 same value... maybe 16b unorm is uncommon enough that it was just easier
 857 to upconvert to 32b float internally?
 858
 859  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 860 16b unorm:   4
 861
 862 32b int:     7
 863 16b int:     6
 864  8b int:     5
 865
 866 32b float:   4
 867 16b float:   3
 868  -->
 869 <enum name="a6xx_2d_ifmt">
 870         <value value="0x10" name="R2D_UNORM8"/>
 871         <value value="0x7"  name="R2D_INT32"/>
 872         <value value="0x6"  name="R2D_INT16"/>
 873         <value value="0x5"  name="R2D_INT8"/>
 874         <value value="0x4"  name="R2D_FLOAT32"/>
 875         <value value="0x3"  name="R2D_FLOAT16"/>
 876         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 877         <value value="0x0"  name="R2D_RAW"/>
 878 </enum>
 879
 880 <domain name="A6XX" width="32">
 881         <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
 882                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 883                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 884                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 885                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 886                 <bitfield name="CP_SW" pos="8"/>
 887                 <bitfield name="CP_HW_ERROR" pos="9"/>
 888                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 889                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 890                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 891                 <bitfield name="CP_IB2" pos="13"/>
 892                 <bitfield name="CP_IB1" pos="14"/>
 893                 <bitfield name="CP_RB" pos="15"/>
 894                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 895                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 896                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 897                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 898                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 899                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 900                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 901                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 902                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 903                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 904                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 905         </bitset>
 906
 907         <bitset name="A6XX_CP_INT">
 908                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 909                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 910                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 911                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 912                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 913                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
 914                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
 915         </bitset>
 916
 917         <reg32 offset="0x0800" name="CP_RB_BASE"/>
 918         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 919         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 920         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
 921         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 922         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 923         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 924         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 925         <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
 926                 <bitfield name="IFPC" pos="0" type="boolean"/>
 927         </reg32>
 928         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 929         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 930         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 931         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
 932         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
 933         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 934         <!-- all the threshold values seem to be in units of quad-dwords: -->
 935         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
 936                 <doc>
 937                         b0..7 seems to contain the size of buffered by not yet processed
 938                         RB level cmdstream.. it's possible that it is a low threshold
 939                         and b8..15 is a high threshold?
 940
 941                         b16..23 identifies where IB1 data starts (and RB data ends?)
 942
 943                         b24..31 identifies where IB2 data starts (and IB1 data ends)
 944                 </doc>
 945                 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
 946                 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
 947                 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
 948                 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
 949         </reg32>
 950         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
 951                 <doc>
 952                         low bits identify where CP_SET_DRAW_STATE stateobj
 953                         processing starts (and IB2 data ends). I'm guessing
 954                         b8 is part of this since (from downstream kgsl):
 955
 956                                 /* ROQ sizes are twice as big on a640/a680 than on a630 */
 957                                 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
 958                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
 959                                         kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
 960                                 } ...
 961                 </doc>
 962                 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
 963                 <!-- total ROQ size: -->
 964                 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
 965         </reg32>
 966         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
 967         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
 968         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
 969         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
 970         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
 971
 972         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
 973                 <reg32 offset="0x0" name="REG" type="uint"/>
 974         </array>
 975         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
 976                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
 977         </array>
 978
 979         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
 980         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
 981         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
 982         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
 983         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
 984         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
 985         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
 986         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
 987         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
 988         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
 989         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
 990         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
 991         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
 992         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
 993         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
 994         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
 995         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
 996         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
 997         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
 998         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
 999         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1000         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1001         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1002         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1003         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1004         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1005         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1006         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1007         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1008         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1009         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1010         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1011         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1012         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1013         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1014         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1015         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1016         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1017         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1018         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1019         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1020         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1021         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1022         <!-- SDS == CP_SET_DRAW_STATE: -->
1023         <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1024         <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1025         <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1026         <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1027         <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1028         <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1029         <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1030         <!--
1031         There are probably similar registers for RB and SDS, teasing out SDS will
1032         take a slightly better test case..
1033          -->
1034         <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1035                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1036                 <bitfield name="REM" low="16" high="31"/>
1037         </reg32>
1038         <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1039                 <doc>number of remaining dwords incl current dword being consumed?</doc>
1040                 <bitfield name="REM" low="16" high="31"/>
1041         </reg32>
1042         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1043         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1044         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1045         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1046         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1047         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1048         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1049         <reg32 offset="0x0210" name="RBBM_STATUS">
1050                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1051                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1052                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1053                 <bitfield high="20" low="20" name="VSC_BUSY" />
1054                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1055                 <bitfield high="18" low="18" name="SP_BUSY" />
1056                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1057                 <bitfield high="16" low="16" name="VPC_BUSY" />
1058                 <bitfield high="15" low="15" name="VFD_BUSY" />
1059                 <bitfield high="14" low="14" name="TESS_BUSY" />
1060                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1061                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1062                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1063                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1064                 <bitfield high="9" low="9" name="A2D_BUSY" />
1065                 <bitfield high="8" low="8" name="CCU_BUSY" />
1066                 <bitfield high="7" low="7" name="RB_BUSY" />
1067                 <bitfield high="6" low="6" name="RAS_BUSY" />
1068                 <bitfield high="5" low="5" name="TSE_BUSY" />
1069                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1070                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1071                 <bitfield high="2" low="2" name="CP_BUSY" />
1072                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1073                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1074         </reg32>
1075         <reg32 offset="0x0213" name="RBBM_STATUS3">
1076                 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1077         </reg32>
1078         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1079         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1080         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1081         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1082         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1083         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1084         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1085         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1086         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1087         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1088         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1089         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1090         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1091         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1092         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1093         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1094         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1095         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1096         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1097         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1098         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1099         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1100         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1101         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1102         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1103         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1104         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1105         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1106         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1107         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1108         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1109         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1110         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1111         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1112         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1113         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1114         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1115         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1116         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1117         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1118         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1119         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1120         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1121         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1122         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1123         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1124         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1125         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1126         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1127         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1128         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1129         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1130         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1131         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1132         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1133         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1134         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1135         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1136         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1137         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1138         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1139         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1140         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1141         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1142         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1143         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1144         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1145         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1146         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1147         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1148         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1149         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1150         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1151         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1152         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1153         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1154         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1155         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1156         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1157         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1158         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1159         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1160         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1161         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1162         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1163         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1164         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1165         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1166         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1167         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1168         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1169         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1170         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1171         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1172         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1173         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1174         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1175         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1176         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1177         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1178         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1179         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1180         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1181         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1182         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1183         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1184         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1185         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1186         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1187         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1188         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1189         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1190         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1191         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1192         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1193         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1194         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1195         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1196         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1197         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1198         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1199         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1200         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1201         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1202         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1203         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1204         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1205         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1206         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1207         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1208         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1209         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1210         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1211         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1212         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1213         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1214         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1215         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1216         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1217         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1218         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1219         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1220         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1221         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1222         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1223         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1224         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1225         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1226         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1227         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1228         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1229         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1230         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1231         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1232         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1233         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1234         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1235         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1236         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1237         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1238         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1239         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1240         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1241         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1242         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1243         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1244         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1245         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1246         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1247         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1248         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1249         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1250         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1251         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1252         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1253         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1254         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1255         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1256         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1257         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1258         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1259         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1260         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1261         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1262         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1263         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1264         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1265         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1266         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1267         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1268         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1269         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1270         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1271         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1272         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1273         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1274         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1275         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1276         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1277         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1278         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1279         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1280         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1281         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1282         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1283         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1284         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1285         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1286         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1287         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1288         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1289         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1290         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1291         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1292         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1293         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1294         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1295         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1296         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1297         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1298         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1299         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1300         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1301         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1302         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1303         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1304         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1305         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1306         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1307         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1308         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1309         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1310         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1311         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1312         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1313         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1314         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1315         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1316         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1317         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1318         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1319         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1320         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1321         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1322         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1323         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1324         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1325         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1326         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1327         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1328         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1329         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1330         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1331         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1332         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1333         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1334         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1335         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1336         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1337         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1338         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1339         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1340         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1341         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1342
1343         <!---
1344             This block of registers aren't tied to perf counters. They
1345             count various geometry stats, for example number of
1346             vertices in, number of primnitives assembled etc.
1347         -->
1348
1349         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1350         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1351         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1352         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1353         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1354         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1355         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1356         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1357         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1358         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1359         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1360         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1361         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1362         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1363         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1364         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1365         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1366         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1367         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1368         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1369         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1370         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1371
1372         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1373         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1374         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1375         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1376         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1377         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1378         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1379         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1380         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1381         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1382         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1383         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1384         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1385         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1386         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1387         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1388         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1389         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1390         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1391         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1392         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1393         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1394         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1395         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1396         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1397         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1398         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1399         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1400         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1401         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1402         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1403         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1404         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1405         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1406         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1407         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1408         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1409         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1410         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1411         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1412         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1413         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1414         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1415         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1416         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1417         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1418         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1419         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1420         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1421         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1422         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1423         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1424         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1425         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1426         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1427         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1428         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1429         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1430         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1431         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1432         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1433         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1434         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1435         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1436         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1437         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1438         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1439         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1440         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1441         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1442         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1443         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1444         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1445         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1446         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1447         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1448         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1449         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1450         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1451         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1452         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1453         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1454         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1455         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1456         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1457         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1458         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1459         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1460         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1461         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1462         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1463         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1464         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1465         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1466         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1467         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1468         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1469         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1470         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1471         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1472         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1473         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1474         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1475         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1476         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1477         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1478         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1479         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1480         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1481         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1482         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1483         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1484         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1485         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1486         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1487         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1488         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1489         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1490         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1491         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1492         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1493         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1494         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1495         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1496         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1497                 <bitfield high="7" low="0" name="PING_INDEX"/>
1498                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1499         </reg32>
1500         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1501                 <bitfield high="5" low="0" name="TRACEEN"/>
1502                 <bitfield high="14" low="12" name="GRANU"/>
1503                 <bitfield high="31" low="28" name="SEGT"/>
1504         </reg32>
1505         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1506                 <bitfield high="27" low="24" name="ENABLE"/>
1507         </reg32>
1508         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1509         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1510         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1511         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1512         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1513         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1514         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1515         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1516         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1517                 <bitfield high="3" low="0" name="BYTEL0"/>
1518                 <bitfield high="7" low="4" name="BYTEL1"/>
1519                 <bitfield high="11" low="8" name="BYTEL2"/>
1520                 <bitfield high="15" low="12" name="BYTEL3"/>
1521                 <bitfield high="19" low="16" name="BYTEL4"/>
1522                 <bitfield high="23" low="20" name="BYTEL5"/>
1523                 <bitfield high="27" low="24" name="BYTEL6"/>
1524                 <bitfield high="31" low="28" name="BYTEL7"/>
1525         </reg32>
1526         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1527                 <bitfield high="3" low="0" name="BYTEL8"/>
1528                 <bitfield high="7" low="4" name="BYTEL9"/>
1529                 <bitfield high="11" low="8" name="BYTEL10"/>
1530                 <bitfield high="15" low="12" name="BYTEL11"/>
1531                 <bitfield high="19" low="16" name="BYTEL12"/>
1532                 <bitfield high="23" low="20" name="BYTEL13"/>
1533                 <bitfield high="27" low="24" name="BYTEL14"/>
1534                 <bitfield high="31" low="28" name="BYTEL15"/>
1535         </reg32>
1536         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1537         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1538         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1539         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1540         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1541         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1542         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1543         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1544         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1545         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1546         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1547         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1548         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1549         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1550         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1551         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1552         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1553         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1554         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1555         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1556         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1557         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1558         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1559         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1560         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1561         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1562         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1563         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1564         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1565         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1566         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1567         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1568         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1569         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1570         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1571         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1572         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1573         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1574         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1575         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1576         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1577         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1578         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1579         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1580         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1581         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1582         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1583         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1584         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1585         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1586         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1587         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1588         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1589         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1590         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1591         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1592         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1593         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1594         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1595         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1596         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1597         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1598         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1599         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1600         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1601         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1602         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1603         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1604         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1605         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1606         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1607         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1608         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1609         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1610         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1611         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1612         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1613         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1614         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1615         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1616         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1617         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1618         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1619         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1620         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1621         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1622         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1623         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1624                 <bitfield high="7" low="0" name="PERFSEL"/>
1625         </reg32>
1626         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1627         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1628         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1629         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1630         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1631         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1632         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1633         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1634         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1635         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1636         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1637         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1638         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1639         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1640         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1641         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1642         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1643         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1644         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1645         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1646         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1647         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1648         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1649         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1650         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1651         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1652         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1653         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1654         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1655         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1656         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1657         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1658         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1659         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1660         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1661         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1662         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1663         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1664         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1665         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1666         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1667         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1668         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1669         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1670         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1671         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1672         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1673         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1674         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1675         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1676         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1677         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1678         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1679         <reg32 offset="0x3001" name="VBIF_CLKON">
1680                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1681         </reg32>
1682         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1683         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1684         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1685         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1686         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1687         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1688                 <bitfield low="0" high="3" name="DATA_SEL"/>
1689         </reg32>
1690         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1691         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1692                 <bitfield low="0" high="8" name="DATA_SEL"/>
1693         </reg32>
1694         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1695         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1696         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1697         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1698         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1699         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1700         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1701         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1702         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1703         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1704         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1705         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1706         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1707         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1708         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1709         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1710         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1711         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1712         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1713         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1714         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1715         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1716
1717         <!-- move/rename these.. -->
1718
1719         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1720         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1721         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1722
1723         <!-- same as RB_BIN_CONTROL -->
1724         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1725                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1726                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1727                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1728                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1729         </reg32>
1730
1731         <!--
1732                 from offset it seems it should be RB, but weird to duplicate
1733                 other regs from same block??
1734          -->
1735         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1736                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1737                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1738         </reg32>
1739
1740         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1741                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1742                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1743         </reg32>
1744         <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1745         <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1746         <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1747         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1748                 <bitfield name="NX" low="1" high="10" type="uint"/>
1749                 <bitfield name="NY" low="11" high="20" type="uint"/>
1750         </reg32>
1751         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1752                 <reg32 offset="0x0" name="REG">
1753                         <doc>
1754                                 Configures the mapping between VSC_PIPE buffer and
1755                                 bin, X/Y specify the bin index in the horiz/vert
1756                                 direction (0,0 is upper left, 0,1 is leftmost bin
1757                                 on second row, and so on).  W/H specify the number
1758                                 of bins assigned to this VSC_PIPE in the horiz/vert
1759                                 dimension.
1760                         </doc>
1761                         <bitfield name="X" low="0" high="9" type="uint"/>
1762                         <bitfield name="Y" low="10" high="19" type="uint"/>
1763                         <bitfield name="W" low="20" high="25" type="uint"/>
1764                         <bitfield name="H" low="26" high="31" type="uint"/>
1765                 </reg32>
1766         </array>
1767         <!--
1768         HW binning primitive & draw streams, which enable draws and primitives
1769         within a draw to be skipped in the main tile pass.  See:
1770         https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1771
1772         Compared to a5xx and earlier, we just program the address of the first
1773         stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1774          -->
1775         <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1776         <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1777         <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1778         <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1779         <reg32 offset="0x0c33" name="VSC_PRIM_STRM_ARRAY_PITCH" shr="4" type="uint"/>
1780         <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1781         <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1782         <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1783         <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1784         <reg32 offset="0x0c37" name="VSC_DRAW_STRM_ARRAY_PITCH" shr="4" type="uint"/>
1785
1786         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1787                 <doc>
1788                         Seems to be a bitmap of which tiles mapped to the VSC
1789                         pipe contain geometry.
1790
1791                         I suppose we can connect a maximum of 32 tiles to a
1792                         single VSC pipe.
1793                 </doc>
1794                 <reg32 offset="0x0" name="REG"/>
1795         </array>
1796
1797         <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1798                 <doc>
1799                         Has the size of data written to corresponding VSC_PRIM_STRM
1800                         buffer.
1801                 </doc>
1802                 <reg32 offset="0x0" name="REG"/>
1803         </array>
1804
1805         <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1806                 <doc>
1807                         Has the size of data written to corresponding VSC pipe, ie.
1808                         same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1809                 </doc>
1810                 <reg32 offset="0x0" name="REG"/>
1811         </array>
1812
1813         <!-- always 0x03200000 ? -->
1814         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1815
1816         <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1817                 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1818                 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1819                 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1820                 <!-- set with depthClampEnable, not clear what it does -->
1821                 <bitfield name="UNK5" pos="5" type="boolean"/>
1822                 <!-- controls near z clip behavior (set for vulkan) -->
1823                 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1824                 <!-- guess based on a3xx and meaning of bits 8 and 9
1825                      if the guess is right then this is related to point sprite clipping -->
1826                 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1827                 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1828                 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1829         </reg32>
1830         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1831         <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
1832         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1833
1834         <enum name="a6xx_layer_type">
1835           <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
1836           <value value="0x1" name="LAYER_3D"/>
1837           <value value="0x2" name="LAYER_CUBEMAP"/>
1838           <value value="0x3" name="LAYER_2D_ARRAY"/>
1839         </enum>
1840
1841         <!-- index of highest layer that can be written to via gl_Layer -->
1842         <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
1843
1844         <reg32 offset="0x8005" name="GRAS_CNTL">
1845                 <!-- see also RB_RENDER_CONTROL0 -->
1846                 <bitfield name="VARYING" pos="0" type="boolean"/>
1847                 <!-- b1 set for interpolateAtCentroid() -->
1848                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1849                 <!-- b2 set instead of b0 when running in per-sample mode -->
1850                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1851                 <!--
1852                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1853                 mode, and frag_face
1854                  -->
1855                 <bitfield name="SIZE" pos="3" type="boolean"/>
1856                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1857                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1858                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1859         </reg32>
1860         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1861                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1862                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1863         </reg32>
1864         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1865         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1866         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1867         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1868         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1869         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1870
1871         <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
1872         <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
1873         <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
1874
1875         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1876                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1877                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1878                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1879                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1880                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1881                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1882                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1883         </reg32>
1884         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1885                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1886                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1887         </reg32>
1888         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1889
1890         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1891                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1892         </reg32>
1893         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1894         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1895         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1896         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1897         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1898                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1899         </reg32>
1900
1901         <!-- always 0x0 -->
1902         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1903
1904         <!-- always 0x0 ? -->
1905         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1906
1907         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1908                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1909         </reg32>
1910
1911         <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
1912
1913         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1914
1915         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1916                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1917         </reg32>
1918         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1919                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1920                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1921         </reg32>
1922
1923         <bitset name="a6xx_sample_config" inline="yes">
1924                 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1925         </bitset>
1926
1927         <bitset name="a6xx_sample_locations" inline="yes">
1928                 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1929                 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1930                 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1931                 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1932                 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1933                 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1934                 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1935                 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1936         </bitset>
1937
1938         <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1939         <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1940         <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1941
1942         <!-- always 0x0 -->
1943         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1944
1945         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1946         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1947         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1948         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1949         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1950         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1951
1952         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1953                 <!--
1954                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1955                 look when we get around to enabling lrz
1956                  -->
1957                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1958                 <doc>LRZ write also disabled for blend/etc.</doc>
1959                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1960                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1961                 <bitfield name="GREATER" pos="2" type="boolean"/>
1962                 <bitfield name="UNK3" pos="3" type="boolean"/>
1963                 <!-- set when depth-test + depth-write enabled -->
1964                 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
1965         </reg32>
1966         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
1967         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1968                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1969         </reg32>
1970         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1971         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1972         <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
1973         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1974                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
1975                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
1976         </reg32>
1977         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1978         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1979         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
1980
1981         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1982                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1983         </reg32>
1984
1985         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
1986
1987         <enum name="a6xx_rotation">
1988           <value value="0x0" name="ROTATE_0"/>
1989           <value value="0x1" name="ROTATE_90"/>
1990           <value value="0x2" name="ROTATE_180"/>
1991           <value value="0x3" name="ROTATE_270"/>
1992           <value value="0x4" name="ROTATE_HFLIP"/>
1993           <value value="0x5" name="ROTATE_VFLIP"/>
1994         </enum>
1995
1996         <bitset name="a6xx_2d_blit_cntl" inline="yes">
1997                 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
1998                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
1999                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2000                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2001
2002                 <bitfield name="UNK" low="17" high="18" type="uint"/>
2003
2004                 <!-- required when blitting D24S8/D24X8 -->
2005                 <bitfield name="D24S8" pos="19" type="boolean"/>
2006                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2007                 <bitfield name="MASK" low="20" high="23"/>
2008                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2009         </bitset>
2010
2011         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2012
2013         <!-- could be the src coords are fixed point? -->
2014         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2015                 <bitfield name="X" low="8" high="31" type="int"/>
2016         </reg32>
2017         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2018                 <bitfield name="X" low="8" high="31" type="int"/>
2019         </reg32>
2020         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2021                 <bitfield name="Y" low="8" high="31" type="int"/>
2022         </reg32>
2023         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2024                 <bitfield name="Y" low="8" high="31" type="int"/>
2025         </reg32>
2026
2027         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2028         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2029
2030         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2031         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2032
2033         <!-- always 0x880 ? -->
2034         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2035
2036         <!-- same as GRAS_BIN_CONTROL: -->
2037         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2038                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2039                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2040                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2041                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2042         </reg32>
2043         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2044                 <!-- always set: ?? -->
2045                 <bitfield name="UNK4" pos="4" type="boolean"/>
2046                 <!-- set during binning pass: -->
2047                 <bitfield name="BINNING" pos="7" type="boolean"/>
2048                 <!-- bit seems to be set whenever depth buffer enabled: -->
2049                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2050                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2051                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2052         </reg32>
2053         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2054                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2055         </reg32>
2056         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2057                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2058                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2059         </reg32>
2060
2061         <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2062         <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2063         <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2064
2065         <!--
2066         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2067         name comes from kernel and is probably right)
2068          -->
2069         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2070                 <!-- see also GRAS_CNTL -->
2071                 <bitfield name="VARYING" pos="0" type="boolean"/>
2072                 <!-- b1 set for interpolateAtCentroid() -->
2073                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2074                 <!-- b2 set instead of b0 when running in per-sample mode -->
2075                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2076                 <!--
2077                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2078                 mode, and frag_face
2079                  -->
2080                 <bitfield name="SIZE" pos="3" type="boolean"/>
2081                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2082                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2083                 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2084                 <bitfield name="UNK10" pos="10" type="boolean"/>
2085         </reg32>
2086         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2087                 <!-- enable bits for various FS sysvalue regs: -->
2088                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2089                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2090                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2091                 <!-- b4 and b5 set in per-sample mode: -->
2092                 <bitfield name="UNK4" pos="4" type="boolean"/>
2093                 <bitfield name="UNK5" pos="5" type="boolean"/>
2094                 <bitfield name="SIZE" pos="6" type="boolean"/>
2095         </reg32>
2096
2097         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2098                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2099                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2100                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2101         </reg32>
2102         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2103                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2104         </reg32>
2105         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2106                 <bitfield name="RT0" low="0" high="3"/>
2107                 <bitfield name="RT1" low="4" high="7"/>
2108                 <bitfield name="RT2" low="8" high="11"/>
2109                 <bitfield name="RT3" low="12" high="15"/>
2110                 <bitfield name="RT4" low="16" high="19"/>
2111                 <bitfield name="RT5" low="20" high="23"/>
2112                 <bitfield name="RT6" low="24" high="27"/>
2113                 <bitfield name="RT7" low="28" high="31"/>
2114         </reg32>
2115         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2116                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2117                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2118                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2119                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2120                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2121                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2122                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2123                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2124         </reg32>
2125         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2126                 <!-- Same as SP_SRGB_CNTL -->
2127                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2128                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2129                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2130                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2131                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2132                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2133                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2134                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2135         </reg32>
2136
2137         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2138                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2139         </reg32>
2140         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2141
2142         <!-- always 0x0 ? -->
2143         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2144         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2145         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2146         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2147         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2148         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2149         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2150
2151         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2152                 <reg32 offset="0x0" name="CONTROL">
2153                         <bitfield name="BLEND" pos="0" type="boolean"/>
2154                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2155                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2156                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2157                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2158                 </reg32>
2159                 <reg32 offset="0x1" name="BLEND_CONTROL">
2160                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2161                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2162                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2163                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2164                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2165                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2166                 </reg32>
2167                 <reg32 offset="0x2" name="BUF_INFO">
2168                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2169                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2170                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2171                 </reg32>
2172                 <!--
2173                 at least in gmem, things seem to be aligned to pitch of 64..
2174                 maybe an artifact of tiled format used in gmem?
2175                  -->
2176                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2177                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2178                 <!--
2179                 Compared to a5xx and before, we configure both a GMEM base and
2180                 external base.  Not sure if this is to facilitate GMEM save/
2181                 restore for context switch, or just to simplify state setup to
2182                 not have to care about GMEM vs BYPASS mode.
2183                  -->
2184                 <reg32 offset="0x5" name="BASE_LO"/>
2185                 <reg32 offset="0x6" name="BASE_HI"/>
2186
2187                 <reg64 offset="0x5" name="BASE" type="waddress"/>
2188
2189                 <reg32 offset="0x7" name="BASE_GMEM"/>
2190         </array>
2191
2192         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2193         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2194         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2195         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2196         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2197                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2198                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2199                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2200         </reg32>
2201         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2202                 <!-- per-mrt enable bit -->
2203                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2204                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2205                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2206                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2207                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2208         </reg32>
2209         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2210                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2211         </reg32>
2212
2213         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2214                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2215                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2216                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2217                 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2218                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2219                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2220         </reg32>
2221         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2222         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2223                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2224         </reg32>
2225 <!-- probably: -->
2226         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2227                 <doc>stride of depth/stencil buffer</doc>
2228         </reg32>
2229         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2230                 <doc>size of layer</doc>
2231         </reg32>
2232         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2233         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2234         <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
2235         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2236
2237         <!-- always 0x0 ? -->
2238         <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
2239         <!-- always 0x0 ? -->
2240         <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
2241
2242         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2243                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2244                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2245                 <!--
2246                         set for stencil operations that require read from stencil
2247                         buffer, but not for example for stencil clear (which does
2248                         not require read).. so guessing this is analogous to
2249                         READ_DEST_ENABLE for color buffer..
2250                  -->
2251                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2252                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2253                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2254                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2255                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2256                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2257                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2258                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2259                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2260         </reg32>
2261         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2262                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2263         </reg32>
2264         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2265                 <doc>stride of stencil buffer</doc>
2266         </reg32>
2267         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2268                 <doc>size of layer</doc>
2269         </reg32>
2270         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2271         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2272         <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
2273         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2274         <reg32 offset="0x8887" name="RB_STENCILREF">
2275                 <bitfield name="REF" low="0" high="7"/>
2276                 <bitfield name="BFREF" low="8" high="15"/>
2277         </reg32>
2278         <reg32 offset="0x8888" name="RB_STENCILMASK">
2279                 <bitfield name="MASK" low="0" high="7"/>
2280                 <bitfield name="BFMASK" low="8" high="15"/>
2281         </reg32>
2282         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2283                 <bitfield name="WRMASK" low="0" high="7"/>
2284                 <bitfield name="BFWRMASK" low="8" high="15"/>
2285         </reg32>
2286         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2287         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2288                 <bitfield name="COPY" pos="1" type="boolean"/>
2289         </reg32>
2290
2291         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2292                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2293         </reg32>
2294
2295         <!-- clamps depth value for depth test/write -->
2296         <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2297         <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2298
2299         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2300         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2301         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2302
2303         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2304                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2305         </reg32>
2306         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2307         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2308         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2309                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2310                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2311                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2312                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2313                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2314         </reg32>
2315         <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
2316         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2317         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2318         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2319         <!-- array-pitch is size of layer -->
2320         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2321         <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
2322         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2323         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2324         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2325                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2326                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2327         </reg32>
2328
2329         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2330         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2331         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2332         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2333
2334         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2335         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2336                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2337                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2338                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2339                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2340                 <doc>
2341                         For clearing depth/stencil
2342                                 1 - depth
2343                                 2 - stencil
2344                                 3 - depth+stencil
2345                         For clearing color buffer:
2346                                 then probably a component mask, I always see 0xf
2347                 </doc>
2348                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2349         </reg32>
2350
2351         <!-- always 0x0 ? -->
2352         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2353
2354         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2355         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2356         <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
2357         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2358                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2359                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2360         </reg32>
2361         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2362                 <reg32 offset="0" name="ADDR_LO"/>
2363                 <reg32 offset="1" name="ADDR_HI"/>
2364                 <reg64 offset="0" name="ADDR" type="waddress"/>
2365                 <reg32 offset="2" name="PITCH">
2366                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2367                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2368                 </reg32>
2369         </array>
2370         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2371         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2372
2373         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2374         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2375
2376         <bitset name="a6xx_2d_surf_info" inline="yes">
2377                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2378                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2379                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2380                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2381                 <bitfield name="SRGB" pos="13" type="boolean"/>
2382                 <!-- the rest is only for src -->
2383                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2384                 <bitfield name="FILTER" pos="16" type="boolean"/>
2385                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2386                 <bitfield name="UNK20" pos="20" type="boolean"/>
2387                 <bitfield name="UNK22" pos="22" type="boolean"/>
2388         </bitset>
2389
2390         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2391         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2392         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2393         <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
2394         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2395                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2396         </reg32>
2397
2398         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2399         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2400         <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
2401         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2402                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2403                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2404         </reg32>
2405
2406         <!-- unlike a5xx, these are per channel values rather than packed -->
2407         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2408         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2409         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2410         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2411
2412         <!-- always 0x1 ? -->
2413         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2414
2415         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2416
2417         <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2418                 <!-- offset into GMEM for something.
2419                         important for sysmem path
2420                         BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2421                         blob values for GMEM path (note: close to GMEM size):
2422                         a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
2423                         SYSMEM path values:
2424                         a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
2425                 -->
2426                 <bitfield name="OFFSET" low="23" high="31" shr="12" type="uint"/>
2427                 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2428                 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2429         </reg32>
2430
2431         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2432
2433         <!-- always 0x00ffff00 ? */ -->
2434         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2435         <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
2436         <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
2437
2438         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2439
2440         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2441                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2442         </reg32>
2443
2444         <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
2445         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2446         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2447
2448         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2449                 <reg32 offset="0x0" name="MODE"/>
2450         </array>
2451         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2452                 <reg32 offset="0x0" name="MODE"/>
2453         </array>
2454
2455         <!-- always 0x0 -->
2456         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2457         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2458
2459         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2460                 <!-- one bit per varying component: -->
2461                 <reg32 offset="0" name="DISABLE"/>
2462         </array>
2463
2464         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2465                 <!-- always 0x10000 when SO enabled.. -->
2466                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2467         </reg32>
2468         <reg32 offset="0x9217" name="VPC_SO_PROG">
2469                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2470                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2471                 <bitfield name="A_EN" pos="11" type="boolean"/>
2472                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2473                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2474                 <bitfield name="B_EN" pos="23" type="boolean"/>
2475         </reg32>
2476
2477         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2478         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2479
2480         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2481                 <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
2482                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2483                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2484                 <reg32 offset="2" name="BUFFER_SIZE"/>
2485                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2486                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2487                 <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
2488                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2489                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2490         </array>
2491
2492         <!-- always 0x0 ? -->
2493         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2494                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2495         </reg32>
2496
2497         <!-- always 0x0 ? -->
2498         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2499
2500         <reg32 offset="0x9301" name="VPC_PACK">
2501                 <doc>
2502                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2503                         plus # of transform-feedback (streamout) varyings if using the
2504                         hw streamout (rather than stg instructions in shader)
2505                 </doc>
2506                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2507                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2508                 <!--
2509                 This seems to be the OUTLOC for the psize output.  It could possibly
2510                 be the max-OUTLOC position, but it is only set when VS writes psize
2511                 (and blob always puts psize at highest OUTLOC)
2512                  -->
2513                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2514         </reg32>
2515
2516         <reg32 offset="0x9302" name="VPC_PACK_GS">
2517                 <doc>
2518                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2519                         plus # of transform-feedback (streamout) varyings if using the
2520                         hw streamout (rather than stg instructions in shader)
2521                 </doc>
2522                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2523                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2524                 <!--
2525                 This seems to be the OUTLOC for the psize output.  It could possibly
2526                 be the max-OUTLOC position, but it is only set when VS writes psize
2527                 (and blob always puts psize at highest OUTLOC)
2528                  -->
2529                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2530         </reg32>
2531
2532         <reg32 offset="0x9303" name="VPC_PACK_3">
2533                 <doc>
2534                         domain shader version of VPC_PACK
2535                 </doc>
2536                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2537                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2538                 <!--
2539                 This seems to be the OUTLOC for the psize output.  It could possibly
2540                 be the max-OUTLOC position, but it is only set when VS writes psize
2541                 (and blob always puts psize at highest OUTLOC)
2542                  -->
2543                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2544         </reg32>
2545
2546         <reg32 offset="0x9304" name="VPC_CNTL_0">
2547                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2548                 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2549                 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2550                 <bitfield name="VARYING" pos="16" type="boolean"/>
2551                 <bitfield name="UNKLOC" low="24" high="31" type="uint"/>
2552         </reg32>
2553
2554         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2555                 <bitfield name="BUF0" pos="0" type="boolean"/>
2556                 <bitfield name="BUF1" pos="3" type="boolean"/>
2557                 <bitfield name="BUF2" pos="6" type="boolean"/>
2558                 <bitfield name="BUF3" pos="9" type="boolean"/>
2559                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2560         </reg32>
2561         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2562                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2563         </reg32>
2564
2565         <!-- always 0x0 ? -->
2566         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2567         <!-- always 0x0 ? -->
2568         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2569
2570         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2571
2572         <!-- always 0x0 ? -->
2573         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2574
2575         <enum name="a6xx_tess_spacing">
2576           <value value="0x0" name="TESS_EQUAL"/>
2577           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2578           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2579         </enum>
2580
2581         <enum name="a6xx_tess_output">
2582           <value value="0x0" name="TESS_POINTS"/>
2583           <value value="0x1" name="TESS_LINES"/>
2584           <value value="0x2" name="TESS_CW_TRIS"/>
2585           <value value="0x3" name="TESS_CCW_TRIS"/>
2586         </enum>
2587
2588         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2589           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2590           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2591         </reg32>
2592
2593         <!-- probably: -->
2594         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2595         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2596
2597         <!-- always 0x1 ? -->
2598         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2599
2600         <!-- probably a mirror of VFD_CONTROL_6 -->
2601         <reg32 offset="0x9806" name="PC_PRIMID_CNTL">
2602                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2603         </reg32>
2604
2605         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2606         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2607
2608         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2609
2610         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2611                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2612                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2613                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2614         </reg32>
2615         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2616                 <doc>
2617                         vertex shader
2618
2619                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2620                         plus # of transform-feedback (streamout) varyings if using the
2621                         hw streamout (rather than stg instructions in shader)
2622                 </doc>
2623                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2624                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2625         </reg32>
2626
2627         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2628                 <doc>
2629                   geometry shader
2630                 </doc>
2631                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2632                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2633                 <bitfield name="LAYER" pos="9" type="boolean"/>
2634                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2635         </reg32>
2636
2637         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2638                 <doc>
2639                         hull shader?
2640
2641                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2642                         plus # of transform-feedback (streamout) varyings if using the
2643                         hw streamout (rather than stg instructions in shader)
2644                 </doc>
2645                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2646                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2647         </reg32>
2648         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2649                 <doc>
2650                         domain shader
2651                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2652                         plus # of transform-feedback (streamout) varyings if using the
2653                         hw streamout (rather than stg instructions in shader)
2654                 </doc>
2655                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2656                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2657         </reg32>
2658
2659         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2660                 <doc>
2661                   geometry shader
2662                 </doc>
2663                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2664                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2665                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2666         </reg32>
2667
2668         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2669                 <doc>
2670                   size in vec4s of per-primitive storage for gs
2671                 </doc>
2672                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2673         </reg32>
2674
2675         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2676
2677         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2678         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2679
2680         <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2681         <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2682                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2683                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
2684         </reg32>
2685         <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
2686         <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
2687         <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
2688         <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
2689
2690         <!-- always 0x0 -->
2691         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2692
2693         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2694                 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2695                 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2696         </reg32>
2697         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2698                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2699                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2700                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2701         </reg32>
2702         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2703                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2704                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2705         </reg32>
2706         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2707                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2708                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2709                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2710         </reg32>
2711         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2712         </reg32>
2713         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2714                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2715         </reg32>
2716         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2717                 <!--
2718                         True if gl_PrimitiveID is read via the FS and there is
2719                         no matching write from the GS, and therefore it needs to
2720                         be passed through via fixed-function logic.
2721                 -->
2722                 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2723         </reg32>
2724
2725         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2726                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2727         </reg32>
2728
2729         <!-- always 0x0 ? -->
2730         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2731         <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2732                 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2733                 <bitfield name="VERTEX" pos="0" type="boolean"/>
2734                 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2735                 <bitfield name="INSTANCE" pos="1" type="boolean"/>
2736         </reg32>
2737
2738         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2739         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2740         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2741                 <reg64 offset="0x0" name="BASE" type="address"/>
2742                 <reg32 offset="0x0" name="BASE_LO"/>
2743                 <reg32 offset="0x1" name="BASE_HI"/>
2744                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2745                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2746         </array>
2747         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2748                 <reg32 offset="0x0" name="INSTR">
2749                         <!-- IDX and byte OFFSET into VFD_FETCH -->
2750                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2751                         <bitfield name="OFFSET" low="5" high="16"/>
2752                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2753                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2754                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2755                         <bitfield name="UNK30" pos="30" type="boolean"/>
2756                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2757                 </reg32>
2758                 <reg32 offset="0x1" name="STEP_RATE"/>
2759         </array>
2760         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2761                 <reg32 offset="0x0" name="INSTR">
2762                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2763                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2764                 </reg32>
2765         </array>
2766
2767         <!-- always 0x1 ? -->
2768         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2769
2770         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2771                 <!--
2772                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2773                 used registers is a bit odd too:
2774                         - used (half): 0-15 68-179 (cnt=128, max=179)
2775                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2776                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2777                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2778                 then:
2779                         - used (merged): 0-191 (cnt=192, max=191)
2780                 So I think if b31 is set, then the half precision registers overlap
2781                 the full precision registers.  (Which seems like a pretty sensible
2782                 feature, actually I'm not sure when you *wouldn't* want to use that,
2783                 since it gives register allocation more flexibility)
2784                  -->
2785                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2786                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2787                 <!-- seems to be nesting level for flow control:.. -->
2788                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2789                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2790                 <bitfield name="VARYING" pos="22" type="boolean"/>
2791                 <!-- set when dFdxFine/dFdyFine is used -->
2792                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2793                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2794                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2795         </bitset>
2796
2797         <bitset name="a6xx_sp_xs_config" inline="yes">
2798                 <!--
2799                 Each of these are set if the given resource type is used
2800                 with the Vulkan/bindless binding model.
2801                 -->
2802                 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2803                 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2804                 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2805                 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2806
2807                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2808                 <!--
2809                 number of textures and samplers.. these might be swapped, with GL I
2810                 always see the same value for both.
2811                  -->
2812                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2813                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2814                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2815         </bitset>
2816
2817         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2818         <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex">
2819                 <!--
2820                 bitmask of true/false conditions for VS brac.N instructions,
2821                 bit N corresponds to brac.N
2822                  -->
2823         </reg32>
2824         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2825                 <!-- # of VS outputs including pos/psize -->
2826                 <bitfield name="VSOUT" low="0" high="5" type="uint"/>
2827         </reg32>
2828         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2829                 <reg32 offset="0x0" name="REG">
2830                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2831                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2832                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2833                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2834                 </reg32>
2835         </array>
2836         <!--
2837         Starting with a5xx, position/psize outputs from shader end up in the
2838         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2839         the last entries too, except when gl_PointCoord is used, blob inserts
2840         an extra varying after, but with a lower OUTLOC position.  If present,
2841         psize is last, preceded by position.
2842          -->
2843         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2844                 <reg32 offset="0x0" name="REG">
2845                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2846                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2847                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2848                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2849                 </reg32>
2850         </array>
2851
2852         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2853         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2854         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2855         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2856         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2857         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2858
2859         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2860         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2861         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2862         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2863         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2864         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2865         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2866         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2867
2868         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2869         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2870                 <!-- # of DS outputs including pos/psize -->
2871                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2872         </reg32>
2873         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2874                 <reg32 offset="0x0" name="REG">
2875                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2876                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2877                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2878                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2879                 </reg32>
2880         </array>
2881         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2882                 <reg32 offset="0x0" name="REG">
2883                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2884                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2885                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2886                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2887                 </reg32>
2888         </array>
2889
2890         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2891         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2892         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2893         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2894         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2895         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2896
2897         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2898         <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE">
2899                 <!-- size of output of previous stage -->
2900         </reg32>
2901         <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex">
2902                 <!--
2903                 bitmask of true/false conditions for FS brac.N instructions,
2904                 bit N corresponds to brac.N
2905                  -->
2906         </reg32>
2907
2908         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
2909                 <!-- # of VS outputs including pos/psize -->
2910                 <bitfield name="GSOUT" low="0" high="5" type="uint"/>
2911                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2912         </reg32>
2913
2914         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
2915                 <reg32 offset="0x0" name="REG">
2916                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2917                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2918                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2919                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2920                 </reg32>
2921         </array>
2922
2923         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
2924                 <reg32 offset="0x0" name="REG">
2925                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2926                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2927                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2928                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2929                 </reg32>
2930         </array>
2931
2932         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
2933         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
2934         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
2935         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2936         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
2937
2938         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
2939         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
2940         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
2941         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
2942         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
2943         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
2944         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
2945         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
2946         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
2947         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
2948         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
2949         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
2950         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
2951         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
2952         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
2953         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
2954
2955         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2956         <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
2957                 <!--
2958                 bitmask of true/false conditions for FS brac.N instructions,
2959                 bit N corresponds to brac.N
2960                  -->
2961         </reg32>
2962         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
2963         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
2964         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
2965
2966         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
2967                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2968                 <bitfield name="UNK8" pos="8" type="boolean"/>
2969                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2970                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2971         </reg32>
2972         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
2973                 <!-- Same as RB_SRGB_CNTL -->
2974                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2975                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2976                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2977                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2978                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2979                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2980                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2981                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2982         </reg32>
2983         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
2984                 <bitfield name="RT0" low="0" high="3"/>
2985                 <bitfield name="RT1" low="4" high="7"/>
2986                 <bitfield name="RT2" low="8" high="11"/>
2987                 <bitfield name="RT3" low="12" high="15"/>
2988                 <bitfield name="RT4" low="16" high="19"/>
2989                 <bitfield name="RT5" low="20" high="23"/>
2990                 <bitfield name="RT6" low="24" high="27"/>
2991                 <bitfield name="RT7" low="28" high="31"/>
2992         </reg32>
2993         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
2994                 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2995                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
2996                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
2997         </reg32>
2998         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
2999                 <bitfield name="MRT" low="0" high="3" type="uint"/>
3000         </reg32>
3001
3002         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3003                 <reg32 offset="0" name="REG">
3004                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3005                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3006                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3007                 </reg32>
3008         </array>
3009
3010         <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3011                 <!-- unknown bits 0x7fc0 always set -->
3012                 <bitfield name="COUNT" low="0" high="2" type="uint"/>
3013                 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3014                 <bitfield name="UNK3" pos="3" type="boolean"/>
3015                 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3016         </reg32>
3017         <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3018                 <reg32 offset="0" name="CMD">
3019                         <bitfield name="SRC" low="0" high="6" type="uint"/>
3020                         <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3021                         <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3022                         <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3023                         <bitfield name="WRMASK" low="22" high="25" type="hex"/>
3024                         <bitfield name="HALF" pos="26" type="boolean"/>
3025                         <!--
3026                         CMD seems always 0x4??  3d, textureProj, textureLod seem to
3027                         skip pre-fetch.. TODO test texelFetch
3028                         CMD is 0x6 when the Vulkan mode is enabled, and
3029                         TEX_ID/SAMP_ID refer to the descriptor sets while the
3030                         indices come from SP_FS_BINDLESS_PREFETCH[n]
3031                          -->
3032                         <bitfield name="CMD" low="27" high="31"/>
3033                 </reg32>
3034         </array>
3035
3036         <!-- TODO confirm that this is actually an array -->
3037         <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3038                 <reg32 offset="0" name="CMD">
3039                         <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
3040                         <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
3041                 </reg32>
3042         </array>
3043
3044         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3045
3046         <!-- always 0x0 ? -->
3047         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3048
3049         <!-- set for compute shaders, always 0x41 -->
3050         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
3051
3052         <!-- set for compute shaders, always 0x0 -->
3053         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3054
3055         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3056
3057         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3058         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3059         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3060         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3061         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3062         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3063         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3064         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3065
3066         <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3067                 <reg64 offset="0" name="ADDR" type="waddress"/>
3068         </array>
3069
3070         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3071                 <doc>per MRT</doc>
3072                 <reg32 offset="0x0" name="REG">
3073                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3074                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3075                 </reg32>
3076         </array>
3077
3078         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3079         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3080         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3081         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3082         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3083
3084         <!--
3085         IBO state for compute shader:
3086          -->
3087         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3088         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3089         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3090
3091         <!-- always 0x5 ? -->
3092         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
3093
3094         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3095         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3096
3097         <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3098                 <reg64 offset="0" name="ADDR" type="waddress"/>
3099         </array>
3100
3101         <!--
3102         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3103         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3104          -->
3105         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3106         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3107         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3108
3109         <!--
3110         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
3111          -->
3112         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3113                 <bitfield name="NORM" pos="0" type="boolean"/>
3114                 <bitfield name="SINT" pos="1" type="boolean"/>
3115                 <bitfield name="UINT" pos="2" type="boolean"/>
3116                 <!-- looks like HW only cares about the base type of this format,
3117                      which matches the ifmt? -->
3118                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3119                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3120                 <bitfield name="SRGB" pos="11" type="boolean"/>
3121                 <!-- some sort of channel mask, not sure what it is for -->
3122                 <bitfield name="MASK" low="12" high="15"/>
3123         </reg32>
3124
3125         <!-- always 0x0 -->
3126         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3127
3128         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3129         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3130
3131         <!-- always 0x3f ? -->
3132         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3133
3134         <!--
3135         The downstream kernel calls the debug cluster of registers
3136         "a6xx_sp_ps_tp_cluster" but this actually specifies the border
3137         color base for compute shaders.
3138         -->
3139         <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3140         <!-- always 0x0 ? -->
3141         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3142         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3143
3144         <!-- could be all the stuff below here is actually TPL1?? -->
3145
3146         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3147                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3148         </reg32>
3149         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3150                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3151                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3152         </reg32>
3153
3154         <!-- looks to work in the same way as a5xx: -->
3155         <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3156         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3157         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3158         <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3159         <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3160         <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3161
3162         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3163
3164         <!--
3165         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3166         badly named or the functionality moved in a6xx.  But downstream kernel
3167         calls this "a6xx_sp_ps_tp_2d_cluster"
3168          -->
3169         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3170         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3171                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3172                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3173         </reg32>
3174         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3175         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3176         <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3177         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3178            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3179         </reg32>
3180
3181         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3182         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3183         <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3184         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3185                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3186                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3187         </reg32>
3188
3189         <!-- always 0x00100000 ? -->
3190         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3191
3192         <!-- always 0x44 ? -->
3193         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3194
3195         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3196                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3197                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3198         </bitset>
3199
3200         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3201         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3202         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3203         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3204
3205         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3206
3207         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3208                 <!-- always 0x7 ? -->
3209         </reg32>
3210         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3211                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3212                 <!-- SAMPLEID is loaded into a half-precision register: -->
3213                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3214                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3215                 <!--
3216                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3217                 to be divided by to scale to a single fragment.  It is probably
3218                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3219                  -->
3220                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3221         </reg32>
3222         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3223                 <!-- register loaded with position (bary.f) -->
3224                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3225                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3226         </reg32>
3227         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3228                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3229                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3230                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3231         </reg32>
3232         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3233                 <!-- unknown regid in low 8b -->
3234         </reg32>
3235         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3236
3237         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3238                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3239                 <!-- localsize is value minus one: -->
3240                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3241                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3242                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3243         </reg32>
3244         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3245                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3246         </reg32>
3247         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3248                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3249         </reg32>
3250         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3251                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3252         </reg32>
3253         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3254                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3255         </reg32>
3256         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3257                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3258         </reg32>
3259         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3260                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3261         </reg32>
3262         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3263                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3264                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3265                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3266                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3267         </reg32>
3268         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3269         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3270         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3271         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3272
3273         <!-- mirror of SP_CS_BINDLESS_BASE -->
3274         <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3275                 <reg64 offset="0" name="ADDR" type="waddress"/>
3276         </array>
3277
3278         <!-- probably: -->
3279         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3280
3281         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3282
3283         <!-- always 0x0 ? -->
3284         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3285
3286         <!-- mirror of SP_BINDLESS_BASE -->
3287         <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3288                 <reg64 offset="0" name="ADDR" type="waddress"/>
3289         </array>
3290
3291         <!-- always 0x80 ? -->
3292         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3293         <!-- always 0x0 ? -->
3294         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3295         <!-- always 0x0 ? -->
3296         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3297
3298 </domain>
3299
3300 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3301 <domain name="A6XX_TEX_SAMP" width="32">
3302         <doc>Texture sampler dwords</doc>
3303         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3304                 <value name="A6XX_TEX_NEAREST" value="0"/>
3305                 <value name="A6XX_TEX_LINEAR" value="1"/>
3306                 <value name="A6XX_TEX_ANISO" value="2"/>
3307                 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3308         </enum>
3309         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3310                 <value name="A6XX_TEX_REPEAT" value="0"/>
3311                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3312                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3313                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3314                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3315         </enum>
3316         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3317                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3318                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3319                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3320                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3321                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3322         </enum>
3323         <enum name="a6xx_reduction_mode">
3324                 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3325                 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3326                 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3327         </enum>
3328
3329         <reg32 offset="0" name="0">
3330                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3331                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3332                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3333                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3334                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3335                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3336                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3337                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3338         </reg32>
3339         <reg32 offset="1" name="1">
3340                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3341                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3342                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3343                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3344                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3345                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3346         </reg32>
3347         <reg32 offset="2" name="2">
3348                 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3349                 <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
3350         </reg32>
3351         <reg32 offset="3" name="3"/>
3352 </domain>
3353
3354 <domain name="A6XX_TEX_CONST" width="32">
3355         <doc>Texture constant dwords</doc>
3356         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3357                 <value name="A6XX_TEX_X" value="0"/>
3358                 <value name="A6XX_TEX_Y" value="1"/>
3359                 <value name="A6XX_TEX_Z" value="2"/>
3360                 <value name="A6XX_TEX_W" value="3"/>
3361                 <value name="A6XX_TEX_ZERO" value="4"/>
3362                 <value name="A6XX_TEX_ONE" value="5"/>
3363         </enum>
3364         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3365                 <value name="A6XX_TEX_1D" value="0"/>
3366                 <value name="A6XX_TEX_2D" value="1"/>
3367                 <value name="A6XX_TEX_CUBE" value="2"/>
3368                 <value name="A6XX_TEX_3D" value="3"/>
3369         </enum>
3370         <reg32 offset="0" name="0">
3371                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3372                 <bitfield name="SRGB" pos="2" type="boolean"/>
3373                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3374                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3375                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3376                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3377                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3378                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3379                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3380                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3381         </reg32>
3382         <reg32 offset="1" name="1">
3383                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3384                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3385         </reg32>
3386         <reg32 offset="2" name="2">
3387                 <!--
3388                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3389                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3390
3391                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3392                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3393                  -->
3394                 <bitfield name="UNK4" pos="4" type="boolean"/>
3395                 <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
3396                 <doc>Pitch in bytes (so actually stride)</doc>
3397                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3398                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3399                 <bitfield name="UNK31" pos="31" type="boolean"/>
3400         </reg32>
3401         <reg32 offset="3" name="3">
3402                 <!--
3403                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3404                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3405                 layer size at the point that it stops being reduced moving to
3406                 higher (smaller) mipmap levels
3407                  -->
3408                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3409                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3410                 <!--
3411                 by default levels with w < 16 are linear
3412                 TILE_ALL makes all levels have tiling
3413                 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3414                  -->
3415                 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
3416                 <bitfield name="FLAG" pos="28" type="boolean"/>
3417         </reg32>
3418         <reg32 offset="4" name="4">
3419                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3420         </reg32>
3421         <reg32 offset="5" name="5">
3422                 <bitfield name="BASE_HI" low="0" high="16"/>
3423                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3424         </reg32>
3425         <reg32 offset="6" name="6"/>
3426         <reg32 offset="7" name="7">
3427                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3428         </reg32>
3429         <reg32 offset="8" name="8">
3430                 <bitfield name="FLAG_HI" low="0" high="16"/>
3431         </reg32>
3432         <reg32 offset="9" name="9">
3433                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3434         </reg32>
3435         <reg32 offset="10" name="10">
3436                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3437                 <!-- log2 size of the first level, required for mipmapping -->
3438                 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3439                 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3440         </reg32>
3441         <reg32 offset="11" name="11"/>
3442         <reg32 offset="12" name="12"/>
3443         <reg32 offset="13" name="13"/>
3444         <reg32 offset="14" name="14"/>
3445         <reg32 offset="15" name="15"/>
3446 </domain>
3447
3448 <!--
3449 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3450 naming is just because I r/e'd SSBOs first.  I should probably come up
3451 with a better name.
3452 -->
3453 <domain name="A6XX_IBO" width="32">
3454         <reg32 offset="0" name="0">
3455                 <!--
3456                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3457                 used but if they are good chance position is same as TEX_CONST
3458                  -->
3459                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3460                 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3461         </reg32>
3462         <reg32 offset="1" name="1">
3463                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3464                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3465         </reg32>
3466         <reg32 offset="2" name="2">
3467                 <!--
3468                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3469                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3470                  -->
3471                 <bitfield name="UNK4" pos="4" type="boolean"/>
3472                 <doc>Pitch in bytes (so actually stride)</doc>
3473                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3474                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3475                 <bitfield name="UNK31" pos="31" type="boolean"/>
3476         </reg32>
3477         <reg32 offset="3" name="3">
3478                 <!--
3479                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3480                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3481                 layer size at the point that it stops being reduced moving to
3482                 higher (smaller) mipmap levels
3483                  -->
3484                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3485                 <bitfield name="UNK27" pos="27" type="boolean"/>
3486                 <bitfield name="FLAG" pos="28" type="boolean"/>
3487         </reg32>
3488         <reg32 offset="4" name="4">
3489                 <bitfield name="BASE_LO" low="0" high="31"/>
3490         </reg32>
3491         <reg32 offset="5" name="5">
3492                 <bitfield name="BASE_HI" low="0" high="16"/>
3493                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3494         </reg32>
3495         <reg32 offset="6" name="6">
3496         </reg32>
3497         <reg32 offset="7" name="7">
3498         </reg32>
3499         <reg32 offset="8" name="8">
3500         </reg32>
3501         <reg32 offset="9" name="9">
3502                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3503         </reg32>
3504         <reg32 offset="10" name="10">
3505                 <!--
3506                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3507                 don't seem to be particularly sensible... or needed for UBWC to work
3508                  -->
3509                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3510         </reg32>
3511 </domain>
3512
3513 <domain name="A6XX_UBO" width="32">
3514         <reg32 offset="0" name="0">
3515                 <bitfield name="BASE_LO" low="0" high="31"/>
3516         </reg32>
3517         <reg32 offset="1" name="1">
3518                 <bitfield name="BASE_HI" low="0" high="16"/>
3519                 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3520         </reg32>
3521 </domain>
3522
3523 <domain name="A6XX_PDC" width="32">
3524         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3525         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3526         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3527         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3528         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3529         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3530         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3531         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3532         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3533         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3534         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3535         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3536         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3537         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3538         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3539         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3540         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3541         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3542         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3543         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3544         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3545         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3546         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3547         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3548         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3549         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3550 </domain>
3551
3552 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3553         <reg32 offset="0x0" name="MEM_0"/>
3554 </domain>
3555
3556 <domain name="A6XX_CX_DBGC" width="32">
3557         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3558                 <bitfield high="7" low="0" name="PING_INDEX"/>
3559                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3560         </reg32>
3561         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3562         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3563         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3564         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3565                 <bitfield high="5" low="0" name="TRACEEN"/>
3566                 <bitfield high="14" low="12" name="GRANU"/>
3567                 <bitfield high="31" low="28" name="SEGT"/>
3568         </reg32>
3569         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3570                 <bitfield high="27" low="24" name="ENABLE"/>
3571         </reg32>
3572         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3573         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3574         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3575         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3576         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3577         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3578         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3579         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3580         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3581                 <bitfield high="3" low="0" name="BYTEL0"/>
3582                 <bitfield high="7" low="4" name="BYTEL1"/>
3583                 <bitfield high="11" low="8" name="BYTEL2"/>
3584                 <bitfield high="15" low="12" name="BYTEL3"/>
3585                 <bitfield high="19" low="16" name="BYTEL4"/>
3586                 <bitfield high="23" low="20" name="BYTEL5"/>
3587                 <bitfield high="27" low="24" name="BYTEL6"/>
3588                 <bitfield high="31" low="28" name="BYTEL7"/>
3589         </reg32>
3590         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3591                 <bitfield high="3" low="0" name="BYTEL8"/>
3592                 <bitfield high="7" low="4" name="BYTEL9"/>
3593                 <bitfield high="11" low="8" name="BYTEL10"/>
3594                 <bitfield high="15" low="12" name="BYTEL11"/>
3595                 <bitfield high="19" low="16" name="BYTEL12"/>
3596                 <bitfield high="23" low="20" name="BYTEL13"/>
3597                 <bitfield high="27" low="24" name="BYTEL14"/>
3598                 <bitfield high="31" low="28" name="BYTEL15"/>
3599         </reg32>
3600
3601         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3602         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3603 </domain>
3604
3605 <domain name="A6XX_CX_MISC" width="32">
3606         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3607         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3608 </domain>
3609
3610 </database>