src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_color_fmt">
  11         <value value="0x02" name="RB6_A8_UNORM"/>
  12         <value value="0x03" name="RB6_R8_UNORM"/>
  13         <value value="0x04" name="RB6_R8_SNORM"/>
  14         <value value="0x05" name="RB6_R8_UINT"/>
  15         <value value="0x06" name="RB6_R8_SINT"/>
  16         <value value="0x08" name="RB6_R4G4B4A4_UNORM"/>
  17         <value value="0x0a" name="RB6_R5G5B5A1_UNORM"/>
  18         <value value="0x0e" name="RB6_R5G6B5_UNORM"/>
  19         <value value="0x0f" name="RB6_R8G8_UNORM"/>
  20         <value value="0x10" name="RB6_R8G8_SNORM"/>
  21         <value value="0x11" name="RB6_R8G8_UINT"/>
  22         <value value="0x12" name="RB6_R8G8_SINT"/>
  23         <value value="0x15" name="RB6_R16_UNORM"/>
  24         <value value="0x16" name="RB6_R16_SNORM"/>
  25         <value value="0x17" name="RB6_R16_FLOAT"/>
  26         <value value="0x18" name="RB6_R16_UINT"/>
  27         <value value="0x19" name="RB6_R16_SINT"/>
  28         <value value="0x30" name="RB6_R8G8B8A8_UNORM"/>
  29         <value value="0x31" name="RB6_R8G8B8_UNORM"/>
  30         <value value="0x32" name="RB6_R8G8B8A8_SNORM"/>
  31         <value value="0x33" name="RB6_R8G8B8A8_UINT"/>
  32         <value value="0x34" name="RB6_R8G8B8A8_SINT"/>
  33         <value value="0x36" name="RB6_R10G10B10A2_FLOAT16"/>  <!-- float16 for 2d blit? -->
  34         <value value="0x37" name="RB6_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
  35         <value value="0x3a" name="RB6_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
  36         <value value="0x42" name="RB6_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
  37         <value value="0x43" name="RB6_R16G16_UNORM"/>
  38         <value value="0x44" name="RB6_R16G16_SNORM"/>
  39         <value value="0x45" name="RB6_R16G16_FLOAT"/>
  40         <value value="0x46" name="RB6_R16G16_UINT"/>
  41         <value value="0x47" name="RB6_R16G16_SINT"/>
  42         <value value="0x4a" name="RB6_R32_FLOAT"/>
  43         <value value="0x4b" name="RB6_R32_UINT"/>
  44         <value value="0x4c" name="RB6_R32_SINT"/>
  45         <value value="0x60" name="RB6_R16G16B16A16_UNORM"/>
  46         <value value="0x61" name="RB6_R16G16B16A16_SNORM"/>
  47         <value value="0x62" name="RB6_R16G16B16A16_FLOAT"/>
  48         <value value="0x63" name="RB6_R16G16B16A16_UINT"/>
  49         <value value="0x64" name="RB6_R16G16B16A16_SINT"/>
  50         <value value="0x67" name="RB6_R32G32_FLOAT"/>
  51         <value value="0x68" name="RB6_R32G32_UINT"/>
  52         <value value="0x69" name="RB6_R32G32_SINT"/>
  53         <value value="0x82" name="RB6_R32G32B32A32_FLOAT"/>
  54         <value value="0x83" name="RB6_R32G32B32A32_UINT"/>
  55         <value value="0x84" name="RB6_R32G32B32A32_SINT"/>
  56         <value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/>
  57         <value value="0xa0" name="RB6_X8Z24_UNORM"/>
  58 </enum>
  59
  60 <!-- these might be same as a5xx -->
  61 <enum name="a6xx_tile_mode">
  62         <value name="TILE6_LINEAR" value="0"/>
  63         <value name="TILE6_2" value="2"/>
  64         <value name="TILE6_3" value="3"/>
  65 </enum>
  66
  67 <!-- these might be same as a5xx -->
  68 <enum name="a6xx_vtx_fmt" prefix="chipset">
  69         <value value="0x03" name="VFMT6_8_UNORM"/>
  70         <value value="0x04" name="VFMT6_8_SNORM"/>
  71         <value value="0x05" name="VFMT6_8_UINT"/>
  72         <value value="0x06" name="VFMT6_8_SINT"/>
  73
  74         <value value="0x0f" name="VFMT6_8_8_UNORM"/>
  75         <value value="0x10" name="VFMT6_8_8_SNORM"/>
  76         <value value="0x11" name="VFMT6_8_8_UINT"/>
  77         <value value="0x12" name="VFMT6_8_8_SINT"/>
  78
  79         <value value="0x15" name="VFMT6_16_UNORM"/>
  80         <value value="0x16" name="VFMT6_16_SNORM"/>
  81         <value value="0x17" name="VFMT6_16_FLOAT"/>
  82         <value value="0x18" name="VFMT6_16_UINT"/>
  83         <value value="0x19" name="VFMT6_16_SINT"/>
  84
  85         <value value="0x21" name="VFMT6_8_8_8_UNORM"/>
  86         <value value="0x22" name="VFMT6_8_8_8_SNORM"/>
  87         <value value="0x23" name="VFMT6_8_8_8_UINT"/>
  88         <value value="0x24" name="VFMT6_8_8_8_SINT"/>
  89
  90         <value value="0x30" name="VFMT6_8_8_8_8_UNORM"/>
  91         <value value="0x32" name="VFMT6_8_8_8_8_SNORM"/>
  92         <value value="0x33" name="VFMT6_8_8_8_8_UINT"/>
  93         <value value="0x34" name="VFMT6_8_8_8_8_SINT"/>
  94
  95         <value value="0x36" name="VFMT6_10_10_10_2_UNORM"/>
  96         <value value="0x39" name="VFMT6_10_10_10_2_SNORM"/>
  97         <value value="0x3a" name="VFMT6_10_10_10_2_UINT"/>
  98         <value value="0x3b" name="VFMT6_10_10_10_2_SINT"/>
  99
 100         <value value="0x42" name="VFMT6_11_11_10_FLOAT"/>
 101
 102         <value value="0x43" name="VFMT6_16_16_UNORM"/>
 103         <value value="0x44" name="VFMT6_16_16_SNORM"/>
 104         <value value="0x45" name="VFMT6_16_16_FLOAT"/>
 105         <value value="0x46" name="VFMT6_16_16_UINT"/>
 106         <value value="0x47" name="VFMT6_16_16_SINT"/>
 107
 108         <value value="0x48" name="VFMT6_32_UNORM"/>
 109         <value value="0x49" name="VFMT6_32_SNORM"/>
 110         <value value="0x4a" name="VFMT6_32_FLOAT"/>
 111         <value value="0x4b" name="VFMT6_32_UINT"/>
 112         <value value="0x4c" name="VFMT6_32_SINT"/>
 113         <value value="0x4d" name="VFMT6_32_FIXED"/>
 114
 115         <value value="0x58" name="VFMT6_16_16_16_UNORM"/>
 116         <value value="0x59" name="VFMT6_16_16_16_SNORM"/>
 117         <value value="0x5a" name="VFMT6_16_16_16_FLOAT"/>
 118         <value value="0x5b" name="VFMT6_16_16_16_UINT"/>
 119         <value value="0x5c" name="VFMT6_16_16_16_SINT"/>
 120
 121         <value value="0x60" name="VFMT6_16_16_16_16_UNORM"/>
 122         <value value="0x61" name="VFMT6_16_16_16_16_SNORM"/>
 123         <value value="0x62" name="VFMT6_16_16_16_16_FLOAT"/>
 124         <value value="0x63" name="VFMT6_16_16_16_16_UINT"/>
 125         <value value="0x64" name="VFMT6_16_16_16_16_SINT"/>
 126
 127         <value value="0x65" name="VFMT6_32_32_UNORM"/>
 128         <value value="0x66" name="VFMT6_32_32_SNORM"/>
 129         <value value="0x67" name="VFMT6_32_32_FLOAT"/>
 130         <value value="0x68" name="VFMT6_32_32_UINT"/>
 131         <value value="0x69" name="VFMT6_32_32_SINT"/>
 132         <value value="0x6a" name="VFMT6_32_32_FIXED"/>
 133
 134         <value value="0x70" name="VFMT6_32_32_32_UNORM"/>
 135         <value value="0x71" name="VFMT6_32_32_32_SNORM"/>
 136         <value value="0x72" name="VFMT6_32_32_32_UINT"/>
 137         <value value="0x73" name="VFMT6_32_32_32_SINT"/>
 138         <value value="0x74" name="VFMT6_32_32_32_FLOAT"/>
 139         <value value="0x75" name="VFMT6_32_32_32_FIXED"/>
 140
 141         <value value="0x80" name="VFMT6_32_32_32_32_UNORM"/>
 142         <value value="0x81" name="VFMT6_32_32_32_32_SNORM"/>
 143         <value value="0x82" name="VFMT6_32_32_32_32_FLOAT"/>
 144         <value value="0x83" name="VFMT6_32_32_32_32_UINT"/>
 145         <value value="0x84" name="VFMT6_32_32_32_32_SINT"/>
 146         <value value="0x85" name="VFMT6_32_32_32_32_FIXED"/>
 147 </enum>
 148
 149 <enum name="a6xx_tex_fmt">
 150         <value value="0x02" name="TFMT6_A8_UNORM"/>
 151         <value value="0x03" name="TFMT6_8_UNORM"/>
 152         <value value="0x04" name="TFMT6_8_SNORM"/>
 153         <value value="0x05" name="TFMT6_8_UINT"/>
 154         <value value="0x06" name="TFMT6_8_SINT"/>
 155         <value value="0x08" name="TFMT6_4_4_4_4_UNORM"/>
 156         <value value="0x0a" name="TFMT6_5_5_5_1_UNORM"/>
 157         <value value="0x0e" name="TFMT6_5_6_5_UNORM"/>
 158         <value value="0x0f" name="TFMT6_8_8_UNORM"/>
 159         <value value="0x10" name="TFMT6_8_8_SNORM"/>
 160         <value value="0x11" name="TFMT6_8_8_UINT"/>
 161         <value value="0x12" name="TFMT6_8_8_SINT"/>
 162         <value value="0x13" name="TFMT6_L8_A8_UNORM"/>
 163         <value value="0x15" name="TFMT6_16_UNORM"/>
 164         <value value="0x16" name="TFMT6_16_SNORM"/>
 165         <value value="0x17" name="TFMT6_16_FLOAT"/>
 166         <value value="0x18" name="TFMT6_16_UINT"/>
 167         <value value="0x19" name="TFMT6_16_SINT"/>
 168         <value value="0x30" name="TFMT6_8_8_8_8_UNORM"/>
 169         <value value="0x31" name="TFMT6_8_8_8_UNORM"/>
 170         <value value="0x32" name="TFMT6_8_8_8_8_SNORM"/>
 171         <value value="0x33" name="TFMT6_8_8_8_8_UINT"/>
 172         <value value="0x34" name="TFMT6_8_8_8_8_SINT"/>
 173         <value value="0x35" name="TFMT6_9_9_9_E5_FLOAT"/>
 174         <value value="0x36" name="TFMT6_10_10_10_2_UNORM"/>
 175         <value value="0x3a" name="TFMT6_10_10_10_2_UINT"/>
 176         <value value="0x42" name="TFMT6_11_11_10_FLOAT"/>
 177         <value value="0x43" name="TFMT6_16_16_UNORM"/>
 178         <value value="0x44" name="TFMT6_16_16_SNORM"/>
 179         <value value="0x45" name="TFMT6_16_16_FLOAT"/>
 180         <value value="0x46" name="TFMT6_16_16_UINT"/>
 181         <value value="0x47" name="TFMT6_16_16_SINT"/>
 182         <value value="0x4a" name="TFMT6_32_FLOAT"/>
 183         <value value="0x4b" name="TFMT6_32_UINT"/>
 184         <value value="0x4c" name="TFMT6_32_SINT"/>
 185         <value value="0x60" name="TFMT6_16_16_16_16_UNORM"/>
 186         <value value="0x61" name="TFMT6_16_16_16_16_SNORM"/>
 187         <value value="0x62" name="TFMT6_16_16_16_16_FLOAT"/>
 188         <value value="0x63" name="TFMT6_16_16_16_16_UINT"/>
 189         <value value="0x64" name="TFMT6_16_16_16_16_SINT"/>
 190         <value value="0x67" name="TFMT6_32_32_FLOAT"/>
 191         <value value="0x68" name="TFMT6_32_32_UINT"/>
 192         <value value="0x69" name="TFMT6_32_32_SINT"/>
 193         <value value="0x72" name="TFMT6_32_32_32_UINT"/>
 194         <value value="0x73" name="TFMT6_32_32_32_SINT"/>
 195         <value value="0x74" name="TFMT6_32_32_32_FLOAT"/>
 196         <value value="0x82" name="TFMT6_32_32_32_32_FLOAT"/>
 197         <value value="0x83" name="TFMT6_32_32_32_32_UINT"/>
 198         <value value="0x84" name="TFMT6_32_32_32_32_SINT"/>
 199         <value value="0x91" name="TFMT6_Z24_UNORM_S8_UINT"/>
 200         <value value="0xa0" name="TFMT6_X8Z24_UNORM"/>
 201
 202         <value value="0xab" name="TFMT6_ETC2_RG11_UNORM"/>
 203         <value value="0xac" name="TFMT6_ETC2_RG11_SNORM"/>
 204         <value value="0xad" name="TFMT6_ETC2_R11_UNORM"/>
 205         <value value="0xae" name="TFMT6_ETC2_R11_SNORM"/>
 206         <value value="0xaf" name="TFMT6_ETC1"/>
 207         <value value="0xb0" name="TFMT6_ETC2_RGB8"/>
 208         <value value="0xb1" name="TFMT6_ETC2_RGBA8"/>
 209         <value value="0xb2" name="TFMT6_ETC2_RGB8A1"/>
 210         <value value="0xb3" name="TFMT6_DXT1"/>
 211         <value value="0xb4" name="TFMT6_DXT3"/>
 212         <value value="0xb5" name="TFMT6_DXT5"/>
 213         <value value="0xb7" name="TFMT6_RGTC1_UNORM"/>
 214         <value value="0xb8" name="TFMT6_RGTC1_SNORM"/>
 215         <value value="0xbb" name="TFMT6_RGTC2_UNORM"/>
 216         <value value="0xbc" name="TFMT6_RGTC2_SNORM"/>
 217         <value value="0xbe" name="TFMT6_BPTC_UFLOAT"/>
 218         <value value="0xbf" name="TFMT6_BPTC_FLOAT"/>
 219         <value value="0xc0" name="TFMT6_BPTC"/>
 220         <value value="0xc1" name="TFMT6_ASTC_4x4"/>
 221         <value value="0xc2" name="TFMT6_ASTC_5x4"/>
 222         <value value="0xc3" name="TFMT6_ASTC_5x5"/>
 223         <value value="0xc4" name="TFMT6_ASTC_6x5"/>
 224         <value value="0xc5" name="TFMT6_ASTC_6x6"/>
 225         <value value="0xc6" name="TFMT6_ASTC_8x5"/>
 226         <value value="0xc7" name="TFMT6_ASTC_8x6"/>
 227         <value value="0xc8" name="TFMT6_ASTC_8x8"/>
 228         <value value="0xc9" name="TFMT6_ASTC_10x5"/>
 229         <value value="0xca" name="TFMT6_ASTC_10x6"/>
 230         <value value="0xcb" name="TFMT6_ASTC_10x8"/>
 231         <value value="0xcc" name="TFMT6_ASTC_10x10"/>
 232         <value value="0xcd" name="TFMT6_ASTC_12x10"/>
 233         <value value="0xce" name="TFMT6_ASTC_12x12"/>
 234 </enum>
 235
 236 <enum name="a6xx_tex_fetchsize">
 237         <value name="TFETCH6_1_BYTE"  value="0"/>
 238         <value name="TFETCH6_2_BYTE"  value="1"/>
 239         <value name="TFETCH6_4_BYTE"  value="2"/>
 240         <value name="TFETCH6_8_BYTE"  value="3"/>
 241         <value name="TFETCH6_16_BYTE" value="4"/>
 242 </enum>
 243
 244 <!-- probably same as a5xx -->
 245 <enum name="a6xx_depth_format">
 246         <value name="DEPTH6_NONE" value="0"/>
 247         <value name="DEPTH6_16" value="1"/>
 248         <value name="DEPTH6_24_8" value="2"/>
 249         <value name="DEPTH6_32" value="4"/>
 250 </enum>
 251
 252 <bitset name="a6x_cp_protect" inline="yes">
 253         <bitfield name="BASE_ADDR" low="0" high="17"/>
 254         <bitfield name="MASK_LEN" low="18" high="30"/>
 255         <bitfield name="READ" pos="31"/>
 256 </bitset>
 257
 258 <enum name="a6xx_shader_id">
 259         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 260         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 261         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 262         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 263         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 264         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 265         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 266         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 267         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 268         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 269         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 270         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 271         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 272         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 273         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 274         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 275         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 276         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 277         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 278         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 279         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 280         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 281         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 282         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 283         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 284         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 285         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 286         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 287         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 288         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 289         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 290         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 291         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 292         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 293         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 294         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 295         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 296         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 297         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 298         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 299         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 300         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 301         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 302 </enum>
 303
 304 <enum name="a6xx_debugbus_id">
 305         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 306         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 307         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 308         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 309         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 310         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 311         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 312         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 313         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 314         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 315         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 316         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 317         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 318         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 319         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 320         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 321         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 322         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 323         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 324         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 325         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 326         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 327         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 328         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 329         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 330         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 331         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 332         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 333         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 334         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 335         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 336         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 337         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 338         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 339         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 340         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 341         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 342         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 343         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 344         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 345         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 346         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 347         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 348 </enum>
 349
 350 <enum name="a6xx_cp_perfcounter_select">
 351         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 352         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 353         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 354         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 355         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 356         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 357         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 358         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 359         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 360         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 361         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 362         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 363         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 364         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 365         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 366         <value value="15" name="PERF_CP_SQE_IDLE"/>
 367         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 368         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 369         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 370         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 371         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 372         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 373         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 374         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 375         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 376         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 377         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 378         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 379         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 380         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 381         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 382         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 383         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 384         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 385         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 386         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 387         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 388         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 389         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 390         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 391         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 392         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 393         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 394         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 395         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 396         <value value="45" name="PERF_CP_PM4_DATA"/>
 397         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 398         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 399         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 400         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 401 </enum>
 402
 403 <enum name="a6xx_rbbm_perfcounter_select">
 404         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 405         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 406         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 407         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 408         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 409         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 410         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 411         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 412         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 413         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 414         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 415         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 416         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 417         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 418 </enum>
 419
 420 <enum name="a6xx_pc_perfcounter_select">
 421         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 422         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 423         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 424         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 425         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 426         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 427         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 428         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 429         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 430         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 431         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 432         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 433         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 434         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 435         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 436         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 437         <value value="16" name="PERF_PC_INSTANCES"/>
 438         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 439         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 440         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 441         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 442         <value value="21" name="PERF_PC_IA_VERTICES"/>
 443         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 444         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 445         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 446         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 447         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 448         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 449         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 450         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 451         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 452         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 453         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 454         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 455         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 456         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 457         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 458         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 459         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 460         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 461         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 462         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 463 </enum>
 464
 465 <enum name="a6xx_vfd_perfcounter_select">
 466         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 467         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 468         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 469         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 470         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 471         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 472         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 473         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 474         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 475         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 476         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 477         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 478         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 479         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 480         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 481         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 482         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 483         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 484         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 485         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 486         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 487         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 488         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 489 </enum>
 490
 491 <enum name="a6xx_hlsq_perfcounter_select">
 492         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 493         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 494         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 495         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 496         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 497         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 498         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 499         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 500         <value value="8" name="PERF_HLSQ_QUADS"/>
 501         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 502         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 503         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 504         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 505         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 506         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 507         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 508         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 509         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 510         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 511         <value value="19" name="PERF_HLSQ_PIXELS"/>
 512         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 513 </enum>
 514
 515 <enum name="a6xx_vpc_perfcounter_select">
 516         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 517         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 518         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 519         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 520         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 521         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 522         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 523         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 524         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 525         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 526         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 527         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 528         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 529         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 530         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 531         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 532         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 533         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 534         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 535         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 536         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 537         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 538         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 539         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 540         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 541         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 542         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 543         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 544 </enum>
 545
 546 <enum name="a6xx_tse_perfcounter_select">
 547         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 548         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 549         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 550         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 551         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 552         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 553         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 554         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 555         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 556         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 557         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 558         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 559         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 560         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 561         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 562         <value value="15" name="PERF_TSE_CINVOCATION"/>
 563         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 564         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 565         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 566         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 567 </enum>
 568
 569 <enum name="a6xx_ras_perfcounter_select">
 570         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 571         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 572         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 573         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 574         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 575         <value value="5" name="PERF_RAS_8X4_TILES"/>
 576         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 577         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 578         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 579         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 580         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 581         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 582         <value value="12" name="PERF_RAS_BLOCKS"/>
 583 </enum>
 584
 585 <enum name="a6xx_uche_perfcounter_select">
 586         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 587         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 588         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 589         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 590         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 591         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 592         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 593         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 594         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 595         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 596         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 597         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 598         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 599         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 600         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 601         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 602         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 603         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 604         <value value="18" name="PERF_UCHE_EVICTS"/>
 605         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 606         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 607         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 608         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 609         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 610         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 611         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 612         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 613         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 614         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 615         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 616         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 617         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 618         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 619         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 620         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 621         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 622         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 623         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 624         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 625         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 626 </enum>
 627
 628 <enum name="a6xx_tp_perfcounter_select">
 629         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 630         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 631         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 632         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 633         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 634         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 635         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 636         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 637         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 638         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 639         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 640         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 641         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 642         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 643         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 644         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 645         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 646         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 647         <value value="18" name="PERF_TP_QUADS_1D"/>
 648         <value value="19" name="PERF_TP_QUADS_2D"/>
 649         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 650         <value value="21" name="PERF_TP_QUADS_3D"/>
 651         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 652         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 653         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 654         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 655         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 656         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 657         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 658         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 659         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 660         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 661         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 662         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 663         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 664         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 665         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 666         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 667         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 668         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 669         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 670         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 671         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 672         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 673         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 674         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 675         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 676         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 677         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 678         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 679         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 680         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 681         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 682         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 683         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 684         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 685         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 686 </enum>
 687
 688 <enum name="a6xx_sp_perfcounter_select">
 689         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 690         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 691         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 692         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 693         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 694         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 695         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 696         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 697         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 698         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 699         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 700         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 701         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 702         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 703         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 704         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 705         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 706         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 707         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 708         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 709         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 710         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 711         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 712         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 713         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 714         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 715         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 716         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 717         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 718         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 719         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 720         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 721         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 722         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 723         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 724         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 725         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 726         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 727         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 728         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 729         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 730         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 731         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 732         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 733         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 734         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 735         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 736         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 737         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 738         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 739         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 740         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 741         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 742         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 743         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 744         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 745         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 746         <value value="57" name="PERF_SP_GPR_READ"/>
 747         <value value="58" name="PERF_SP_GPR_WRITE"/>
 748         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 749         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 750         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 751         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 752         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 753         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 754         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 755         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 756         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 757         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 758         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 759         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 760         <value value="71" name="PERF_SP_WORKING_EU"/>
 761         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 762         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 763         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 764         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 765         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 766         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 767         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 768         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 769         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 770         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 771         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 772         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 773         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 774 </enum>
 775
 776 <enum name="a6xx_rb_perfcounter_select">
 777         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 778         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 779         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 780         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 781         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 782         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 783         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 784         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 785         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 786         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 787         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 788         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 789         <value value="12" name="PERF_RB_Z_READ"/>
 790         <value value="13" name="PERF_RB_Z_WRITE"/>
 791         <value value="14" name="PERF_RB_C_READ"/>
 792         <value value="15" name="PERF_RB_C_WRITE"/>
 793         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 794         <value value="17" name="PERF_RB_Z_PASS"/>
 795         <value value="18" name="PERF_RB_Z_FAIL"/>
 796         <value value="19" name="PERF_RB_S_FAIL"/>
 797         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 798         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 799         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 800         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 801         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 802         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 803         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 804         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 805         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 806         <value value="29" name="PERF_RB_3D_PIXELS"/>
 807         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 808         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 809         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 810         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 811         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 812         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 813         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 814         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 815         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 816         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 817         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 818         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 819         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 820         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 821         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 822         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 823         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 824         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 825 </enum>
 826
 827 <enum name="a6xx_vsc_perfcounter_select">
 828         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 829         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 830         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 831         <value value="3" name="PERF_VSC_EOT_NUM"/>
 832         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 833 </enum>
 834
 835 <enum name="a6xx_ccu_perfcounter_select">
 836         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 837         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 838         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 839         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 840         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 841         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 842         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 843         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 844         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 845         <value value="9" name="PERF_CCU_GMEM_READ"/>
 846         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 847         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 848         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 849         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 850         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 851         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 852         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 853         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 854         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 855         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 856         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 857         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 858         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 859         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 860         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 861         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 862         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 863         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 864         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 865 </enum>
 866
 867 <enum name="a6xx_lrz_perfcounter_select">
 868         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 869         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 870         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 871         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 872         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 873         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 874         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 875         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 876         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 877         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 878         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 879         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 880         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 881         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 882         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 883         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 884         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 885         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 886         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 887         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 888         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 889         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 890         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 891         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 892         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 893         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 894         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 895         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 896 </enum>
 897
 898 <enum name="a6xx_cmp_perfcounter_select">
 899         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 900         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 901         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 902         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 903         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 904         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 905         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 906         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 907         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 908         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 909         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 910         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 911         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 912         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 913         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 914         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 915         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 916         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 917         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 918         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 919         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 920         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 921         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 922         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 923         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 924         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 925         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 926         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 927         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 928         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 929         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 930         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 931         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 932         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 933         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 934         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 935         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 936         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 937         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 938         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 939 </enum>
 940
 941 <!--
 942 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 943 component type/size, so I think it relates to internal format used for
 944 blending?  The one exception is that 16b unorm and 32b float use the
 945 same value... maybe 16b unorm is uncommon enough that it was just easier
 946 to upconvert to 32b float internally?
 947
 948  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
 949 16b unorm:   4
 950
 951 32b int:     7
 952 16b int:     6
 953  8b int:     5
 954
 955 32b float:   4
 956 16b float:   3
 957  -->
 958 <enum name="a6xx_2d_ifmt">
 959         <value value="0x10" name="R2D_UNORM8"/>
 960         <value value="0x7"  name="R2D_INT32"/>
 961         <value value="0x6"  name="R2D_INT16"/>
 962         <value value="0x5"  name="R2D_INT8"/>
 963         <value value="0x4"  name="R2D_FLOAT32"/>
 964         <value value="0x3"  name="R2D_FLOAT16"/>
 965         <value value="0x1"  name="R2D_UNORM8_SRGB"/>
 966 </enum>
 967
 968 <domain name="A6XX" width="32">
 969         <bitset name="A6XX_RBBM_INT_0_MASK">
 970                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 971                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 972                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 973                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 974                 <bitfield name="CP_SW" pos="8"/>
 975                 <bitfield name="CP_HW_ERROR" pos="9"/>
 976                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 977                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 978                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 979                 <bitfield name="CP_IB2" pos="13"/>
 980                 <bitfield name="CP_IB1" pos="14"/>
 981                 <bitfield name="CP_RB" pos="15"/>
 982                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 983                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 984                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 985                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 986                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 987                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 988                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 989                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 990                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 991                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 992                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 993         </bitset>
 994
 995         <bitset name="A6XX_CP_INT">
 996                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 997                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 998                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 999                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
1000                 <bitfield name="CP_AHB_ERROR" pos="5"/>
1001                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
1002                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
1003         </bitset>
1004
1005         <reg32 offset="0x0800" name="CP_RB_BASE"/>
1006         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
1007         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
1008         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
1009         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
1010         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
1011         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
1012         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
1013         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
1014         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
1015         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
1016         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
1017         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
1018         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
1019         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"/>
1020         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"/>
1021         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1022         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1023         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
1024         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1025         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1026
1027         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1028                 <reg32 offset="0x0" name="REG" type="uint"/>
1029         </array>
1030         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1031                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1032         </array>
1033
1034         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1035         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1036         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1037         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1038         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1039         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1040         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1041         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1042         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1043         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1044         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1045         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1046         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1047         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1048         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1049         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1050         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1051         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1052         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1053         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1054         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1055         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1056         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1057         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1058         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1059         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1060         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1061         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1062         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1063         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1064         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1065         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1066         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1067         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1068         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1069         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1070         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1071         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1072         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1073         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1074         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1075         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1076         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1077         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1078         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1079         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1080         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1081         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1082         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1083         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1084         <reg32 offset="0x0210" name="RBBM_STATUS">
1085                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1086                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1087                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1088                 <bitfield high="20" low="20" name="VSC_BUSY" />
1089                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1090                 <bitfield high="18" low="18" name="SP_BUSY" />
1091                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1092                 <bitfield high="16" low="16" name="VPC_BUSY" />
1093                 <bitfield high="15" low="15" name="VFD_BUSY" />
1094                 <bitfield high="14" low="14" name="TESS_BUSY" />
1095                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1096                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1097                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1098                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1099                 <bitfield high="9" low="9" name="A2D_BUSY" />
1100                 <bitfield high="8" low="8" name="CCU_BUSY" />
1101                 <bitfield high="7" low="7" name="RB_BUSY" />
1102                 <bitfield high="6" low="6" name="RAS_BUSY" />
1103                 <bitfield high="5" low="5" name="TSE_BUSY" />
1104                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1105                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1106                 <bitfield high="2" low="2" name="CP_BUSY" />
1107                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1108                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1109         </reg32>
1110         <reg32 offset="0x0213" name="RBBM_STATUS3"/>
1111         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1112         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1113         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1114         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1115         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1116         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1117         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1118         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1119         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1120         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1121         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1122         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1123         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1124         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1125         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1126         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1127         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1128         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1129         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1130         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1131         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1132         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1133         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1134         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1135         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1136         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1137         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1138         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1139         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1140         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1141         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1142         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1143         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1144         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1145         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1146         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1147         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1148         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1149         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1150         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1151         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1152         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1153         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1154         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1155         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1156         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1157         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1158         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1159         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1160         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1161         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1162         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1163         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1164         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1165         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1166         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1167         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1168         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1169         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1170         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1171         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1172         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1173         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1174         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1175         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1176         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1177         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1178         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1179         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1180         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1181         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1182         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1183         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1184         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1185         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1186         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1187         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1188         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1189         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1190         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1191         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1192         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1193         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1194         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1195         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1196         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1197         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1198         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1199         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1200         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1201         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1202         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1203         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1204         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1205         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1206         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1207         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1208         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1209         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1210         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1211         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1212         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1213         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1214         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1215         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1216         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1217         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1218         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1219         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1220         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1221         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1222         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1223         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1224         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1225         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1226         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1227         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1228         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1229         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1230         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1231         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1232         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1233         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1234         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1235         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1236         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1237         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1238         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1239         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1240         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1241         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1242         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1243         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1244         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1245         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1246         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1247         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1248         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1249         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1250         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1251         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1252         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1253         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1254         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1255         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1256         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1257         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1258         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1259         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1260         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1261         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1262         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1263         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1264         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1265         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1266         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1267         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1268         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1269         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1270         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1271         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1272         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1273         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1274         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1275         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1276         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1277         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1278         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1279         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1280         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1281         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1282         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1283         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1284         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1285         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1286         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1287         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1288         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1289         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1290         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1291         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1292         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1293         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1294         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1295         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1296         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1297         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1298         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1299         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1300         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1301         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1302         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1303         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1304         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1305         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1306         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1307         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1308         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1309         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1310         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1311         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1312         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1313         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1314         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1315         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1316         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1317         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1318         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1319         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1320         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1321         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1322         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1323         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1324         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1325         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1326         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1327         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1328         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1329         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1330         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1331         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1332         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1333         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1334         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1335         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1336         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1337         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1338         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1339         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1340         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1341         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1342         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1343         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1344         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1345         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1346         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1347         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1348         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1349         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1350         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1351         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1352         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1353         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1354         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1355         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1356         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1357         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1358         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1359         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1360         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1361         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1362         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1363         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1364         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1365         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1366         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1367         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1368         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1369         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1370         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1371         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1372         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1373         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1374         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1375
1376         <!---
1377             This block of registers aren't tied to perf counters. They
1378             count various geometry stats, for example number of
1379             vertices in, number of primnitives assembled etc.
1380         -->
1381
1382         <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>
1383         <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1384         <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>
1385         <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1386         <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>
1387         <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1388         <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>
1389         <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1390         <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>
1391         <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1392         <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>
1393         <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1394         <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>
1395         <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1396         <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>
1397         <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1398         <!-- PRIMCTR_8 appears to count number of primitives coming out of GS -->
1399         <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>
1400         <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1401         <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>
1402         <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1403         <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1404         <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1405
1406
1407         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1408         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1409         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1410         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1411         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1412         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1413         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1414         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1415         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1416         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1417         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1418         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1419         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1420         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1421         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1422         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1423         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1424         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1425         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1426         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1427         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1428         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1429         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1430         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1431         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1432         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1433         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1434         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1435         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1436         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1437         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1438         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1439         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1440         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1441         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1442         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1443         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1444         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1445         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1446         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1447         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1448         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1449         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1450         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1451         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1452         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1453         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1454         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1455         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1456         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1457         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1458         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1459         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1460         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1461         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1462         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1463         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1464         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1465         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1466         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1467         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1468         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1469         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1470         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1471         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1472         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1473         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1474         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1475         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1476         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1477         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1478         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1479         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1480         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1481         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1482         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1483         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1484         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1485         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1486         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1487         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1488         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1489         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1490         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1491         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1492         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1493         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1494         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1495         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1496         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1497         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1498         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1499         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1500         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1501         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1502         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1503         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1504         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1505         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1506         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1507         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1508         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1509         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1510         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1511         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1512         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1513         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1514         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1515         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1516         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1517         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1518         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1519         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1520         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1521         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1522         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1523         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1524         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1525         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1526         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1527         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1528         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1529         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1530         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1531         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1532                 <bitfield high="7" low="0" name="PING_INDEX"/>
1533                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1534         </reg32>
1535         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1536                 <bitfield high="5" low="0" name="TRACEEN"/>
1537                 <bitfield high="14" low="12" name="GRANU"/>
1538                 <bitfield high="31" low="28" name="SEGT"/>
1539         </reg32>
1540         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1541                 <bitfield high="27" low="24" name="ENABLE"/>
1542         </reg32>
1543         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1544         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1545         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1546         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1547         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1548         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1549         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1550         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1551         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1552                 <bitfield high="3" low="0" name="BYTEL0"/>
1553                 <bitfield high="7" low="4" name="BYTEL1"/>
1554                 <bitfield high="11" low="8" name="BYTEL2"/>
1555                 <bitfield high="15" low="12" name="BYTEL3"/>
1556                 <bitfield high="19" low="16" name="BYTEL4"/>
1557                 <bitfield high="23" low="20" name="BYTEL5"/>
1558                 <bitfield high="27" low="24" name="BYTEL6"/>
1559                 <bitfield high="31" low="28" name="BYTEL7"/>
1560         </reg32>
1561         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1562                 <bitfield high="3" low="0" name="BYTEL8"/>
1563                 <bitfield high="7" low="4" name="BYTEL9"/>
1564                 <bitfield high="11" low="8" name="BYTEL10"/>
1565                 <bitfield high="15" low="12" name="BYTEL11"/>
1566                 <bitfield high="19" low="16" name="BYTEL12"/>
1567                 <bitfield high="23" low="20" name="BYTEL13"/>
1568                 <bitfield high="27" low="24" name="BYTEL14"/>
1569                 <bitfield high="31" low="28" name="BYTEL15"/>
1570         </reg32>
1571         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1572         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1573         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1574         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1575         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1576         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1577         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1578         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1579         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1580         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1581         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1582         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1583         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1584         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1585         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1586         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1587         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1588         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1589         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1590         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1591         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1592         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1593         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1594         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1595         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1596         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1597         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1598         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1599         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1600         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1601         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1602         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1603         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1604         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1605         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1606         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1607         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1608         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1609         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1610         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1611         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1612         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1613         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1614         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1615         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1616         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1617         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1618         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1619         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1620         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1621         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1622         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1623         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1624         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1625         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1626         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1627         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1628         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1629         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1630         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1631         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1632         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1633         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1634         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1635         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1636         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1637         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1638         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1639         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1640         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1641         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1642         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1643         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1644         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1645         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1646         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1647         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1648         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1649         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1650         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1651         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1652         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1653         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1654         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1655         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1656         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1657         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1658         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1659                 <bitfield high="7" low="0" name="PERFSEL"/>
1660         </reg32>
1661         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1662         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1663         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1664         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1665         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1666         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1667         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1668         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1669         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1670         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1671         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1672         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1673         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1674         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1675         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1676         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1677         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1678         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1679         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1680         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1681         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1682         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1683         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1684         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1685         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1686         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1687         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1688         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1689         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1690         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1691         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1692         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1693         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1694         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1695         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1696         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1697         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1698         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1699         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1700         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1701         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1702         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1703         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1704         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1705         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1706         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1707         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1708         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1709         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1710         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1711         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1712         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1713         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1714         <reg32 offset="0x3001" name="VBIF_CLKON">
1715                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1716         </reg32>
1717         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1718         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1719         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1720         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1721         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1722         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1723                 <bitfield low="0" high="3" name="DATA_SEL"/>
1724         </reg32>
1725         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1726         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1727                 <bitfield low="0" high="8" name="DATA_SEL"/>
1728         </reg32>
1729         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1730         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1731         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1732         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1733         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1734         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1735         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1736         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1737         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1738         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1739         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1740         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1741         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1742         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1743         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1744         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1745         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1746         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1747         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1748         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1749         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1750         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1751
1752         <!-- move/rename these.. -->
1753
1754         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1755         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1756         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1757
1758         <!-- same as RB_BIN_CONTROL -->
1759         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1760                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1761                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1762                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1763                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1764         </reg32>
1765
1766         <!--
1767                 from offset it seems it should be RB, but weird to duplicate
1768                 other regs from same block??
1769          -->
1770         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1771                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1772                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1773         </reg32>
1774
1775         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1776                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1777                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1778         </reg32>
1779         <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
1780         <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
1781         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1782                 <bitfield name="NX" low="1" high="10" type="uint"/>
1783                 <bitfield name="NY" low="11" high="20" type="uint"/>
1784         </reg32>
1785         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1786                 <reg32 offset="0x0" name="REG">
1787                         <doc>
1788                                 Configures the mapping between VSC_PIPE buffer and
1789                                 bin, X/Y specify the bin index in the horiz/vert
1790                                 direction (0,0 is upper left, 0,1 is leftmost bin
1791                                 on second row, and so on).  W/H specify the number
1792                                 of bins assigned to this VSC_PIPE in the horiz/vert
1793                                 dimension.
1794                         </doc>
1795                         <bitfield name="X" low="0" high="9" type="uint"/>
1796                         <bitfield name="Y" low="10" high="19" type="uint"/>
1797                         <bitfield name="W" low="20" high="25" type="uint"/>
1798                         <bitfield name="H" low="26" high="31" type="uint"/>
1799                 </reg32>
1800         </array>
1801         <!--
1802         compared to a5xx and earlier, we just program the address of the first
1803         visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH)
1804
1805         TODO now there seem to be two buffers of VSC data (both referenced by
1806         CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
1807         to have the larger pitch.
1808
1809         The "DATA2" buffer is probably actually the main visibility stream; it
1810         is at least the larger of the two.
1811
1812         For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
1813         uses something somewhat larger) for many cases, although required value
1814         can ramp up somewhat higher.  Values less than 0x20 trigger GPU hangs
1815         even with small amount of geometry (so possibly 0x20 is minimum
1816         alignment or something like that).  So far I can't seem to find any-
1817         thing that needs values larger than 0x20
1818          -->
1819         <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
1820         <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
1821         <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
1822         <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
1823         <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
1824         <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
1825         <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
1826         <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
1827
1828         <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1829                 <doc>
1830                         Seems to be a bitmap of which tiles mapped to the VSC
1831                         pipe contain geometry.
1832
1833                         I suppose we can connect a maximum of 32 tiles to a
1834                         single VSC pipe.
1835                 </doc>
1836                 <reg32 offset="0x0" name="REG"/>
1837         </array>
1838
1839         <array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
1840                 <doc>
1841                         Has the size of data written to corresponding VSC_DATA2
1842                         buffer.
1843                 </doc>
1844                 <reg32 offset="0x0" name="REG"/>
1845         </array>
1846
1847         <array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
1848                 <doc>
1849                         Has the size of data written to corresponding VSC pipe, ie.
1850                         same thing that is written out to VSC_SIZE_ADDRESS_LO/HI
1851                 </doc>
1852                 <reg32 offset="0x0" name="REG"/>
1853         </array>
1854
1855         <!-- always 0x03200000 ? -->
1856         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1857
1858         <reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/>
1859         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1860         <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
1861
1862         <enum name="a6xx_layer_type">
1863           <value value="0x0" name="MULTISAMPLE_ARRAY"/>
1864           <value value="0x1" name="ARRAY"/> <!-- 2d array and 3d -->
1865           <value value="0x2" name="CUBEMAP"/>
1866         </enum>
1867
1868         <reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
1869                 <bitfield name="LAYERED" pos="0" type="boolean"/>
1870                 <bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
1871         </reg32>
1872
1873         <reg32 offset="0x8005" name="GRAS_CNTL">
1874                 <!-- see also RB_RENDER_CONTROL0 -->
1875                 <bitfield name="VARYING" pos="0" type="boolean"/>
1876                 <!-- b1 set for interpolateAtCentroid() -->
1877                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1878                 <!-- b2 set instead of b0 when running in per-sample mode -->
1879                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1880                 <!--
1881                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1882                 mode, and frag_face
1883                  -->
1884                 <bitfield name="SIZE" pos="3" type="boolean"/>
1885                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1886                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1887                 <bitfield name="XCOORD" pos="6" type="boolean"/>
1888                 <bitfield name="YCOORD" pos="7" type="boolean"/>
1889                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
1890                 <bitfield name="WCOORD" pos="9" type="boolean"/>
1891         </reg32>
1892         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1893                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1894                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1895         </reg32>
1896         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1897         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1898         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1899         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1900         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1901         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1902
1903         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1904                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1905                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1906                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1907                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1908                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1909                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1910                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1911         </reg32>
1912         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1913                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1914                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1915         </reg32>
1916         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1917
1918         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1919                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1920         </reg32>
1921         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1922         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1923         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1924         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1925         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1926                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1927         </reg32>
1928
1929         <!-- always 0x0 -->
1930         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1931
1932         <!-- always 0x0 ? -->
1933         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1934
1935         <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
1936                 <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
1937         </reg32>
1938
1939         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1940
1941         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1942                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1943         </reg32>
1944         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1945                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1946                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1947         </reg32>
1948
1949         <!-- always 0x0 -->
1950         <reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/>
1951         <!-- always 0x0 -->
1952         <reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/>
1953         <!-- always 0x0 -->
1954         <reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/>
1955         <!-- always 0x0 -->
1956         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1957
1958         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1959         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1960         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1961         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1962         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1963         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1964
1965         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1966                 <!--
1967                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1968                 look when we get around to enabling lrz
1969                  -->
1970                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1971                 <doc>LRZ write also disabled for blend/etc.</doc>
1972                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1973                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1974                 <bitfield name="GREATER" pos="2" type="boolean"/>
1975                 <!-- set at end of batch that had LRZ enabled (to flush/disable it?) -->
1976                 <bitfield name="UNK3" pos="3" type="boolean"/>
1977                 <!-- set when depth-test + depth-write enabled -->
1978                 <bitfield name="UNK4" pos="4" type="boolean"/>
1979         </reg32>
1980         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
1981         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1982                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
1983         </reg32>
1984         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1985         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1986         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1987                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
1988                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
1989         </reg32>
1990         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1991         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1992
1993         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1994                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1995         </reg32>
1996
1997         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
1998
1999         <enum name="a6xx_rotation">
2000           <value value="0x0" name="ROTATE_0"/>
2001           <value value="0x1" name="ROTATE_90"/>
2002           <value value="0x2" name="ROTATE_180"/>
2003           <value value="0x3" name="ROTATE_270"/>
2004           <value value="0x4" name="ROTATE_HFLIP"/>
2005           <value value="0x5" name="ROTATE_VFLIP"/>
2006         </enum>
2007
2008         <bitset name="a6xx_2d_blit_cntl" inline="yes">
2009                 <bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/>
2010                 <bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/>
2011                 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2012                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
2013                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2014                 <!-- required when blitting D24S8/D24X8 -->
2015                 <bitfield name="D24S8" pos="19" type="boolean"/>
2016                 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2017                 <bitfield name="MASK" low="20" high="23"/>
2018                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2019         </bitset>
2020
2021         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2022
2023         <!-- could be the src coords are fixed point? -->
2024         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
2025                 <bitfield name="X" low="8" high="31" type="int"/>
2026         </reg32>
2027         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
2028                 <bitfield name="X" low="8" high="31" type="int"/>
2029         </reg32>
2030         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
2031                 <bitfield name="Y" low="8" high="31" type="int"/>
2032         </reg32>
2033         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
2034                 <bitfield name="Y" low="8" high="31" type="int"/>
2035         </reg32>
2036
2037         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
2038         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
2039
2040         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2041         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2042
2043         <!-- always 0x880 ? -->
2044         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
2045
2046         <!-- same as GRAS_BIN_CONTROL: -->
2047         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2048                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
2049                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
2050                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2051                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2052         </reg32>
2053         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2054                 <!-- always set: ?? -->
2055                 <bitfield name="UNK4" pos="4" type="boolean"/>
2056                 <!-- set during binning pass: -->
2057                 <bitfield name="BINNING" pos="7" type="boolean"/>
2058                 <!-- bit seems to be set whenever depth buffer enabled: -->
2059                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2060                 <!-- bitmask of MRTs using UBWC flag buffer: -->
2061                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2062         </reg32>
2063         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2064                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2065         </reg32>
2066         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2067                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2068                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2069         </reg32>
2070
2071         <!-- always 0x0 ? -->
2072         <reg32 offset="0x8804" name="RB_UNKNOWN_8804"/>
2073         <!-- always 0x0 ? -->
2074         <reg32 offset="0x8805" name="RB_UNKNOWN_8805"/>
2075         <!-- always 0x0 ? -->
2076         <reg32 offset="0x8806" name="RB_UNKNOWN_8806"/>
2077
2078         <!--
2079         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2080         name comes from kernel and is probably right)
2081          -->
2082         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2083                 <!-- see also GRAS_CNTL -->
2084                 <bitfield name="VARYING" pos="0" type="boolean"/>
2085                 <!-- b1 set for interpolateAtCentroid() -->
2086                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2087                 <!-- b2 set instead of b0 when running in per-sample mode -->
2088                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2089                 <!--
2090                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2091                 mode, and frag_face
2092                  -->
2093                 <bitfield name="SIZE" pos="3" type="boolean"/>
2094                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2095                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2096                 <bitfield name="XCOORD" pos="6" type="boolean"/>
2097                 <bitfield name="YCOORD" pos="7" type="boolean"/>
2098                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
2099                 <bitfield name="WCOORD" pos="9" type="boolean"/>
2100                 <bitfield name="UNK10" pos="10" type="boolean"/>
2101         </reg32>
2102         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2103                 <!-- enable bits for various FS sysvalue regs: -->
2104                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2105                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2106                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2107                 <!-- b4 and b5 set in per-sample mode: -->
2108                 <bitfield name="UNK4" pos="4" type="boolean"/>
2109                 <bitfield name="UNK5" pos="5" type="boolean"/>
2110                 <bitfield name="SIZE" pos="6" type="boolean"/>
2111         </reg32>
2112
2113         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2114                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2115                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2116         </reg32>
2117         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2118                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2119         </reg32>
2120         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2121                 <bitfield name="RT0" low="0" high="3"/>
2122                 <bitfield name="RT1" low="4" high="7"/>
2123                 <bitfield name="RT2" low="8" high="11"/>
2124                 <bitfield name="RT3" low="12" high="15"/>
2125                 <bitfield name="RT4" low="16" high="19"/>
2126                 <bitfield name="RT5" low="20" high="23"/>
2127                 <bitfield name="RT6" low="24" high="27"/>
2128                 <bitfield name="RT7" low="28" high="31"/>
2129         </reg32>
2130         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2131                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2132                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2133                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2134                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2135                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2136                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2137                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2138                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2139         </reg32>
2140         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2141                 <!-- Same as SP_SRGB_CNTL -->
2142                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2143                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2144                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2145                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2146                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2147                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2148                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2149                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2150         </reg32>
2151
2152         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2153                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2154         </reg32>
2155         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2156
2157         <!-- always 0x0 ? -->
2158         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2159         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2160         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2161         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2162         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2163         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2164         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2165
2166         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2167                 <reg32 offset="0x0" name="CONTROL">
2168                         <bitfield name="BLEND" pos="0" type="boolean"/>
2169                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2170                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2171                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2172                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2173                 </reg32>
2174                 <reg32 offset="0x1" name="BLEND_CONTROL">
2175                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2176                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2177                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2178                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2179                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2180                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2181                 </reg32>
2182                 <reg32 offset="0x2" name="BUF_INFO">
2183                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2184                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2185                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2186                 </reg32>
2187                 <!--
2188                 at least in gmem, things seem to be aligned to pitch of 64..
2189                 maybe an artifact of tiled format used in gmem?
2190                  -->
2191                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2192                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2193                 <!--
2194                 Compared to a5xx and before, we configure both a GMEM base and
2195                 external base.  Not sure if this is to facilitate GMEM save/
2196                 restore for context switch, or just to simplify state setup to
2197                 not have to care about GMEM vs BYPASS mode.
2198                  -->
2199                 <reg32 offset="0x5" name="BASE_LO"/>
2200                 <reg32 offset="0x6" name="BASE_HI"/>
2201                 <reg32 offset="0x7" name="BASE_GMEM"/>
2202         </array>
2203
2204         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2205         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2206         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2207         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2208         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2209                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2210                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2211                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2212         </reg32>
2213         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2214                 <!-- per-mrt enable bit -->
2215                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2216                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2217                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2218                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2219         </reg32>
2220         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2221                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2222         </reg32>
2223
2224         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2225                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2226                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2227                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2228                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2229                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2230         </reg32>
2231         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2232         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2233                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2234         </reg32>
2235 <!-- probably: -->
2236         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2237                 <doc>stride of depth/stencil buffer</doc>
2238         </reg32>
2239         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2240                 <doc>size of layer</doc>
2241         </reg32>
2242         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2243         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2244         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2245
2246         <!-- always 0x0 ? -->
2247         <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
2248         <!-- always 0x0 ? -->
2249         <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
2250
2251         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2252                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2253                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2254                 <!--
2255                         set for stencil operations that require read from stencil
2256                         buffer, but not for example for stencil clear (which does
2257                         not require read).. so guessing this is analogous to
2258                         READ_DEST_ENABLE for color buffer..
2259                  -->
2260                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2261                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2262                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2263                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2264                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2265                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2266                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2267                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2268                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2269         </reg32>
2270         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2271                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2272         </reg32>
2273         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2274                 <doc>stride of stencil buffer</doc>
2275         </reg32>
2276         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2277                 <doc>size of layer</doc>
2278         </reg32>
2279         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2280         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2281         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2282         <reg32 offset="0x8887" name="RB_STENCILREF">
2283                 <bitfield name="REF" low="0" high="7"/>
2284                 <bitfield name="BFREF" low="8" high="15"/>
2285         </reg32>
2286         <reg32 offset="0x8888" name="RB_STENCILMASK">
2287                 <bitfield name="MASK" low="0" high="7"/>
2288                 <bitfield name="BFMASK" low="8" high="15"/>
2289         </reg32>
2290         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2291                 <bitfield name="WRMASK" low="0" high="7"/>
2292                 <bitfield name="BFWRMASK" low="8" high="15"/>
2293         </reg32>
2294         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2295         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2296                 <bitfield name="COPY" pos="1" type="boolean"/>
2297         </reg32>
2298
2299         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2300                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2301         </reg32>
2302
2303         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2304         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2305         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2306
2307         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2308                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2309         </reg32>
2310         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2311         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2312         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2313                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2314                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2315                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2316                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/>
2317                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2318         </reg32>
2319         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2320         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2321         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2322         <!-- array-pitch is size of layer -->
2323         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2324         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2325         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2326         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2327                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2328                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2329         </reg32>
2330
2331         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2332         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2333         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2334         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2335
2336         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2337         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2338                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2339                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2340                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2341                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2342                 <doc>
2343                         For clearing depth/stencil
2344                                 1 - depth
2345                                 2 - stencil
2346                                 3 - depth+stencil
2347                         For clearing color buffer:
2348                                 then probably a component mask, I always see 0xf
2349                 </doc>
2350                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2351         </reg32>
2352
2353         <!-- always 0x0 ? -->
2354         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2355
2356         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2357         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2358         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2359                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2360                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2361         </reg32>
2362         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2363                 <reg32 offset="0" name="ADDR_LO"/>
2364                 <reg32 offset="1" name="ADDR_HI"/>
2365                 <reg32 offset="2" name="PITCH">
2366                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2367                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2368                 </reg32>
2369         </array>
2370         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2371         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2372
2373         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2374         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2375
2376         <bitset name="a6xx_2d_surf_info" inline="yes">
2377                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2378                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2379                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2380                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2381                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2382                 <bitfield name="SRGB" pos="13" type="boolean"/>
2383                 <!-- the rest is only for src -->
2384                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2385                 <bitfield name="FILTER" pos="16" type="boolean"/>
2386                 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2387         </bitset>
2388
2389         <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2390         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2391         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2392         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2393                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2394         </reg32>
2395
2396         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2397         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2398         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2399                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2400                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2401         </reg32>
2402
2403         <!-- unlike a5xx, these are per channel values rather than packed -->
2404         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2405         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2406         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2407         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2408
2409         <!-- always 0x1 ? -->
2410         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2411
2412         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2413
2414         <reg32 offset="0x8e07" name="RB_CCU_CNTL"/>  <!-- always 7c400004 or 10000000 -->
2415
2416         <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
2417
2418         <!-- always 0x00ffff00 ? */ -->
2419         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2420         <reg32 offset="0x9101" name="VPC_UNKNOWN_9102"/>
2421
2422         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2423
2424         <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
2425                 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2426         </reg32>
2427
2428         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2429         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2430
2431         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2432                 <reg32 offset="0x0" name="MODE"/>
2433         </array>
2434         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2435                 <reg32 offset="0x0" name="MODE"/>
2436         </array>
2437
2438         <!-- always 0x0 -->
2439         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2440         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2441
2442         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2443                 <!-- one bit per varying component: -->
2444                 <reg32 offset="0" name="DISABLE"/>
2445         </array>
2446
2447         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2448                 <!-- always 0x10000 when SO enabled.. -->
2449                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2450         </reg32>
2451         <reg32 offset="0x9217" name="VPC_SO_PROG">
2452                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2453                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2454                 <bitfield name="A_EN" pos="11" type="boolean"/>
2455                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2456                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2457                 <bitfield name="B_EN" pos="23" type="boolean"/>
2458         </reg32>
2459
2460         <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2461         <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2462
2463         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2464                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2465                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2466                 <reg32 offset="2" name="BUFFER_SIZE"/>
2467                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2468                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2469                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2470                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2471         </array>
2472
2473         <!-- always 0x0 ? -->
2474         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2475                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2476         </reg32>
2477
2478         <!-- always 0x0 ? -->
2479         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2480
2481         <reg32 offset="0x9301" name="VPC_PACK">
2482                 <doc>
2483                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2484                         plus # of transform-feedback (streamout) varyings if using the
2485                         hw streamout (rather than stg instructions in shader)
2486                 </doc>
2487                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2488                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2489                 <!--
2490                 This seems to be the OUTLOC for the psize output.  It could possibly
2491                 be the max-OUTLOC position, but it is only set when VS writes psize
2492                 (and blob always puts psize at highest OUTLOC)
2493                  -->
2494                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2495         </reg32>
2496
2497         <reg32 offset="0x9302" name="VPC_PACK_GS">
2498                 <doc>
2499                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2500                         plus # of transform-feedback (streamout) varyings if using the
2501                         hw streamout (rather than stg instructions in shader)
2502                 </doc>
2503                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2504                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2505                 <!--
2506                 This seems to be the OUTLOC for the psize output.  It could possibly
2507                 be the max-OUTLOC position, but it is only set when VS writes psize
2508                 (and blob always puts psize at highest OUTLOC)
2509                  -->
2510                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2511         </reg32>
2512
2513         <reg32 offset="0x9303" name="VPC_PACK_3">
2514                 <doc>
2515                         domain shader version of VPC_PACK
2516                 </doc>
2517                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2518                 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2519                 <!--
2520                 This seems to be the OUTLOC for the psize output.  It could possibly
2521                 be the max-OUTLOC position, but it is only set when VS writes psize
2522                 (and blob always puts psize at highest OUTLOC)
2523                  -->
2524                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2525         </reg32>
2526
2527         <reg32 offset="0x9304" name="VPC_CNTL_0">
2528                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2529                 <bitfield name="VARYING" pos="16" type="boolean"/>
2530         </reg32>
2531
2532         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2533                 <bitfield name="BUF0" pos="0" type="boolean"/>
2534                 <bitfield name="BUF1" pos="3" type="boolean"/>
2535                 <bitfield name="BUF2" pos="6" type="boolean"/>
2536                 <bitfield name="BUF3" pos="9" type="boolean"/>
2537                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2538         </reg32>
2539         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2540                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2541         </reg32>
2542
2543         <!-- always 0x0 ? -->
2544         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2545         <!-- always 0x0 ? -->
2546         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2547
2548         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2549
2550         <!-- always 0x0 ? -->
2551         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2552
2553         <enum name="a6xx_tess_spacing">
2554           <value value="0x0" name="TESS_EQUAL"/>
2555           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2556           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2557         </enum>
2558
2559         <enum name="a6xx_tess_output">
2560           <value value="0x0" name="TESS_POINTS"/>
2561           <value value="0x1" name="TESS_LINES"/>
2562           <value value="0x2" name="TESS_CW_TRIS"/>
2563           <value value="0x3" name="TESS_CCW_TRIS"/>
2564         </enum>
2565
2566         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2567           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2568           <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2569         </reg32>
2570
2571         <!-- probably: -->
2572         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2573         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2574
2575         <!-- always 0x1 ? -->
2576         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2577         <reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>
2578
2579         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2580         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2581
2582         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2583
2584         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2585                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2586                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2587                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2588         </reg32>
2589         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2590                 <doc>
2591                         vertex shader
2592
2593                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2594                         plus # of transform-feedback (streamout) varyings if using the
2595                         hw streamout (rather than stg instructions in shader)
2596                 </doc>
2597                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2598                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2599         </reg32>
2600
2601         <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
2602                 <doc>
2603                   geometry shader
2604                 </doc>
2605                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2606                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2607                 <bitfield name="LAYER" pos="9" type="boolean"/>
2608                 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2609         </reg32>
2610
2611         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2612                 <doc>
2613                         hull shader?
2614
2615                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2616                         plus # of transform-feedback (streamout) varyings if using the
2617                         hw streamout (rather than stg instructions in shader)
2618                 </doc>
2619                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2620                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2621         </reg32>
2622         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2623                 <doc>
2624                         domain shader
2625                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2626                         plus # of transform-feedback (streamout) varyings if using the
2627                         hw streamout (rather than stg instructions in shader)
2628                 </doc>
2629                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2630                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2631         </reg32>
2632
2633         <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2634                 <doc>
2635                   geometry shader
2636                 </doc>
2637                 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2638                 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2639                 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2640         </reg32>
2641
2642         <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2643                 <doc>
2644                   size in vec4s of per-primitive storage for gs
2645                 </doc>
2646                 <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
2647         </reg32>
2648
2649         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2650
2651         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2652         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2653
2654         <!-- always 0x0 -->
2655         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2656
2657         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2658                 <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2659         </reg32>
2660         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2661                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2662                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2663                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2664         </reg32>
2665         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2666                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2667                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2668         </reg32>
2669         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2670                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2671                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2672                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2673         </reg32>
2674         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2675         </reg32>
2676         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2677                 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2678         </reg32>
2679         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2680         </reg32>
2681
2682         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2683                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2684         </reg32>
2685
2686         <!-- always 0x0 ? -->
2687         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2688         <reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/>
2689
2690         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2691         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2692         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2693                 <reg32 offset="0x0" name="BASE_LO"/>
2694                 <reg32 offset="0x1" name="BASE_HI"/>
2695                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2696                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2697         </array>
2698         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2699                 <reg32 offset="0x0" name="INSTR">
2700                         <!-- IDX appears to index into VFD_FETCH[] -->
2701                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2702                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2703                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_vtx_fmt"/>
2704                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2705                         <bitfield name="UNK30" pos="30" type="boolean"/>
2706                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2707                 </reg32>
2708                 <reg32 offset="0x1" name="STEP_RATE"/>
2709         </array>
2710         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2711                 <reg32 offset="0x0" name="INSTR">
2712                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2713                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2714                 </reg32>
2715         </array>
2716
2717         <!-- always 0x1 ? -->
2718         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2719
2720         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2721                 <!-- # of VS outputs including pos/psize -->
2722                 <bitfield name="VSOUT" low="0" high="4" type="uint"/>
2723         </reg32>
2724         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2725                 <reg32 offset="0x0" name="REG">
2726                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2727                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2728                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2729                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2730                 </reg32>
2731         </array>
2732         <!--
2733         Starting with a5xx, position/psize outputs from shader end up in the
2734         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2735         the last entries too, except when gl_PointCoord is used, blob inserts
2736         an extra varying after, but with a lower OUTLOC position.  If present,
2737         psize is last, preceded by position.
2738          -->
2739         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2740                 <reg32 offset="0x0" name="REG">
2741                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2742                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2743                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2744                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2745                 </reg32>
2746         </array>
2747
2748         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2749                 <!--
2750                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2751                 used registers is a bit odd too:
2752                         - used (half): 0-15 68-179 (cnt=128, max=179)
2753                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2754                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2755                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2756                 then:
2757                         - used (merged): 0-191 (cnt=192, max=191)
2758                 So I think if b31 is set, then the half precision registers overlap
2759                 the full precision registers.  (Which seems like a pretty sensible
2760                 feature, actually I'm not sure when you *wouldn't* want to use that,
2761                 since it gives register allocation more flexibility)
2762                  -->
2763                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2764                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2765                 <!-- seems to be nesting level for flow control:.. -->
2766                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2767                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2768                 <bitfield name="VARYING" pos="22" type="boolean"/>
2769                 <!-- set when dFdxFine/dFdyFine is used -->
2770                 <bitfield name="DIFF_FINE" pos="23" type="boolean"/>
2771                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2772                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2773         </bitset>
2774
2775         <bitset name="a6xx_sp_xs_config" inline="yes">
2776                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2777                 <!--
2778                 number of textures and samplers.. these might be swapped, with GL I
2779                 always see the same value for both.
2780                  -->
2781                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2782                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2783                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2784         </bitset>
2785
2786         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2787         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2788         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2789         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2790         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2791         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2792         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2793
2794         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2795         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2796         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2797         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2798         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2799         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2800         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2801         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2802
2803         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2804         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2805                 <!-- # of DS outputs including pos/psize -->
2806                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2807         </reg32>
2808         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2809                 <reg32 offset="0x0" name="REG">
2810                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2811                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2812                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2813                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2814                 </reg32>
2815         </array>
2816         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2817                 <reg32 offset="0x0" name="REG">
2818                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2819                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2820                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2821                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2822                 </reg32>
2823         </array>
2824
2825         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2826         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2827         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2828         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2829         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2830         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2831
2832         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2833         <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
2834
2835         <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
2836                 <!-- # of VS outputs including pos/psize -->
2837                 <bitfield name="GSOUT" low="0" high="4" type="uint"/>
2838                 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2839         </reg32>
2840
2841         <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
2842                 <reg32 offset="0x0" name="REG">
2843                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2844                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2845                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2846                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2847                 </reg32>
2848         </array>
2849
2850         <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
2851                 <reg32 offset="0x0" name="REG">
2852                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2853                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2854                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2855                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2856                 </reg32>
2857         </array>
2858
2859         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
2860         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
2861         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
2862         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2863         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
2864
2865         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
2866         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
2867         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
2868         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
2869         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
2870         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
2871         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
2872         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
2873         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
2874         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
2875         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
2876         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
2877         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
2878         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
2879         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
2880         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
2881
2882         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2883         <reg32 offset="0xa981" name="SP_UNKNOWN_A981">
2884                 <bitfield name="FACE0" pos="0" type="boolean"/>
2885                 <bitfield name="FACE1" pos="1" type="boolean"/>
2886                 <bitfield name="FACE2" pos="2" type="boolean"/>
2887                 <bitfield name="FACE3" pos="3" type="boolean"/>
2888                 <bitfield name="FACE4" pos="4" type="boolean"/>
2889                 <bitfield name="FACE5" pos="5" type="boolean"/>
2890         </reg32>
2891         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
2892         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
2893         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
2894
2895         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
2896                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2897                 <bitfield name="UNK8" pos="8" type="boolean"/>
2898                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2899         </reg32>
2900         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
2901                 <!-- Same as RB_SRGB_CNTL -->
2902                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2903                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2904                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2905                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2906                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2907                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2908                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2909                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2910         </reg32>
2911         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
2912                 <bitfield name="RT0" low="0" high="3"/>
2913                 <bitfield name="RT1" low="4" high="7"/>
2914                 <bitfield name="RT2" low="8" high="11"/>
2915                 <bitfield name="RT3" low="12" high="15"/>
2916                 <bitfield name="RT4" low="16" high="19"/>
2917                 <bitfield name="RT5" low="20" high="23"/>
2918                 <bitfield name="RT6" low="24" high="27"/>
2919                 <bitfield name="RT7" low="28" high="31"/>
2920         </reg32>
2921         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
2922                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
2923                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
2924         </reg32>
2925         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
2926                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2927         </reg32>
2928
2929         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
2930                 <reg32 offset="0" name="REG">
2931                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2932                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2933                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2934                 </reg32>
2935         </array>
2936
2937         <reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/>
2938
2939         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
2940
2941         <!-- always 0x0 ? -->
2942         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
2943
2944         <!-- set for compute shaders, always 0x41 -->
2945         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
2946
2947         <!-- set for compute shaders, always 0x0 -->
2948         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
2949
2950         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
2951
2952         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
2953         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
2954         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
2955         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
2956         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
2957         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
2958         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
2959         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
2960
2961         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
2962                 <doc>per MRT</doc>
2963                 <reg32 offset="0x0" name="REG">
2964                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2965                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
2966                 </reg32>
2967         </array>
2968
2969         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2970         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
2971         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
2972         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
2973         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
2974
2975         <!--
2976         IBO state for compute shader:
2977          -->
2978         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
2979         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
2980         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
2981
2982         <!-- always 0x5 ? -->
2983         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
2984
2985         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
2986         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
2987
2988         <!--
2989         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
2990         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
2991          -->
2992         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
2993         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
2994         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
2995
2996         <!--
2997         not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
2998          -->
2999         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
3000                 <bitfield name="NORM" pos="0" type="boolean"/>
3001                 <bitfield name="SINT" pos="1" type="boolean"/>
3002                 <bitfield name="UINT" pos="2" type="boolean"/>
3003                 <!-- looks like HW only cares about the base type of this format,
3004                      which matches the ifmt? -->
3005                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/>
3006                 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3007                 <bitfield name="SRGB" pos="11" type="boolean"/>
3008                 <!-- some sort of channel mask, not sure what it is for -->
3009                 <bitfield name="MASK" low="12" high="15"/>
3010         </reg32>
3011
3012         <!-- always 0x0 -->
3013         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3014
3015         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3016         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3017
3018         <!-- always 0x3f ? -->
3019         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3020
3021         <!-- always 0x0 ? -->
3022         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3023         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3024
3025         <!-- could be all the stuff below here is actually TPL1?? -->
3026
3027         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3028                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3029         </reg32>
3030         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3031                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3032                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3033         </reg32>
3034
3035         <!-- looks to work in the same way as a5xx: -->
3036         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3037         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3038         <!-- always 0x0 ? -->
3039         <reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/>
3040
3041         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3042
3043         <!--
3044         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3045         badly named or the functionality moved in a6xx.  But downstream kernel
3046         calls this "a6xx_sp_ps_tp_2d_cluster"
3047          -->
3048         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3049         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3050                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3051                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3052         </reg32>
3053         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3054         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3055         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3056            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
3057         </reg32>
3058
3059         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3060         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3061         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3062                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3063                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
3064         </reg32>
3065
3066         <!-- always 0x00100000 ? -->
3067         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3068
3069         <!-- always 0x44 ? -->
3070         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3071
3072         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3073                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3074                 <bitfield name="ENABLED" pos="8" type="boolean"/>
3075         </bitset>
3076
3077         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3078         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3079         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3080         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3081
3082         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3083
3084         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3085                 <!-- always 0x7 ? -->
3086         </reg32>
3087         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3088                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3089                 <!-- SAMPLEID is loaded into a half-precision register: -->
3090                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3091                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3092                 <!--
3093                 SIZE is the "size" of the primitive, ie. what the i/j coords need
3094                 to be divided by to scale to a single fragment.  It is probably
3095                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3096                  -->
3097                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3098         </reg32>
3099         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3100                 <!-- register loaded with position (bary.f) -->
3101                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
3102                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
3103         </reg32>
3104         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3105                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
3106                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3107                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3108         </reg32>
3109         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3110                 <!-- unknown regid in low 8b -->
3111         </reg32>
3112         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3113
3114         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3115                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3116                 <!-- localsize is value minus one: -->
3117                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3118                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3119                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3120         </reg32>
3121         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3122                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3123         </reg32>
3124         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3125                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3126         </reg32>
3127         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3128                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3129         </reg32>
3130         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3131                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3132         </reg32>
3133         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3134                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3135         </reg32>
3136         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3137                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3138         </reg32>
3139         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3140                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3141                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
3142                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
3143                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3144         </reg32>
3145         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3146         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3147         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3148         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3149
3150         <!-- probably: -->
3151         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
3152
3153         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3154
3155         <!-- always 0x0 ? -->
3156         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
3157
3158         <!-- always 0x80 ? -->
3159         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3160         <!-- always 0x0 ? -->
3161         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3162         <!-- always 0x0 ? -->
3163         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3164
3165 </domain>
3166
3167 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3168 <domain name="A6XX_TEX_SAMP" width="32">
3169         <doc>Texture sampler dwords</doc>
3170         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3171                 <value name="A6XX_TEX_NEAREST" value="0"/>
3172                 <value name="A6XX_TEX_LINEAR" value="1"/>
3173                 <value name="A6XX_TEX_ANISO" value="2"/>
3174         </enum>
3175         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3176                 <value name="A6XX_TEX_REPEAT" value="0"/>
3177                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3178                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3179                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3180                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3181         </enum>
3182         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3183                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3184                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3185                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3186                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3187                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3188         </enum>
3189         <reg32 offset="0" name="0">
3190                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3191                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3192                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3193                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3194                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3195                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3196                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3197                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3198         </reg32>
3199         <reg32 offset="1" name="1">
3200                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3201                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3202                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3203                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3204                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3205                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3206         </reg32>
3207         <reg32 offset="2" name="2">
3208                 <bitfield name="BCOLOR_OFFSET" low="0" high="31"/>
3209         </reg32>
3210         <reg32 offset="3" name="3"/>
3211 </domain>
3212
3213 <domain name="A6XX_TEX_CONST" width="32">
3214         <doc>Texture constant dwords</doc>
3215         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3216                 <value name="A6XX_TEX_X" value="0"/>
3217                 <value name="A6XX_TEX_Y" value="1"/>
3218                 <value name="A6XX_TEX_Z" value="2"/>
3219                 <value name="A6XX_TEX_W" value="3"/>
3220                 <value name="A6XX_TEX_ZERO" value="4"/>
3221                 <value name="A6XX_TEX_ONE" value="5"/>
3222         </enum>
3223         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3224                 <value name="A6XX_TEX_1D" value="0"/>
3225                 <value name="A6XX_TEX_2D" value="1"/>
3226                 <value name="A6XX_TEX_CUBE" value="2"/>
3227                 <value name="A6XX_TEX_3D" value="3"/>
3228         </enum>
3229         <reg32 offset="0" name="0">
3230                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3231                 <bitfield name="SRGB" pos="2" type="boolean"/>
3232                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3233                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3234                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3235                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3236                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3237                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3238                 <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
3239                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3240         </reg32>
3241         <reg32 offset="1" name="1">
3242                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3243                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3244         </reg32>
3245         <reg32 offset="2" name="2">
3246                 <!--
3247                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3248                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3249
3250                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3251                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3252                  -->
3253                 <bitfield name="UNK4" pos="4" type="boolean"/>
3254                 <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
3255                 <doc>Pitch in bytes (so actually stride)</doc>
3256                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3257                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3258                 <bitfield name="UNK31" pos="31" type="boolean"/>
3259         </reg32>
3260         <reg32 offset="3" name="3">
3261                 <!--
3262                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3263                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3264                 layer size at the point that it stops being reduced moving to
3265                 higher (smaller) mipmap levels
3266                  -->
3267                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3268                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3269                 <bitfield name="UNK27" pos="27" type="boolean"/>
3270                 <bitfield name="FLAG" pos="28" type="boolean"/>
3271         </reg32>
3272         <reg32 offset="4" name="4">
3273                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3274         </reg32>
3275         <reg32 offset="5" name="5">
3276                 <bitfield name="BASE_HI" low="0" high="16"/>
3277                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3278         </reg32>
3279         <reg32 offset="6" name="6"/>
3280         <reg32 offset="7" name="7">
3281                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3282         </reg32>
3283         <reg32 offset="8" name="8">
3284                 <bitfield name="FLAG_HI" low="0" high="16"/>
3285         </reg32>
3286         <reg32 offset="9" name="9">
3287                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3288         </reg32>
3289         <reg32 offset="10" name="10">
3290                 <!--
3291                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3292                 don't seem to be particularly sensible... or needed for UBWC to work
3293                  -->
3294                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3295         </reg32>
3296         <reg32 offset="11" name="11"/>
3297         <reg32 offset="12" name="12"/>
3298         <reg32 offset="13" name="13"/>
3299         <reg32 offset="14" name="14"/>
3300         <reg32 offset="15" name="15"/>
3301 </domain>
3302
3303 <!--
3304 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3305 naming is just because I r/e'd SSBOs first.  I should probably come up
3306 with a better name.
3307 -->
3308 <domain name="A6XX_IBO" width="32">
3309         <reg32 offset="0" name="0">
3310                 <!--
3311                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3312                 used but if they are good chance position is same as TEX_CONST
3313                  -->
3314                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3315                 <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
3316         </reg32>
3317         <reg32 offset="1" name="1">
3318                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3319                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3320         </reg32>
3321         <reg32 offset="2" name="2">
3322                 <!--
3323                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3324                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3325                  -->
3326                 <bitfield name="UNK4" pos="4" type="boolean"/>
3327                 <doc>Pitch in bytes (so actually stride)</doc>
3328                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3329                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3330                 <bitfield name="UNK31" pos="31" type="boolean"/>
3331         </reg32>
3332         <reg32 offset="3" name="3">
3333                 <!--
3334                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3335                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3336                 layer size at the point that it stops being reduced moving to
3337                 higher (smaller) mipmap levels
3338                  -->
3339                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3340                 <bitfield name="UNK27" pos="27" type="boolean"/>
3341                 <bitfield name="FLAG" pos="28" type="boolean"/>
3342         </reg32>
3343         <reg32 offset="4" name="4">
3344                 <bitfield name="BASE_LO" low="0" high="31"/>
3345         </reg32>
3346         <reg32 offset="5" name="5">
3347                 <bitfield name="BASE_HI" low="0" high="16"/>
3348                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3349         </reg32>
3350         <reg32 offset="6" name="6">
3351         </reg32>
3352         <reg32 offset="7" name="7">
3353         </reg32>
3354         <reg32 offset="8" name="8">
3355         </reg32>
3356         <reg32 offset="9" name="9">
3357                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3358         </reg32>
3359         <reg32 offset="10" name="10">
3360                 <!--
3361                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3362                 don't seem to be particularly sensible... or needed for UBWC to work
3363                  -->
3364                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3365         </reg32>
3366 </domain>
3367
3368 <domain name="A6XX_UBO" width="32">
3369         <reg32 offset="0" name="0">
3370                 <bitfield name="BASE_LO" low="0" high="31"/>
3371         </reg32>
3372         <reg32 offset="1" name="1">
3373                 <bitfield name="BASE_HI" low="0" high="16"/>
3374                 <!-- size probably in high bits -->
3375         </reg32>
3376 </domain>
3377
3378 <domain name="CP_UNK_A6XX_55" width="32">
3379         <reg32 offset="0" name="0">
3380                 <bitfield name="BASE_LO" low="0" high="31"/>
3381         </reg32>
3382         <reg32 offset="1" name="1">
3383                 <bitfield name="BASE_HI" low="0" high="16"/>
3384         </reg32>
3385         <reg32 offset="2" name="2">
3386                 <bitfield name="SIZE" low="0" high="15"/>
3387         </reg32>
3388 </domain>
3389
3390 <domain name="A6XX_PDC" width="32">
3391         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3392         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3393         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3394         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3395         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3396         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3397         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3398         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3399         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3400         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3401         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3402         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3403         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3404         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3405         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3406         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3407         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3408         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3409         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3410         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3411         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3412         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3413         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3414         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3415         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3416         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3417 </domain>
3418
3419 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3420         <reg32 offset="0x0" name="MEM_0"/>
3421 </domain>
3422
3423 <domain name="A6XX_CX_DBGC" width="32">
3424         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3425                 <bitfield high="7" low="0" name="PING_INDEX"/>
3426                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3427         </reg32>
3428         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3429         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3430         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3431         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3432                 <bitfield high="5" low="0" name="TRACEEN"/>
3433                 <bitfield high="14" low="12" name="GRANU"/>
3434                 <bitfield high="31" low="28" name="SEGT"/>
3435         </reg32>
3436         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3437                 <bitfield high="27" low="24" name="ENABLE"/>
3438         </reg32>
3439         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3440         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3441         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3442         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3443         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3444         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3445         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3446         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3447         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3448                 <bitfield high="3" low="0" name="BYTEL0"/>
3449                 <bitfield high="7" low="4" name="BYTEL1"/>
3450                 <bitfield high="11" low="8" name="BYTEL2"/>
3451                 <bitfield high="15" low="12" name="BYTEL3"/>
3452                 <bitfield high="19" low="16" name="BYTEL4"/>
3453                 <bitfield high="23" low="20" name="BYTEL5"/>
3454                 <bitfield high="27" low="24" name="BYTEL6"/>
3455                 <bitfield high="31" low="28" name="BYTEL7"/>
3456         </reg32>
3457         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3458                 <bitfield high="3" low="0" name="BYTEL8"/>
3459                 <bitfield high="7" low="4" name="BYTEL9"/>
3460                 <bitfield high="11" low="8" name="BYTEL10"/>
3461                 <bitfield high="15" low="12" name="BYTEL11"/>
3462                 <bitfield high="19" low="16" name="BYTEL12"/>
3463                 <bitfield high="23" low="20" name="BYTEL13"/>
3464                 <bitfield high="27" low="24" name="BYTEL14"/>
3465                 <bitfield high="31" low="28" name="BYTEL15"/>
3466         </reg32>
3467
3468         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3469         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3470 </domain>
3471
3472 <domain name="A6XX_CX_MISC" width="32">
3473         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3474         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3475 </domain>
3476
3477 </database>