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freedreno: update generated headers
[mesa.git] / src / freedreno / registers / a6xx.xml.h
1 #ifndef A6XX_XML
2 #define A6XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-06-11 15:59:35)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2019 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum a6xx_color_fmt {
50 RB6_A8_UNORM = 2,
51 RB6_R8_UNORM = 3,
52 RB6_R8_SNORM = 4,
53 RB6_R8_UINT = 5,
54 RB6_R8_SINT = 6,
55 RB6_R4G4B4A4_UNORM = 8,
56 RB6_R5G5B5A1_UNORM = 10,
57 RB6_R5G6B5_UNORM = 14,
58 RB6_R8G8_UNORM = 15,
59 RB6_R8G8_SNORM = 16,
60 RB6_R8G8_UINT = 17,
61 RB6_R8G8_SINT = 18,
62 RB6_R16_UNORM = 21,
63 RB6_R16_SNORM = 22,
64 RB6_R16_FLOAT = 23,
65 RB6_R16_UINT = 24,
66 RB6_R16_SINT = 25,
67 RB6_R8G8B8A8_UNORM = 48,
68 RB6_R8G8B8_UNORM = 49,
69 RB6_R8G8B8A8_SNORM = 50,
70 RB6_R8G8B8A8_UINT = 51,
71 RB6_R8G8B8A8_SINT = 52,
72 RB6_R10G10B10A2_UNORM = 55,
73 RB6_R10G10B10A2_UINT = 58,
74 RB6_R11G11B10_FLOAT = 66,
75 RB6_R16G16_UNORM = 67,
76 RB6_R16G16_SNORM = 68,
77 RB6_R16G16_FLOAT = 69,
78 RB6_R16G16_UINT = 70,
79 RB6_R16G16_SINT = 71,
80 RB6_R32_FLOAT = 74,
81 RB6_R32_UINT = 75,
82 RB6_R32_SINT = 76,
83 RB6_R16G16B16A16_UNORM = 96,
84 RB6_R16G16B16A16_SNORM = 97,
85 RB6_R16G16B16A16_FLOAT = 98,
86 RB6_R16G16B16A16_UINT = 99,
87 RB6_R16G16B16A16_SINT = 100,
88 RB6_R32G32_FLOAT = 103,
89 RB6_R32G32_UINT = 104,
90 RB6_R32G32_SINT = 105,
91 RB6_R32G32B32A32_FLOAT = 130,
92 RB6_R32G32B32A32_UINT = 131,
93 RB6_R32G32B32A32_SINT = 132,
94 RB6_Z24_UNORM_S8_UINT = 145,
95 RB6_X8Z24_UNORM = 160,
96 };
97
98 enum a6xx_tile_mode {
99 TILE6_LINEAR = 0,
100 TILE6_2 = 2,
101 TILE6_3 = 3,
102 };
103
104 enum a6xx_vtx_fmt {
105 VFMT6_8_UNORM = 3,
106 VFMT6_8_SNORM = 4,
107 VFMT6_8_UINT = 5,
108 VFMT6_8_SINT = 6,
109 VFMT6_8_8_UNORM = 15,
110 VFMT6_8_8_SNORM = 16,
111 VFMT6_8_8_UINT = 17,
112 VFMT6_8_8_SINT = 18,
113 VFMT6_16_UNORM = 21,
114 VFMT6_16_SNORM = 22,
115 VFMT6_16_FLOAT = 23,
116 VFMT6_16_UINT = 24,
117 VFMT6_16_SINT = 25,
118 VFMT6_8_8_8_UNORM = 33,
119 VFMT6_8_8_8_SNORM = 34,
120 VFMT6_8_8_8_UINT = 35,
121 VFMT6_8_8_8_SINT = 36,
122 VFMT6_8_8_8_8_UNORM = 48,
123 VFMT6_8_8_8_8_SNORM = 50,
124 VFMT6_8_8_8_8_UINT = 51,
125 VFMT6_8_8_8_8_SINT = 52,
126 VFMT6_10_10_10_2_UNORM = 54,
127 VFMT6_10_10_10_2_SNORM = 57,
128 VFMT6_10_10_10_2_UINT = 58,
129 VFMT6_10_10_10_2_SINT = 59,
130 VFMT6_11_11_10_FLOAT = 66,
131 VFMT6_16_16_UNORM = 67,
132 VFMT6_16_16_SNORM = 68,
133 VFMT6_16_16_FLOAT = 69,
134 VFMT6_16_16_UINT = 70,
135 VFMT6_16_16_SINT = 71,
136 VFMT6_32_UNORM = 72,
137 VFMT6_32_SNORM = 73,
138 VFMT6_32_FLOAT = 74,
139 VFMT6_32_UINT = 75,
140 VFMT6_32_SINT = 76,
141 VFMT6_32_FIXED = 77,
142 VFMT6_16_16_16_UNORM = 88,
143 VFMT6_16_16_16_SNORM = 89,
144 VFMT6_16_16_16_FLOAT = 90,
145 VFMT6_16_16_16_UINT = 91,
146 VFMT6_16_16_16_SINT = 92,
147 VFMT6_16_16_16_16_UNORM = 96,
148 VFMT6_16_16_16_16_SNORM = 97,
149 VFMT6_16_16_16_16_FLOAT = 98,
150 VFMT6_16_16_16_16_UINT = 99,
151 VFMT6_16_16_16_16_SINT = 100,
152 VFMT6_32_32_UNORM = 101,
153 VFMT6_32_32_SNORM = 102,
154 VFMT6_32_32_FLOAT = 103,
155 VFMT6_32_32_UINT = 104,
156 VFMT6_32_32_SINT = 105,
157 VFMT6_32_32_FIXED = 106,
158 VFMT6_32_32_32_UNORM = 112,
159 VFMT6_32_32_32_SNORM = 113,
160 VFMT6_32_32_32_UINT = 114,
161 VFMT6_32_32_32_SINT = 115,
162 VFMT6_32_32_32_FLOAT = 116,
163 VFMT6_32_32_32_FIXED = 117,
164 VFMT6_32_32_32_32_UNORM = 128,
165 VFMT6_32_32_32_32_SNORM = 129,
166 VFMT6_32_32_32_32_FLOAT = 130,
167 VFMT6_32_32_32_32_UINT = 131,
168 VFMT6_32_32_32_32_SINT = 132,
169 VFMT6_32_32_32_32_FIXED = 133,
170 };
171
172 enum a6xx_tex_fmt {
173 TFMT6_A8_UNORM = 2,
174 TFMT6_8_UNORM = 3,
175 TFMT6_8_SNORM = 4,
176 TFMT6_8_UINT = 5,
177 TFMT6_8_SINT = 6,
178 TFMT6_4_4_4_4_UNORM = 8,
179 TFMT6_5_5_5_1_UNORM = 10,
180 TFMT6_5_6_5_UNORM = 14,
181 TFMT6_8_8_UNORM = 15,
182 TFMT6_8_8_SNORM = 16,
183 TFMT6_8_8_UINT = 17,
184 TFMT6_8_8_SINT = 18,
185 TFMT6_L8_A8_UNORM = 19,
186 TFMT6_16_UNORM = 21,
187 TFMT6_16_SNORM = 22,
188 TFMT6_16_FLOAT = 23,
189 TFMT6_16_UINT = 24,
190 TFMT6_16_SINT = 25,
191 TFMT6_8_8_8_8_UNORM = 48,
192 TFMT6_8_8_8_UNORM = 49,
193 TFMT6_8_8_8_8_SNORM = 50,
194 TFMT6_8_8_8_8_UINT = 51,
195 TFMT6_8_8_8_8_SINT = 52,
196 TFMT6_9_9_9_E5_FLOAT = 53,
197 TFMT6_10_10_10_2_UNORM = 54,
198 TFMT6_10_10_10_2_UINT = 58,
199 TFMT6_11_11_10_FLOAT = 66,
200 TFMT6_16_16_UNORM = 67,
201 TFMT6_16_16_SNORM = 68,
202 TFMT6_16_16_FLOAT = 69,
203 TFMT6_16_16_UINT = 70,
204 TFMT6_16_16_SINT = 71,
205 TFMT6_32_FLOAT = 74,
206 TFMT6_32_UINT = 75,
207 TFMT6_32_SINT = 76,
208 TFMT6_16_16_16_16_UNORM = 96,
209 TFMT6_16_16_16_16_SNORM = 97,
210 TFMT6_16_16_16_16_FLOAT = 98,
211 TFMT6_16_16_16_16_UINT = 99,
212 TFMT6_16_16_16_16_SINT = 100,
213 TFMT6_32_32_FLOAT = 103,
214 TFMT6_32_32_UINT = 104,
215 TFMT6_32_32_SINT = 105,
216 TFMT6_32_32_32_UINT = 114,
217 TFMT6_32_32_32_SINT = 115,
218 TFMT6_32_32_32_FLOAT = 116,
219 TFMT6_32_32_32_32_FLOAT = 130,
220 TFMT6_32_32_32_32_UINT = 131,
221 TFMT6_32_32_32_32_SINT = 132,
222 TFMT6_Z24_UNORM_S8_UINT = 145,
223 TFMT6_X8Z24_UNORM = 160,
224 TFMT6_ETC2_RG11_UNORM = 171,
225 TFMT6_ETC2_RG11_SNORM = 172,
226 TFMT6_ETC2_R11_UNORM = 173,
227 TFMT6_ETC2_R11_SNORM = 174,
228 TFMT6_ETC1 = 175,
229 TFMT6_ETC2_RGB8 = 176,
230 TFMT6_ETC2_RGBA8 = 177,
231 TFMT6_ETC2_RGB8A1 = 178,
232 TFMT6_DXT1 = 179,
233 TFMT6_DXT3 = 180,
234 TFMT6_DXT5 = 181,
235 TFMT6_RGTC1_UNORM = 183,
236 TFMT6_RGTC1_SNORM = 184,
237 TFMT6_RGTC2_UNORM = 187,
238 TFMT6_RGTC2_SNORM = 188,
239 TFMT6_BPTC_UFLOAT = 190,
240 TFMT6_BPTC_FLOAT = 191,
241 TFMT6_BPTC = 192,
242 TFMT6_ASTC_4x4 = 193,
243 TFMT6_ASTC_5x4 = 194,
244 TFMT6_ASTC_5x5 = 195,
245 TFMT6_ASTC_6x5 = 196,
246 TFMT6_ASTC_6x6 = 197,
247 TFMT6_ASTC_8x5 = 198,
248 TFMT6_ASTC_8x6 = 199,
249 TFMT6_ASTC_8x8 = 200,
250 TFMT6_ASTC_10x5 = 201,
251 TFMT6_ASTC_10x6 = 202,
252 TFMT6_ASTC_10x8 = 203,
253 TFMT6_ASTC_10x10 = 204,
254 TFMT6_ASTC_12x10 = 205,
255 TFMT6_ASTC_12x12 = 206,
256 };
257
258 enum a6xx_tex_fetchsize {
259 TFETCH6_1_BYTE = 0,
260 TFETCH6_2_BYTE = 1,
261 TFETCH6_4_BYTE = 2,
262 TFETCH6_8_BYTE = 3,
263 TFETCH6_16_BYTE = 4,
264 };
265
266 enum a6xx_depth_format {
267 DEPTH6_NONE = 0,
268 DEPTH6_16 = 1,
269 DEPTH6_24_8 = 2,
270 DEPTH6_32 = 4,
271 };
272
273 enum a6xx_shader_id {
274 A6XX_TP0_TMO_DATA = 9,
275 A6XX_TP0_SMO_DATA = 10,
276 A6XX_TP0_MIPMAP_BASE_DATA = 11,
277 A6XX_TP1_TMO_DATA = 25,
278 A6XX_TP1_SMO_DATA = 26,
279 A6XX_TP1_MIPMAP_BASE_DATA = 27,
280 A6XX_SP_INST_DATA = 41,
281 A6XX_SP_LB_0_DATA = 42,
282 A6XX_SP_LB_1_DATA = 43,
283 A6XX_SP_LB_2_DATA = 44,
284 A6XX_SP_LB_3_DATA = 45,
285 A6XX_SP_LB_4_DATA = 46,
286 A6XX_SP_LB_5_DATA = 47,
287 A6XX_SP_CB_BINDLESS_DATA = 48,
288 A6XX_SP_CB_LEGACY_DATA = 49,
289 A6XX_SP_UAV_DATA = 50,
290 A6XX_SP_INST_TAG = 51,
291 A6XX_SP_CB_BINDLESS_TAG = 52,
292 A6XX_SP_TMO_UMO_TAG = 53,
293 A6XX_SP_SMO_TAG = 54,
294 A6XX_SP_STATE_DATA = 55,
295 A6XX_HLSQ_CHUNK_CVS_RAM = 73,
296 A6XX_HLSQ_CHUNK_CPS_RAM = 74,
297 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
298 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
299 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
300 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
301 A6XX_HLSQ_CVS_MISC_RAM = 80,
302 A6XX_HLSQ_CPS_MISC_RAM = 81,
303 A6XX_HLSQ_INST_RAM = 82,
304 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
305 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
306 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
307 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
308 A6XX_HLSQ_INST_RAM_TAG = 87,
309 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
310 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
311 A6XX_HLSQ_PWR_REST_RAM = 90,
312 A6XX_HLSQ_PWR_REST_TAG = 91,
313 A6XX_HLSQ_DATAPATH_META = 96,
314 A6XX_HLSQ_FRONTEND_META = 97,
315 A6XX_HLSQ_INDIRECT_META = 98,
316 A6XX_HLSQ_BACKEND_META = 99,
317 };
318
319 enum a6xx_debugbus_id {
320 A6XX_DBGBUS_CP = 1,
321 A6XX_DBGBUS_RBBM = 2,
322 A6XX_DBGBUS_VBIF = 3,
323 A6XX_DBGBUS_HLSQ = 4,
324 A6XX_DBGBUS_UCHE = 5,
325 A6XX_DBGBUS_DPM = 6,
326 A6XX_DBGBUS_TESS = 7,
327 A6XX_DBGBUS_PC = 8,
328 A6XX_DBGBUS_VFDP = 9,
329 A6XX_DBGBUS_VPC = 10,
330 A6XX_DBGBUS_TSE = 11,
331 A6XX_DBGBUS_RAS = 12,
332 A6XX_DBGBUS_VSC = 13,
333 A6XX_DBGBUS_COM = 14,
334 A6XX_DBGBUS_LRZ = 16,
335 A6XX_DBGBUS_A2D = 17,
336 A6XX_DBGBUS_CCUFCHE = 18,
337 A6XX_DBGBUS_GMU_CX = 19,
338 A6XX_DBGBUS_RBP = 20,
339 A6XX_DBGBUS_DCS = 21,
340 A6XX_DBGBUS_DBGC = 22,
341 A6XX_DBGBUS_CX = 23,
342 A6XX_DBGBUS_GMU_GX = 24,
343 A6XX_DBGBUS_TPFCHE = 25,
344 A6XX_DBGBUS_GBIF_GX = 26,
345 A6XX_DBGBUS_GPC = 29,
346 A6XX_DBGBUS_LARC = 30,
347 A6XX_DBGBUS_HLSQ_SPTP = 31,
348 A6XX_DBGBUS_RB_0 = 32,
349 A6XX_DBGBUS_RB_1 = 33,
350 A6XX_DBGBUS_UCHE_WRAPPER = 36,
351 A6XX_DBGBUS_CCU_0 = 40,
352 A6XX_DBGBUS_CCU_1 = 41,
353 A6XX_DBGBUS_VFD_0 = 56,
354 A6XX_DBGBUS_VFD_1 = 57,
355 A6XX_DBGBUS_VFD_2 = 58,
356 A6XX_DBGBUS_VFD_3 = 59,
357 A6XX_DBGBUS_SP_0 = 64,
358 A6XX_DBGBUS_SP_1 = 65,
359 A6XX_DBGBUS_TPL1_0 = 72,
360 A6XX_DBGBUS_TPL1_1 = 73,
361 A6XX_DBGBUS_TPL1_2 = 74,
362 A6XX_DBGBUS_TPL1_3 = 75,
363 };
364
365 enum a6xx_cp_perfcounter_select {
366 PERF_CP_ALWAYS_COUNT = 0,
367 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
368 PERF_CP_BUSY_CYCLES = 2,
369 PERF_CP_NUM_PREEMPTIONS = 3,
370 PERF_CP_PREEMPTION_REACTION_DELAY = 4,
371 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
372 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
373 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
374 PERF_CP_PREDICATED_DRAWS_KILLED = 8,
375 PERF_CP_MODE_SWITCH = 9,
376 PERF_CP_ZPASS_DONE = 10,
377 PERF_CP_CONTEXT_DONE = 11,
378 PERF_CP_CACHE_FLUSH = 12,
379 PERF_CP_LONG_PREEMPTIONS = 13,
380 PERF_CP_SQE_I_CACHE_STARVE = 14,
381 PERF_CP_SQE_IDLE = 15,
382 PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
383 PERF_CP_SQE_PM4_STARVE_SDS = 17,
384 PERF_CP_SQE_MRB_STARVE = 18,
385 PERF_CP_SQE_RRB_STARVE = 19,
386 PERF_CP_SQE_VSD_STARVE = 20,
387 PERF_CP_VSD_DECODE_STARVE = 21,
388 PERF_CP_SQE_PIPE_OUT_STALL = 22,
389 PERF_CP_SQE_SYNC_STALL = 23,
390 PERF_CP_SQE_PM4_WFI_STALL = 24,
391 PERF_CP_SQE_SYS_WFI_STALL = 25,
392 PERF_CP_SQE_T4_EXEC = 26,
393 PERF_CP_SQE_LOAD_STATE_EXEC = 27,
394 PERF_CP_SQE_SAVE_SDS_STATE = 28,
395 PERF_CP_SQE_DRAW_EXEC = 29,
396 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
397 PERF_CP_SQE_EXEC_PROFILED = 31,
398 PERF_CP_MEMORY_POOL_EMPTY = 32,
399 PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
400 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
401 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
402 PERF_CP_AHB_STALL_SQE_GMU = 36,
403 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
404 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
405 PERF_CP_CLUSTER0_EMPTY = 39,
406 PERF_CP_CLUSTER1_EMPTY = 40,
407 PERF_CP_CLUSTER2_EMPTY = 41,
408 PERF_CP_CLUSTER3_EMPTY = 42,
409 PERF_CP_CLUSTER4_EMPTY = 43,
410 PERF_CP_CLUSTER5_EMPTY = 44,
411 PERF_CP_PM4_DATA = 45,
412 PERF_CP_PM4_HEADERS = 46,
413 PERF_CP_VBIF_READ_BEATS = 47,
414 PERF_CP_VBIF_WRITE_BEATS = 48,
415 PERF_CP_SQE_INSTR_COUNTER = 49,
416 };
417
418 enum a6xx_rbbm_perfcounter_select {
419 PERF_RBBM_ALWAYS_COUNT = 0,
420 PERF_RBBM_ALWAYS_ON = 1,
421 PERF_RBBM_TSE_BUSY = 2,
422 PERF_RBBM_RAS_BUSY = 3,
423 PERF_RBBM_PC_DCALL_BUSY = 4,
424 PERF_RBBM_PC_VSD_BUSY = 5,
425 PERF_RBBM_STATUS_MASKED = 6,
426 PERF_RBBM_COM_BUSY = 7,
427 PERF_RBBM_DCOM_BUSY = 8,
428 PERF_RBBM_VBIF_BUSY = 9,
429 PERF_RBBM_VSC_BUSY = 10,
430 PERF_RBBM_TESS_BUSY = 11,
431 PERF_RBBM_UCHE_BUSY = 12,
432 PERF_RBBM_HLSQ_BUSY = 13,
433 };
434
435 enum a6xx_pc_perfcounter_select {
436 PERF_PC_BUSY_CYCLES = 0,
437 PERF_PC_WORKING_CYCLES = 1,
438 PERF_PC_STALL_CYCLES_VFD = 2,
439 PERF_PC_STALL_CYCLES_TSE = 3,
440 PERF_PC_STALL_CYCLES_VPC = 4,
441 PERF_PC_STALL_CYCLES_UCHE = 5,
442 PERF_PC_STALL_CYCLES_TESS = 6,
443 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
444 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
445 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
446 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
447 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
448 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
449 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
450 PERF_PC_STARVE_CYCLES_DI = 14,
451 PERF_PC_VIS_STREAMS_LOADED = 15,
452 PERF_PC_INSTANCES = 16,
453 PERF_PC_VPC_PRIMITIVES = 17,
454 PERF_PC_DEAD_PRIM = 18,
455 PERF_PC_LIVE_PRIM = 19,
456 PERF_PC_VERTEX_HITS = 20,
457 PERF_PC_IA_VERTICES = 21,
458 PERF_PC_IA_PRIMITIVES = 22,
459 PERF_PC_GS_PRIMITIVES = 23,
460 PERF_PC_HS_INVOCATIONS = 24,
461 PERF_PC_DS_INVOCATIONS = 25,
462 PERF_PC_VS_INVOCATIONS = 26,
463 PERF_PC_GS_INVOCATIONS = 27,
464 PERF_PC_DS_PRIMITIVES = 28,
465 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
466 PERF_PC_3D_DRAWCALLS = 30,
467 PERF_PC_2D_DRAWCALLS = 31,
468 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
469 PERF_TESS_BUSY_CYCLES = 33,
470 PERF_TESS_WORKING_CYCLES = 34,
471 PERF_TESS_STALL_CYCLES_PC = 35,
472 PERF_TESS_STARVE_CYCLES_PC = 36,
473 PERF_PC_TSE_TRANSACTION = 37,
474 PERF_PC_TSE_VERTEX = 38,
475 PERF_PC_TESS_PC_UV_TRANS = 39,
476 PERF_PC_TESS_PC_UV_PATCHES = 40,
477 PERF_PC_TESS_FACTOR_TRANS = 41,
478 };
479
480 enum a6xx_vfd_perfcounter_select {
481 PERF_VFD_BUSY_CYCLES = 0,
482 PERF_VFD_STALL_CYCLES_UCHE = 1,
483 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
484 PERF_VFD_STALL_CYCLES_SP_INFO = 3,
485 PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
486 PERF_VFD_STARVE_CYCLES_UCHE = 5,
487 PERF_VFD_RBUFFER_FULL = 6,
488 PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
489 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
490 PERF_VFD_NUM_ATTRIBUTES = 9,
491 PERF_VFD_UPPER_SHADER_FIBERS = 10,
492 PERF_VFD_LOWER_SHADER_FIBERS = 11,
493 PERF_VFD_MODE_0_FIBERS = 12,
494 PERF_VFD_MODE_1_FIBERS = 13,
495 PERF_VFD_MODE_2_FIBERS = 14,
496 PERF_VFD_MODE_3_FIBERS = 15,
497 PERF_VFD_MODE_4_FIBERS = 16,
498 PERF_VFD_TOTAL_VERTICES = 17,
499 PERF_VFDP_STALL_CYCLES_VFD = 18,
500 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
501 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
502 PERF_VFDP_STARVE_CYCLES_PC = 21,
503 PERF_VFDP_VS_STAGE_WAVES = 22,
504 };
505
506 enum a6xx_hlsq_perfcounter_select {
507 PERF_HLSQ_BUSY_CYCLES = 0,
508 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
509 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
510 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
511 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
512 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
513 PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
514 PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
515 PERF_HLSQ_QUADS = 8,
516 PERF_HLSQ_CS_INVOCATIONS = 9,
517 PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
518 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
519 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
520 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
521 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
522 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
523 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
524 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
525 PERF_HLSQ_STALL_CYCLES_VPC = 18,
526 PERF_HLSQ_PIXELS = 19,
527 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
528 };
529
530 enum a6xx_vpc_perfcounter_select {
531 PERF_VPC_BUSY_CYCLES = 0,
532 PERF_VPC_WORKING_CYCLES = 1,
533 PERF_VPC_STALL_CYCLES_UCHE = 2,
534 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
535 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
536 PERF_VPC_STALL_CYCLES_PC = 5,
537 PERF_VPC_STALL_CYCLES_SP_LM = 6,
538 PERF_VPC_STARVE_CYCLES_SP = 7,
539 PERF_VPC_STARVE_CYCLES_LRZ = 8,
540 PERF_VPC_PC_PRIMITIVES = 9,
541 PERF_VPC_SP_COMPONENTS = 10,
542 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
543 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
544 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
545 PERF_VPC_LM_TRANSACTION = 14,
546 PERF_VPC_STREAMOUT_TRANSACTION = 15,
547 PERF_VPC_VS_BUSY_CYCLES = 16,
548 PERF_VPC_PS_BUSY_CYCLES = 17,
549 PERF_VPC_VS_WORKING_CYCLES = 18,
550 PERF_VPC_PS_WORKING_CYCLES = 19,
551 PERF_VPC_STARVE_CYCLES_RB = 20,
552 PERF_VPC_NUM_VPCRAM_READ_POS = 21,
553 PERF_VPC_WIT_FULL_CYCLES = 22,
554 PERF_VPC_VPCRAM_FULL_CYCLES = 23,
555 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
556 PERF_VPC_NUM_VPCRAM_WRITE = 25,
557 PERF_VPC_NUM_VPCRAM_READ_SO = 26,
558 PERF_VPC_NUM_ATTR_REQ_LM = 27,
559 };
560
561 enum a6xx_tse_perfcounter_select {
562 PERF_TSE_BUSY_CYCLES = 0,
563 PERF_TSE_CLIPPING_CYCLES = 1,
564 PERF_TSE_STALL_CYCLES_RAS = 2,
565 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
566 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
567 PERF_TSE_STARVE_CYCLES_PC = 5,
568 PERF_TSE_INPUT_PRIM = 6,
569 PERF_TSE_INPUT_NULL_PRIM = 7,
570 PERF_TSE_TRIVAL_REJ_PRIM = 8,
571 PERF_TSE_CLIPPED_PRIM = 9,
572 PERF_TSE_ZERO_AREA_PRIM = 10,
573 PERF_TSE_FACENESS_CULLED_PRIM = 11,
574 PERF_TSE_ZERO_PIXEL_PRIM = 12,
575 PERF_TSE_OUTPUT_NULL_PRIM = 13,
576 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
577 PERF_TSE_CINVOCATION = 15,
578 PERF_TSE_CPRIMITIVES = 16,
579 PERF_TSE_2D_INPUT_PRIM = 17,
580 PERF_TSE_2D_ALIVE_CYCLES = 18,
581 PERF_TSE_CLIP_PLANES = 19,
582 };
583
584 enum a6xx_ras_perfcounter_select {
585 PERF_RAS_BUSY_CYCLES = 0,
586 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
587 PERF_RAS_STALL_CYCLES_LRZ = 2,
588 PERF_RAS_STARVE_CYCLES_TSE = 3,
589 PERF_RAS_SUPER_TILES = 4,
590 PERF_RAS_8X4_TILES = 5,
591 PERF_RAS_MASKGEN_ACTIVE = 6,
592 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
593 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
594 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
595 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
596 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
597 PERF_RAS_BLOCKS = 12,
598 };
599
600 enum a6xx_uche_perfcounter_select {
601 PERF_UCHE_BUSY_CYCLES = 0,
602 PERF_UCHE_STALL_CYCLES_ARBITER = 1,
603 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
604 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
605 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
606 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
607 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
608 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
609 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
610 PERF_UCHE_READ_REQUESTS_TP = 9,
611 PERF_UCHE_READ_REQUESTS_VFD = 10,
612 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
613 PERF_UCHE_READ_REQUESTS_LRZ = 12,
614 PERF_UCHE_READ_REQUESTS_SP = 13,
615 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
616 PERF_UCHE_WRITE_REQUESTS_SP = 15,
617 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
618 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
619 PERF_UCHE_EVICTS = 18,
620 PERF_UCHE_BANK_REQ0 = 19,
621 PERF_UCHE_BANK_REQ1 = 20,
622 PERF_UCHE_BANK_REQ2 = 21,
623 PERF_UCHE_BANK_REQ3 = 22,
624 PERF_UCHE_BANK_REQ4 = 23,
625 PERF_UCHE_BANK_REQ5 = 24,
626 PERF_UCHE_BANK_REQ6 = 25,
627 PERF_UCHE_BANK_REQ7 = 26,
628 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
629 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
630 PERF_UCHE_GMEM_READ_BEATS = 29,
631 PERF_UCHE_TPH_REF_FULL = 30,
632 PERF_UCHE_TPH_VICTIM_FULL = 31,
633 PERF_UCHE_TPH_EXT_FULL = 32,
634 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
635 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
636 PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
637 PERF_UCHE_VBIF_READ_BEATS_PC = 36,
638 PERF_UCHE_READ_REQUESTS_PC = 37,
639 PERF_UCHE_RAM_READ_REQ = 38,
640 PERF_UCHE_RAM_WRITE_REQ = 39,
641 };
642
643 enum a6xx_tp_perfcounter_select {
644 PERF_TP_BUSY_CYCLES = 0,
645 PERF_TP_STALL_CYCLES_UCHE = 1,
646 PERF_TP_LATENCY_CYCLES = 2,
647 PERF_TP_LATENCY_TRANS = 3,
648 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
649 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
650 PERF_TP_L1_CACHELINE_REQUESTS = 6,
651 PERF_TP_L1_CACHELINE_MISSES = 7,
652 PERF_TP_SP_TP_TRANS = 8,
653 PERF_TP_TP_SP_TRANS = 9,
654 PERF_TP_OUTPUT_PIXELS = 10,
655 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
656 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
657 PERF_TP_QUADS_RECEIVED = 13,
658 PERF_TP_QUADS_OFFSET = 14,
659 PERF_TP_QUADS_SHADOW = 15,
660 PERF_TP_QUADS_ARRAY = 16,
661 PERF_TP_QUADS_GRADIENT = 17,
662 PERF_TP_QUADS_1D = 18,
663 PERF_TP_QUADS_2D = 19,
664 PERF_TP_QUADS_BUFFER = 20,
665 PERF_TP_QUADS_3D = 21,
666 PERF_TP_QUADS_CUBE = 22,
667 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
668 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
669 PERF_TP_OUTPUT_PIXELS_POINT = 25,
670 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
671 PERF_TP_OUTPUT_PIXELS_MIP = 27,
672 PERF_TP_OUTPUT_PIXELS_ANISO = 28,
673 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
674 PERF_TP_FLAG_CACHE_REQUESTS = 30,
675 PERF_TP_FLAG_CACHE_MISSES = 31,
676 PERF_TP_L1_5_L2_REQUESTS = 32,
677 PERF_TP_2D_OUTPUT_PIXELS = 33,
678 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
679 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
680 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
681 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
682 PERF_TP_TPA2TPC_TRANS = 38,
683 PERF_TP_L1_MISSES_ASTC_1TILE = 39,
684 PERF_TP_L1_MISSES_ASTC_2TILE = 40,
685 PERF_TP_L1_MISSES_ASTC_4TILE = 41,
686 PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
687 PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
688 PERF_TP_L1_BANK_CONFLICT = 44,
689 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
690 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
691 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
692 PERF_TP_FRONTEND_WORKING_CYCLES = 48,
693 PERF_TP_L1_TAG_WORKING_CYCLES = 49,
694 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
695 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
696 PERF_TP_BACKEND_WORKING_CYCLES = 52,
697 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
698 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
699 PERF_TP_STARVE_CYCLES_SP = 55,
700 PERF_TP_STARVE_CYCLES_UCHE = 56,
701 };
702
703 enum a6xx_sp_perfcounter_select {
704 PERF_SP_BUSY_CYCLES = 0,
705 PERF_SP_ALU_WORKING_CYCLES = 1,
706 PERF_SP_EFU_WORKING_CYCLES = 2,
707 PERF_SP_STALL_CYCLES_VPC = 3,
708 PERF_SP_STALL_CYCLES_TP = 4,
709 PERF_SP_STALL_CYCLES_UCHE = 5,
710 PERF_SP_STALL_CYCLES_RB = 6,
711 PERF_SP_NON_EXECUTION_CYCLES = 7,
712 PERF_SP_WAVE_CONTEXTS = 8,
713 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
714 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
715 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
716 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
717 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
718 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
719 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
720 PERF_SP_WAVE_CTRL_CYCLES = 16,
721 PERF_SP_WAVE_LOAD_CYCLES = 17,
722 PERF_SP_WAVE_EMIT_CYCLES = 18,
723 PERF_SP_WAVE_NOP_CYCLES = 19,
724 PERF_SP_WAVE_WAIT_CYCLES = 20,
725 PERF_SP_WAVE_FETCH_CYCLES = 21,
726 PERF_SP_WAVE_IDLE_CYCLES = 22,
727 PERF_SP_WAVE_END_CYCLES = 23,
728 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
729 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
730 PERF_SP_WAVE_JOIN_CYCLES = 26,
731 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
732 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
733 PERF_SP_LM_ATOMICS = 29,
734 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
735 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
736 PERF_SP_GM_ATOMICS = 32,
737 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
738 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
739 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
740 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
741 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
742 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
743 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
744 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
745 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
746 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
747 PERF_SP_VS_INSTRUCTIONS = 43,
748 PERF_SP_FS_INSTRUCTIONS = 44,
749 PERF_SP_ADDR_LOCK_COUNT = 45,
750 PERF_SP_UCHE_READ_TRANS = 46,
751 PERF_SP_UCHE_WRITE_TRANS = 47,
752 PERF_SP_EXPORT_VPC_TRANS = 48,
753 PERF_SP_EXPORT_RB_TRANS = 49,
754 PERF_SP_PIXELS_KILLED = 50,
755 PERF_SP_ICL1_REQUESTS = 51,
756 PERF_SP_ICL1_MISSES = 52,
757 PERF_SP_HS_INSTRUCTIONS = 53,
758 PERF_SP_DS_INSTRUCTIONS = 54,
759 PERF_SP_GS_INSTRUCTIONS = 55,
760 PERF_SP_CS_INSTRUCTIONS = 56,
761 PERF_SP_GPR_READ = 57,
762 PERF_SP_GPR_WRITE = 58,
763 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
764 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
765 PERF_SP_LM_BANK_CONFLICTS = 61,
766 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
767 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
768 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
769 PERF_SP_LM_WORKING_CYCLES = 65,
770 PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
771 PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
772 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
773 PERF_SP_STARVE_CYCLES_HLSQ = 69,
774 PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
775 PERF_SP_WORKING_EU = 71,
776 PERF_SP_ANY_EU_WORKING = 72,
777 PERF_SP_WORKING_EU_FS_STAGE = 73,
778 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
779 PERF_SP_WORKING_EU_VS_STAGE = 75,
780 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
781 PERF_SP_WORKING_EU_CS_STAGE = 77,
782 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
783 PERF_SP_GPR_READ_PREFETCH = 79,
784 PERF_SP_GPR_READ_CONFLICT = 80,
785 PERF_SP_GPR_WRITE_CONFLICT = 81,
786 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
787 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
788 PERF_SP_EXECUTABLE_WAVES = 84,
789 };
790
791 enum a6xx_rb_perfcounter_select {
792 PERF_RB_BUSY_CYCLES = 0,
793 PERF_RB_STALL_CYCLES_HLSQ = 1,
794 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
795 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
796 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
797 PERF_RB_STARVE_CYCLES_SP = 5,
798 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
799 PERF_RB_STARVE_CYCLES_CCU = 7,
800 PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
801 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
802 PERF_RB_Z_WORKLOAD = 10,
803 PERF_RB_HLSQ_ACTIVE = 11,
804 PERF_RB_Z_READ = 12,
805 PERF_RB_Z_WRITE = 13,
806 PERF_RB_C_READ = 14,
807 PERF_RB_C_WRITE = 15,
808 PERF_RB_TOTAL_PASS = 16,
809 PERF_RB_Z_PASS = 17,
810 PERF_RB_Z_FAIL = 18,
811 PERF_RB_S_FAIL = 19,
812 PERF_RB_BLENDED_FXP_COMPONENTS = 20,
813 PERF_RB_BLENDED_FP16_COMPONENTS = 21,
814 PERF_RB_PS_INVOCATIONS = 22,
815 PERF_RB_2D_ALIVE_CYCLES = 23,
816 PERF_RB_2D_STALL_CYCLES_A2D = 24,
817 PERF_RB_2D_STARVE_CYCLES_SRC = 25,
818 PERF_RB_2D_STARVE_CYCLES_SP = 26,
819 PERF_RB_2D_STARVE_CYCLES_DST = 27,
820 PERF_RB_2D_VALID_PIXELS = 28,
821 PERF_RB_3D_PIXELS = 29,
822 PERF_RB_BLENDER_WORKING_CYCLES = 30,
823 PERF_RB_ZPROC_WORKING_CYCLES = 31,
824 PERF_RB_CPROC_WORKING_CYCLES = 32,
825 PERF_RB_SAMPLER_WORKING_CYCLES = 33,
826 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
827 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
828 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
829 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
830 PERF_RB_STALL_CYCLES_VPC = 38,
831 PERF_RB_2D_INPUT_TRANS = 39,
832 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
833 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
834 PERF_RB_BLENDED_FP32_COMPONENTS = 42,
835 PERF_RB_COLOR_PIX_TILES = 43,
836 PERF_RB_STALL_CYCLES_CCU = 44,
837 PERF_RB_EARLY_Z_ARB3_GRANT = 45,
838 PERF_RB_LATE_Z_ARB3_GRANT = 46,
839 PERF_RB_EARLY_Z_SKIP_GRANT = 47,
840 };
841
842 enum a6xx_vsc_perfcounter_select {
843 PERF_VSC_BUSY_CYCLES = 0,
844 PERF_VSC_WORKING_CYCLES = 1,
845 PERF_VSC_STALL_CYCLES_UCHE = 2,
846 PERF_VSC_EOT_NUM = 3,
847 PERF_VSC_INPUT_TILES = 4,
848 };
849
850 enum a6xx_ccu_perfcounter_select {
851 PERF_CCU_BUSY_CYCLES = 0,
852 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
853 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
854 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
855 PERF_CCU_DEPTH_BLOCKS = 4,
856 PERF_CCU_COLOR_BLOCKS = 5,
857 PERF_CCU_DEPTH_BLOCK_HIT = 6,
858 PERF_CCU_COLOR_BLOCK_HIT = 7,
859 PERF_CCU_PARTIAL_BLOCK_READ = 8,
860 PERF_CCU_GMEM_READ = 9,
861 PERF_CCU_GMEM_WRITE = 10,
862 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
863 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
864 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
865 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
866 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
867 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
868 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
869 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
870 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
871 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
872 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
873 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
874 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
875 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
876 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
877 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
878 PERF_CCU_2D_RD_REQ = 27,
879 PERF_CCU_2D_WR_REQ = 28,
880 };
881
882 enum a6xx_lrz_perfcounter_select {
883 PERF_LRZ_BUSY_CYCLES = 0,
884 PERF_LRZ_STARVE_CYCLES_RAS = 1,
885 PERF_LRZ_STALL_CYCLES_RB = 2,
886 PERF_LRZ_STALL_CYCLES_VSC = 3,
887 PERF_LRZ_STALL_CYCLES_VPC = 4,
888 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
889 PERF_LRZ_STALL_CYCLES_UCHE = 6,
890 PERF_LRZ_LRZ_READ = 7,
891 PERF_LRZ_LRZ_WRITE = 8,
892 PERF_LRZ_READ_LATENCY = 9,
893 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
894 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
895 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
896 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
897 PERF_LRZ_FULL_8X8_TILES = 14,
898 PERF_LRZ_PARTIAL_8X8_TILES = 15,
899 PERF_LRZ_TILE_KILLED = 16,
900 PERF_LRZ_TOTAL_PIXEL = 17,
901 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
902 PERF_LRZ_FULLY_COVERED_TILES = 19,
903 PERF_LRZ_PARTIAL_COVERED_TILES = 20,
904 PERF_LRZ_FEEDBACK_ACCEPT = 21,
905 PERF_LRZ_FEEDBACK_DISCARD = 22,
906 PERF_LRZ_FEEDBACK_STALL = 23,
907 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
908 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
909 PERF_LRZ_STALL_CYCLES_VC = 26,
910 PERF_LRZ_RAS_MASK_TRANS = 27,
911 };
912
913 enum a6xx_cmp_perfcounter_select {
914 PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
915 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
916 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
917 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
918 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
919 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
920 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
921 PERF_CMPDECMP_VBIF_READ_DATA = 7,
922 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
923 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
924 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
925 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
926 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
927 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
928 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
929 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
930 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
931 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
932 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
933 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
934 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
935 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
936 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
937 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
938 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
939 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
940 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
941 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
942 PERF_CMPDECMP_2D_RD_DATA = 28,
943 PERF_CMPDECMP_2D_WR_DATA = 29,
944 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
945 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
946 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
947 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
948 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
949 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
950 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
951 PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
952 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
953 PERF_CMPDECMP_2D_PIXELS = 39,
954 };
955
956 enum a6xx_2d_ifmt {
957 R2D_UNORM8 = 16,
958 R2D_INT32 = 7,
959 R2D_INT16 = 6,
960 R2D_INT8 = 5,
961 R2D_FLOAT32 = 4,
962 R2D_FLOAT16 = 3,
963 };
964
965 enum a6xx_tess_spacing {
966 TESS_EQUAL = 0,
967 TESS_FRACTIONAL_ODD = 2,
968 TESS_FRACTIONAL_EVEN = 3,
969 };
970
971 enum a6xx_tex_filter {
972 A6XX_TEX_NEAREST = 0,
973 A6XX_TEX_LINEAR = 1,
974 A6XX_TEX_ANISO = 2,
975 };
976
977 enum a6xx_tex_clamp {
978 A6XX_TEX_REPEAT = 0,
979 A6XX_TEX_CLAMP_TO_EDGE = 1,
980 A6XX_TEX_MIRROR_REPEAT = 2,
981 A6XX_TEX_CLAMP_TO_BORDER = 3,
982 A6XX_TEX_MIRROR_CLAMP = 4,
983 };
984
985 enum a6xx_tex_aniso {
986 A6XX_TEX_ANISO_1 = 0,
987 A6XX_TEX_ANISO_2 = 1,
988 A6XX_TEX_ANISO_4 = 2,
989 A6XX_TEX_ANISO_8 = 3,
990 A6XX_TEX_ANISO_16 = 4,
991 };
992
993 enum a6xx_tex_swiz {
994 A6XX_TEX_X = 0,
995 A6XX_TEX_Y = 1,
996 A6XX_TEX_Z = 2,
997 A6XX_TEX_W = 3,
998 A6XX_TEX_ZERO = 4,
999 A6XX_TEX_ONE = 5,
1000 };
1001
1002 enum a6xx_tex_type {
1003 A6XX_TEX_1D = 0,
1004 A6XX_TEX_2D = 1,
1005 A6XX_TEX_CUBE = 2,
1006 A6XX_TEX_3D = 3,
1007 };
1008
1009 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1010 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
1011 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
1012 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1013 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1014 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1015 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1016 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1017 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1018 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1019 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1020 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1021 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1022 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1023 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1024 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1025 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
1026 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1027 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1028 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1029 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1030 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1031 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1032 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
1033 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
1034 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
1035 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
1036 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
1037 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
1038 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
1039 #define REG_A6XX_CP_RB_BASE 0x00000800
1040
1041 #define REG_A6XX_CP_RB_BASE_HI 0x00000801
1042
1043 #define REG_A6XX_CP_RB_CNTL 0x00000802
1044
1045 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
1046
1047 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
1048
1049 #define REG_A6XX_CP_RB_RPTR 0x00000806
1050
1051 #define REG_A6XX_CP_RB_WPTR 0x00000807
1052
1053 #define REG_A6XX_CP_SQE_CNTL 0x00000808
1054
1055 #define REG_A6XX_CP_HW_FAULT 0x00000821
1056
1057 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1058
1059 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1060
1061 #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
1062
1063 #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1064
1065 #define REG_A6XX_CP_MISC_CNTL 0x00000840
1066
1067 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1068
1069 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
1070
1071 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
1072
1073 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841
1074
1075 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
1076
1077 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
1078
1079 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
1080
1081 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1082
1083 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1084
1085 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1086
1087 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1088 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
1089 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1090 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1091 {
1092 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1093 }
1094 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
1095 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
1096 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1097 {
1098 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1099 }
1100 #define A6XX_CP_PROTECT_REG_READ 0x80000000
1101
1102 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
1103
1104 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
1105
1106 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
1107
1108 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
1109
1110 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
1111
1112 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1113
1114 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1115
1116 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1117
1118 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1119
1120 #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
1121
1122 #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1123
1124 #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1125
1126 #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1127
1128 #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1129
1130 #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1131
1132 #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1133
1134 #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1135
1136 #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1137
1138 #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1139
1140 #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1141
1142 #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1143
1144 #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1145
1146 #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1147
1148 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1149
1150 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1151
1152 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1153
1154 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1155
1156 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
1157
1158 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
1159
1160 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
1161
1162 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
1163
1164 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
1165
1166 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
1167
1168 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
1169
1170 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
1171
1172 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
1173
1174 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
1175
1176 #define REG_A6XX_CP_IB1_BASE 0x00000928
1177
1178 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929
1179
1180 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
1181
1182 #define REG_A6XX_CP_IB2_BASE 0x0000092b
1183
1184 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1185
1186 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1187
1188 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1189
1190 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1191
1192 #define REG_A6XX_CP_AHB_CNTL 0x0000098d
1193
1194 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1195
1196 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1197
1198 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1199
1200 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1201
1202 #define REG_A6XX_RBBM_STATUS 0x00000210
1203 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1204 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1205 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
1206 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
1207 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
1208 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
1209 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
1210 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
1211 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
1212 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
1213 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
1214 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
1215 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
1216 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
1217 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
1218 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
1219 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
1220 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
1221 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
1222 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
1223 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
1224 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
1225 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1226 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1227
1228 #define REG_A6XX_RBBM_STATUS3 0x00000213
1229
1230 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1231
1232 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
1233
1234 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1235
1236 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1237
1238 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1239
1240 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1241
1242 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1243
1244 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1245
1246 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1247
1248 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1249
1250 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1251
1252 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1253
1254 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1255
1256 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1257
1258 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1259
1260 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1261
1262 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1263
1264 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1265
1266 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1267
1268 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1269
1270 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1271
1272 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1273
1274 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1275
1276 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1277
1278 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1279
1280 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1281
1282 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1283
1284 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1285
1286 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1287
1288 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1289
1290 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1291
1292 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1293
1294 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1295
1296 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1297
1298 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1299
1300 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1301
1302 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1303
1304 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1305
1306 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1307
1308 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1309
1310 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1311
1312 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1313
1314 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1315
1316 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1317
1318 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1319
1320 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1321
1322 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1323
1324 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1325
1326 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1327
1328 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1329
1330 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1331
1332 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1333
1334 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1335
1336 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1337
1338 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1339
1340 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1341
1342 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1343
1344 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1345
1346 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1347
1348 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1349
1350 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1351
1352 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1353
1354 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1355
1356 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1357
1358 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1359
1360 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1361
1362 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1363
1364 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1365
1366 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1367
1368 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1369
1370 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1371
1372 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1373
1374 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1375
1376 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1377
1378 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1379
1380 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1381
1382 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1383
1384 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1385
1386 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1387
1388 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1389
1390 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1391
1392 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1393
1394 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1395
1396 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1397
1398 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1399
1400 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1401
1402 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1403
1404 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1405
1406 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1407
1408 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1409
1410 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1411
1412 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1413
1414 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1415
1416 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1417
1418 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1419
1420 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1421
1422 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1423
1424 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1425
1426 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1427
1428 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1429
1430 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1431
1432 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1433
1434 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1435
1436 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1437
1438 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1439
1440 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1441
1442 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1443
1444 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1445
1446 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1447
1448 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1449
1450 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1451
1452 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1453
1454 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1455
1456 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1457
1458 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1459
1460 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1461
1462 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1463
1464 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1465
1466 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1467
1468 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1469
1470 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1471
1472 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1473
1474 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1475
1476 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1477
1478 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1479
1480 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1481
1482 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1483
1484 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1485
1486 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1487
1488 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1489
1490 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1491
1492 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1493
1494 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1495
1496 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1497
1498 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1499
1500 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1501
1502 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1503
1504 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1505
1506 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1507
1508 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1509
1510 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1511
1512 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1513
1514 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1515
1516 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1517
1518 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1519
1520 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1521
1522 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1523
1524 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1525
1526 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1527
1528 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1529
1530 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1531
1532 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1533
1534 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1535
1536 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1537
1538 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1539
1540 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1541
1542 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1543
1544 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1545
1546 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1547
1548 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1549
1550 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1551
1552 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
1553
1554 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
1555
1556 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
1557
1558 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
1559
1560 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
1561
1562 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
1563
1564 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
1565
1566 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
1567
1568 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
1569
1570 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
1571
1572 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
1573
1574 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
1575
1576 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
1577
1578 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
1579
1580 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
1581
1582 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1583
1584 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1585
1586 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1587
1588 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1589
1590 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1591
1592 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1593
1594 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1595
1596 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1597
1598 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1599
1600 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1601
1602 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1603
1604 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1605
1606 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1607
1608 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1609
1610 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1611
1612 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1613
1614 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1615
1616 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1617
1618 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1619
1620 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1621
1622 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1623
1624 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1625
1626 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1627
1628 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1629
1630 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1631
1632 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1633
1634 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1635
1636 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1637
1638 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1639
1640 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1641
1642 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1643
1644 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1645
1646 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1647
1648 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1649
1650 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1651
1652 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1653
1654 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1655
1656 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1657
1658 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1659
1660 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1661
1662 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1663
1664 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1665
1666 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1667
1668 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1669
1670 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1671
1672 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1673
1674 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1675
1676 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1677
1678 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1679
1680 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1681
1682 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1683
1684 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1685
1686 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1687
1688 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1689
1690 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1691
1692 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1693
1694 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1695
1696 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1697
1698 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1699
1700 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1701
1702 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1703
1704 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1705
1706 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1707
1708 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1709
1710 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1711
1712 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1713
1714 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1715
1716 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1717
1718 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1719
1720 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1721
1722 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1723
1724 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1725
1726 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1727
1728 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1729
1730 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1731
1732 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1733
1734 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1735
1736 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1737
1738 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1739
1740 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1741
1742 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1743
1744 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1745
1746 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1747
1748 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1749
1750 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1751
1752 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1753
1754 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1755
1756 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1757
1758 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1759
1760 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1761
1762 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1763
1764 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1765
1766 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1767
1768 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1769
1770 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1771
1772 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1773
1774 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1775
1776 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1777
1778 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1779
1780 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1781
1782 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1783
1784 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1785
1786 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1787
1788 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1789
1790 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1791
1792 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1793
1794 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1795
1796 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1797
1798 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1799
1800 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1801
1802 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1803
1804 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1805
1806 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1807
1808 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1809
1810 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1811
1812 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1813
1814 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1815
1816 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1817
1818 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1819
1820 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1821
1822 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1823
1824 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1825
1826 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1827
1828 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1829
1830 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1831
1832 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1833
1834 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1835
1836 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1837
1838 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1839
1840 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1841
1842 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1843
1844 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1845
1846 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1847
1848 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1849
1850 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1851
1852 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1853
1854 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1855
1856 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1857
1858 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1859
1860 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1861
1862 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1863
1864 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1865
1866 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1867
1868 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1869
1870 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1871
1872 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1873
1874 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1875
1876 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1877
1878 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1879
1880 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1881
1882 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1883
1884 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1885
1886 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1887
1888 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1889
1890 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1891
1892 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1893
1894 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1895
1896 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1897
1898 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1899
1900 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1901
1902 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1903
1904 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1905
1906 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1907
1908 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1909
1910 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1911
1912 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1913
1914 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1915
1916 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1917
1918 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1919
1920 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1921
1922 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1923
1924 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1925
1926 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1927
1928 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1929
1930 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1931
1932 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
1933
1934 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
1935
1936 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
1937
1938 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
1939
1940 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
1941
1942 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
1943
1944 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
1945
1946 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
1947
1948 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
1949
1950 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
1951
1952 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
1953
1954 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
1955
1956 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
1957
1958 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
1959
1960 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
1961
1962 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
1963
1964 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
1965
1966 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
1967
1968 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
1969
1970 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
1971
1972 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
1973
1974 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
1975
1976 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
1977
1978 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
1979
1980 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
1981
1982 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
1983
1984 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
1985
1986 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
1987
1988 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
1989
1990 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
1991
1992 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
1993
1994 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
1995
1996 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
1997
1998 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
1999
2000 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
2001
2002 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
2003
2004 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
2005
2006 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
2007 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
2008 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
2009 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
2010 {
2011 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
2012 }
2013 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
2014 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
2015 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
2016 {
2017 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
2018 }
2019
2020 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
2021 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
2022 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
2023 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
2024 {
2025 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
2026 }
2027 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
2028 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
2029 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
2030 {
2031 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
2032 }
2033 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
2034 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
2035 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
2036 {
2037 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
2038 }
2039
2040 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
2041 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
2042 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
2043 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
2044 {
2045 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
2046 }
2047
2048 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
2049
2050 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
2051
2052 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
2053
2054 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
2055
2056 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
2057
2058 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
2059
2060 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
2061
2062 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
2063
2064 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
2065 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
2066 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
2067 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
2068 {
2069 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
2070 }
2071 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
2072 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
2073 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
2074 {
2075 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
2076 }
2077 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
2078 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
2079 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
2080 {
2081 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
2082 }
2083 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
2084 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
2085 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
2086 {
2087 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
2088 }
2089 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
2090 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
2091 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
2092 {
2093 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
2094 }
2095 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
2096 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
2097 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
2098 {
2099 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
2100 }
2101 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
2102 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
2103 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
2104 {
2105 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
2106 }
2107 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
2108 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
2109 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
2110 {
2111 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
2112 }
2113
2114 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
2115 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
2116 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
2117 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
2118 {
2119 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
2120 }
2121 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
2122 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
2123 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
2124 {
2125 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
2126 }
2127 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
2128 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
2129 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
2130 {
2131 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
2132 }
2133 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
2134 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
2135 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
2136 {
2137 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
2138 }
2139 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
2140 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
2141 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
2142 {
2143 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
2144 }
2145 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
2146 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
2147 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
2148 {
2149 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
2150 }
2151 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
2152 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
2153 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
2154 {
2155 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
2156 }
2157 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
2158 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
2159 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2160 {
2161 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2162 }
2163
2164 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2165
2166 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2167
2168 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
2169
2170 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
2171
2172 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
2173
2174 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
2175
2176 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
2177
2178 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
2179
2180 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
2181
2182 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
2183
2184 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
2185
2186 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
2187
2188 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
2189
2190 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
2191
2192 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
2193
2194 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
2195
2196 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
2197
2198 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
2199
2200 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
2201
2202 #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
2203
2204 #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
2205
2206 #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
2207
2208 #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
2209
2210 #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
2211
2212 #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
2213
2214 #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
2215
2216 #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
2217
2218 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
2219
2220 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
2221
2222 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
2223
2224 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
2225
2226 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
2227
2228 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
2229
2230 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
2231
2232 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
2233
2234 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
2235
2236 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
2237
2238 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
2239
2240 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
2241
2242 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
2243
2244 #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
2245
2246 #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
2247
2248 #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
2249
2250 #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
2251
2252 #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
2253
2254 #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
2255
2256 #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
2257
2258 #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
2259
2260 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
2261
2262 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
2263
2264 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
2265
2266 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
2267
2268 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
2269
2270 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
2271
2272 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2273
2274 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2275
2276 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2277
2278 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
2279
2280 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
2281
2282 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
2283
2284 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
2285
2286 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
2287
2288 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
2289
2290 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
2291
2292 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
2293
2294 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
2295
2296 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
2297
2298 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
2299
2300 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
2301
2302 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
2303
2304 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
2305
2306 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
2307
2308 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
2309
2310 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2311
2312 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2313
2314 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2315
2316 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2317
2318 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
2319
2320 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
2321
2322 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
2323
2324 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
2325
2326 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
2327
2328 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
2329
2330 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
2331
2332 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
2333
2334 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2335
2336 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2337
2338 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2339 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2340 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
2341 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2342 {
2343 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2344 }
2345
2346 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
2347
2348 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
2349
2350 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
2351
2352 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
2353
2354 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
2355
2356 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
2357
2358 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
2359
2360 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
2361
2362 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
2363
2364 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
2365
2366 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
2367
2368 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
2369
2370 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
2371
2372 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
2373
2374 #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
2375
2376 #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
2377
2378 #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
2379
2380 #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
2381
2382 #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
2383
2384 #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
2385
2386 #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
2387
2388 #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
2389
2390 #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
2391
2392 #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
2393
2394 #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
2395
2396 #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
2397
2398 #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
2399
2400 #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
2401
2402 #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
2403
2404 #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
2405
2406 #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
2407
2408 #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
2409
2410 #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
2411
2412 #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
2413
2414 #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
2415
2416 #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
2417
2418 #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
2419
2420 #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
2421
2422 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
2423
2424 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
2425
2426 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
2427
2428 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
2429
2430 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
2431
2432 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
2433
2434 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
2435
2436 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
2437
2438 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
2439
2440 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
2441
2442 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
2443
2444 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
2445
2446 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
2447
2448 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
2449
2450 #define REG_A6XX_VBIF_VERSION 0x00003000
2451
2452 #define REG_A6XX_VBIF_CLKON 0x00003001
2453 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
2454
2455 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2456
2457 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
2458
2459 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
2460
2461 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2462
2463 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2464
2465 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2466 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
2467 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
2468 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2469 {
2470 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2471 }
2472
2473 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2474
2475 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2476 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
2477 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
2478 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2479 {
2480 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2481 }
2482
2483 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
2484
2485 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
2486
2487 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
2488
2489 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
2490
2491 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
2492
2493 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
2494
2495 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
2496
2497 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
2498
2499 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
2500
2501 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2502
2503 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2504
2505 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2506
2507 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2508
2509 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2510
2511 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2512
2513 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2514
2515 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2516
2517 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2518
2519 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2520
2521 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2522
2523 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2524
2525 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2526
2527 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
2528 #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
2529 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
2530 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
2531 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
2532 {
2533 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
2534 }
2535 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000
2536 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
2537 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
2538 {
2539 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
2540 }
2541
2542 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
2543 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2544 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
2545 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
2546 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2547 {
2548 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2549 }
2550 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2551 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
2552 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2553 {
2554 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2555 }
2556
2557 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
2558 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2559 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
2560 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
2561 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2562 {
2563 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2564 }
2565 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2566 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
2567 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2568 {
2569 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2570 }
2571
2572 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
2573 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff
2574 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
2575 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2576 {
2577 assert(!(val & 0x1f));
2578 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2579 }
2580 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00
2581 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
2582 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2583 {
2584 assert(!(val & 0xf));
2585 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2586 }
2587 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
2588 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
2589
2590 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
2591 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff
2592 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
2593 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
2594 {
2595 assert(!(val & 0x1f));
2596 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
2597 }
2598 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00
2599 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
2600 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
2601 {
2602 assert(!(val & 0xf));
2603 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
2604 }
2605
2606 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2607 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2608 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2609 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2610 {
2611 assert(!(val & 0x1f));
2612 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2613 }
2614 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2615 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
2616 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2617 {
2618 assert(!(val & 0xf));
2619 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2620 }
2621
2622 #define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03
2623
2624 #define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04
2625
2626 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2627 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2628 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
2629 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2630 {
2631 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2632 }
2633 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
2634 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
2635 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2636 {
2637 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2638 }
2639
2640 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2641
2642 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2643 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2644 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2645 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2646 {
2647 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2648 }
2649 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2650 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2651 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2652 {
2653 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2654 }
2655 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
2656 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2657 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2658 {
2659 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2660 }
2661 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2662 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
2663 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2664 {
2665 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2666 }
2667
2668 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30
2669
2670 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31
2671
2672 #define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32
2673
2674 #define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33
2675 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff
2676 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0
2677 static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
2678 {
2679 assert(!(val & 0xf));
2680 return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
2681 }
2682
2683 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34
2684
2685 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35
2686
2687 #define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36
2688
2689 #define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37
2690 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff
2691 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0
2692 static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
2693 {
2694 assert(!(val & 0xf));
2695 return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
2696 }
2697
2698 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2699
2700 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2701
2702 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2703
2704 #define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000
2705
2706 #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001
2707
2708 #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004
2709
2710 #define REG_A6XX_GRAS_CNTL 0x00008005
2711 #define A6XX_GRAS_CNTL_VARYING 0x00000001
2712 #define A6XX_GRAS_CNTL_CENTROID 0x00000002
2713 #define A6XX_GRAS_CNTL_PERSAMP_VARYING 0x00000004
2714 #define A6XX_GRAS_CNTL_SIZE 0x00000008
2715 #define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
2716 #define A6XX_GRAS_CNTL_XCOORD 0x00000040
2717 #define A6XX_GRAS_CNTL_YCOORD 0x00000080
2718 #define A6XX_GRAS_CNTL_ZCOORD 0x00000100
2719 #define A6XX_GRAS_CNTL_WCOORD 0x00000200
2720
2721 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2722 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2723 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2724 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2725 {
2726 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2727 }
2728 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2729 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2730 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2731 {
2732 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2733 }
2734
2735 #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010
2736 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2737 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2738 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2739 {
2740 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2741 }
2742
2743 #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011
2744 #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2745 #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2746 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
2747 {
2748 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2749 }
2750
2751 #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012
2752 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2753 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2754 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2755 {
2756 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2757 }
2758
2759 #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013
2760 #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2761 #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2762 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
2763 {
2764 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2765 }
2766
2767 #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014
2768 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2769 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2770 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2771 {
2772 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2773 }
2774
2775 #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015
2776 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2777 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2778 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2779 {
2780 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2781 }
2782
2783 #define REG_A6XX_GRAS_SU_CNTL 0x00008090
2784 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2785 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2786 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2787 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2788 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2789 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2790 {
2791 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2792 }
2793 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2794 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2795
2796 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2797 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2798 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2799 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2800 {
2801 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2802 }
2803 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2804 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2805 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2806 {
2807 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2808 }
2809
2810 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2811 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2812 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
2813 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2814 {
2815 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2816 }
2817
2818 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
2819 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2820
2821 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2822 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2823 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2824 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2825 {
2826 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2827 }
2828
2829 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2830 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2831 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2832 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2833 {
2834 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2835 }
2836
2837 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2838 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2839 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2840 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2841 {
2842 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2843 }
2844
2845 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2846 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2847 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2848 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2849 {
2850 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2851 }
2852
2853 #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
2854
2855 #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b
2856
2857 #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
2858
2859 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2860 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2861 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2862 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2863 {
2864 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2865 }
2866
2867 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
2868 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2869 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2870 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2871 {
2872 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2873 }
2874 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2875
2876 #define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4
2877
2878 #define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5
2879
2880 #define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6
2881
2882 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
2883
2884 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0
2885 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2886 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2887 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2888 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2889 {
2890 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2891 }
2892 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2893 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2894 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2895 {
2896 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2897 }
2898
2899 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1
2900 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2901 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2902 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2903 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2904 {
2905 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2906 }
2907 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2908 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2909 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2910 {
2911 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2912 }
2913
2914 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0
2915 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2916 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2917 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2918 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2919 {
2920 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2921 }
2922 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2923 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2924 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2925 {
2926 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2927 }
2928
2929 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1
2930 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2931 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2932 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2933 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2934 {
2935 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2936 }
2937 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2938 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2939 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2940 {
2941 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2942 }
2943
2944 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
2945 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2946 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2947 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2948 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2949 {
2950 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2951 }
2952 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2953 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2954 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2955 {
2956 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2957 }
2958
2959 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
2960 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2961 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2962 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2963 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2964 {
2965 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2966 }
2967 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2968 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2969 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2970 {
2971 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2972 }
2973
2974 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2975 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2976 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2977 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2978 #define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008
2979 #define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010
2980
2981 #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
2982
2983 #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
2984 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
2985 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
2986 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
2987 {
2988 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2989 }
2990
2991 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
2992
2993 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
2994
2995 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
2996 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff
2997 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
2998 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2999 {
3000 assert(!(val & 0x1f));
3001 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
3002 }
3003 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
3004 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3005 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3006 {
3007 assert(!(val & 0x1f));
3008 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3009 }
3010
3011 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
3012
3013 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
3014
3015 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
3016 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3017
3018 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
3019
3020 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
3021 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000003
3022 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
3023 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(uint32_t val)
3024 {
3025 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
3026 }
3027 #define A6XX_GRAS_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004
3028 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000010
3029 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3030 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
3031 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3032 {
3033 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3034 }
3035 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
3036 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
3037 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
3038 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3039 {
3040 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
3041 }
3042
3043 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
3044 #define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0xffffff00
3045 #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8
3046 static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(int32_t val)
3047 {
3048 return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
3049 }
3050
3051 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
3052 #define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0xffffff00
3053 #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8
3054 static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(int32_t val)
3055 {
3056 return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
3057 }
3058
3059 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
3060 #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0xffffff00
3061 #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8
3062 static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(int32_t val)
3063 {
3064 return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
3065 }
3066
3067 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
3068 #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0xffffff00
3069 #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8
3070 static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(int32_t val)
3071 {
3072 return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
3073 }
3074
3075 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405
3076 #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000
3077 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff
3078 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
3079 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
3080 {
3081 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
3082 }
3083 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000
3084 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
3085 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
3086 {
3087 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
3088 }
3089
3090 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406
3091 #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000
3092 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff
3093 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
3094 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
3095 {
3096 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
3097 }
3098 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000
3099 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
3100 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
3101 {
3102 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
3103 }
3104
3105 #define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a
3106 #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3107 #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff
3108 #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0
3109 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
3110 {
3111 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
3112 }
3113 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3114 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16
3115 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
3116 {
3117 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
3118 }
3119
3120 #define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b
3121 #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3122 #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff
3123 #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0
3124 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
3125 {
3126 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
3127 }
3128 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3129 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16
3130 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
3131 {
3132 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
3133 }
3134
3135 #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
3136
3137 #define REG_A6XX_RB_BIN_CONTROL 0x00008800
3138 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff
3139 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
3140 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3141 {
3142 assert(!(val & 0x1f));
3143 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3144 }
3145 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00
3146 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
3147 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3148 {
3149 assert(!(val & 0xf));
3150 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3151 }
3152 #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
3153 #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
3154
3155 #define REG_A6XX_RB_RENDER_CNTL 0x00008801
3156 #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
3157 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
3158 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
3159 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
3160 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
3161 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3162 {
3163 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3164 }
3165
3166 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
3167 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3168 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3169 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3170 {
3171 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3172 }
3173
3174 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
3175 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3176 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3177 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3178 {
3179 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3180 }
3181 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3182
3183 #define REG_A6XX_RB_UNKNOWN_8804 0x00008804
3184
3185 #define REG_A6XX_RB_UNKNOWN_8805 0x00008805
3186
3187 #define REG_A6XX_RB_UNKNOWN_8806 0x00008806
3188
3189 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
3190 #define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
3191 #define A6XX_RB_RENDER_CONTROL0_CENTROID 0x00000002
3192 #define A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING 0x00000004
3193 #define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
3194 #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
3195 #define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
3196 #define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
3197 #define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
3198 #define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
3199 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
3200
3201 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
3202 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3203 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
3204 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
3205 #define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
3206 #define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
3207 #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
3208
3209 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
3210 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
3211 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
3212
3213 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
3214 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
3215 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
3216 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3217 {
3218 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3219 }
3220
3221 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
3222 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3223 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
3224 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3225 {
3226 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3227 }
3228 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3229 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
3230 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3231 {
3232 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3233 }
3234 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3235 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
3236 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3237 {
3238 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3239 }
3240 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3241 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3242 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3243 {
3244 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3245 }
3246 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3247 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3248 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3249 {
3250 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3251 }
3252 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3253 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3254 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3255 {
3256 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3257 }
3258 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3259 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3260 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3261 {
3262 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3263 }
3264 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3265 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3266 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3267 {
3268 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3269 }
3270
3271 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e
3272 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
3273 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
3274 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3275 {
3276 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3277 }
3278 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
3279 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
3280 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3281 {
3282 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3283 }
3284 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
3285 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
3286 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3287 {
3288 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3289 }
3290 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
3291 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
3292 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3293 {
3294 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3295 }
3296 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
3297 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
3298 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3299 {
3300 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3301 }
3302 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
3303 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
3304 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3305 {
3306 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3307 }
3308 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
3309 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
3310 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3311 {
3312 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3313 }
3314 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
3315 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
3316 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3317 {
3318 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3319 }
3320
3321 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f
3322 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
3323 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
3324 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
3325 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
3326 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
3327 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
3328 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
3329 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
3330
3331 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
3332 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3333
3334 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811
3335
3336 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818
3337
3338 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819
3339
3340 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
3341
3342 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
3343
3344 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
3345
3346 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
3347
3348 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
3349
3350 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3351
3352 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3353 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
3354 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
3355 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3356 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3357 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
3358 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3359 {
3360 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3361 }
3362 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3363 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3364 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3365 {
3366 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3367 }
3368
3369 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3370 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3371 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3372 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3373 {
3374 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3375 }
3376 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3377 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3378 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3379 {
3380 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3381 }
3382 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3383 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3384 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3385 {
3386 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3387 }
3388 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3389 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3390 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3391 {
3392 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3393 }
3394 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3395 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3396 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3397 {
3398 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3399 }
3400 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3401 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3402 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3403 {
3404 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3405 }
3406
3407 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3408 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3409 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3410 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3411 {
3412 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3413 }
3414 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3415 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3416 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3417 {
3418 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3419 }
3420 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3421 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3422 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3423 {
3424 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3425 }
3426
3427 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3428 #define A6XX_RB_MRT_PITCH__MASK 0xffffffff
3429 #define A6XX_RB_MRT_PITCH__SHIFT 0
3430 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3431 {
3432 assert(!(val & 0x3f));
3433 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3434 }
3435
3436 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3437 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3438 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3439 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3440 {
3441 assert(!(val & 0x3f));
3442 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3443 }
3444
3445 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3446
3447 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3448
3449 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3450
3451 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
3452 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
3453 #define A6XX_RB_BLEND_RED_F32__SHIFT 0
3454 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3455 {
3456 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3457 }
3458
3459 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
3460 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3461 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
3462 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3463 {
3464 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3465 }
3466
3467 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
3468 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3469 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
3470 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3471 {
3472 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3473 }
3474
3475 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
3476 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3477 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
3478 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3479 {
3480 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3481 }
3482
3483 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
3484 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3485 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3486 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3487 {
3488 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3489 }
3490 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3491 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3492 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3493 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3494 {
3495 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3496 }
3497
3498 #define REG_A6XX_RB_BLEND_CNTL 0x00008865
3499 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3500 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3501 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3502 {
3503 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3504 }
3505 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3506 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3507 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3508 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3509 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3510 {
3511 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3512 }
3513
3514 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
3515 #define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3516
3517 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
3518 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3519 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3520 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3521 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3522 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3523 {
3524 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3525 }
3526 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3527
3528 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
3529 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3530 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3531 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3532 {
3533 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3534 }
3535
3536 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
3537 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3538 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3539 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3540 {
3541 assert(!(val & 0x3f));
3542 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3543 }
3544
3545 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
3546 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3547 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3548 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3549 {
3550 assert(!(val & 0x3f));
3551 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3552 }
3553
3554 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
3555
3556 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
3557
3558 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
3559
3560 #define REG_A6XX_RB_UNKNOWN_8878 0x00008878
3561
3562 #define REG_A6XX_RB_UNKNOWN_8879 0x00008879
3563
3564 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
3565 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3566 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3567 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3568 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3569 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3570 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3571 {
3572 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3573 }
3574 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3575 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3576 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3577 {
3578 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3579 }
3580 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3581 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3582 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3583 {
3584 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3585 }
3586 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3587 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3588 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3589 {
3590 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3591 }
3592 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3593 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3594 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3595 {
3596 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3597 }
3598 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3599 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3600 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3601 {
3602 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3603 }
3604 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3605 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3606 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3607 {
3608 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3609 }
3610 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3611 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3612 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3613 {
3614 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3615 }
3616
3617 #define REG_A6XX_RB_STENCIL_INFO 0x00008881
3618 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3619
3620 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
3621 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff
3622 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
3623 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3624 {
3625 assert(!(val & 0x3f));
3626 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3627 }
3628
3629 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3630 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3631 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
3632 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3633 {
3634 assert(!(val & 0x3f));
3635 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3636 }
3637
3638 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
3639
3640 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
3641
3642 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
3643
3644 #define REG_A6XX_RB_STENCILREF 0x00008887
3645 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
3646 #define A6XX_RB_STENCILREF_REF__SHIFT 0
3647 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3648 {
3649 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3650 }
3651 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
3652 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8
3653 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3654 {
3655 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3656 }
3657
3658 #define REG_A6XX_RB_STENCILMASK 0x00008888
3659 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
3660 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0
3661 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3662 {
3663 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3664 }
3665 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
3666 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
3667 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3668 {
3669 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3670 }
3671
3672 #define REG_A6XX_RB_STENCILWRMASK 0x00008889
3673 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
3674 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
3675 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3676 {
3677 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3678 }
3679 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
3680 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
3681 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3682 {
3683 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3684 }
3685
3686 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
3687 #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3688 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3689 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
3690 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3691 {
3692 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3693 }
3694 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3695 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3696 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3697 {
3698 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3699 }
3700
3701 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3702 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3703
3704 #define REG_A6XX_RB_LRZ_CNTL 0x00008898
3705 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
3706
3707 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3708
3709 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
3710 #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3711 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff
3712 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
3713 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3714 {
3715 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3716 }
3717 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000
3718 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
3719 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3720 {
3721 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3722 }
3723
3724 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
3725 #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3726 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff
3727 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
3728 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3729 {
3730 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3731 }
3732 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000
3733 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
3734 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3735 {
3736 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3737 }
3738
3739 #define REG_A6XX_RB_MSAA_CNTL 0x000088d5
3740 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
3741 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
3742 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3743 {
3744 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3745 }
3746
3747 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
3748
3749 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
3750 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
3751 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
3752 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3753 {
3754 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3755 }
3756 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
3757 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
3758 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
3759 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3760 {
3761 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3762 }
3763 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
3764 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
3765 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3766 {
3767 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3768 }
3769 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
3770 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
3771 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3772 {
3773 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3774 }
3775
3776 #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
3777
3778 #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
3779
3780 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3781 #define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3782 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
3783 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3784 {
3785 assert(!(val & 0x3f));
3786 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3787 }
3788
3789 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
3790 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3791 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3792 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3793 {
3794 assert(!(val & 0x3f));
3795 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3796 }
3797
3798 #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
3799
3800 #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
3801
3802 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
3803 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
3804 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
3805 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
3806 {
3807 assert(!(val & 0x3f));
3808 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
3809 }
3810 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x003ff800
3811 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
3812 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
3813 {
3814 assert(!(val & 0x7f));
3815 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
3816 }
3817
3818 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
3819
3820 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
3821
3822 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
3823
3824 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
3825
3826 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
3827 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3828 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002
3829 #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
3830 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
3831 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
3832 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
3833 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3834 {
3835 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3836 }
3837
3838 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
3839
3840 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
3841
3842 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
3843
3844 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
3845 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3846 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3847 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3848 {
3849 assert(!(val & 0x3f));
3850 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
3851 }
3852 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
3853 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3854 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3855 {
3856 assert(!(val & 0x7f));
3857 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3858 }
3859
3860 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3861
3862 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3863
3864 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
3865
3866 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3867 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3868 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3869 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3870 {
3871 assert(!(val & 0x3f));
3872 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3873 }
3874 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
3875 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3876 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3877 {
3878 assert(!(val & 0x7f));
3879 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3880 }
3881
3882 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
3883
3884 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
3885
3886 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
3887 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000003
3888 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
3889 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(uint32_t val)
3890 {
3891 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
3892 }
3893 #define A6XX_RB_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004
3894 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000010
3895 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3896 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
3897 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3898 {
3899 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3900 }
3901 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
3902 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
3903 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
3904 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3905 {
3906 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
3907 }
3908
3909 #define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01
3910
3911 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
3912 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3913 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3914 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3915 {
3916 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3917 }
3918 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
3919 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
3920 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3921 {
3922 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
3923 }
3924 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3925 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3926 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3927 {
3928 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3929 }
3930 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
3931
3932 #define REG_A6XX_RB_2D_DST_LO 0x00008c18
3933
3934 #define REG_A6XX_RB_2D_DST_HI 0x00008c19
3935
3936 #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a
3937 #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
3938 #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
3939 static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
3940 {
3941 assert(!(val & 0x3f));
3942 return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
3943 }
3944
3945 #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
3946
3947 #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
3948
3949 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
3950 #define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK 0x000007ff
3951 #define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT 0
3952 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(uint32_t val)
3953 {
3954 assert(!(val & 0x3f));
3955 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK;
3956 }
3957 #define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
3958 #define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
3959 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
3960 {
3961 assert(!(val & 0x7f));
3962 return ((val >> 7) << A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK;
3963 }
3964
3965 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
3966
3967 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
3968
3969 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
3970
3971 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
3972
3973 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
3974
3975 #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
3976
3977 #define REG_A6XX_RB_CCU_CNTL 0x00008e07
3978
3979 #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101
3980
3981 #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104
3982
3983 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
3984
3985 #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108
3986
3987 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3988
3989 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3990
3991 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3992
3993 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3994
3995 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
3996
3997 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
3998
3999 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4000
4001 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4002
4003 #define REG_A6XX_VPC_SO_CNTL 0x00009216
4004 #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
4005
4006 #define REG_A6XX_VPC_SO_PROG 0x00009217
4007 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4008 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
4009 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4010 {
4011 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4012 }
4013 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
4014 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
4015 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4016 {
4017 assert(!(val & 0x3));
4018 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4019 }
4020 #define A6XX_VPC_SO_PROG_A_EN 0x00000800
4021 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
4022 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
4023 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4024 {
4025 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4026 }
4027 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4028 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
4029 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4030 {
4031 assert(!(val & 0x3));
4032 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4033 }
4034 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
4035
4036 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4037
4038 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4039
4040 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4041
4042 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4043
4044 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4045
4046 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4047
4048 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4049
4050 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
4051
4052 #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236
4053 #define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK 0x00000001
4054 #define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT 0
4055 static inline uint32_t A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(uint32_t val)
4056 {
4057 return ((val) << A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT) & A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK;
4058 }
4059
4060 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
4061
4062 #define REG_A6XX_VPC_PACK 0x00009301
4063 #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4064 #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0
4065 static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
4066 {
4067 return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
4068 }
4069 #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00
4070 #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8
4071 static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
4072 {
4073 return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
4074 }
4075 #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000
4076 #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16
4077 static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
4078 {
4079 return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
4080 }
4081
4082 #define REG_A6XX_VPC_PACK_3 0x00009303
4083 #define A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK 0x000000ff
4084 #define A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT 0
4085 static inline uint32_t A6XX_VPC_PACK_3_STRIDE_IN_VPC(uint32_t val)
4086 {
4087 return ((val) << A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK;
4088 }
4089 #define A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK 0x0000ff00
4090 #define A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT 8
4091 static inline uint32_t A6XX_VPC_PACK_3_NUMNONPOSVAR(uint32_t val)
4092 {
4093 return ((val) << A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK;
4094 }
4095 #define A6XX_VPC_PACK_3_PSIZELOC__MASK 0x00ff0000
4096 #define A6XX_VPC_PACK_3_PSIZELOC__SHIFT 16
4097 static inline uint32_t A6XX_VPC_PACK_3_PSIZELOC(uint32_t val)
4098 {
4099 return ((val) << A6XX_VPC_PACK_3_PSIZELOC__SHIFT) & A6XX_VPC_PACK_3_PSIZELOC__MASK;
4100 }
4101
4102 #define REG_A6XX_VPC_CNTL_0 0x00009304
4103 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
4104 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
4105 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4106 {
4107 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4108 }
4109 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
4110
4111 #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
4112 #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
4113 #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
4114 #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
4115 #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
4116 #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
4117
4118 #define REG_A6XX_VPC_SO_OVERRIDE 0x00009306
4119 #define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
4120
4121 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
4122
4123 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
4124
4125 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4126
4127 #define REG_A6XX_PC_UNKNOWN_9801 0x00009801
4128
4129 #define REG_A6XX_PC_TESS_CNTL 0x00009802
4130 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
4131 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
4132 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4133 {
4134 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
4135 }
4136 #define A6XX_PC_TESS_CNTL_CCW 0x00000004
4137 #define A6XX_PC_TESS_CNTL_PRIMITIVES 0x00000008
4138
4139 #define REG_A6XX_PC_RESTART_INDEX 0x00009803
4140
4141 #define REG_A6XX_PC_MODE_CNTL 0x00009804
4142
4143 #define REG_A6XX_PC_UNKNOWN_9805 0x00009805
4144
4145 #define REG_A6XX_PC_UNKNOWN_9806 0x00009806
4146
4147 #define REG_A6XX_PC_UNKNOWN_9980 0x00009980
4148
4149 #define REG_A6XX_PC_UNKNOWN_9981 0x00009981
4150
4151 #define REG_A6XX_PC_UNKNOWN_9990 0x00009990
4152
4153 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4154 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
4155 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
4156
4157 #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01
4158 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f
4159 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0
4160 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
4161 {
4162 return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
4163 }
4164 #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100
4165
4166 #define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
4167 #define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK 0x0000007f
4168 #define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT 0
4169 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC(uint32_t val)
4170 {
4171 return ((val) << A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK;
4172 }
4173 #define A6XX_PC_PRIMITIVE_CNTL_3_PSIZE 0x00000100
4174
4175 #define REG_A6XX_PC_PRIMITIVE_CNTL_4 0x00009b04
4176 #define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK 0x0000007f
4177 #define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT 0
4178 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(uint32_t val)
4179 {
4180 return ((val) << A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK;
4181 }
4182 #define A6XX_PC_PRIMITIVE_CNTL_4_PSIZE 0x00000100
4183
4184 #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
4185
4186 #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
4187
4188 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
4189
4190 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
4191
4192 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
4193
4194 #define REG_A6XX_VFD_CONTROL_0 0x0000a000
4195 #define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
4196 #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
4197 static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
4198 {
4199 return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
4200 }
4201
4202 #define REG_A6XX_VFD_CONTROL_1 0x0000a001
4203 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
4204 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
4205 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4206 {
4207 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4208 }
4209 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
4210 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
4211 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4212 {
4213 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4214 }
4215 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
4216 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
4217 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4218 {
4219 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4220 }
4221
4222 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
4223 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
4224 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
4225 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
4226 {
4227 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
4228 }
4229 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
4230 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
4231 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
4232 {
4233 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
4234 }
4235
4236 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
4237 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
4238 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
4239 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
4240 {
4241 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
4242 }
4243 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
4244 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
4245 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4246 {
4247 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4248 }
4249 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4250 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
4251 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4252 {
4253 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4254 }
4255
4256 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
4257
4258 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
4259
4260 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
4261
4262 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
4263 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
4264
4265 #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
4266
4267 #define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009
4268
4269 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
4270
4271 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
4272
4273 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4274
4275 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4276
4277 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
4278
4279 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4280
4281 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
4282
4283 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4284
4285 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4286 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
4287 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
4288 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4289 {
4290 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
4291 }
4292 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
4293 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
4294 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
4295 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
4296 {
4297 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
4298 }
4299 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
4300 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
4301 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4302 {
4303 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
4304 }
4305 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
4306 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
4307
4308 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
4309
4310 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4311
4312 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4313 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
4314 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
4315 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4316 {
4317 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4318 }
4319 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
4320 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
4321 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4322 {
4323 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4324 }
4325
4326 #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
4327
4328 #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802
4329 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
4330 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
4331 static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4332 {
4333 return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4334 }
4335
4336 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4337
4338 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4339 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4340 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
4341 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4342 {
4343 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
4344 }
4345 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4346 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
4347 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4348 {
4349 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4350 }
4351 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
4352 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
4353 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4354 {
4355 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
4356 }
4357 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4358 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
4359 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4360 {
4361 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4362 }
4363
4364 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4365
4366 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4367 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4368 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
4369 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4370 {
4371 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4372 }
4373 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4374 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
4375 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4376 {
4377 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4378 }
4379 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4380 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
4381 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4382 {
4383 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4384 }
4385 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4386 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
4387 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4388 {
4389 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4390 }
4391
4392 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
4393 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4394 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4395 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4396 {
4397 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4398 }
4399 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4400 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4401 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4402 {
4403 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4404 }
4405 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4406 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4407 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4408 {
4409 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4410 }
4411 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4412 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
4413 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4414 {
4415 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4416 }
4417 #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
4418 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
4419 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
4420
4421 #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
4422
4423 #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
4424
4425 #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
4426
4427 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
4428
4429 #define REG_A6XX_SP_VS_CONFIG 0x0000a823
4430 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
4431 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
4432 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
4433 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
4434 {
4435 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
4436 }
4437 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
4438 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
4439 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
4440 {
4441 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
4442 }
4443 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
4444 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
4445 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
4446 {
4447 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
4448 }
4449
4450 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
4451
4452 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
4453 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4454 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4455 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4456 {
4457 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4458 }
4459 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4460 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4461 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4462 {
4463 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4464 }
4465 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4466 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4467 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4468 {
4469 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4470 }
4471 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4472 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
4473 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4474 {
4475 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4476 }
4477 #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
4478 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
4479 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
4480
4481 #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
4482
4483 #define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
4484
4485 #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
4486
4487 #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
4488
4489 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
4490
4491 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
4492 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
4493 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
4494 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
4495 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
4496 {
4497 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
4498 }
4499 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
4500 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
4501 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
4502 {
4503 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
4504 }
4505 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
4506 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
4507 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
4508 {
4509 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
4510 }
4511
4512 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
4513
4514 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
4515 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4516 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4517 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4518 {
4519 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4520 }
4521 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4522 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4523 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4524 {
4525 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4526 }
4527 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4528 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4529 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4530 {
4531 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4532 }
4533 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4534 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
4535 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4536 {
4537 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4538 }
4539 #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
4540 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
4541 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
4542
4543 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
4544 #define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK 0x0000001f
4545 #define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT 0
4546 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(uint32_t val)
4547 {
4548 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK;
4549 }
4550
4551 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
4552
4553 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
4554 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
4555 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
4556 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
4557 {
4558 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
4559 }
4560 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4561 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
4562 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
4563 {
4564 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
4565 }
4566 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
4567 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
4568 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
4569 {
4570 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
4571 }
4572 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4573 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
4574 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
4575 {
4576 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
4577 }
4578
4579 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
4580
4581 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
4582 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4583 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
4584 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
4585 {
4586 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
4587 }
4588 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4589 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
4590 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
4591 {
4592 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
4593 }
4594 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4595 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
4596 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
4597 {
4598 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
4599 }
4600 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4601 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
4602 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
4603 {
4604 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
4605 }
4606
4607 #define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
4608
4609 #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
4610
4611 #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
4612
4613 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
4614
4615 #define REG_A6XX_SP_DS_CONFIG 0x0000a863
4616 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
4617 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
4618 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
4619 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
4620 {
4621 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
4622 }
4623 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
4624 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
4625 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
4626 {
4627 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
4628 }
4629 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
4630 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
4631 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
4632 {
4633 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
4634 }
4635
4636 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
4637
4638 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
4639 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4640 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4641 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4642 {
4643 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4644 }
4645 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4646 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4647 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4648 {
4649 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4650 }
4651 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4652 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4653 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4654 {
4655 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4656 }
4657 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4658 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
4659 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4660 {
4661 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4662 }
4663 #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
4664 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
4665 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
4666
4667 #define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871
4668
4669 #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
4670
4671 #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
4672
4673 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
4674
4675 #define REG_A6XX_SP_GS_CONFIG 0x0000a894
4676 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
4677 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
4678 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
4679 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
4680 {
4681 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
4682 }
4683 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
4684 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
4685 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
4686 {
4687 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
4688 }
4689 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
4690 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
4691 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
4692 {
4693 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
4694 }
4695
4696 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
4697
4698 #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
4699
4700 #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
4701
4702 #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
4703
4704 #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
4705
4706 #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
4707
4708 #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
4709
4710 #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
4711
4712 #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
4713
4714 #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
4715
4716 #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
4717
4718 #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
4719
4720 #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
4721
4722 #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
4723
4724 #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
4725
4726 #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
4727
4728 #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
4729
4730 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
4731 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4732 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4733 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4734 {
4735 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4736 }
4737 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4738 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4739 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4740 {
4741 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4742 }
4743 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4744 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4745 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4746 {
4747 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4748 }
4749 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4750 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
4751 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4752 {
4753 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4754 }
4755 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
4756 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
4757 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
4758
4759 #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
4760
4761 #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
4762
4763 #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
4764
4765 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
4766 #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
4767 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
4768 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4769
4770 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
4771 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
4772 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
4773 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
4774 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
4775 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
4776 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
4777 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
4778 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
4779
4780 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
4781 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
4782 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
4783 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
4784 {
4785 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
4786 }
4787 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
4788 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
4789 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
4790 {
4791 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
4792 }
4793 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
4794 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
4795 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
4796 {
4797 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
4798 }
4799 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
4800 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
4801 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
4802 {
4803 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
4804 }
4805 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
4806 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
4807 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
4808 {
4809 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
4810 }
4811 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
4812 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
4813 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
4814 {
4815 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
4816 }
4817 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
4818 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
4819 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
4820 {
4821 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
4822 }
4823 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
4824 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
4825 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
4826 {
4827 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
4828 }
4829
4830 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
4831 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
4832 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
4833 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
4834 {
4835 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
4836 }
4837 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
4838 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
4839 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
4840 {
4841 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
4842 }
4843
4844 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
4845 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
4846 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
4847 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
4848 {
4849 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
4850 }
4851
4852 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4853
4854 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4855 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4856 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
4857 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
4858 {
4859 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4860 }
4861 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
4862 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
4863
4864 #define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e
4865
4866 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
4867
4868 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
4869
4870 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
4871
4872 #define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
4873
4874 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
4875
4876 #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
4877
4878 #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
4879
4880 #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
4881
4882 #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
4883
4884 #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
4885
4886 #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
4887
4888 #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
4889
4890 #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
4891
4892 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4893
4894 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4895 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4896 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4897 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4898 {
4899 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
4900 }
4901 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4902
4903 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
4904 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4905 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4906 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4907 {
4908 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4909 }
4910 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4911 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4912 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4913 {
4914 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4915 }
4916 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4917 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4918 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4919 {
4920 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4921 }
4922 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4923 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
4924 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4925 {
4926 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4927 }
4928 #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
4929 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
4930 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
4931
4932 #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
4933
4934 #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
4935
4936 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
4937 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
4938 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
4939 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
4940 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
4941 {
4942 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
4943 }
4944 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
4945 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
4946 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
4947 {
4948 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
4949 }
4950 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
4951 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
4952 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
4953 {
4954 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
4955 }
4956
4957 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
4958
4959 #define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
4960
4961 #define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
4962
4963 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
4964
4965 #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
4966
4967 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
4968 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
4969 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
4970 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
4971 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
4972 {
4973 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
4974 }
4975 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
4976 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
4977 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
4978 {
4979 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
4980 }
4981 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
4982 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
4983 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
4984 {
4985 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
4986 }
4987
4988 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
4989
4990 #define REG_A6XX_SP_IBO_LO 0x0000ab1a
4991
4992 #define REG_A6XX_SP_IBO_HI 0x0000ab1b
4993
4994 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20
4995
4996 #define REG_A6XX_SP_2D_SRC_FORMAT 0x0000acc0
4997 #define A6XX_SP_2D_SRC_FORMAT_NORM 0x00000001
4998 #define A6XX_SP_2D_SRC_FORMAT_SINT 0x00000002
4999 #define A6XX_SP_2D_SRC_FORMAT_UINT 0x00000004
5000 #define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK 0x000007f8
5001 #define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT 3
5002 static inline uint32_t A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(enum a6xx_color_fmt val)
5003 {
5004 return ((val) << A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK;
5005 }
5006
5007 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
5008
5009 #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
5010
5011 #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
5012
5013 #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
5014
5015 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
5016
5017 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
5018
5019 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
5020 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
5021 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
5022 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
5023 {
5024 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
5025 }
5026
5027 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
5028 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
5029 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
5030 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
5031 {
5032 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
5033 }
5034 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
5035
5036 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
5037
5038 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
5039
5040 #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304
5041
5042 #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
5043
5044 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
5045 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5046 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
5047 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
5048 {
5049 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
5050 }
5051 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5052 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
5053 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
5054 {
5055 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
5056 }
5057 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5058 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
5059 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5060 {
5061 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
5062 }
5063 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
5064 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
5065 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
5066 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
5067 {
5068 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
5069 }
5070 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
5071
5072 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
5073 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
5074 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
5075 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
5076 {
5077 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
5078 }
5079 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
5080 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
5081 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
5082 {
5083 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
5084 }
5085
5086 #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
5087
5088 #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
5089
5090 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
5091 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
5092 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
5093 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
5094 {
5095 assert(!(val & 0x3f));
5096 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
5097 }
5098
5099 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
5100
5101 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
5102
5103 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
5104 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
5105 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
5106 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
5107 {
5108 assert(!(val & 0x3f));
5109 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
5110 }
5111 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
5112 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
5113 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
5114 {
5115 assert(!(val & 0x7f));
5116 return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
5117 }
5118
5119 #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
5120
5121 #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
5122
5123 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
5124 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
5125 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
5126 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
5127 {
5128 assert(!(val & 0x3));
5129 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
5130 }
5131 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
5132
5133 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
5134 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
5135 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
5136 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
5137 {
5138 assert(!(val & 0x3));
5139 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
5140 }
5141 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
5142
5143 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
5144 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
5145 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
5146 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
5147 {
5148 assert(!(val & 0x3));
5149 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
5150 }
5151 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
5152
5153 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
5154 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
5155 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
5156 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
5157 {
5158 assert(!(val & 0x3));
5159 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
5160 }
5161 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
5162
5163 #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
5164
5165 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
5166
5167 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
5168 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
5169 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
5170 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
5171 {
5172 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
5173 }
5174 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
5175 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
5176 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
5177 {
5178 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
5179 }
5180 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
5181 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
5182 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
5183 {
5184 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
5185 }
5186 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
5187 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
5188 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
5189 {
5190 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
5191 }
5192
5193 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
5194 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK 0x000000ff
5195 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT 0
5196 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(uint32_t val)
5197 {
5198 return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK;
5199 }
5200 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK 0x00ff0000
5201 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT 16
5202 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(uint32_t val)
5203 {
5204 return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK;
5205 }
5206
5207 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
5208 #define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK 0x000000ff
5209 #define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT 0
5210 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(uint32_t val)
5211 {
5212 return ((val) << A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK;
5213 }
5214 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
5215 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
5216 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
5217 {
5218 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
5219 }
5220 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
5221 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
5222 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
5223 {
5224 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
5225 }
5226
5227 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
5228
5229 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
5230 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
5231 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
5232 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
5233 {
5234 assert(!(val & 0x3));
5235 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
5236 }
5237 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
5238
5239 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
5240 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
5241 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
5242 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
5243 {
5244 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
5245 }
5246 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
5247 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
5248 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
5249 {
5250 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
5251 }
5252 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
5253 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
5254 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
5255 {
5256 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
5257 }
5258 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
5259 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
5260 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
5261 {
5262 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
5263 }
5264
5265 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
5266 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
5267 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
5268 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
5269 {
5270 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
5271 }
5272
5273 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
5274 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
5275 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
5276 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
5277 {
5278 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
5279 }
5280
5281 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
5282 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
5283 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
5284 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
5285 {
5286 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
5287 }
5288
5289 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
5290 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
5291 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
5292 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
5293 {
5294 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
5295 }
5296
5297 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
5298 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
5299 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
5300 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
5301 {
5302 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
5303 }
5304
5305 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
5306 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
5307 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
5308 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
5309 {
5310 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
5311 }
5312
5313 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
5314 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
5315 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
5316 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
5317 {
5318 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
5319 }
5320 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
5321 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
5322 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
5323 {
5324 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
5325 }
5326 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
5327 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
5328 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
5329 {
5330 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
5331 }
5332 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
5333 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
5334 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
5335 {
5336 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
5337 }
5338
5339 #define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
5340
5341 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
5342
5343 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
5344
5345 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
5346
5347 #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08
5348
5349 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
5350 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
5351 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
5352 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
5353 {
5354 assert(!(val & 0x3));
5355 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
5356 }
5357 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
5358
5359 #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11
5360
5361 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
5362
5363 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
5364
5365 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
5366
5367 #define REG_A6XX_TEX_SAMP_0 0x00000000
5368 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
5369 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
5370 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
5371 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
5372 {
5373 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
5374 }
5375 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
5376 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
5377 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
5378 {
5379 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
5380 }
5381 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
5382 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
5383 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
5384 {
5385 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
5386 }
5387 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
5388 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
5389 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
5390 {
5391 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
5392 }
5393 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
5394 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
5395 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
5396 {
5397 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
5398 }
5399 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
5400 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
5401 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
5402 {
5403 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
5404 }
5405 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
5406 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
5407 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
5408 {
5409 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
5410 }
5411
5412 #define REG_A6XX_TEX_SAMP_1 0x00000001
5413 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
5414 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
5415 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5416 {
5417 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5418 }
5419 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
5420 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
5421 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
5422 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
5423 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
5424 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
5425 {
5426 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
5427 }
5428 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5429 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
5430 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
5431 {
5432 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
5433 }
5434
5435 #define REG_A6XX_TEX_SAMP_2 0x00000002
5436 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffffff
5437 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 0
5438 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5439 {
5440 return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5441 }
5442
5443 #define REG_A6XX_TEX_SAMP_3 0x00000003
5444
5445 #define REG_A6XX_TEX_CONST_0 0x00000000
5446 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
5447 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
5448 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
5449 {
5450 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
5451 }
5452 #define A6XX_TEX_CONST_0_SRGB 0x00000004
5453 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
5454 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
5455 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
5456 {
5457 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
5458 }
5459 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
5460 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
5461 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
5462 {
5463 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
5464 }
5465 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
5466 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
5467 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
5468 {
5469 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
5470 }
5471 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
5472 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
5473 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
5474 {
5475 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
5476 }
5477 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
5478 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
5479 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5480 {
5481 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
5482 }
5483 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
5484 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
5485 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5486 {
5487 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
5488 }
5489 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
5490 #define A6XX_TEX_CONST_0_FMT__SHIFT 22
5491 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
5492 {
5493 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
5494 }
5495 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
5496 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30
5497 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5498 {
5499 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
5500 }
5501
5502 #define REG_A6XX_TEX_CONST_1 0x00000001
5503 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
5504 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
5505 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
5506 {
5507 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
5508 }
5509 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5510 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
5511 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
5512 {
5513 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
5514 }
5515
5516 #define REG_A6XX_TEX_CONST_2 0x00000002
5517 #define A6XX_TEX_CONST_2_UNK4 0x00000010
5518 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
5519 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
5520 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
5521 {
5522 return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
5523 }
5524 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5525 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
5526 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
5527 {
5528 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
5529 }
5530 #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
5531 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29
5532 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
5533 {
5534 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
5535 }
5536 #define A6XX_TEX_CONST_2_UNK31 0x80000000
5537
5538 #define REG_A6XX_TEX_CONST_3 0x00000003
5539 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5540 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
5541 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5542 {
5543 assert(!(val & 0xfff));
5544 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5545 }
5546 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
5547 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
5548 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5549 {
5550 assert(!(val & 0xfff));
5551 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5552 }
5553 #define A6XX_TEX_CONST_3_UNK27 0x08000000
5554 #define A6XX_TEX_CONST_3_FLAG 0x10000000
5555
5556 #define REG_A6XX_TEX_CONST_4 0x00000004
5557 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
5558 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
5559 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
5560 {
5561 assert(!(val & 0x1f));
5562 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
5563 }
5564
5565 #define REG_A6XX_TEX_CONST_5 0x00000005
5566 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
5567 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
5568 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
5569 {
5570 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
5571 }
5572 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
5573 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
5574 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
5575 {
5576 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
5577 }
5578
5579 #define REG_A6XX_TEX_CONST_6 0x00000006
5580
5581 #define REG_A6XX_TEX_CONST_7 0x00000007
5582 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
5583 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
5584 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
5585 {
5586 assert(!(val & 0x1f));
5587 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
5588 }
5589
5590 #define REG_A6XX_TEX_CONST_8 0x00000008
5591 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
5592 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
5593 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
5594 {
5595 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
5596 }
5597
5598 #define REG_A6XX_TEX_CONST_9 0x00000009
5599 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
5600 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
5601 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
5602 {
5603 assert(!(val & 0xf));
5604 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
5605 }
5606
5607 #define REG_A6XX_TEX_CONST_10 0x0000000a
5608 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
5609 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
5610 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
5611 {
5612 assert(!(val & 0x3f));
5613 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
5614 }
5615
5616 #define REG_A6XX_TEX_CONST_11 0x0000000b
5617
5618 #define REG_A6XX_TEX_CONST_12 0x0000000c
5619
5620 #define REG_A6XX_TEX_CONST_13 0x0000000d
5621
5622 #define REG_A6XX_TEX_CONST_14 0x0000000e
5623
5624 #define REG_A6XX_TEX_CONST_15 0x0000000f
5625
5626 #define REG_A6XX_IBO_0 0x00000000
5627 #define A6XX_IBO_0_TILE_MODE__MASK 0x00000003
5628 #define A6XX_IBO_0_TILE_MODE__SHIFT 0
5629 static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
5630 {
5631 return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
5632 }
5633 #define A6XX_IBO_0_FMT__MASK 0x3fc00000
5634 #define A6XX_IBO_0_FMT__SHIFT 22
5635 static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_tex_fmt val)
5636 {
5637 return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
5638 }
5639
5640 #define REG_A6XX_IBO_1 0x00000001
5641 #define A6XX_IBO_1_WIDTH__MASK 0x00007fff
5642 #define A6XX_IBO_1_WIDTH__SHIFT 0
5643 static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
5644 {
5645 return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
5646 }
5647 #define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000
5648 #define A6XX_IBO_1_HEIGHT__SHIFT 15
5649 static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
5650 {
5651 return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
5652 }
5653
5654 #define REG_A6XX_IBO_2 0x00000002
5655 #define A6XX_IBO_2_UNK4 0x00000010
5656 #define A6XX_IBO_2_PITCH__MASK 0x1fffff80
5657 #define A6XX_IBO_2_PITCH__SHIFT 7
5658 static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
5659 {
5660 return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
5661 }
5662 #define A6XX_IBO_2_TYPE__MASK 0x60000000
5663 #define A6XX_IBO_2_TYPE__SHIFT 29
5664 static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
5665 {
5666 return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
5667 }
5668 #define A6XX_IBO_2_UNK31 0x80000000
5669
5670 #define REG_A6XX_IBO_3 0x00000003
5671 #define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff
5672 #define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0
5673 static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
5674 {
5675 assert(!(val & 0xfff));
5676 return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
5677 }
5678 #define A6XX_IBO_3_UNK27 0x08000000
5679 #define A6XX_IBO_3_FLAG 0x10000000
5680
5681 #define REG_A6XX_IBO_4 0x00000004
5682 #define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
5683 #define A6XX_IBO_4_BASE_LO__SHIFT 0
5684 static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
5685 {
5686 return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
5687 }
5688
5689 #define REG_A6XX_IBO_5 0x00000005
5690 #define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff
5691 #define A6XX_IBO_5_BASE_HI__SHIFT 0
5692 static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
5693 {
5694 return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
5695 }
5696 #define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000
5697 #define A6XX_IBO_5_DEPTH__SHIFT 17
5698 static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
5699 {
5700 return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
5701 }
5702
5703 #define REG_A6XX_IBO_6 0x00000006
5704
5705 #define REG_A6XX_IBO_7 0x00000007
5706
5707 #define REG_A6XX_IBO_8 0x00000008
5708
5709 #define REG_A6XX_IBO_9 0x00000009
5710 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
5711 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
5712 static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
5713 {
5714 assert(!(val & 0xf));
5715 return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
5716 }
5717
5718 #define REG_A6XX_IBO_10 0x0000000a
5719 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
5720 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
5721 static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
5722 {
5723 assert(!(val & 0x3f));
5724 return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
5725 }
5726
5727 #define REG_A6XX_UBO_0 0x00000000
5728 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
5729 #define A6XX_UBO_0_BASE_LO__SHIFT 0
5730 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
5731 {
5732 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
5733 }
5734
5735 #define REG_A6XX_UBO_1 0x00000001
5736 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
5737 #define A6XX_UBO_1_BASE_HI__SHIFT 0
5738 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
5739 {
5740 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
5741 }
5742
5743 #define REG_CP_UNK_A6XX_55_0 0x00000000
5744 #define CP_UNK_A6XX_55_0_BASE_LO__MASK 0xffffffff
5745 #define CP_UNK_A6XX_55_0_BASE_LO__SHIFT 0
5746 static inline uint32_t CP_UNK_A6XX_55_0_BASE_LO(uint32_t val)
5747 {
5748 return ((val) << CP_UNK_A6XX_55_0_BASE_LO__SHIFT) & CP_UNK_A6XX_55_0_BASE_LO__MASK;
5749 }
5750
5751 #define REG_CP_UNK_A6XX_55_1 0x00000001
5752 #define CP_UNK_A6XX_55_1_BASE_HI__MASK 0x0001ffff
5753 #define CP_UNK_A6XX_55_1_BASE_HI__SHIFT 0
5754 static inline uint32_t CP_UNK_A6XX_55_1_BASE_HI(uint32_t val)
5755 {
5756 return ((val) << CP_UNK_A6XX_55_1_BASE_HI__SHIFT) & CP_UNK_A6XX_55_1_BASE_HI__MASK;
5757 }
5758
5759 #define REG_CP_UNK_A6XX_55_2 0x00000002
5760 #define CP_UNK_A6XX_55_2_SIZE__MASK 0x0000ffff
5761 #define CP_UNK_A6XX_55_2_SIZE__SHIFT 0
5762 static inline uint32_t CP_UNK_A6XX_55_2_SIZE(uint32_t val)
5763 {
5764 return ((val) << CP_UNK_A6XX_55_2_SIZE__SHIFT) & CP_UNK_A6XX_55_2_SIZE__MASK;
5765 }
5766
5767 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
5768
5769 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
5770
5771 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
5772
5773 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
5774
5775 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
5776
5777 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
5778
5779 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
5780
5781 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
5782
5783 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
5784
5785 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
5786
5787 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
5788
5789 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
5790
5791 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
5792
5793 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
5794
5795 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
5796
5797 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
5798
5799 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
5800
5801 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
5802
5803 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
5804
5805 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
5806
5807 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
5808
5809 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
5810
5811 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
5812
5813 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
5814
5815 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
5816
5817 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
5818
5819 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
5820
5821 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
5822 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
5823 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
5824 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
5825 {
5826 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
5827 }
5828 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
5829 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
5830 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
5831 {
5832 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
5833 }
5834
5835 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
5836
5837 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
5838
5839 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
5840
5841 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
5842 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
5843 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
5844 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
5845 {
5846 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
5847 }
5848 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
5849 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
5850 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
5851 {
5852 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
5853 }
5854 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
5855 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
5856 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
5857 {
5858 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
5859 }
5860
5861 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
5862 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
5863 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
5864 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
5865 {
5866 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
5867 }
5868
5869 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
5870
5871 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
5872
5873 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
5874
5875 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
5876
5877 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
5878
5879 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
5880
5881 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
5882
5883 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
5884
5885 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
5886 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
5887 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
5888 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
5889 {
5890 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
5891 }
5892 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
5893 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
5894 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
5895 {
5896 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
5897 }
5898 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
5899 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
5900 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
5901 {
5902 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
5903 }
5904 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
5905 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
5906 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
5907 {
5908 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
5909 }
5910 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
5911 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
5912 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
5913 {
5914 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
5915 }
5916 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
5917 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
5918 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
5919 {
5920 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
5921 }
5922 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
5923 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
5924 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
5925 {
5926 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
5927 }
5928 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
5929 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
5930 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
5931 {
5932 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
5933 }
5934
5935 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
5936 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
5937 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
5938 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
5939 {
5940 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
5941 }
5942 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
5943 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
5944 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
5945 {
5946 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
5947 }
5948 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
5949 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
5950 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
5951 {
5952 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
5953 }
5954 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
5955 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
5956 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
5957 {
5958 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
5959 }
5960 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
5961 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
5962 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
5963 {
5964 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
5965 }
5966 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
5967 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
5968 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
5969 {
5970 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
5971 }
5972 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
5973 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
5974 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
5975 {
5976 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
5977 }
5978 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
5979 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
5980 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
5981 {
5982 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
5983 }
5984
5985 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
5986
5987 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
5988
5989 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
5990
5991 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
5992
5993
5994 #endif /* A6XX_XML */