src/freedreno/registers/adreno_pm4.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="vgt_event_type">
   7         <value name="VS_DEALLOC" value="0"/>
   8         <value name="PS_DEALLOC" value="1"/>
   9         <value name="VS_DONE_TS" value="2"/>
  10         <value name="PS_DONE_TS" value="3"/>
  11         <value name="CACHE_FLUSH_TS" value="4"/>
  12         <value name="CONTEXT_DONE" value="5"/>
  13         <value name="CACHE_FLUSH" value="6"/>
  14         <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
  15         <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
  16         <value name="VIZQUERY_END" value="8"/>
  17         <value name="SC_WAIT_WC" value="9"/>
  18         <value name="RST_PIX_CNT" value="13"/>
  19         <value name="RST_VTX_CNT" value="14"/>
  20         <value name="TILE_FLUSH" value="15"/>
  21         <value name="STAT_EVENT" value="16"/>
  22         <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
  23         <value name="ZPASS_DONE" value="21"/>
  24         <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
  25         <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
  26         <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
  27         <value name="VS_FETCH_DONE" value="27"/>
  28         <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
  29
  30         <!-- a5xx events -->
  31         <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
  32         <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
  33         <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
  34         <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
  35         <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
  36         <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
  37         <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
  38         <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
  39         <value name="BLIT" value="30" variants="A5XX,A6XX"/>
  40         <value name="UNK_25" value="37" variants="A5XX"/>
  41         <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
  42         <value name="UNK_2C" value="44" variants="A5XX"/>
  43         <value name="UNK_2D" value="45" variants="A5XX"/>
  44
  45         <!-- a6xx events -->
  46         <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
  47 </enum>
  48
  49 <enum name="pc_di_primtype">
  50         <value name="DI_PT_NONE" value="0"/>
  51         <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
  52         <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
  53         <value name="DI_PT_LINELIST" value="2"/>
  54         <value name="DI_PT_LINESTRIP" value="3"/>
  55         <value name="DI_PT_TRILIST" value="4"/>
  56         <value name="DI_PT_TRIFAN" value="5"/>
  57         <value name="DI_PT_TRISTRIP" value="6"/>
  58         <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
  59         <value name="DI_PT_RECTLIST" value="8"/>
  60         <value name="DI_PT_POINTLIST" value="9"/>
  61         <value name="DI_PT_LINE_ADJ" value="0xa"/>
  62         <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
  63         <value name="DI_PT_TRI_ADJ" value="0xc"/>
  64         <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
  65         <value name="DI_PT_PATCHES" value="0x29"/>
  66 </enum>
  67
  68 <enum name="pc_di_src_sel">
  69         <value name="DI_SRC_SEL_DMA" value="0"/>
  70         <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
  71         <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
  72         <value name="DI_SRC_SEL_RESERVED" value="3"/>
  73 </enum>
  74
  75 <enum name="pc_di_face_cull_sel">
  76         <value name="DI_FACE_CULL_NONE" value="0"/>
  77         <value name="DI_FACE_CULL_FETCH" value="1"/>
  78         <value name="DI_FACE_BACKFACE_CULL" value="2"/>
  79         <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
  80 </enum>
  81
  82 <enum name="pc_di_index_size">
  83         <value name="INDEX_SIZE_IGN" value="0"/>
  84         <value name="INDEX_SIZE_16_BIT" value="0"/>
  85         <value name="INDEX_SIZE_32_BIT" value="1"/>
  86         <value name="INDEX_SIZE_8_BIT" value="2"/>
  87         <value name="INDEX_SIZE_INVALID"/>
  88 </enum>
  89
  90 <enum name="pc_di_vis_cull_mode">
  91         <value name="IGNORE_VISIBILITY" value="0"/>
  92         <value name="USE_VISIBILITY" value="1"/>
  93 </enum>
  94
  95 <enum name="adreno_pm4_packet_type">
  96         <value name="CP_TYPE0_PKT" value="0x00000000"/>
  97         <value name="CP_TYPE1_PKT" value="0x40000000"/>
  98         <value name="CP_TYPE2_PKT" value="0x80000000"/>
  99         <value name="CP_TYPE3_PKT" value="0xc0000000"/>
 100         <value name="CP_TYPE4_PKT" value="0x40000000"/>
 101         <value name="CP_TYPE7_PKT" value="0x70000000"/>
 102 </enum>
 103
 104 <!--
 105    Note that in some cases, the same packet id is recycled on a later
 106    generation, so variants attribute is used to distinguish.   They
 107    may not be completely accurate, we would probably have to analyze
 108    the pfp and me/pm4 firmware to verify the packet is actually
 109    handled on a particular generation.  But it is at least enough to
 110    disambiguate the packet-id's that were re-used for different
 111    packets starting with a5xx.
 112  -->
 113 <enum name="adreno_pm4_type3_packets">
 114         <doc>initialize CP's micro-engine</doc>
 115         <value name="CP_ME_INIT" value="0x48"/>
 116         <doc>skip N 32-bit words to get to the next packet</doc>
 117         <value name="CP_NOP" value="0x10"/>
 118         <doc>
 119                 indirect buffer dispatch.  prefetch parser uses this packet
 120                 type to determine whether to pre-fetch the IB
 121         </doc>
 122         <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 123         <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 124         <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
 125         <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 126         <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 127         <doc>wait for the IDLE state of the engine</doc>
 128         <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
 129         <doc>wait until a register or memory location is a specific value</doc>
 130         <value name="CP_WAIT_REG_MEM" value="0x3c"/>
 131         <doc>wait until a register location is equal to a specific value</doc>
 132         <value name="CP_WAIT_REG_EQ" value="0x52"/>
 133         <doc>wait until a register location is >= a specific value</doc>
 134         <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
 135         <doc>wait until a read completes</doc>
 136         <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
 137         <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
 138         <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
 139         <doc>register read/modify/write</doc>
 140         <value name="CP_REG_RMW" value="0x21"/>
 141         <doc>Set binning configuration registers</doc>
 142         <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
 143         <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
 144         <doc>reads register in chip and writes to memory</doc>
 145         <value name="CP_REG_TO_MEM" value="0x3e"/>
 146         <doc>write N 32-bit words to memory</doc>
 147         <value name="CP_MEM_WRITE" value="0x3d"/>
 148         <doc>write CP_PROG_COUNTER value to memory</doc>
 149         <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
 150         <doc>conditional execution of a sequence of packets</doc>
 151         <value name="CP_COND_EXEC" value="0x44"/>
 152         <doc>conditional write to memory or register</doc>
 153         <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
 154         <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
 155         <doc>generate an event that creates a write to memory when completed</doc>
 156         <value name="CP_EVENT_WRITE" value="0x46"/>
 157         <doc>generate a VS|PS_done event</doc>
 158         <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
 159         <doc>generate a cache flush done event</doc>
 160         <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
 161         <doc>generate a z_pass done event</doc>
 162         <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
 163         <doc>
 164                 not sure the real name, but this seems to be what is used for
 165                 opencl, instead of CP_DRAW_INDX..
 166         </doc>
 167         <value name="CP_RUN_OPENCL" value="0x31"/>
 168         <doc>initiate fetch of index buffer and draw</doc>
 169         <value name="CP_DRAW_INDX" value="0x22"/>
 170         <doc>draw using supplied indices in packet</doc>
 171         <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
 172         <doc>initiate fetch of index buffer and binIDs and draw</doc>
 173         <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
 174         <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
 175         <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
 176         <doc>begin/end initiator for viz query extent processing</doc>
 177         <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
 178         <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
 179         <value name="CP_SET_STATE" value="0x25"/>
 180         <doc>load constant into chip and to memory</doc>
 181         <value name="CP_SET_CONSTANT" value="0x2d"/>
 182         <doc>load sequencer instruction memory (pointer-based)</doc>
 183         <value name="CP_IM_LOAD" value="0x27"/>
 184         <doc>load sequencer instruction memory (code embedded in packet)</doc>
 185         <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 186         <doc>load constants from a location in memory</doc>
 187         <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
 188         <doc>selective invalidation of state pointers</doc>
 189         <value name="CP_INVALIDATE_STATE" value="0x3b"/>
 190         <doc>dynamically changes shader instruction memory partition</doc>
 191         <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
 192         <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
 193         <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
 194         <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
 195         <value name="CP_SET_BIN_SELECT" value="0x51"/>
 196         <doc>updates the current context, if needed</doc>
 197         <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
 198         <doc>generate interrupt from the command stream</doc>
 199         <value name="CP_INTERRUPT" value="0x40"/>
 200         <doc>copy sequencer instruction memory to system memory</doc>
 201         <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
 202
 203         <!-- For a20x -->
 204 <!-- TODO handle variants..
 205         <doc>
 206                 Program an offset that will added to the BIN_BASE value of
 207                 the 3D_DRAW_INDX_BIN packet
 208         </doc>
 209         <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
 210  -->
 211
 212         <!-- for a22x -->
 213         <doc>
 214                 sets draw initiator flags register in PFP, gets bitwise-ORed into
 215                 every draw initiator
 216         </doc>
 217         <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
 218         <doc>sets the register protection mode</doc>
 219         <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
 220
 221         <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
 222
 223         <!-- for a3xx -->
 224         <doc>load high level sequencer command</doc>
 225         <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
 226         <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
 227         <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
 228         <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
 229         <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
 230         <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
 231         <doc>Load a buffer with pre-fetch enabled</doc>
 232         <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 233         <doc>Set bin (?)</doc>
 234         <value name="CP_SET_BIN" value="0x4c"/>
 235
 236         <doc>test 2 memory locations to dword values specified</doc>
 237         <value name="CP_TEST_TWO_MEMS" value="0x71"/>
 238
 239         <doc>Write register, ignoring context state for context sensitive registers</doc>
 240         <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
 241
 242         <doc>Record the real-time when this packet is processed by PFP</doc>
 243         <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
 244
 245         <!-- Used to switch GPU between secure and non-secure modes -->
 246         <value name="CP_SET_SECURE_MODE" value="0x66"/>
 247
 248         <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
 249         <value name="CP_WAIT_FOR_ME" value="0x13"/>
 250
 251         <!-- for a4xx -->
 252         <doc>
 253                 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
 254                 groups of registers.  Looks like it can be used to create state
 255                 objects in GPU memory, and on state change only emit pointer
 256                 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
 257                 overhead:
 258
 259                 (A4x) save PM4 stream pointers to execute upon a visible draw
 260         </doc>
 261         <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
 262         <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
 263         <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
 264         <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
 265         <value name="CP_DRAW_AUTO" value="0x24"/>
 266
 267         <value name="CP_UNKNOWN_19" value="0x19"/>
 268
 269         <doc>set to 1 for fastclear..:</doc>
 270         <value name="CP_UNKNOWN_1A" value="0x1a"/>
 271
 272         <value name="CP_UNKNOWN_4E" value="0x4e"/>
 273
 274         <doc>
 275                 for A4xx
 276                 Write to register with address that does not fit into type-0 pkt
 277         </doc>
 278         <value name="CP_WIDE_REG_WRITE" value="0x74"/>
 279
 280         <doc>copy from ME scratch RAM to a register</doc>
 281         <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
 282
 283         <doc>Copy from REG to ME scratch RAM</doc>
 284         <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
 285
 286         <doc>Wait for memory writes to complete</doc>
 287         <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
 288
 289         <doc>Conditional execution based on register comparison</doc>
 290         <value name="CP_COND_REG_EXEC" value="0x47"/>
 291
 292         <doc>Memory to REG copy</doc>
 293         <value name="CP_MEM_TO_REG" value="0x42"/>
 294
 295         <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
 296         <value name="CP_EXEC_CS" value="0x33"/>
 297
 298         <doc>
 299                 for a5xx
 300         </doc>
 301         <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 302         <!-- switches SMMU pagetable, used on a5xx only -->
 303         <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
 304         <!-- for a6xx -->
 305         <doc>Tells CP the current mode of GPU operation</doc>
 306         <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
 307         <doc>Instruct CP to set a few internal CP registers</doc>
 308         <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 309         <!--
 310         pairs of regid and value.. seems to be used to program some TF
 311         related regs:
 312          -->
 313         <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
 314         <!-- A5XX Enable yield in RB only -->
 315         <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
 316         <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
 317         <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
 318         <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
 319         <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
 320         <!-- Enable/Disable/Defer A5x global preemption model -->
 321         <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
 322         <!-- Enable/Disable A5x local preemption model -->
 323         <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
 324         <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
 325         <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
 326         <!-- Inform CP about current render mode (needed for a5xx preemption) -->
 327         <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
 328         <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
 329         <!-- check if this works on earlier.. -->
 330         <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
 331         <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
 332
 333         <!-- Test specified bit in specified register and set predicate -->
 334         <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
 335
 336         <!--
 337         Seems to set the mode flags which control which CP_SET_DRAW_STATE
 338         packets are executed, based on their ENABLE_MASK values
 339
 340         CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
 341         packets w/ ENABLE_MASK & 0x6 to execute immediately
 342          -->
 343         <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
 344
 345         <!--
 346         Seems like there are now separate blocks of state for VS vs FS/CS
 347         (probably these amounts to geometry vs fragments so that geometry
 348         stage of the pipeline for next draw can start while fragment stage
 349         of current draw is still running.  The format of the payload of the
 350         packets is the same, the only difference is the offsets of the regs
 351         the firmware code that handles the packet writes.
 352
 353         Note that for CL, starting with a6xx, the preferred # of local
 354         threads is no longer the same as the max, implying that the shader
 355         core can now run warps from unrelated shaders (ie.
 356         CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
 357         CL_KERNEL_WORK_GROUP_SIZE)
 358          -->
 359         <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
 360         <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
 361         <!--
 362         Note: For IBO state (Image/SSBOs) which have shared state across
 363         shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
 364         compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
 365         interchangable.
 366          -->
 367         <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
 368
 369         <!-- internal packets: -->
 370         <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
 371         <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
 372         <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
 373         <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
 374         <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
 375         <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
 376         <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
 377         <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
 378
 379         <!-- jmptable entry used to handle type4 packet on a5xx+: -->
 380         <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
 381 <!--
 382 unknown a6xx opcodes:
 383
 384 opcode: (null) (14) (5 dwords)
 385 opcode: (null) (55) (4 dwords)
 386 opcode: (null) (6d) (4 dwords)
 387  -->
 388         <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
 389         <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
 390
 391         <!--
 392         Seems to always have the payload:
 393           00000002 00008801 00004010
 394         or:
 395           00000002 00008801 00004090
 396         or:
 397           00000002 00008801 00000010
 398           00000002 00008801 00010010
 399           00000002 00008801 00d64010
 400           ...
 401         Note set for compute shaders..
 402         Is 0x8801 a register offset?
 403         This appears to be a special sort of register write packet
 404         more or less, but the firmware has some special handling..
 405         Seems like it intercepts/modifies certain register offsets,
 406         but others are treated like a normal PKT4 reg write.  I
 407         guess there are some registers that the fw controls certain
 408         bits.
 409          -->
 410         <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
 411
 412 </enum>
 413
 414
 415 <domain name="CP_LOAD_STATE" width="32">
 416         <doc>Load state, a3xx (and later?)</doc>
 417         <enum name="adreno_state_block">
 418                 <value name="SB_VERT_TEX" value="0"/>
 419                 <value name="SB_VERT_MIPADDR" value="1"/>
 420                 <value name="SB_FRAG_TEX" value="2"/>
 421                 <value name="SB_FRAG_MIPADDR" value="3"/>
 422                 <value name="SB_VERT_SHADER" value="4"/>
 423                 <value name="SB_GEOM_SHADER" value="5"/>
 424                 <value name="SB_FRAG_SHADER" value="6"/>
 425                 <value name="SB_COMPUTE_SHADER" value="7"/>
 426         </enum>
 427         <enum name="adreno_state_type">
 428                 <value name="ST_SHADER" value="0"/>
 429                 <value name="ST_CONSTANTS" value="1"/>
 430         </enum>
 431         <enum name="adreno_state_src">
 432                 <value name="SS_DIRECT" value="0">
 433                         <doc>inline with the CP_LOAD_STATE packet</doc>
 434                 </value>
 435                 <value name="SS_INVALID_ALL_IC" value="2"/>
 436                 <value name="SS_INVALID_PART_IC" value="3"/>
 437                 <value name="SS_INDIRECT" value="4">
 438                         <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
 439                 </value>
 440                 <value name="SS_INDIRECT_TCM" value="5"/>
 441                 <value name="SS_INDIRECT_STM" value="6"/>
 442         </enum>
 443         <reg32 offset="0" name="0">
 444                 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
 445                 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
 446                 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
 447                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 448         </reg32>
 449         <reg32 offset="1" name="1">
 450                 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
 451                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 452         </reg32>
 453 </domain>
 454
 455 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
 456         <doc>Load state, a4xx+</doc>
 457         <enum name="a4xx_state_block">
 458                 <!--
 459                 unknown: 0x7 and 0xf <- seen in compute shader
 460
 461                 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
 462                 Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
 463                 the gpuaddr of the following shader constants block.  DST_OFF seems
 464                 to specify which shader stage:
 465
 466                     16 -> vert
 467                     36 -> tcs
 468                     56 -> tes
 469                     76 -> geom
 470                     96 -> frag
 471
 472                 Example:
 473
 474 opcode: CP_LOAD_STATE4 (30) (12 dwords)
 475         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
 476         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
 477         { EXT_SRC_ADDR_HI = 0 }
 478                         0000: c0264100 00000000 00000000 00000000
 479                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
 480
 481 opcode: CP_LOAD_STATE4 (30) (4 dwords)
 482         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 483         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
 484         { EXT_SRC_ADDR_HI = 0 }
 485                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 486                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 487                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
 488
 489                 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
 490
 491                  -->
 492                 <value name="SB4_VS_TEX"    value="0x0"/>
 493                 <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 494                 <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 495                 <value name="SB4_GS_TEX"    value="0x3"/>
 496                 <value name="SB4_FS_TEX"    value="0x4"/>
 497                 <value name="SB4_CS_TEX"    value="0x5"/>
 498                 <value name="SB4_VS_SHADER" value="0x8"/>
 499                 <value name="SB4_HS_SHADER" value="0x9"/>
 500                 <value name="SB4_DS_SHADER" value="0xa"/>
 501                 <value name="SB4_GS_SHADER" value="0xb"/>
 502                 <value name="SB4_FS_SHADER" value="0xc"/>
 503                 <value name="SB4_CS_SHADER" value="0xd"/>
 504                 <!--
 505                 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
 506                 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
 507
 508                 Compute has it's own dedicated SSBO state, it seems, but the rest
 509                 of the stages share state
 510                  -->
 511                 <value name="SB4_SSBO"   value="0xe"/>
 512                 <value name="SB4_CS_SSBO"   value="0xf"/>
 513         </enum>
 514         <enum name="a4xx_state_type">
 515                 <value name="ST4_SHADER" value="0"/>
 516                 <value name="ST4_CONSTANTS" value="1"/>
 517                 <value name="ST4_UBO" value="2"/>
 518         </enum>
 519         <enum name="a4xx_state_src">
 520                 <value name="SS4_DIRECT" value="0"/>
 521                 <value name="SS4_INDIRECT" value="2"/>
 522         </enum>
 523         <reg32 offset="0" name="0">
 524                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 525                 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
 526                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
 527                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 528         </reg32>
 529         <reg32 offset="1" name="1">
 530                 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
 531                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 532         </reg32>
 533         <reg32 offset="2" name="2" variants="A5XX-">
 534                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 535         </reg32>
 536 </domain>
 537
 538 <!-- looks basically same CP_LOAD_STATE4 -->
 539 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
 540         <doc>Load state, a6xx+</doc>
 541         <enum name="a6xx_state_block">
 542                 <value name="SB6_VS_TEX"    value="0x0"/>
 543                 <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 544                 <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 545                 <value name="SB6_GS_TEX"    value="0x3"/>
 546                 <value name="SB6_FS_TEX"    value="0x4"/>
 547                 <value name="SB6_CS_TEX"    value="0x5"/>
 548                 <value name="SB6_VS_SHADER" value="0x8"/>
 549                 <value name="SB6_HS_SHADER" value="0x9"/>
 550                 <value name="SB6_DS_SHADER" value="0xa"/>
 551                 <value name="SB6_GS_SHADER" value="0xb"/>
 552                 <value name="SB6_FS_SHADER" value="0xc"/>
 553                 <value name="SB6_CS_SHADER" value="0xd"/>
 554                 <value name="SB6_IBO"       value="0xe"/>
 555                 <value name="SB6_CS_IBO"    value="0xf"/>
 556         </enum>
 557         <enum name="a6xx_state_type">
 558                 <value name="ST6_SHADER" value="0"/>
 559                 <value name="ST6_CONSTANTS" value="1"/>
 560                 <value name="ST6_UBO" value="2"/>
 561                 <value name="ST6_IBO" value="3"/>
 562         </enum>
 563         <enum name="a6xx_state_src">
 564                 <value name="SS6_DIRECT" value="0"/>
 565                 <value name="SS6_INDIRECT" value="2"/>
 566         </enum>
 567         <reg32 offset="0" name="0">
 568                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 569                 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
 570                 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
 571                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
 572                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 573         </reg32>
 574         <reg32 offset="1" name="1">
 575                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 576         </reg32>
 577         <reg32 offset="2" name="2">
 578                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 579         </reg32>
 580 </domain>
 581
 582 <bitset name="vgt_draw_initiator" inline="yes">
 583         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 584         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 585         <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
 586         <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
 587         <bitfield name="NOT_EOP" pos="12" type="boolean"/>
 588         <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
 589         <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
 590         <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
 591 </bitset>
 592
 593 <!-- changed on a4xx: -->
 594 <enum name="a4xx_index_size">
 595         <value name="INDEX4_SIZE_8_BIT" value="0"/>
 596         <value name="INDEX4_SIZE_16_BIT" value="1"/>
 597         <value name="INDEX4_SIZE_32_BIT" value="2"/>
 598 </enum>
 599
 600 <enum name="a6xx_patch_type">
 601   <value name="TESS_QUADS" value="0"/>
 602   <value name="TESS_TRIANGLES" value="1"/>
 603   <value name="TESS_ISOLINES" value="2"/>
 604 </enum>
 605
 606 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
 607         <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
 608         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 609         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 610         <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 611         <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 612         <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
 613         <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 614 </bitset>
 615
 616 <domain name="CP_DRAW_INDX" width="32">
 617         <reg32 offset="0" name="0">
 618                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 619         </reg32>
 620         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 621         <reg32 offset="2" name="2">
 622                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 623         </reg32>
 624         <reg32 offset="3" name="3">
 625                 <bitfield name="INDX_BASE" low="0" high="31"/>
 626         </reg32>
 627         <reg32 offset="4" name="4">
 628                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 629         </reg32>
 630 </domain>
 631
 632 <domain name="CP_DRAW_INDX_2" width="32">
 633         <reg32 offset="0" name="0">
 634                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 635         </reg32>
 636         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 637         <reg32 offset="2" name="2">
 638                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 639         </reg32>
 640         <!-- followed by NUM_INDICES indices.. -->
 641 </domain>
 642
 643 <domain name="CP_DRAW_INDX_OFFSET" width="32">
 644         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 645         <reg32 offset="1" name="1">
 646                 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
 647         </reg32>
 648         <reg32 offset="2" name="2">
 649                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 650         </reg32>
 651         <reg32 offset="3" name="3">
 652         </reg32>
 653         <reg32 offset="4" name="4">
 654                 <bitfield name="INDX_BASE" low="0" high="31"/>
 655         </reg32>
 656         <reg32 offset="5" name="5">
 657                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 658         </reg32>
 659 </domain>
 660
 661 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 662         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 663         <reg32 offset="1" name="1">
 664                 <bitfield name="INDIRECT" low="0" high="31"/>
 665         </reg32>
 666         <stripe variants="A5XX-">
 667                 <reg32 offset="2" name="2">
 668                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 669                 </reg32>
 670         </stripe>
 671 </domain>
 672
 673 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 674         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 675         <stripe variants="A4XX">
 676                 <reg32 offset="1" name="1">
 677                         <bitfield name="INDX_BASE" low="0" high="31"/>
 678                 </reg32>
 679                 <reg32 offset="2" name="2">
 680                         <!-- max # of bytes in index buffer -->
 681                         <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
 682                 </reg32>
 683                 <reg32 offset="3" name="3">
 684                         <bitfield name="INDIRECT" low="0" high="31"/>
 685                 </reg32>
 686         </stripe>
 687         <stripe variants="A5XX-">
 688                 <reg32 offset="1" name="1">
 689                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 690                 </reg32>
 691                 <reg32 offset="2" name="2">
 692                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 693                 </reg32>
 694                 <reg32 offset="3" name="3">
 695                         <!-- max # of elements in index buffer -->
 696                         <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
 697                 </reg32>
 698                 <reg32 offset="4" name="4">
 699                         <bitfield name="INDIRECT_LO" low="0" high="31"/>
 700                 </reg32>
 701                 <reg32 offset="5" name="5">
 702                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 703                 </reg32>
 704         </stripe>
 705 </domain>
 706
 707 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
 708         <array offset="0" name="" stride="3" length="100">
 709                 <reg32 offset="0" name="0">
 710                         <bitfield name="COUNT" low="0" high="15" type="uint"/>
 711                         <bitfield name="DIRTY" pos="16" type="boolean"/>
 712                         <bitfield name="DISABLE" pos="17" type="boolean"/>
 713                         <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 714                         <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
 715                         <!--
 716                         I think this is a bitmask of states that this group applies to
 717                         (ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
 718                         emits different VS state at the same time, with ENABLE_MASK=0x1
 719                         for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
 720                         -->
 721                         <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
 722                         <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 723                 </reg32>
 724                 <reg32 offset="1" name="1">
 725                         <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
 726                 </reg32>
 727                 <reg32 offset="2" name="2" variants="A5XX-">
 728                         <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
 729                 </reg32>
 730         </array>
 731 </domain>
 732
 733 <domain name="CP_SET_BIN" width="32">
 734         <doc>value at offset 0 always seems to be 0x00000000..</doc>
 735         <reg32 offset="0" name="0"/>
 736         <reg32 offset="1" name="1">
 737                 <bitfield name="X1" low="0" high="15" type="uint"/>
 738                 <bitfield name="Y1" low="16" high="31" type="uint"/>
 739         </reg32>
 740         <reg32 offset="2" name="2">
 741                 <bitfield name="X2" low="0" high="15" type="uint"/>
 742                 <bitfield name="Y2" low="16" high="31" type="uint"/>
 743         </reg32>
 744 </domain>
 745
 746 <domain name="CP_SET_BIN_DATA" width="32">
 747         <reg32 offset="0" name="0">
 748                 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
 749                 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
 750         </reg32>
 751         <reg32 offset="1" name="1">
 752                 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
 753                 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
 754         </reg32>
 755 </domain>
 756
 757 <domain name="CP_SET_BIN_DATA5" width="32">
 758         <reg32 offset="0" name="0">
 759                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 760                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 761                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 762                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 763         </reg32>
 764         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 765         <reg32 offset="1" name="1">
 766                 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
 767         </reg32>
 768         <reg32 offset="2" name="2">
 769                 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
 770         </reg32>
 771         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 772         <reg32 offset="3" name="3">
 773                 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
 774         </reg32>
 775         <reg32 offset="4" name="4">
 776                 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
 777         </reg32>
 778         <!-- what is this new address? -->
 779         <reg32 offset="5" name="5">
 780                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 781         </reg32>
 782         <reg32 offset="6" name="6">
 783                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 784         </reg32>
 785 </domain>
 786
 787 <domain name="CP_REG_TO_MEM" width="32">
 788         <reg32 offset="0" name="0">
 789                 <bitfield name="REG" low="0" high="15" type="hex"/>
 790                 <!--
 791                 number of regsiters/dwords copied is CNT+1.. unsure
 792                 about # of bits
 793                  -->
 794                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 795                 <bitfield name="64B" pos="30" type="boolean"/>
 796                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 797         </reg32>
 798         <reg32 offset="1" name="1">
 799                 <bitfield name="DEST" low="0" high="31"/>
 800         </reg32>
 801         <reg32 offset="2" name="2" variants="A5XX-">
 802                 <bitfield name="DEST_HI" low="0" high="31"/>
 803         </reg32>
 804 </domain>
 805
 806 <domain name="CP_MEM_TO_REG" width="32">
 807         <reg32 offset="0" name="0">
 808                 <bitfield name="REG" low="0" high="15" type="hex"/>
 809                 <!--
 810                 number of regsiters/dwords copied is CNT+1.. unsure
 811                 about # of bits
 812                  -->
 813                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 814                 <bitfield name="64B" pos="30" type="boolean"/>
 815                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 816         </reg32>
 817         <reg32 offset="1" name="1">
 818                 <bitfield name="SRC" low="0" high="31"/>
 819         </reg32>
 820         <reg32 offset="2" name="2" variants="A5XX-">
 821                 <bitfield name="SRC_HI" low="0" high="31"/>
 822         </reg32>
 823 </domain>
 824
 825 <domain name="CP_MEM_TO_MEM" width="32">
 826         <reg32 offset="0" name="0">
 827                 <!--
 828                 not sure how many src operands we have, but the low
 829                 bits negate the n'th src argument.
 830                  -->
 831                 <bitfield name="NEG_A" pos="0" type="boolean"/>
 832                 <bitfield name="NEG_B" pos="1" type="boolean"/>
 833                 <bitfield name="NEG_C" pos="2" type="boolean"/>
 834
 835                 <!-- if set treat src/dst as 64bit values -->
 836                 <bitfield name="DOUBLE" pos="29" type="boolean"/>
 837         </reg32>
 838         <!--
 839         followed by sequence of addresses.. the first is the
 840         destination and the rest are N src addresses which are
 841         summed (after being negated if NEG_x bit set) allowing
 842         to do things like 'result += end - start' (which turns
 843         out to be useful for queries and accumulating results
 844         across multiple tiles)
 845          -->
 846 </domain>
 847
 848 <enum name="cp_cond_function">
 849         <value value="0" name="WRITE_ALWAYS"/>
 850         <value value="1" name="WRITE_LT"/>
 851         <value value="2" name="WRITE_LE"/>
 852         <value value="3" name="WRITE_EQ"/>
 853         <value value="4" name="WRITE_NE"/>
 854         <value value="5" name="WRITE_GE"/>
 855         <value value="6" name="WRITE_GT"/>
 856 </enum>
 857
 858 <domain name="CP_COND_WRITE" width="32">
 859         <reg32 offset="0" name="0">
 860                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 861                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 862                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 863         </reg32>
 864         <reg32 offset="1" name="1">
 865                 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
 866         </reg32>
 867         <reg32 offset="2" name="2">
 868                 <bitfield name="REF" low="0" high="31"/>
 869         </reg32>
 870         <reg32 offset="3" name="3">
 871                 <bitfield name="MASK" low="0" high="31"/>
 872         </reg32>
 873         <reg32 offset="4" name="4">
 874                 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
 875         </reg32>
 876         <reg32 offset="5" name="5">
 877                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 878         </reg32>
 879 </domain>
 880
 881 <domain name="CP_COND_WRITE5" width="32">
 882         <reg32 offset="0" name="0">
 883                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 884                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 885                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 886         </reg32>
 887         <reg32 offset="1" name="1">
 888                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 889         </reg32>
 890         <reg32 offset="2" name="2">
 891                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 892         </reg32>
 893         <reg32 offset="3" name="3">
 894                 <bitfield name="REF" low="0" high="31"/>
 895         </reg32>
 896         <reg32 offset="4" name="4">
 897                 <bitfield name="MASK" low="0" high="31"/>
 898         </reg32>
 899         <reg32 offset="5" name="5">
 900                 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
 901         </reg32>
 902         <reg32 offset="6" name="6">
 903                 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
 904         </reg32>
 905         <reg32 offset="7" name="7">
 906                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 907         </reg32>
 908 </domain>
 909
 910 <domain name="CP_DISPATCH_COMPUTE" width="32">
 911         <reg32 offset="0" name="0"/>
 912         <reg32 offset="1" name="1">
 913                 <bitfield name="X" low="0" high="31"/>
 914         </reg32>
 915         <reg32 offset="2" name="2">
 916                 <bitfield name="Y" low="0" high="31"/>
 917         </reg32>
 918         <reg32 offset="3" name="3">
 919                 <bitfield name="Z" low="0" high="31"/>
 920         </reg32>
 921 </domain>
 922
 923 <domain name="CP_SET_RENDER_MODE" width="32">
 924         <enum name="render_mode_cmd">
 925                 <value value="1" name="BYPASS"/>
 926                 <value value="2" name="BINNING"/>
 927                 <value value="3" name="GMEM"/>
 928                 <value value="5" name="BLIT2D"/>
 929                 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
 930                 <value value="7" name="BLIT2DSCALE"/>
 931                 <!-- 8 set before going back to BYPASS exiting 2D -->
 932                 <value value="8" name="END2D"/>
 933         </enum>
 934         <reg32 offset="0" name="0">
 935                 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
 936                 <!--
 937                 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
 938                 0x21xx range.. possibly (at least some) a5xx variants have a
 939                 2d core?
 940                  -->
 941         </reg32>
 942         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 943         <reg32 offset="1" name="1">
 944                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 945         </reg32>
 946         <reg32 offset="2" name="2">
 947                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 948         </reg32>
 949         <reg32 offset="3" name="3">
 950                 <!--
 951                 set when in GMEM.. maybe indicates GMEM contents need to be
 952                 preserved on ctx switch?
 953                  -->
 954                 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
 955                 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
 956         </reg32>
 957         <reg32 offset="4" name="4"/>
 958         <!-- second buffer looks like some cmdstream.. length in dwords: -->
 959         <reg32 offset="5" name="5">
 960                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 961         </reg32>
 962         <reg32 offset="6" name="6">
 963                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
 964         </reg32>
 965         <reg32 offset="7" name="7">
 966                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 967         </reg32>
 968 </domain>
 969
 970 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
 971 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
 972         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 973         <reg32 offset="0" name="0">
 974                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 975         </reg32>
 976         <reg32 offset="1" name="1">
 977                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 978         </reg32>
 979         <reg32 offset="2" name="2">
 980         </reg32>
 981         <!-- second buffer looks like some cmdstream.. length in dwords: -->
 982         <reg32 offset="3" name="3">
 983                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 984         </reg32>
 985         <reg32 offset="4" name="4"/>
 986         <reg32 offset="5" name="5">
 987                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
 988         </reg32>
 989         <reg32 offset="6" name="6">
 990                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 991         </reg32>
 992         <reg32 offset="7" name="7"/>
 993 </domain>
 994
 995 <domain name="CP_PERFCOUNTER_ACTION" width="32">
 996         <reg32 offset="0" name="0">
 997         </reg32>
 998         <reg32 offset="1" name="1">
 999                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1000         </reg32>
1001         <reg32 offset="2" name="2">
1002                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1003         </reg32>
1004 </domain>
1005
1006 <domain name="CP_EVENT_WRITE" width="32">
1007         <reg32 offset="0" name="0">
1008                 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1009                 <!-- when set, write back timestamp instead of value from packet: -->
1010                 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1011         </reg32>
1012         <!--
1013         TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1014         context switch?
1015          -->
1016         <reg32 offset="1" name="1">
1017                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1018         </reg32>
1019         <reg32 offset="2" name="2">
1020                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1021         </reg32>
1022         <reg32 offset="3" name="3">
1023                 <!-- ??? -->
1024         </reg32>
1025 </domain>
1026
1027 <domain name="CP_BLIT" width="32">
1028         <enum name="cp_blit_cmd">
1029                 <value value="0" name="BLIT_OP_FILL"/>
1030                 <value value="1" name="BLIT_OP_COPY"/>
1031                 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1032         </enum>
1033         <reg32 offset="0" name="0">
1034                 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1035         </reg32>
1036         <reg32 offset="1" name="1">
1037                 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1038                 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1039         </reg32>
1040         <reg32 offset="2" name="2">
1041                 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1042                 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1043         </reg32>
1044         <reg32 offset="3" name="3">
1045                 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1046                 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1047         </reg32>
1048         <reg32 offset="4" name="4">
1049                 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1050                 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1051         </reg32>
1052 </domain>
1053
1054 <domain name="CP_EXEC_CS" width="32">
1055         <reg32 offset="0" name="0">
1056         </reg32>
1057         <reg32 offset="1" name="1">
1058                 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1059         </reg32>
1060         <reg32 offset="2" name="2">
1061                 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1062         </reg32>
1063         <reg32 offset="3" name="3">
1064                 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1065         </reg32>
1066 </domain>
1067
1068 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1069         <reg32 offset="0" name="0">
1070         </reg32>
1071         <stripe variants="A4XX">
1072                 <reg32 offset="1" name="1">
1073                         <bitfield name="ADDR" low="0" high="31"/>
1074                 </reg32>
1075                 <reg32 offset="2" name="2">
1076                         <!-- localsize is value minus one: -->
1077                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1078                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1079                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1080                 </reg32>
1081         </stripe>
1082         <stripe variants="A5XX-">
1083                 <reg32 offset="1" name="1">
1084                         <bitfield name="ADDR_LO" low="0" high="31"/>
1085                 </reg32>
1086                 <reg32 offset="2" name="2">
1087                         <bitfield name="ADDR_HI" low="0" high="31"/>
1088                 </reg32>
1089                 <reg32 offset="3" name="3">
1090                         <!-- localsize is value minus one: -->
1091                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1092                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1093                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1094                 </reg32>
1095         </stripe>
1096 </domain>
1097
1098 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1099         <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1100         <enum name="a6xx_render_mode">
1101                 <value value="1" name="RM6_BYPASS"/>
1102                 <value value="2" name="RM6_BINNING"/>
1103                 <value value="4" name="RM6_GMEM"/>
1104                 <value value="5" name="RM6_BLIT2D"/>
1105                 <value value="6" name="RM6_RESOLVE"/>
1106                 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1107         </enum>
1108         <reg32 offset="0" name="0">
1109                 <bitfield name="MARKER" low="0" high="3"/>
1110                 <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
1111                 <!-- IFPC - inter-frame power collapse -->
1112                 <bitfield name="IFPC" pos="8" type="boolean"/>
1113         </reg32>
1114 </domain>
1115
1116 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1117         <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1118         <enum name="pseudo_reg">
1119                 <value value="0" name="SMMU_INFO"/>
1120                 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1121                 <value value="2" name="SECURE_SAVE_ADDR"/>
1122                 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1123                 <value value="4" name="COUNTER"/>
1124         </enum>
1125         <array offset="0" name="" stride="3" length="100">
1126                 <reg32 offset="0" name="0">
1127                         <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1128                 </reg32>
1129                 <reg32 offset="1" name="1">
1130                         <bitfield name="LO" low="0" high="31"/>
1131                 </reg32>
1132                 <reg32 offset="2" name="2">
1133                         <bitfield name="HI" low="0" high="31"/>
1134                 </reg32>
1135         </array>
1136 </domain>
1137
1138 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1139         <doc>
1140                 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1141                 So:
1142
1143                         opcode: CP_REG_TEST (39) (2 dwords)
1144                                 { REG = 0xc10 | BIT = 0 }
1145                                        0000: 70b90001 00000c10
1146                         opcode: CP_COND_REG_EXEC (47) (3 dwords)
1147                                        0000: 70c70002 10000000 00000004
1148                         opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1149
1150                 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1151                 offset 0x0c10 is 1
1152         </doc>
1153         <reg32 offset="0" name="0">
1154                 <!-- the register to test -->
1155                 <bitfield name="REG" low="0" high="11"/>
1156                 <!-- the bit to test -->
1157                 <bitfield name="BIT" low="20" high="24" type="uint"/>
1158                 <bitfield name="UNK25" pos="25" type="boolean"/>
1159         </reg32>
1160 </domain>
1161
1162 <!-- I *think* this existed at least as far back as a4xx -->
1163 <domain name="CP_COND_REG_EXEC" width="32">
1164         <reg32 offset="0" name="0">
1165                 <bitfield name="UNK28" pos="28" type="boolean"/>
1166         </reg32>
1167         <reg32 offset="1" name="1">
1168                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1169         </reg32>
1170 </domain>
1171
1172 </database>
1173