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freedreno/a6xx: Define the register fields for polygon fill mode.
[mesa.git] / src / freedreno / registers / adreno_pm4.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
6 <enum name="vgt_event_type">
7 <value name="VS_DEALLOC" value="0"/>
8 <value name="PS_DEALLOC" value="1"/>
9 <value name="VS_DONE_TS" value="2"/>
10 <value name="PS_DONE_TS" value="3"/>
11 <value name="CACHE_FLUSH_TS" value="4"/>
12 <value name="CONTEXT_DONE" value="5"/>
13 <value name="CACHE_FLUSH" value="6"/>
14 <value name="VIZQUERY_START" value="7" variants="A2XX"/>
15 <value name="HLSQ_FLUSH" value="7" variants="A3XX,A4XX"/>
16 <value name="VIZQUERY_END" value="8" variants="A2XX"/>
17 <value name="SC_WAIT_WC" value="9"/>
18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
19 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
20 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
21 <value name="RST_PIX_CNT" value="13"/>
22 <value name="RST_VTX_CNT" value="14"/>
23 <value name="TILE_FLUSH" value="15"/>
24 <value name="STAT_EVENT" value="16"/>
25 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
26 <value name="ZPASS_DONE" value="21"/>
27 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
28 <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
29 <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
30 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
31 <value name="VS_FETCH_DONE" value="27"/>
32 <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
33
34 <!-- a5xx events -->
35 <value name="WT_DONE_TS" value="8" variants="A5XX,A6XX"/>
36 <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
37 <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
38 <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
39 <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
40 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
41 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
42 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
43 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX,A6XX"/>
44 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX,A6XX"/>
45 <value name="BLIT" value="30" variants="A5XX,A6XX"/>
46 <value name="UNK_25" value="37" variants="A5XX"/>
47 <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
48 <value name="UNK_2C" value="44" variants="A5XX"/>
49 <value name="UNK_2D" value="45" variants="A5XX"/>
50
51 <!-- a6xx events -->
52 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
53 </enum>
54
55 <enum name="pc_di_primtype">
56 <value name="DI_PT_NONE" value="0"/>
57 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
58 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
59 <value name="DI_PT_LINELIST" value="2"/>
60 <value name="DI_PT_LINESTRIP" value="3"/>
61 <value name="DI_PT_TRILIST" value="4"/>
62 <value name="DI_PT_TRIFAN" value="5"/>
63 <value name="DI_PT_TRISTRIP" value="6"/>
64 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
65 <value name="DI_PT_RECTLIST" value="8"/>
66 <value name="DI_PT_POINTLIST" value="9"/>
67 <value name="DI_PT_LINE_ADJ" value="0xa"/>
68 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
69 <value name="DI_PT_TRI_ADJ" value="0xc"/>
70 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
71
72 <value name="DI_PT_PATCHES0" value="0x1f"/>
73 <value name="DI_PT_PATCHES1" value="0x20"/>
74 <value name="DI_PT_PATCHES2" value="0x21"/>
75 <value name="DI_PT_PATCHES3" value="0x22"/>
76 <value name="DI_PT_PATCHES4" value="0x23"/>
77 <value name="DI_PT_PATCHES5" value="0x24"/>
78 <value name="DI_PT_PATCHES6" value="0x25"/>
79 <value name="DI_PT_PATCHES7" value="0x26"/>
80 <value name="DI_PT_PATCHES8" value="0x27"/>
81 <value name="DI_PT_PATCHES9" value="0x28"/>
82 <value name="DI_PT_PATCHES10" value="0x29"/>
83 <value name="DI_PT_PATCHES11" value="0x2a"/>
84 <value name="DI_PT_PATCHES12" value="0x2b"/>
85 <value name="DI_PT_PATCHES13" value="0x2c"/>
86 <value name="DI_PT_PATCHES14" value="0x2d"/>
87 <value name="DI_PT_PATCHES15" value="0x2e"/>
88 <value name="DI_PT_PATCHES16" value="0x2f"/>
89 <value name="DI_PT_PATCHES17" value="0x30"/>
90 <value name="DI_PT_PATCHES18" value="0x31"/>
91 <value name="DI_PT_PATCHES19" value="0x32"/>
92 <value name="DI_PT_PATCHES20" value="0x33"/>
93 <value name="DI_PT_PATCHES21" value="0x34"/>
94 <value name="DI_PT_PATCHES22" value="0x35"/>
95 <value name="DI_PT_PATCHES23" value="0x36"/>
96 <value name="DI_PT_PATCHES24" value="0x37"/>
97 <value name="DI_PT_PATCHES25" value="0x38"/>
98 <value name="DI_PT_PATCHES26" value="0x39"/>
99 <value name="DI_PT_PATCHES27" value="0x3a"/>
100 <value name="DI_PT_PATCHES28" value="0x3b"/>
101 <value name="DI_PT_PATCHES29" value="0x3c"/>
102 <value name="DI_PT_PATCHES30" value="0x3d"/>
103 <value name="DI_PT_PATCHES31" value="0x3e"/>
104 </enum>
105
106 <enum name="pc_di_src_sel">
107 <value name="DI_SRC_SEL_DMA" value="0"/>
108 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
109 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
110 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
111 </enum>
112
113 <enum name="pc_di_face_cull_sel">
114 <value name="DI_FACE_CULL_NONE" value="0"/>
115 <value name="DI_FACE_CULL_FETCH" value="1"/>
116 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
117 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
118 </enum>
119
120 <enum name="pc_di_index_size">
121 <value name="INDEX_SIZE_IGN" value="0"/>
122 <value name="INDEX_SIZE_16_BIT" value="0"/>
123 <value name="INDEX_SIZE_32_BIT" value="1"/>
124 <value name="INDEX_SIZE_8_BIT" value="2"/>
125 <value name="INDEX_SIZE_INVALID"/>
126 </enum>
127
128 <enum name="pc_di_vis_cull_mode">
129 <value name="IGNORE_VISIBILITY" value="0"/>
130 <value name="USE_VISIBILITY" value="1"/>
131 </enum>
132
133 <enum name="adreno_pm4_packet_type">
134 <value name="CP_TYPE0_PKT" value="0x00000000"/>
135 <value name="CP_TYPE1_PKT" value="0x40000000"/>
136 <value name="CP_TYPE2_PKT" value="0x80000000"/>
137 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
138 <value name="CP_TYPE4_PKT" value="0x40000000"/>
139 <value name="CP_TYPE7_PKT" value="0x70000000"/>
140 </enum>
141
142 <!--
143 Note that in some cases, the same packet id is recycled on a later
144 generation, so variants attribute is used to distinguish. They
145 may not be completely accurate, we would probably have to analyze
146 the pfp and me/pm4 firmware to verify the packet is actually
147 handled on a particular generation. But it is at least enough to
148 disambiguate the packet-id's that were re-used for different
149 packets starting with a5xx.
150 -->
151 <enum name="adreno_pm4_type3_packets">
152 <doc>initialize CP's micro-engine</doc>
153 <value name="CP_ME_INIT" value="0x48"/>
154 <doc>skip N 32-bit words to get to the next packet</doc>
155 <value name="CP_NOP" value="0x10"/>
156 <doc>
157 indirect buffer dispatch. prefetch parser uses this packet
158 type to determine whether to pre-fetch the IB
159 </doc>
160 <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
161 <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
162 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
163 <doc>
164 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
165 another buffer at the same level. Must be at the end of IB, and
166 doesn't work with draw state IB's.
167 </doc>
168 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
169 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
170 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
171 <doc>wait for the IDLE state of the engine</doc>
172 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
173 <doc>wait until a register or memory location is a specific value</doc>
174 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
175 <doc>wait until a register location is equal to a specific value</doc>
176 <value name="CP_WAIT_REG_EQ" value="0x52"/>
177 <doc>wait until a register location is >= a specific value</doc>
178 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
179 <doc>wait until a read completes</doc>
180 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
181 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
182 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
183 <doc>register read/modify/write</doc>
184 <value name="CP_REG_RMW" value="0x21"/>
185 <doc>Set binning configuration registers</doc>
186 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
187 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
188 <doc>reads register in chip and writes to memory</doc>
189 <value name="CP_REG_TO_MEM" value="0x3e"/>
190 <doc>write N 32-bit words to memory</doc>
191 <value name="CP_MEM_WRITE" value="0x3d"/>
192 <doc>write CP_PROG_COUNTER value to memory</doc>
193 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
194 <doc>conditional execution of a sequence of packets</doc>
195 <value name="CP_COND_EXEC" value="0x44"/>
196 <doc>conditional write to memory or register</doc>
197 <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
198 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
199 <doc>generate an event that creates a write to memory when completed</doc>
200 <value name="CP_EVENT_WRITE" value="0x46"/>
201 <doc>generate a VS|PS_done event</doc>
202 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
203 <doc>generate a cache flush done event</doc>
204 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
205 <doc>generate a z_pass done event</doc>
206 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
207 <doc>
208 not sure the real name, but this seems to be what is used for
209 opencl, instead of CP_DRAW_INDX..
210 </doc>
211 <value name="CP_RUN_OPENCL" value="0x31"/>
212 <doc>initiate fetch of index buffer and draw</doc>
213 <value name="CP_DRAW_INDX" value="0x22"/>
214 <doc>draw using supplied indices in packet</doc>
215 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
216 <doc>initiate fetch of index buffer and binIDs and draw</doc>
217 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
218 <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
219 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
220 <doc>begin/end initiator for viz query extent processing</doc>
221 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
222 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
223 <value name="CP_SET_STATE" value="0x25"/>
224 <doc>load constant into chip and to memory</doc>
225 <value name="CP_SET_CONSTANT" value="0x2d"/>
226 <doc>load sequencer instruction memory (pointer-based)</doc>
227 <value name="CP_IM_LOAD" value="0x27"/>
228 <doc>load sequencer instruction memory (code embedded in packet)</doc>
229 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
230 <doc>load constants from a location in memory</doc>
231 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
232 <doc>selective invalidation of state pointers</doc>
233 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
234 <doc>dynamically changes shader instruction memory partition</doc>
235 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
236 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
237 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
238 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
239 <value name="CP_SET_BIN_SELECT" value="0x51"/>
240 <doc>updates the current context, if needed</doc>
241 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
242 <doc>generate interrupt from the command stream</doc>
243 <value name="CP_INTERRUPT" value="0x40"/>
244 <doc>copy sequencer instruction memory to system memory</doc>
245 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
246
247 <!-- For a20x -->
248 <!-- TODO handle variants..
249 <doc>
250 Program an offset that will added to the BIN_BASE value of
251 the 3D_DRAW_INDX_BIN packet
252 </doc>
253 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
254 -->
255
256 <!-- for a22x -->
257 <doc>
258 sets draw initiator flags register in PFP, gets bitwise-ORed into
259 every draw initiator
260 </doc>
261 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
262 <doc>sets the register protection mode</doc>
263 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
264
265 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
266
267 <!-- for a3xx -->
268 <doc>load high level sequencer command</doc>
269 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
270 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
271 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
272 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
273 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
274 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
275 <doc>Load a buffer with pre-fetch enabled</doc>
276 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
277 <doc>Set bin (?)</doc>
278 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
279
280 <doc>test 2 memory locations to dword values specified</doc>
281 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
282
283 <doc>Write register, ignoring context state for context sensitive registers</doc>
284 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
285
286 <doc>Record the real-time when this packet is processed by PFP</doc>
287 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
288
289 <!-- Used to switch GPU between secure and non-secure modes -->
290 <value name="CP_SET_SECURE_MODE" value="0x66"/>
291
292 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
293 <value name="CP_WAIT_FOR_ME" value="0x13"/>
294
295 <!-- for a4xx -->
296 <doc>
297 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
298 groups of registers. Looks like it can be used to create state
299 objects in GPU memory, and on state change only emit pointer
300 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
301 overhead:
302
303 (A4x) save PM4 stream pointers to execute upon a visible draw
304 </doc>
305 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
306 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
307 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
308 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
309 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX"/>
310 <value name="CP_DRAW_AUTO" value="0x24"/>
311
312 <value name="CP_UNKNOWN_19" value="0x19"/>
313
314 <doc>set to 1 for fastclear..:</doc>
315 <value name="CP_UNKNOWN_1A" value="0x1a"/>
316
317 <value name="CP_UNKNOWN_4E" value="0x4e"/>
318
319 <doc>
320 for A4xx
321 Write to register with address that does not fit into type-0 pkt
322 </doc>
323 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
324
325 <doc>copy from ME scratch RAM to a register</doc>
326 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
327
328 <doc>Copy from REG to ME scratch RAM</doc>
329 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
330
331 <doc>Wait for memory writes to complete</doc>
332 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
333
334 <doc>Conditional execution based on register comparison</doc>
335 <value name="CP_COND_REG_EXEC" value="0x47"/>
336
337 <doc>Memory to REG copy</doc>
338 <value name="CP_MEM_TO_REG" value="0x42"/>
339
340 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
341 <value name="CP_EXEC_CS" value="0x33"/>
342
343 <doc>
344 for a5xx
345 </doc>
346 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
347 <!-- switches SMMU pagetable, used on a5xx only -->
348 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
349 <!-- for a6xx -->
350 <doc>Tells CP the current mode of GPU operation</doc>
351 <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
352 <doc>Instruct CP to set a few internal CP registers</doc>
353 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
354 <!--
355 pairs of regid and value.. seems to be used to program some TF
356 related regs:
357 -->
358 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
359 <!-- A5XX Enable yield in RB only -->
360 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
361 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
362 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
363 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
364 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
365 <!-- Enable/Disable/Defer A5x global preemption model -->
366 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
367 <!-- Enable/Disable A5x local preemption model -->
368 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
369 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
370 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
371 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
372 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
373 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
374 <!-- check if this works on earlier.. -->
375 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
376 <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
377
378 <!-- Test specified bit in specified register and set predicate -->
379 <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
380
381 <!--
382 Seems to set the mode flags which control which CP_SET_DRAW_STATE
383 packets are executed, based on their ENABLE_MASK values
384
385 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
386 packets w/ ENABLE_MASK & 0x6 to execute immediately
387 -->
388 <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
389
390 <!--
391 Seems like there are now separate blocks of state for VS vs FS/CS
392 (probably these amounts to geometry vs fragments so that geometry
393 stage of the pipeline for next draw can start while fragment stage
394 of current draw is still running. The format of the payload of the
395 packets is the same, the only difference is the offsets of the regs
396 the firmware code that handles the packet writes.
397
398 Note that for CL, starting with a6xx, the preferred # of local
399 threads is no longer the same as the max, implying that the shader
400 core can now run warps from unrelated shaders (ie.
401 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
402 CL_KERNEL_WORK_GROUP_SIZE)
403 -->
404 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
405 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
406 <!--
407 Note: For IBO state (Image/SSBOs) which have shared state across
408 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
409 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
410 interchangable.
411 -->
412 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
413
414 <!-- internal packets: -->
415 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
416 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
417 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
418 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
419 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
420 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
421 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
422 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
423
424 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
425 <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
426
427 <!-- TODO do these exist on A5xx? -->
428 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
429 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
430 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
431 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
432 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
433 <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
434 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
435 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
436
437 <!--
438 Seems to always have the payload:
439 00000002 00008801 00004010
440 or:
441 00000002 00008801 00004090
442 or:
443 00000002 00008801 00000010
444 00000002 00008801 00010010
445 00000002 00008801 00d64010
446 ...
447 Note set for compute shaders..
448 Is 0x8801 a register offset?
449 This appears to be a special sort of register write packet
450 more or less, but the firmware has some special handling..
451 Seems like it intercepts/modifies certain register offsets,
452 but others are treated like a normal PKT4 reg write. I
453 guess there are some registers that the fw controls certain
454 bits.
455 -->
456 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
457
458 </enum>
459
460
461 <domain name="CP_LOAD_STATE" width="32">
462 <doc>Load state, a3xx (and later?)</doc>
463 <enum name="adreno_state_block">
464 <value name="SB_VERT_TEX" value="0"/>
465 <value name="SB_VERT_MIPADDR" value="1"/>
466 <value name="SB_FRAG_TEX" value="2"/>
467 <value name="SB_FRAG_MIPADDR" value="3"/>
468 <value name="SB_VERT_SHADER" value="4"/>
469 <value name="SB_GEOM_SHADER" value="5"/>
470 <value name="SB_FRAG_SHADER" value="6"/>
471 <value name="SB_COMPUTE_SHADER" value="7"/>
472 </enum>
473 <enum name="adreno_state_type">
474 <value name="ST_SHADER" value="0"/>
475 <value name="ST_CONSTANTS" value="1"/>
476 </enum>
477 <enum name="adreno_state_src">
478 <value name="SS_DIRECT" value="0">
479 <doc>inline with the CP_LOAD_STATE packet</doc>
480 </value>
481 <value name="SS_INVALID_ALL_IC" value="2"/>
482 <value name="SS_INVALID_PART_IC" value="3"/>
483 <value name="SS_INDIRECT" value="4">
484 <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
485 </value>
486 <value name="SS_INDIRECT_TCM" value="5"/>
487 <value name="SS_INDIRECT_STM" value="6"/>
488 </enum>
489 <reg32 offset="0" name="0">
490 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
491 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
492 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
493 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
494 </reg32>
495 <reg32 offset="1" name="1">
496 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
497 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
498 </reg32>
499 </domain>
500
501 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
502 <doc>Load state, a4xx+</doc>
503 <enum name="a4xx_state_block">
504 <!--
505 unknown: 0x7 and 0xf <- seen in compute shader
506
507 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
508 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
509 the gpuaddr of the following shader constants block. DST_OFF seems
510 to specify which shader stage:
511
512 16 -> vert
513 36 -> tcs
514 56 -> tes
515 76 -> geom
516 96 -> frag
517
518 Example:
519
520 opcode: CP_LOAD_STATE4 (30) (12 dwords)
521 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
522 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
523 { EXT_SRC_ADDR_HI = 0 }
524 0000: c0264100 00000000 00000000 00000000
525 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
526
527 opcode: CP_LOAD_STATE4 (30) (4 dwords)
528 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
529 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
530 { EXT_SRC_ADDR_HI = 0 }
531 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
532 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
533 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
534
535 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
536
537 -->
538 <value name="SB4_VS_TEX" value="0x0"/>
539 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
540 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
541 <value name="SB4_GS_TEX" value="0x3"/>
542 <value name="SB4_FS_TEX" value="0x4"/>
543 <value name="SB4_CS_TEX" value="0x5"/>
544 <value name="SB4_VS_SHADER" value="0x8"/>
545 <value name="SB4_HS_SHADER" value="0x9"/>
546 <value name="SB4_DS_SHADER" value="0xa"/>
547 <value name="SB4_GS_SHADER" value="0xb"/>
548 <value name="SB4_FS_SHADER" value="0xc"/>
549 <value name="SB4_CS_SHADER" value="0xd"/>
550 <!--
551 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
552 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
553
554 Compute has it's own dedicated SSBO state, it seems, but the rest
555 of the stages share state
556 -->
557 <value name="SB4_SSBO" value="0xe"/>
558 <value name="SB4_CS_SSBO" value="0xf"/>
559 </enum>
560 <enum name="a4xx_state_type">
561 <value name="ST4_SHADER" value="0"/>
562 <value name="ST4_CONSTANTS" value="1"/>
563 <value name="ST4_UBO" value="2"/>
564 </enum>
565 <enum name="a4xx_state_src">
566 <value name="SS4_DIRECT" value="0"/>
567 <value name="SS4_INDIRECT" value="2"/>
568 </enum>
569 <reg32 offset="0" name="0">
570 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
571 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
572 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
573 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
574 </reg32>
575 <reg32 offset="1" name="1">
576 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
577 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
578 </reg32>
579 <reg32 offset="2" name="2" variants="A5XX-">
580 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
581 </reg32>
582 </domain>
583
584 <!-- looks basically same CP_LOAD_STATE4 -->
585 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
586 <doc>Load state, a6xx+</doc>
587 <enum name="a6xx_state_block">
588 <value name="SB6_VS_TEX" value="0x0"/>
589 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
590 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
591 <value name="SB6_GS_TEX" value="0x3"/>
592 <value name="SB6_FS_TEX" value="0x4"/>
593 <value name="SB6_CS_TEX" value="0x5"/>
594 <value name="SB6_VS_SHADER" value="0x8"/>
595 <value name="SB6_HS_SHADER" value="0x9"/>
596 <value name="SB6_DS_SHADER" value="0xa"/>
597 <value name="SB6_GS_SHADER" value="0xb"/>
598 <value name="SB6_FS_SHADER" value="0xc"/>
599 <value name="SB6_CS_SHADER" value="0xd"/>
600 <value name="SB6_IBO" value="0xe"/>
601 <value name="SB6_CS_IBO" value="0xf"/>
602 </enum>
603 <enum name="a6xx_state_type">
604 <value name="ST6_SHADER" value="0"/>
605 <value name="ST6_CONSTANTS" value="1"/>
606 <value name="ST6_UBO" value="2"/>
607 <value name="ST6_IBO" value="3"/>
608 </enum>
609 <enum name="a6xx_state_src">
610 <value name="SS6_DIRECT" value="0"/>
611 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
612 <value name="SS6_INDIRECT" value="2"/>
613 </enum>
614 <reg32 offset="0" name="0">
615 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
616 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
617 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
618 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
619 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
620 </reg32>
621 <reg32 offset="1" name="1">
622 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
623 </reg32>
624 <reg32 offset="2" name="2">
625 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
626 </reg32>
627 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
628 </domain>
629
630 <bitset name="vgt_draw_initiator" inline="yes">
631 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
632 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
633 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
634 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
635 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
636 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
637 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
638 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
639 </bitset>
640
641 <!-- changed on a4xx: -->
642 <enum name="a4xx_index_size">
643 <value name="INDEX4_SIZE_8_BIT" value="0"/>
644 <value name="INDEX4_SIZE_16_BIT" value="1"/>
645 <value name="INDEX4_SIZE_32_BIT" value="2"/>
646 </enum>
647
648 <enum name="a6xx_patch_type">
649 <value name="TESS_QUADS" value="0"/>
650 <value name="TESS_TRIANGLES" value="1"/>
651 <value name="TESS_ISOLINES" value="2"/>
652 </enum>
653
654 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
655 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
656 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
657 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
658 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
659 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
660 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
661 <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
662 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
663 </bitset>
664
665 <domain name="CP_DRAW_INDX" width="32">
666 <reg32 offset="0" name="0">
667 <bitfield name="VIZ_QUERY" low="0" high="31"/>
668 </reg32>
669 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
670 <reg32 offset="2" name="2">
671 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
672 </reg32>
673 <reg32 offset="3" name="3">
674 <bitfield name="INDX_BASE" low="0" high="31"/>
675 </reg32>
676 <reg32 offset="4" name="4">
677 <bitfield name="INDX_SIZE" low="0" high="31"/>
678 </reg32>
679 </domain>
680
681 <domain name="CP_DRAW_INDX_2" width="32">
682 <reg32 offset="0" name="0">
683 <bitfield name="VIZ_QUERY" low="0" high="31"/>
684 </reg32>
685 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
686 <reg32 offset="2" name="2">
687 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
688 </reg32>
689 <!-- followed by NUM_INDICES indices.. -->
690 </domain>
691
692 <domain name="CP_DRAW_INDX_OFFSET" width="32">
693 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
694 <reg32 offset="1" name="1">
695 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
696 </reg32>
697 <reg32 offset="2" name="2">
698 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
699 </reg32>
700 <reg32 offset="3" name="3">
701 </reg32>
702
703 <stripe variants="A5XX-">
704 <reg32 offset="4" name="4">
705 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
706 </reg32>
707 <reg32 offset="5" name="5">
708 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
709 </reg32>
710 <reg64 offset="4" name="INDX_BASE" type="address"/>
711 <reg32 offset="6" name="6">
712 <bitfield name="INDX_SIZE" low="0" high="31"/>
713 </reg32>
714 </stripe>
715
716 <reg32 offset="4" name="4">
717 <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
718 </reg32>
719
720 <reg32 offset="5" name="5">
721 <bitfield name="INDX_SIZE" low="0" high="31"/>
722 </reg32>
723 </domain>
724
725 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
726 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
727 <strip variants="A4XX">
728 <reg32 offset="1" name="1">
729 <bitfield name="INDIRECT" low="0" high="31"/>
730 </reg32>
731 </strip>
732 <stripe variants="A5XX-">
733 <reg32 offset="1" name="1">
734 <bitfield name="INDIRECT_LO" low="0" high="31"/>
735 </reg32>
736 <reg32 offset="2" name="2">
737 <bitfield name="INDIRECT_HI" low="0" high="31"/>
738 </reg32>
739 <reg64 offset="1" name="INDIRECT" type="address"/>
740 </stripe>
741 </domain>
742
743 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
744 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
745 <stripe variants="A4XX">
746 <reg32 offset="1" name="1">
747 <bitfield name="INDX_BASE" low="0" high="31"/>
748 </reg32>
749 <reg32 offset="2" name="2">
750 <!-- max # of bytes in index buffer -->
751 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
752 </reg32>
753 <reg32 offset="3" name="3">
754 <bitfield name="INDIRECT" low="0" high="31"/>
755 </reg32>
756 </stripe>
757 <stripe variants="A5XX-">
758 <reg32 offset="1" name="1">
759 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
760 </reg32>
761 <reg32 offset="2" name="2">
762 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
763 </reg32>
764 <reg64 offset="1" name="INDX_BASE" type="address"/>
765 <reg32 offset="3" name="3">
766 <!-- max # of elements in index buffer -->
767 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
768 </reg32>
769 <reg32 offset="4" name="4">
770 <bitfield name="INDIRECT_LO" low="0" high="31"/>
771 </reg32>
772 <reg32 offset="5" name="5">
773 <bitfield name="INDIRECT_HI" low="0" high="31"/>
774 </reg32>
775 <reg64 offset="4" name="INDIRECT" type="address"/>
776 </stripe>
777 </domain>
778
779 <domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
780 <enum name="a6xx_draw_indirect_opcode">
781 <value name="INDIRECT_OP_NORMAL" value="0x2"/>
782 <value name="INDIRECT_OP_INDEXED" value="0x4"/>
783 </enum>
784 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
785 <reg32 offset="1" name="1">
786 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode"/>
787 <doc>
788 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
789 be updated for each draw to {draw_id, first_vertex, first_instance, 0}
790 value of 0 disables it
791 </doc>
792 <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
793 </reg32>
794 <reg32 offset="2" name="2">
795 <bitfield name="DRAW_COUNT" low="0" high="31" type="hex"/>
796 </reg32>
797 <doc>for opcode 2: indirect address. for opcode 4: index address</doc>
798 <reg64 offset="3" name="ADDRESS_0" type="address"/>
799 <reg32 offset="5" name="5">
800 <doc>for opcode 2: stride. for opcode 4: max_indices</doc>
801 <bitfield name="PARAM_0" low="0" high="31" type="hex"/>
802 </reg32>
803 <doc>last 3 dwords only for opcode 4</doc>
804 <reg64 offset="6" name="INDIRECT" type="address"/>
805 <reg32 offset="8" name="8">
806 <bitfield name="STRIDE" low="0" high="31" type="hex"/>
807 </reg32>
808 </domain>
809
810 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
811 <array offset="0" name="" stride="3" length="100">
812 <reg32 offset="0" name="0">
813 <bitfield name="COUNT" low="0" high="15" type="uint"/>
814 <bitfield name="DIRTY" pos="16" type="boolean"/>
815 <bitfield name="DISABLE" pos="17" type="boolean"/>
816 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
817 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
818 <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
819 <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
820 <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
821 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
822 </reg32>
823 <reg32 offset="1" name="1">
824 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
825 </reg32>
826 <reg32 offset="2" name="2" variants="A5XX-">
827 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
828 </reg32>
829 </array>
830 </domain>
831
832 <domain name="CP_SET_BIN" width="32">
833 <doc>value at offset 0 always seems to be 0x00000000..</doc>
834 <reg32 offset="0" name="0"/>
835 <reg32 offset="1" name="1">
836 <bitfield name="X1" low="0" high="15" type="uint"/>
837 <bitfield name="Y1" low="16" high="31" type="uint"/>
838 </reg32>
839 <reg32 offset="2" name="2">
840 <bitfield name="X2" low="0" high="15" type="uint"/>
841 <bitfield name="Y2" low="16" high="31" type="uint"/>
842 </reg32>
843 </domain>
844
845 <domain name="CP_SET_BIN_DATA" width="32">
846 <reg32 offset="0" name="0">
847 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
848 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
849 </reg32>
850 <reg32 offset="1" name="1">
851 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
852 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
853 </reg32>
854 </domain>
855
856 <domain name="CP_SET_BIN_DATA5" width="32">
857 <reg32 offset="0" name="0">
858 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
859 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
860 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
861 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
862 </reg32>
863 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
864 <reg32 offset="1" name="1">
865 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
866 </reg32>
867 <reg32 offset="2" name="2">
868 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
869 </reg32>
870 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
871 <reg32 offset="3" name="3">
872 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
873 </reg32>
874 <reg32 offset="4" name="4">
875 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
876 </reg32>
877 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
878 <reg32 offset="5" name="5">
879 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
880 </reg32>
881 <reg32 offset="6" name="6">
882 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
883 </reg32>
884 </domain>
885
886 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
887 <doc>
888 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
889 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
890 for Vulkan where these values aren't known when the command
891 stream is recorded.
892 </doc>
893 <reg32 offset="0" name="0">
894 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
895 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
896 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
897 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
898 </reg32>
899 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
900 <reg32 offset="1" name="1">
901 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
902 </reg32>
903 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
904 <reg32 offset="2" name="2">
905 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
906 </reg32>
907 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
908 <reg32 offset="3" name="3">
909 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
910 </reg32>
911 </domain>
912
913 <domain name="CP_REG_RMW" width="32">
914 <doc>
915 Modifies DST_REG using two sources that can either be registers
916 or immediates. If SRC1_ADD is set, then do the following:
917
918 $dst = (($dst &amp; $src0) rot $rotate) + $src1
919
920 Otherwise:
921
922 $dst = (($dst &amp; $src0) rot $rotate) | $src1
923
924 Here "rot" means rotate left.
925 </doc>
926 <reg32 offset="0" name="0">
927 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
928 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
929 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
930 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
931 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
932 </reg32>
933 <reg32 offset="1" name="1">
934 <bitfield name="SRC0" low="0" high="31" type="uint"/>
935 </reg32>
936 <reg32 offset="2" name="2">
937 <bitfield name="SRC1" low="0" high="31" type="uint"/>
938 </reg32>
939 </domain>
940
941 <domain name="CP_REG_TO_MEM" width="32">
942 <reg32 offset="0" name="0">
943 <bitfield name="REG" low="0" high="15" type="hex"/>
944 <!-- number of registers/dwords copied is max(CNT, 1). -->
945 <bitfield name="CNT" low="18" high="29" type="uint"/>
946 <bitfield name="64B" pos="30" type="boolean"/>
947 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
948 </reg32>
949 <reg32 offset="1" name="1">
950 <bitfield name="DEST" low="0" high="31"/>
951 </reg32>
952 <reg32 offset="2" name="2" variants="A5XX-">
953 <bitfield name="DEST_HI" low="0" high="31"/>
954 </reg32>
955 </domain>
956
957 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
958 <doc>
959 Like CP_REG_TO_MEM, but the memory address to write to can be
960 offsetted using either one or two registers or scratch
961 registers.
962 </doc>
963 <reg32 offset="0" name="0">
964 <bitfield name="REG" low="0" high="15" type="hex"/>
965 <!-- number of registers/dwords copied is max(CNT, 1). -->
966 <bitfield name="CNT" low="18" high="29" type="uint"/>
967 <bitfield name="64B" pos="30" type="boolean"/>
968 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
969 </reg32>
970 <reg32 offset="1" name="1">
971 <bitfield name="DEST" low="0" high="31"/>
972 </reg32>
973 <reg32 offset="2" name="2" variants="A5XX-">
974 <bitfield name="DEST_HI" low="0" high="31"/>
975 </reg32>
976 <reg32 offset="3" name="3">
977 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
978 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
979 </reg32>
980 <!-- followed by an optional identical OFFSET1 dword -->
981 </domain>
982
983 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
984 <doc>
985 Like CP_REG_TO_MEM, but the memory address to write to can be
986 offsetted using a DWORD in memory.
987 </doc>
988 <reg32 offset="0" name="0">
989 <bitfield name="REG" low="0" high="15" type="hex"/>
990 <!-- number of registers/dwords copied is max(CNT, 1). -->
991 <bitfield name="CNT" low="18" high="29" type="uint"/>
992 <bitfield name="64B" pos="30" type="boolean"/>
993 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
994 </reg32>
995 <reg32 offset="1" name="1">
996 <bitfield name="DEST" low="0" high="31"/>
997 </reg32>
998 <reg32 offset="2" name="2" variants="A5XX-">
999 <bitfield name="DEST_HI" low="0" high="31"/>
1000 </reg32>
1001 <reg32 offset="3" name="3">
1002 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1003 </reg32>
1004 <reg32 offset="4" name="4">
1005 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1006 </reg32>
1007 </domain>
1008
1009 <domain name="CP_MEM_TO_REG" width="32">
1010 <reg32 offset="0" name="0">
1011 <bitfield name="REG" low="0" high="15" type="hex"/>
1012 <!-- number of registers/dwords copied is max(CNT, 1). -->
1013 <bitfield name="CNT" low="19" high="29" type="uint"/>
1014 <!-- shift each DWORD left by 2 while copying -->
1015 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1016 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1017 <bitfield name="UNK31" pos="31" type="boolean"/>
1018 </reg32>
1019 <reg32 offset="1" name="1">
1020 <bitfield name="SRC" low="0" high="31"/>
1021 </reg32>
1022 <reg32 offset="2" name="2" variants="A5XX-">
1023 <bitfield name="SRC_HI" low="0" high="31"/>
1024 </reg32>
1025 </domain>
1026
1027 <domain name="CP_MEM_TO_MEM" width="32">
1028 <reg32 offset="0" name="0">
1029 <!--
1030 not sure how many src operands we have, but the low
1031 bits negate the n'th src argument.
1032 -->
1033 <bitfield name="NEG_A" pos="0" type="boolean"/>
1034 <bitfield name="NEG_B" pos="1" type="boolean"/>
1035 <bitfield name="NEG_C" pos="2" type="boolean"/>
1036
1037 <!-- if set treat src/dst as 64bit values -->
1038 <bitfield name="DOUBLE" pos="29" type="boolean"/>
1039 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1040 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1041 <!-- some other kind of wait -->
1042 <bitfield name="UNK31" pos="31" type="boolean"/>
1043 </reg32>
1044 <!--
1045 followed by sequence of addresses.. the first is the
1046 destination and the rest are N src addresses which are
1047 summed (after being negated if NEG_x bit set) allowing
1048 to do things like 'result += end - start' (which turns
1049 out to be useful for queries and accumulating results
1050 across multiple tiles)
1051 -->
1052 </domain>
1053
1054 <domain name="CP_MEMCPY" width="32">
1055 <reg32 offset="0" name="0">
1056 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1057 </reg32>
1058 <reg32 offset="1" name="1">
1059 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1060 </reg32>
1061 <reg32 offset="2" name="2">
1062 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1063 </reg32>
1064 <reg32 offset="3" name="3">
1065 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1066 </reg32>
1067 <reg32 offset="4" name="4">
1068 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1069 </reg32>
1070 </domain>
1071
1072 <domain name="CP_REG_TO_SCRATCH" width="32">
1073 <reg32 offset="0" name="0">
1074 <bitfield name="REG" low="0" high="17" type="hex"/>
1075 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1076 <!-- number of registers/dwords copied is CNT + 1. -->
1077 <bitfield name="CNT" low="24" high="26" type="uint"/>
1078 </reg32>
1079 </domain>
1080
1081 <domain name="CP_SCRATCH_TO_REG" width="32">
1082 <reg32 offset="0" name="0">
1083 <bitfield name="REG" low="0" high="17" type="hex"/>
1084 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1085 <bitfield name="UNK18" pos="18" type="boolean"/>
1086 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1087 <!-- number of registers/dwords copied is CNT + 1. -->
1088 <bitfield name="CNT" low="24" high="26" type="uint"/>
1089 </reg32>
1090 </domain>
1091
1092 <domain name="CP_SCRATCH_WRITE" width="32">
1093 <reg32 offset="0" name="0">
1094 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1095 </reg32>
1096 <!-- followed by one or more DWORDs to write to scratch registers -->
1097 </domain>
1098
1099 <domain name="CP_MEM_WRITE" width="32">
1100 <reg32 offset="0" name="0">
1101 <bitfield name="ADDR_LO" low="0" high="31"/>
1102 </reg32>
1103 <reg32 offset="1" name="1">
1104 <bitfield name="ADDR_HI" low="0" high="31"/>
1105 </reg32>
1106 <!-- followed by the DWORDs to write -->
1107 </domain>
1108
1109 <enum name="cp_cond_function">
1110 <value value="0" name="WRITE_ALWAYS"/>
1111 <value value="1" name="WRITE_LT"/>
1112 <value value="2" name="WRITE_LE"/>
1113 <value value="3" name="WRITE_EQ"/>
1114 <value value="4" name="WRITE_NE"/>
1115 <value value="5" name="WRITE_GE"/>
1116 <value value="6" name="WRITE_GT"/>
1117 </enum>
1118
1119 <domain name="CP_COND_WRITE" width="32">
1120 <reg32 offset="0" name="0">
1121 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1122 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1123 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1124 </reg32>
1125 <reg32 offset="1" name="1">
1126 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1127 </reg32>
1128 <reg32 offset="2" name="2">
1129 <bitfield name="REF" low="0" high="31"/>
1130 </reg32>
1131 <reg32 offset="3" name="3">
1132 <bitfield name="MASK" low="0" high="31"/>
1133 </reg32>
1134 <reg32 offset="4" name="4">
1135 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1136 </reg32>
1137 <reg32 offset="5" name="5">
1138 <bitfield name="WRITE_DATA" low="0" high="31"/>
1139 </reg32>
1140 </domain>
1141
1142 <domain name="CP_COND_WRITE5" width="32">
1143 <reg32 offset="0" name="0">
1144 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1145 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1146 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1147 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1148 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1149 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1150 </reg32>
1151 <reg32 offset="1" name="1">
1152 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1153 </reg32>
1154 <reg32 offset="2" name="2">
1155 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1156 </reg32>
1157 <reg32 offset="3" name="3">
1158 <bitfield name="REF" low="0" high="31"/>
1159 </reg32>
1160 <reg32 offset="4" name="4">
1161 <bitfield name="MASK" low="0" high="31"/>
1162 </reg32>
1163 <reg32 offset="5" name="5">
1164 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1165 </reg32>
1166 <reg32 offset="6" name="6">
1167 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1168 </reg32>
1169 <reg32 offset="7" name="7">
1170 <bitfield name="WRITE_DATA" low="0" high="31"/>
1171 </reg32>
1172 </domain>
1173
1174 <domain name="CP_WAIT_MEM_GTE" width="32">
1175 <doc>
1176 Wait until a memory value is greater than or equal to the
1177 reference, using signed comparison.
1178 </doc>
1179 <reg32 offset="0" name="0">
1180 <!-- Reserved for flags, presumably? Unused in FW -->
1181 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1182 </reg32>
1183 <reg32 offset="1" name="1">
1184 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1185 </reg32>
1186 <reg32 offset="2" name="2">
1187 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1188 </reg32>
1189 <reg32 offset="3" name="3">
1190 <bitfield name="REF" low="0" high="31"/>
1191 </reg32>
1192 </domain>
1193
1194 <domain name="CP_WAIT_REG_MEM" width="32">
1195 <doc>
1196 This uses the same internal comparison as CP_COND_WRITE,
1197 but waits until the comparison is true instead. It busy-loops in
1198 the CP for the given number of cycles before trying again.
1199 </doc>
1200 <reg32 offset="0" name="0">
1201 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1202 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1203 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1204 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1205 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1206 </reg32>
1207 <reg32 offset="1" name="1">
1208 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1209 </reg32>
1210 <reg32 offset="2" name="2">
1211 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1212 </reg32>
1213 <reg32 offset="3" name="3">
1214 <bitfield name="REF" low="0" high="31"/>
1215 </reg32>
1216 <reg32 offset="4" name="4">
1217 <bitfield name="MASK" low="0" high="31"/>
1218 </reg32>
1219 <reg32 offset="5" name="5">
1220 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1221 </reg32>
1222 </domain>
1223
1224 <domain name="CP_WAIT_TWO_REGS" width="32">
1225 <doc>
1226 Waits for REG0 to not be 0 or REG1 to not equal REF
1227 </doc>
1228 <reg32 offset="0" name="0">
1229 <bitfield name="REG0" low="0" high="17" type="hex"/>
1230 </reg32>
1231 <reg32 offset="1" name="1">
1232 <bitfield name="REG1" low="0" high="17" type="hex"/>
1233 </reg32>
1234 <reg32 offset="2" name="2">
1235 <bitfield name="REF" low="0" high="31" type="uint"/>
1236 </reg32>
1237 </domain>
1238
1239 <domain name="CP_DISPATCH_COMPUTE" width="32">
1240 <reg32 offset="0" name="0"/>
1241 <reg32 offset="1" name="1">
1242 <bitfield name="X" low="0" high="31"/>
1243 </reg32>
1244 <reg32 offset="2" name="2">
1245 <bitfield name="Y" low="0" high="31"/>
1246 </reg32>
1247 <reg32 offset="3" name="3">
1248 <bitfield name="Z" low="0" high="31"/>
1249 </reg32>
1250 </domain>
1251
1252 <domain name="CP_SET_RENDER_MODE" width="32">
1253 <enum name="render_mode_cmd">
1254 <value value="1" name="BYPASS"/>
1255 <value value="2" name="BINNING"/>
1256 <value value="3" name="GMEM"/>
1257 <value value="5" name="BLIT2D"/>
1258 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1259 <value value="7" name="BLIT2DSCALE"/>
1260 <!-- 8 set before going back to BYPASS exiting 2D -->
1261 <value value="8" name="END2D"/>
1262 </enum>
1263 <reg32 offset="0" name="0">
1264 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1265 <!--
1266 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1267 0x21xx range.. possibly (at least some) a5xx variants have a
1268 2d core?
1269 -->
1270 </reg32>
1271 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1272 <reg32 offset="1" name="1">
1273 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1274 </reg32>
1275 <reg32 offset="2" name="2">
1276 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1277 </reg32>
1278 <reg32 offset="3" name="3">
1279 <!--
1280 set when in GMEM.. maybe indicates GMEM contents need to be
1281 preserved on ctx switch?
1282 -->
1283 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1284 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1285 </reg32>
1286 <reg32 offset="4" name="4"/>
1287 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1288 <reg32 offset="5" name="5">
1289 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1290 </reg32>
1291 <reg32 offset="6" name="6">
1292 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1293 </reg32>
1294 <reg32 offset="7" name="7">
1295 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1296 </reg32>
1297 </domain>
1298
1299 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1300 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1301 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1302 <reg32 offset="0" name="0">
1303 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1304 </reg32>
1305 <reg32 offset="1" name="1">
1306 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1307 </reg32>
1308 <reg32 offset="2" name="2">
1309 </reg32>
1310 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1311 <reg32 offset="3" name="3">
1312 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1313 </reg32>
1314 <reg32 offset="4" name="4"/>
1315 <reg32 offset="5" name="5">
1316 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1317 </reg32>
1318 <reg32 offset="6" name="6">
1319 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1320 </reg32>
1321 <reg32 offset="7" name="7"/>
1322 </domain>
1323
1324 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1325 <reg32 offset="0" name="0">
1326 </reg32>
1327 <reg32 offset="1" name="1">
1328 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1329 </reg32>
1330 <reg32 offset="2" name="2">
1331 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1332 </reg32>
1333 </domain>
1334
1335 <domain name="CP_EVENT_WRITE" width="32">
1336 <reg32 offset="0" name="0">
1337 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1338 <!-- when set, write back timestamp instead of value from packet: -->
1339 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1340 </reg32>
1341 <!--
1342 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1343 context switch?
1344 -->
1345 <reg32 offset="1" name="1">
1346 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1347 </reg32>
1348 <reg32 offset="2" name="2">
1349 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1350 </reg32>
1351 <reg32 offset="3" name="3">
1352 <!-- ??? -->
1353 </reg32>
1354 </domain>
1355
1356 <domain name="CP_BLIT" width="32">
1357 <enum name="cp_blit_cmd">
1358 <value value="0" name="BLIT_OP_FILL"/>
1359 <value value="1" name="BLIT_OP_COPY"/>
1360 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1361 </enum>
1362 <reg32 offset="0" name="0">
1363 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1364 </reg32>
1365 <reg32 offset="1" name="1">
1366 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1367 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1368 </reg32>
1369 <reg32 offset="2" name="2">
1370 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1371 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1372 </reg32>
1373 <reg32 offset="3" name="3">
1374 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1375 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1376 </reg32>
1377 <reg32 offset="4" name="4">
1378 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1379 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1380 </reg32>
1381 </domain>
1382
1383 <domain name="CP_EXEC_CS" width="32">
1384 <reg32 offset="0" name="0">
1385 </reg32>
1386 <reg32 offset="1" name="1">
1387 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1388 </reg32>
1389 <reg32 offset="2" name="2">
1390 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1391 </reg32>
1392 <reg32 offset="3" name="3">
1393 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1394 </reg32>
1395 </domain>
1396
1397 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1398 <reg32 offset="0" name="0">
1399 </reg32>
1400 <stripe variants="A4XX">
1401 <reg32 offset="1" name="1">
1402 <bitfield name="ADDR" low="0" high="31"/>
1403 </reg32>
1404 <reg32 offset="2" name="2">
1405 <!-- localsize is value minus one: -->
1406 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1407 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1408 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1409 </reg32>
1410 </stripe>
1411 <stripe variants="A5XX-">
1412 <reg32 offset="1" name="1">
1413 <bitfield name="ADDR_LO" low="0" high="31"/>
1414 </reg32>
1415 <reg32 offset="2" name="2">
1416 <bitfield name="ADDR_HI" low="0" high="31"/>
1417 </reg32>
1418 <reg32 offset="3" name="3">
1419 <!-- localsize is value minus one: -->
1420 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1421 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1422 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1423 </reg32>
1424 </stripe>
1425 </domain>
1426
1427 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1428 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1429 <enum name="a6xx_render_mode">
1430 <value value="1" name="RM6_BYPASS"/>
1431 <value value="2" name="RM6_BINNING"/>
1432 <value value="4" name="RM6_GMEM"/>
1433 <value value="5" name="RM6_ENDVIS"/>
1434 <value value="6" name="RM6_RESOLVE"/>
1435 <value value="7" name="RM6_YIELD"/>
1436 <value value="8" name="RM6_COMPUTE"/>
1437 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1438
1439 <!--
1440 These values come from a6xx_set_marker() in the
1441 downstream kernel, and they can only be set by the kernel
1442 -->
1443 <value value="0xd" name="RM6_IB1LIST_START"/>
1444 <value value="0xe" name="RM6_IB1LIST_END"/>
1445 <!-- IFPC - inter-frame power collapse -->
1446 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1447 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1448 </enum>
1449 <reg32 offset="0" name="0">
1450 <!--
1451 NOTE: blob driver and some versions of freedreno/turnip set
1452 b4, which is unused (at least by current sqe fw), but interferes
1453 with parsing if we extend the size of the bitfield to include
1454 b8 (only sent by kernel mode driver). Really, the way the
1455 parsing works in the firmware, only b0-b3 are considered, but
1456 if b8 is set, the low bits are interpreted differently. To
1457 model this, without getting confused by spurious b4, this is
1458 described as two overlapping bitfields:
1459 -->
1460 <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1461 <bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
1462 </reg32>
1463 </domain>
1464
1465 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1466 <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1467 <enum name="pseudo_reg">
1468 <value value="0" name="SMMU_INFO"/>
1469 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1470 <value value="2" name="SECURE_SAVE_ADDR"/>
1471 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1472 <value value="4" name="COUNTER"/>
1473 </enum>
1474 <array offset="0" name="" stride="3" length="100">
1475 <reg32 offset="0" name="0">
1476 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1477 </reg32>
1478 <reg32 offset="1" name="1">
1479 <bitfield name="LO" low="0" high="31"/>
1480 </reg32>
1481 <reg32 offset="2" name="2">
1482 <bitfield name="HI" low="0" high="31"/>
1483 </reg32>
1484 </array>
1485 </domain>
1486
1487 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1488 <doc>
1489 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1490 So:
1491
1492 opcode: CP_REG_TEST (39) (2 dwords)
1493 { REG = 0xc10 | BIT = 0 }
1494 0000: 70b90001 00000c10
1495 opcode: CP_COND_REG_EXEC (47) (3 dwords)
1496 0000: 70c70002 10000000 00000004
1497 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1498
1499 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1500 offset 0x0c10 is 1
1501 </doc>
1502 <reg32 offset="0" name="0">
1503 <!-- the register to test -->
1504 <bitfield name="REG" low="0" high="11"/>
1505 <!-- the bit to test -->
1506 <bitfield name="BIT" low="20" high="24" type="uint"/>
1507 <!-- execute CP_WAIT_FOR_ME beforehand -->
1508 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1509 </reg32>
1510 </domain>
1511
1512 <!-- I *think* this existed at least as far back as a4xx -->
1513 <domain name="CP_COND_REG_EXEC" width="32">
1514 <enum name="compare_mode">
1515 <!-- use the predicate bit set by CP_REG_TEST -->
1516 <value value="1" name="PRED_TEST"/>
1517 <!-- compare two registers directly for equality -->
1518 <value value="2" name="REG_COMPARE"/>
1519 <!-- test if certain render modes are set via CP_SET_MARKER -->
1520 <value value="3" name="RENDER_MODE" variants="A6XX-"/>
1521 </enum>
1522 <reg32 offset="0" name="0">
1523 <bitfield name="REG0" low="0" high="17" type="hex"/>
1524
1525 <!--
1526 Note: these bits have the same meaning, and use the same
1527 internal mechanism as the bits in CP_SET_DRAW_STATE.
1528 When RENDER_MODE is selected, they're used as
1529 a bitmask of which modes pass the test.
1530 -->
1531
1532 <!-- RM6_BINNING -->
1533 <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
1534 <!-- all others -->
1535 <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
1536 <!-- RM6_BYPASS -->
1537 <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
1538
1539 <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1540 </reg32>
1541
1542 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1543
1544 <reg32 offset="1" name="1">
1545 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1546 </reg32>
1547 </domain>
1548
1549 <domain name="CP_COND_EXEC" width="32">
1550 <doc>
1551 Executes the following DWORDs of commands if the dword at ADDR0
1552 is not equal to 0 and the dword at ADDR1 is less than REF
1553 (signed comparison).
1554 </doc>
1555 <reg32 offset="0" name="0">
1556 <bitfield name="ADDR0_LO" low="0" high="31"/>
1557 </reg32>
1558 <reg32 offset="1" name="1">
1559 <bitfield name="ADDR0_HI" low="0" high="31"/>
1560 </reg32>
1561 <reg32 offset="2" name="2">
1562 <bitfield name="ADDR1_LO" low="0" high="31"/>
1563 </reg32>
1564 <reg32 offset="3" name="3">
1565 <bitfield name="ADDR1_HI" low="0" high="31"/>
1566 </reg32>
1567 <reg32 offset="4" name="4">
1568 <bitfield name="REF" low="0" high="31"/>
1569 </reg32>
1570 <reg32 offset="5" name="5">
1571 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1572 </reg32>
1573 </domain>
1574
1575 <domain name="CP_SET_CTXSWITCH_IB" width="32">
1576 <doc>
1577 Used by the userspace driver to set various IB's which are
1578 executed during context save/restore for handling
1579 state that isn't restored by the
1580 context switch routine itself.
1581 </doc>
1582 <enum name="ctxswitch_ib">
1583 <value name="RESTORE_IB" value="0">
1584 <doc>Executed unconditionally when switching back to the context.</doc>
1585 </value>
1586 <value name="YIELD_RESTORE_IB" value="1">
1587 <doc>
1588 Executed when switching back after switching
1589 away during execution of
1590 a CP_SET_MARKER packet with RM6_YIELD as the
1591 payload *and* the normal save routine was
1592 bypassed for a shorter one. I think this is
1593 connected to the "skipsaverestore" bit set by
1594 the kernel when preempting.
1595 </doc>
1596 </value>
1597 <value name="SAVE_IB" value="2">
1598 <doc>
1599 Executed when switching away from the context,
1600 except for context switches initiated via
1601 CP_YIELD.
1602 </doc>
1603 </value>
1604 <value name="RB_SAVE_IB" value="3">
1605 <doc>
1606 This can only be set by the RB (i.e. the kernel)
1607 and executes with protected mode off, but
1608 is otherwise similar to SAVE_IB.
1609 </doc>
1610 </value>
1611 </enum>
1612 <reg32 offset="0" name="0">
1613 <bitfield name="ADDR_LO" low="0" high="31"/>
1614 </reg32>
1615 <reg32 offset="1" name="1">
1616 <bitfield name="ADDR_HI" low="0" high="31"/>
1617 </reg32>
1618 <reg32 offset="2" name="2">
1619 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
1620 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1621 </reg32>
1622 </domain>
1623
1624 <domain name="CP_REG_WRITE" width="32">
1625 <enum name="reg_tracker">
1626 <doc>
1627 Keep shadow copies of these registers and only set them
1628 when drawing, avoiding redundant writes:
1629 - VPC_CNTL_0
1630 - HLSQ_CONTROL_1_REG
1631 - HLSQ_UNKNOWN_B980
1632 </doc>
1633 <value name="TRACK_CNTL_REG" value="0x1"/>
1634 <doc>
1635 Track RB_RENDER_CNTL, and insert a WFI in the following
1636 situation:
1637 - There is a write that disables binning
1638 - There was a draw with binning left enabled, but in
1639 BYPASS mode
1640 Presumably this is a hang workaround?
1641 </doc>
1642 <value name="TRACK_RENDER_CNTL" value="0x2"/>
1643 <doc>
1644 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
1645 the data to write is 0. Used by the Vulkan blob with
1646 PC_UNKNOWN_9B07, but this isn't predicated on particular
1647 register(s) like the others.
1648 </doc>
1649 <value name="UNK_EVENT_WRITE" value="0x4"/>
1650 </enum>
1651 <reg32 offset="0" name="0">
1652 <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
1653 </reg32>
1654 </domain>
1655
1656 </database>
1657