src/freedreno/registers/adreno_pm4.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="vgt_event_type">
   7         <value name="VS_DEALLOC" value="0"/>
   8         <value name="PS_DEALLOC" value="1"/>
   9         <value name="VS_DONE_TS" value="2"/>
  10         <value name="PS_DONE_TS" value="3"/>
  11         <value name="CACHE_FLUSH_TS" value="4"/>
  12         <value name="CONTEXT_DONE" value="5"/>
  13         <value name="CACHE_FLUSH" value="6"/>
  14         <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
  15         <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
  16         <value name="VIZQUERY_END" value="8"/>
  17         <value name="SC_WAIT_WC" value="9"/>
  18         <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
  19         <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
  20         <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
  21         <value name="RST_PIX_CNT" value="13"/>
  22         <value name="RST_VTX_CNT" value="14"/>
  23         <value name="TILE_FLUSH" value="15"/>
  24         <value name="STAT_EVENT" value="16"/>
  25         <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
  26         <value name="ZPASS_DONE" value="21"/>
  27         <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
  28         <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
  29         <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
  30         <value name="VS_FETCH_DONE" value="27"/>
  31         <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
  32
  33         <!-- a5xx events -->
  34         <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
  35         <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
  36         <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
  37         <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
  38         <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
  39         <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
  40         <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
  41         <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX,A6XX"/>
  42         <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX,A6XX"/>
  43         <value name="BLIT" value="30" variants="A5XX,A6XX"/>
  44         <value name="UNK_25" value="37" variants="A5XX"/>
  45         <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
  46         <value name="UNK_2C" value="44" variants="A5XX"/>
  47         <value name="UNK_2D" value="45" variants="A5XX"/>
  48
  49         <!-- a6xx events -->
  50         <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
  51 </enum>
  52
  53 <enum name="pc_di_primtype">
  54         <value name="DI_PT_NONE" value="0"/>
  55         <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
  56         <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
  57         <value name="DI_PT_LINELIST" value="2"/>
  58         <value name="DI_PT_LINESTRIP" value="3"/>
  59         <value name="DI_PT_TRILIST" value="4"/>
  60         <value name="DI_PT_TRIFAN" value="5"/>
  61         <value name="DI_PT_TRISTRIP" value="6"/>
  62         <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
  63         <value name="DI_PT_RECTLIST" value="8"/>
  64         <value name="DI_PT_POINTLIST" value="9"/>
  65         <value name="DI_PT_LINE_ADJ" value="0xa"/>
  66         <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
  67         <value name="DI_PT_TRI_ADJ" value="0xc"/>
  68         <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
  69
  70         <value name="DI_PT_PATCHES0" value="0x1f"/>
  71         <value name="DI_PT_PATCHES1" value="0x20"/>
  72         <value name="DI_PT_PATCHES2" value="0x21"/>
  73         <value name="DI_PT_PATCHES3" value="0x22"/>
  74         <value name="DI_PT_PATCHES4" value="0x23"/>
  75         <value name="DI_PT_PATCHES5" value="0x24"/>
  76         <value name="DI_PT_PATCHES6" value="0x25"/>
  77         <value name="DI_PT_PATCHES7" value="0x26"/>
  78         <value name="DI_PT_PATCHES8" value="0x27"/>
  79         <value name="DI_PT_PATCHES9" value="0x28"/>
  80         <value name="DI_PT_PATCHES10" value="0x29"/>
  81         <value name="DI_PT_PATCHES11" value="0x2a"/>
  82         <value name="DI_PT_PATCHES12" value="0x2b"/>
  83         <value name="DI_PT_PATCHES13" value="0x2c"/>
  84         <value name="DI_PT_PATCHES14" value="0x2d"/>
  85         <value name="DI_PT_PATCHES15" value="0x2e"/>
  86         <value name="DI_PT_PATCHES16" value="0x2f"/>
  87         <value name="DI_PT_PATCHES17" value="0x30"/>
  88         <value name="DI_PT_PATCHES18" value="0x31"/>
  89         <value name="DI_PT_PATCHES19" value="0x32"/>
  90         <value name="DI_PT_PATCHES20" value="0x33"/>
  91         <value name="DI_PT_PATCHES21" value="0x34"/>
  92         <value name="DI_PT_PATCHES22" value="0x35"/>
  93         <value name="DI_PT_PATCHES23" value="0x36"/>
  94         <value name="DI_PT_PATCHES24" value="0x37"/>
  95         <value name="DI_PT_PATCHES25" value="0x38"/>
  96         <value name="DI_PT_PATCHES26" value="0x39"/>
  97         <value name="DI_PT_PATCHES27" value="0x3a"/>
  98         <value name="DI_PT_PATCHES28" value="0x3b"/>
  99         <value name="DI_PT_PATCHES29" value="0x3c"/>
 100         <value name="DI_PT_PATCHES30" value="0x3d"/>
 101         <value name="DI_PT_PATCHES31" value="0x3e"/>
 102 </enum>
 103
 104 <enum name="pc_di_src_sel">
 105         <value name="DI_SRC_SEL_DMA" value="0"/>
 106         <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
 107         <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
 108         <value name="DI_SRC_SEL_RESERVED" value="3"/>
 109 </enum>
 110
 111 <enum name="pc_di_face_cull_sel">
 112         <value name="DI_FACE_CULL_NONE" value="0"/>
 113         <value name="DI_FACE_CULL_FETCH" value="1"/>
 114         <value name="DI_FACE_BACKFACE_CULL" value="2"/>
 115         <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
 116 </enum>
 117
 118 <enum name="pc_di_index_size">
 119         <value name="INDEX_SIZE_IGN" value="0"/>
 120         <value name="INDEX_SIZE_16_BIT" value="0"/>
 121         <value name="INDEX_SIZE_32_BIT" value="1"/>
 122         <value name="INDEX_SIZE_8_BIT" value="2"/>
 123         <value name="INDEX_SIZE_INVALID"/>
 124 </enum>
 125
 126 <enum name="pc_di_vis_cull_mode">
 127         <value name="IGNORE_VISIBILITY" value="0"/>
 128         <value name="USE_VISIBILITY" value="1"/>
 129 </enum>
 130
 131 <enum name="adreno_pm4_packet_type">
 132         <value name="CP_TYPE0_PKT" value="0x00000000"/>
 133         <value name="CP_TYPE1_PKT" value="0x40000000"/>
 134         <value name="CP_TYPE2_PKT" value="0x80000000"/>
 135         <value name="CP_TYPE3_PKT" value="0xc0000000"/>
 136         <value name="CP_TYPE4_PKT" value="0x40000000"/>
 137         <value name="CP_TYPE7_PKT" value="0x70000000"/>
 138 </enum>
 139
 140 <!--
 141    Note that in some cases, the same packet id is recycled on a later
 142    generation, so variants attribute is used to distinguish.   They
 143    may not be completely accurate, we would probably have to analyze
 144    the pfp and me/pm4 firmware to verify the packet is actually
 145    handled on a particular generation.  But it is at least enough to
 146    disambiguate the packet-id's that were re-used for different
 147    packets starting with a5xx.
 148  -->
 149 <enum name="adreno_pm4_type3_packets">
 150         <doc>initialize CP's micro-engine</doc>
 151         <value name="CP_ME_INIT" value="0x48"/>
 152         <doc>skip N 32-bit words to get to the next packet</doc>
 153         <value name="CP_NOP" value="0x10"/>
 154         <doc>
 155                 indirect buffer dispatch.  prefetch parser uses this packet
 156                 type to determine whether to pre-fetch the IB
 157         </doc>
 158         <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 159         <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 160         <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
 161         <doc>
 162                 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
 163                 another buffer at the same level. Must be at the end of IB, and
 164                 doesn't work with draw state IB's.
 165         </doc>
 166         <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
 167         <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 168         <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 169         <doc>wait for the IDLE state of the engine</doc>
 170         <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
 171         <doc>wait until a register or memory location is a specific value</doc>
 172         <value name="CP_WAIT_REG_MEM" value="0x3c"/>
 173         <doc>wait until a register location is equal to a specific value</doc>
 174         <value name="CP_WAIT_REG_EQ" value="0x52"/>
 175         <doc>wait until a register location is >= a specific value</doc>
 176         <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
 177         <doc>wait until a read completes</doc>
 178         <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
 179         <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
 180         <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
 181         <doc>register read/modify/write</doc>
 182         <value name="CP_REG_RMW" value="0x21"/>
 183         <doc>Set binning configuration registers</doc>
 184         <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
 185         <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
 186         <doc>reads register in chip and writes to memory</doc>
 187         <value name="CP_REG_TO_MEM" value="0x3e"/>
 188         <doc>write N 32-bit words to memory</doc>
 189         <value name="CP_MEM_WRITE" value="0x3d"/>
 190         <doc>write CP_PROG_COUNTER value to memory</doc>
 191         <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
 192         <doc>conditional execution of a sequence of packets</doc>
 193         <value name="CP_COND_EXEC" value="0x44"/>
 194         <doc>conditional write to memory or register</doc>
 195         <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
 196         <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
 197         <doc>generate an event that creates a write to memory when completed</doc>
 198         <value name="CP_EVENT_WRITE" value="0x46"/>
 199         <doc>generate a VS|PS_done event</doc>
 200         <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
 201         <doc>generate a cache flush done event</doc>
 202         <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
 203         <doc>generate a z_pass done event</doc>
 204         <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
 205         <doc>
 206                 not sure the real name, but this seems to be what is used for
 207                 opencl, instead of CP_DRAW_INDX..
 208         </doc>
 209         <value name="CP_RUN_OPENCL" value="0x31"/>
 210         <doc>initiate fetch of index buffer and draw</doc>
 211         <value name="CP_DRAW_INDX" value="0x22"/>
 212         <doc>draw using supplied indices in packet</doc>
 213         <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
 214         <doc>initiate fetch of index buffer and binIDs and draw</doc>
 215         <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
 216         <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
 217         <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
 218         <doc>begin/end initiator for viz query extent processing</doc>
 219         <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
 220         <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
 221         <value name="CP_SET_STATE" value="0x25"/>
 222         <doc>load constant into chip and to memory</doc>
 223         <value name="CP_SET_CONSTANT" value="0x2d"/>
 224         <doc>load sequencer instruction memory (pointer-based)</doc>
 225         <value name="CP_IM_LOAD" value="0x27"/>
 226         <doc>load sequencer instruction memory (code embedded in packet)</doc>
 227         <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 228         <doc>load constants from a location in memory</doc>
 229         <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
 230         <doc>selective invalidation of state pointers</doc>
 231         <value name="CP_INVALIDATE_STATE" value="0x3b"/>
 232         <doc>dynamically changes shader instruction memory partition</doc>
 233         <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
 234         <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
 235         <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
 236         <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
 237         <value name="CP_SET_BIN_SELECT" value="0x51"/>
 238         <doc>updates the current context, if needed</doc>
 239         <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
 240         <doc>generate interrupt from the command stream</doc>
 241         <value name="CP_INTERRUPT" value="0x40"/>
 242         <doc>copy sequencer instruction memory to system memory</doc>
 243         <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
 244
 245         <!-- For a20x -->
 246 <!-- TODO handle variants..
 247         <doc>
 248                 Program an offset that will added to the BIN_BASE value of
 249                 the 3D_DRAW_INDX_BIN packet
 250         </doc>
 251         <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
 252  -->
 253
 254         <!-- for a22x -->
 255         <doc>
 256                 sets draw initiator flags register in PFP, gets bitwise-ORed into
 257                 every draw initiator
 258         </doc>
 259         <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
 260         <doc>sets the register protection mode</doc>
 261         <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
 262
 263         <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
 264
 265         <!-- for a3xx -->
 266         <doc>load high level sequencer command</doc>
 267         <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
 268         <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
 269         <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
 270         <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
 271         <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
 272         <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
 273         <doc>Load a buffer with pre-fetch enabled</doc>
 274         <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 275         <doc>Set bin (?)</doc>
 276         <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
 277
 278         <doc>test 2 memory locations to dword values specified</doc>
 279         <value name="CP_TEST_TWO_MEMS" value="0x71"/>
 280
 281         <doc>Write register, ignoring context state for context sensitive registers</doc>
 282         <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
 283
 284         <doc>Record the real-time when this packet is processed by PFP</doc>
 285         <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
 286
 287         <!-- Used to switch GPU between secure and non-secure modes -->
 288         <value name="CP_SET_SECURE_MODE" value="0x66"/>
 289
 290         <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
 291         <value name="CP_WAIT_FOR_ME" value="0x13"/>
 292
 293         <!-- for a4xx -->
 294         <doc>
 295                 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
 296                 groups of registers.  Looks like it can be used to create state
 297                 objects in GPU memory, and on state change only emit pointer
 298                 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
 299                 overhead:
 300
 301                 (A4x) save PM4 stream pointers to execute upon a visible draw
 302         </doc>
 303         <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
 304         <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
 305         <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
 306         <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
 307         <value name="CP_DRAW_AUTO" value="0x24"/>
 308
 309         <value name="CP_UNKNOWN_19" value="0x19"/>
 310
 311         <doc>set to 1 for fastclear..:</doc>
 312         <value name="CP_UNKNOWN_1A" value="0x1a"/>
 313
 314         <value name="CP_UNKNOWN_4E" value="0x4e"/>
 315
 316         <doc>
 317                 for A4xx
 318                 Write to register with address that does not fit into type-0 pkt
 319         </doc>
 320         <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
 321
 322         <doc>copy from ME scratch RAM to a register</doc>
 323         <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
 324
 325         <doc>Copy from REG to ME scratch RAM</doc>
 326         <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
 327
 328         <doc>Wait for memory writes to complete</doc>
 329         <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
 330
 331         <doc>Conditional execution based on register comparison</doc>
 332         <value name="CP_COND_REG_EXEC" value="0x47"/>
 333
 334         <doc>Memory to REG copy</doc>
 335         <value name="CP_MEM_TO_REG" value="0x42"/>
 336
 337         <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
 338         <value name="CP_EXEC_CS" value="0x33"/>
 339
 340         <doc>
 341                 for a5xx
 342         </doc>
 343         <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 344         <!-- switches SMMU pagetable, used on a5xx only -->
 345         <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
 346         <!-- for a6xx -->
 347         <doc>Tells CP the current mode of GPU operation</doc>
 348         <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
 349         <doc>Instruct CP to set a few internal CP registers</doc>
 350         <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 351         <!--
 352         pairs of regid and value.. seems to be used to program some TF
 353         related regs:
 354          -->
 355         <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
 356         <!-- A5XX Enable yield in RB only -->
 357         <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
 358         <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
 359         <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
 360         <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
 361         <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
 362         <!-- Enable/Disable/Defer A5x global preemption model -->
 363         <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
 364         <!-- Enable/Disable A5x local preemption model -->
 365         <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
 366         <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
 367         <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
 368         <!-- Inform CP about current render mode (needed for a5xx preemption) -->
 369         <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
 370         <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
 371         <!-- check if this works on earlier.. -->
 372         <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
 373         <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
 374
 375         <!-- Test specified bit in specified register and set predicate -->
 376         <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
 377
 378         <!--
 379         Seems to set the mode flags which control which CP_SET_DRAW_STATE
 380         packets are executed, based on their ENABLE_MASK values
 381
 382         CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
 383         packets w/ ENABLE_MASK & 0x6 to execute immediately
 384          -->
 385         <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
 386
 387         <!--
 388         Seems like there are now separate blocks of state for VS vs FS/CS
 389         (probably these amounts to geometry vs fragments so that geometry
 390         stage of the pipeline for next draw can start while fragment stage
 391         of current draw is still running.  The format of the payload of the
 392         packets is the same, the only difference is the offsets of the regs
 393         the firmware code that handles the packet writes.
 394
 395         Note that for CL, starting with a6xx, the preferred # of local
 396         threads is no longer the same as the max, implying that the shader
 397         core can now run warps from unrelated shaders (ie.
 398         CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
 399         CL_KERNEL_WORK_GROUP_SIZE)
 400          -->
 401         <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
 402         <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
 403         <!--
 404         Note: For IBO state (Image/SSBOs) which have shared state across
 405         shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
 406         compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
 407         interchangable.
 408          -->
 409         <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
 410
 411         <!-- internal packets: -->
 412         <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
 413         <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
 414         <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
 415         <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
 416         <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
 417         <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
 418         <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
 419         <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
 420
 421         <!-- jmptable entry used to handle type4 packet on a5xx+: -->
 422         <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
 423
 424         <!-- TODO do these exist on A5xx? -->
 425         <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
 426         <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
 427         <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
 428         <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
 429         <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
 430         <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
 431         <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
 432         <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
 433
 434         <!--
 435         Seems to always have the payload:
 436           00000002 00008801 00004010
 437         or:
 438           00000002 00008801 00004090
 439         or:
 440           00000002 00008801 00000010
 441           00000002 00008801 00010010
 442           00000002 00008801 00d64010
 443           ...
 444         Note set for compute shaders..
 445         Is 0x8801 a register offset?
 446         This appears to be a special sort of register write packet
 447         more or less, but the firmware has some special handling..
 448         Seems like it intercepts/modifies certain register offsets,
 449         but others are treated like a normal PKT4 reg write.  I
 450         guess there are some registers that the fw controls certain
 451         bits.
 452          -->
 453         <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
 454
 455 </enum>
 456
 457
 458 <domain name="CP_LOAD_STATE" width="32">
 459         <doc>Load state, a3xx (and later?)</doc>
 460         <enum name="adreno_state_block">
 461                 <value name="SB_VERT_TEX" value="0"/>
 462                 <value name="SB_VERT_MIPADDR" value="1"/>
 463                 <value name="SB_FRAG_TEX" value="2"/>
 464                 <value name="SB_FRAG_MIPADDR" value="3"/>
 465                 <value name="SB_VERT_SHADER" value="4"/>
 466                 <value name="SB_GEOM_SHADER" value="5"/>
 467                 <value name="SB_FRAG_SHADER" value="6"/>
 468                 <value name="SB_COMPUTE_SHADER" value="7"/>
 469         </enum>
 470         <enum name="adreno_state_type">
 471                 <value name="ST_SHADER" value="0"/>
 472                 <value name="ST_CONSTANTS" value="1"/>
 473         </enum>
 474         <enum name="adreno_state_src">
 475                 <value name="SS_DIRECT" value="0">
 476                         <doc>inline with the CP_LOAD_STATE packet</doc>
 477                 </value>
 478                 <value name="SS_INVALID_ALL_IC" value="2"/>
 479                 <value name="SS_INVALID_PART_IC" value="3"/>
 480                 <value name="SS_INDIRECT" value="4">
 481                         <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
 482                 </value>
 483                 <value name="SS_INDIRECT_TCM" value="5"/>
 484                 <value name="SS_INDIRECT_STM" value="6"/>
 485         </enum>
 486         <reg32 offset="0" name="0">
 487                 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
 488                 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
 489                 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
 490                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 491         </reg32>
 492         <reg32 offset="1" name="1">
 493                 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
 494                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 495         </reg32>
 496 </domain>
 497
 498 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
 499         <doc>Load state, a4xx+</doc>
 500         <enum name="a4xx_state_block">
 501                 <!--
 502                 unknown: 0x7 and 0xf <- seen in compute shader
 503
 504                 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
 505                 Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
 506                 the gpuaddr of the following shader constants block.  DST_OFF seems
 507                 to specify which shader stage:
 508
 509                     16 -> vert
 510                     36 -> tcs
 511                     56 -> tes
 512                     76 -> geom
 513                     96 -> frag
 514
 515                 Example:
 516
 517 opcode: CP_LOAD_STATE4 (30) (12 dwords)
 518         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
 519         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
 520         { EXT_SRC_ADDR_HI = 0 }
 521                         0000: c0264100 00000000 00000000 00000000
 522                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
 523
 524 opcode: CP_LOAD_STATE4 (30) (4 dwords)
 525         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 526         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
 527         { EXT_SRC_ADDR_HI = 0 }
 528                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 529                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 530                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
 531
 532                 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
 533
 534                  -->
 535                 <value name="SB4_VS_TEX"    value="0x0"/>
 536                 <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 537                 <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 538                 <value name="SB4_GS_TEX"    value="0x3"/>
 539                 <value name="SB4_FS_TEX"    value="0x4"/>
 540                 <value name="SB4_CS_TEX"    value="0x5"/>
 541                 <value name="SB4_VS_SHADER" value="0x8"/>
 542                 <value name="SB4_HS_SHADER" value="0x9"/>
 543                 <value name="SB4_DS_SHADER" value="0xa"/>
 544                 <value name="SB4_GS_SHADER" value="0xb"/>
 545                 <value name="SB4_FS_SHADER" value="0xc"/>
 546                 <value name="SB4_CS_SHADER" value="0xd"/>
 547                 <!--
 548                 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
 549                 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
 550
 551                 Compute has it's own dedicated SSBO state, it seems, but the rest
 552                 of the stages share state
 553                  -->
 554                 <value name="SB4_SSBO"   value="0xe"/>
 555                 <value name="SB4_CS_SSBO"   value="0xf"/>
 556         </enum>
 557         <enum name="a4xx_state_type">
 558                 <value name="ST4_SHADER" value="0"/>
 559                 <value name="ST4_CONSTANTS" value="1"/>
 560                 <value name="ST4_UBO" value="2"/>
 561         </enum>
 562         <enum name="a4xx_state_src">
 563                 <value name="SS4_DIRECT" value="0"/>
 564                 <value name="SS4_INDIRECT" value="2"/>
 565         </enum>
 566         <reg32 offset="0" name="0">
 567                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 568                 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
 569                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
 570                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 571         </reg32>
 572         <reg32 offset="1" name="1">
 573                 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
 574                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 575         </reg32>
 576         <reg32 offset="2" name="2" variants="A5XX-">
 577                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 578         </reg32>
 579 </domain>
 580
 581 <!-- looks basically same CP_LOAD_STATE4 -->
 582 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
 583         <doc>Load state, a6xx+</doc>
 584         <enum name="a6xx_state_block">
 585                 <value name="SB6_VS_TEX"    value="0x0"/>
 586                 <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 587                 <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 588                 <value name="SB6_GS_TEX"    value="0x3"/>
 589                 <value name="SB6_FS_TEX"    value="0x4"/>
 590                 <value name="SB6_CS_TEX"    value="0x5"/>
 591                 <value name="SB6_VS_SHADER" value="0x8"/>
 592                 <value name="SB6_HS_SHADER" value="0x9"/>
 593                 <value name="SB6_DS_SHADER" value="0xa"/>
 594                 <value name="SB6_GS_SHADER" value="0xb"/>
 595                 <value name="SB6_FS_SHADER" value="0xc"/>
 596                 <value name="SB6_CS_SHADER" value="0xd"/>
 597                 <value name="SB6_IBO"       value="0xe"/>
 598                 <value name="SB6_CS_IBO"    value="0xf"/>
 599         </enum>
 600         <enum name="a6xx_state_type">
 601                 <value name="ST6_SHADER" value="0"/>
 602                 <value name="ST6_CONSTANTS" value="1"/>
 603                 <value name="ST6_UBO" value="2"/>
 604                 <value name="ST6_IBO" value="3"/>
 605         </enum>
 606         <enum name="a6xx_state_src">
 607                 <value name="SS6_DIRECT" value="0"/>
 608                 <value name="SS6_INDIRECT" value="2"/>
 609         </enum>
 610         <reg32 offset="0" name="0">
 611                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 612                 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
 613                 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
 614                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
 615                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 616         </reg32>
 617         <reg32 offset="1" name="1">
 618                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 619         </reg32>
 620         <reg32 offset="2" name="2">
 621                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 622         </reg32>
 623 </domain>
 624
 625 <bitset name="vgt_draw_initiator" inline="yes">
 626         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 627         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 628         <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
 629         <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
 630         <bitfield name="NOT_EOP" pos="12" type="boolean"/>
 631         <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
 632         <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
 633         <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
 634 </bitset>
 635
 636 <!-- changed on a4xx: -->
 637 <enum name="a4xx_index_size">
 638         <value name="INDEX4_SIZE_8_BIT" value="0"/>
 639         <value name="INDEX4_SIZE_16_BIT" value="1"/>
 640         <value name="INDEX4_SIZE_32_BIT" value="2"/>
 641 </enum>
 642
 643 <enum name="a6xx_patch_type">
 644   <value name="TESS_QUADS" value="0"/>
 645   <value name="TESS_TRIANGLES" value="1"/>
 646   <value name="TESS_ISOLINES" value="2"/>
 647 </enum>
 648
 649 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
 650         <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
 651         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 652         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 653         <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 654         <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 655         <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
 656         <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
 657         <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 658 </bitset>
 659
 660 <domain name="CP_DRAW_INDX" width="32">
 661         <reg32 offset="0" name="0">
 662                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 663         </reg32>
 664         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 665         <reg32 offset="2" name="2">
 666                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 667         </reg32>
 668         <reg32 offset="3" name="3">
 669                 <bitfield name="INDX_BASE" low="0" high="31"/>
 670         </reg32>
 671         <reg32 offset="4" name="4">
 672                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 673         </reg32>
 674 </domain>
 675
 676 <domain name="CP_DRAW_INDX_2" width="32">
 677         <reg32 offset="0" name="0">
 678                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 679         </reg32>
 680         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 681         <reg32 offset="2" name="2">
 682                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 683         </reg32>
 684         <!-- followed by NUM_INDICES indices.. -->
 685 </domain>
 686
 687 <domain name="CP_DRAW_INDX_OFFSET" width="32">
 688         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 689         <reg32 offset="1" name="1">
 690                 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
 691         </reg32>
 692         <reg32 offset="2" name="2">
 693                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 694         </reg32>
 695         <reg32 offset="3" name="3">
 696         </reg32>
 697
 698         <stripe variants="A5XX-">
 699                 <reg32 offset="4" name="4">
 700                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 701                 </reg32>
 702                 <reg32 offset="5" name="5">
 703                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 704                 </reg32>
 705                 <reg32 offset="6" name="6">
 706                         <bitfield name="INDX_SIZE" low="0" high="31"/>
 707                 </reg32>
 708         </stripe>
 709
 710         <reg32 offset="4" name="4">
 711                 <bitfield name="INDX_BASE" low="0" high="31"/>
 712         </reg32>
 713
 714         <reg32 offset="5" name="5">
 715                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 716         </reg32>
 717 </domain>
 718
 719 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 720         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 721         <reg32 offset="1" name="1">
 722                 <bitfield name="INDIRECT" low="0" high="31"/>
 723         </reg32>
 724         <stripe variants="A5XX-">
 725                 <reg32 offset="2" name="2">
 726                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 727                 </reg32>
 728         </stripe>
 729 </domain>
 730
 731 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 732         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 733         <stripe variants="A4XX">
 734                 <reg32 offset="1" name="1">
 735                         <bitfield name="INDX_BASE" low="0" high="31"/>
 736                 </reg32>
 737                 <reg32 offset="2" name="2">
 738                         <!-- max # of bytes in index buffer -->
 739                         <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
 740                 </reg32>
 741                 <reg32 offset="3" name="3">
 742                         <bitfield name="INDIRECT" low="0" high="31"/>
 743                 </reg32>
 744         </stripe>
 745         <stripe variants="A5XX-">
 746                 <reg32 offset="1" name="1">
 747                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 748                 </reg32>
 749                 <reg32 offset="2" name="2">
 750                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 751                 </reg32>
 752                 <reg32 offset="3" name="3">
 753                         <!-- max # of elements in index buffer -->
 754                         <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
 755                 </reg32>
 756                 <reg32 offset="4" name="4">
 757                         <bitfield name="INDIRECT_LO" low="0" high="31"/>
 758                 </reg32>
 759                 <reg32 offset="5" name="5">
 760                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 761                 </reg32>
 762         </stripe>
 763 </domain>
 764
 765 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
 766         <array offset="0" name="" stride="3" length="100">
 767                 <reg32 offset="0" name="0">
 768                         <bitfield name="COUNT" low="0" high="15" type="uint"/>
 769                         <bitfield name="DIRTY" pos="16" type="boolean"/>
 770                         <bitfield name="DISABLE" pos="17" type="boolean"/>
 771                         <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 772                         <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
 773                         <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
 774                         <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
 775                         <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
 776                         <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 777                 </reg32>
 778                 <reg32 offset="1" name="1">
 779                         <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
 780                 </reg32>
 781                 <reg32 offset="2" name="2" variants="A5XX-">
 782                         <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
 783                 </reg32>
 784         </array>
 785 </domain>
 786
 787 <domain name="CP_SET_BIN" width="32">
 788         <doc>value at offset 0 always seems to be 0x00000000..</doc>
 789         <reg32 offset="0" name="0"/>
 790         <reg32 offset="1" name="1">
 791                 <bitfield name="X1" low="0" high="15" type="uint"/>
 792                 <bitfield name="Y1" low="16" high="31" type="uint"/>
 793         </reg32>
 794         <reg32 offset="2" name="2">
 795                 <bitfield name="X2" low="0" high="15" type="uint"/>
 796                 <bitfield name="Y2" low="16" high="31" type="uint"/>
 797         </reg32>
 798 </domain>
 799
 800 <domain name="CP_SET_BIN_DATA" width="32">
 801         <reg32 offset="0" name="0">
 802                 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
 803                 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
 804         </reg32>
 805         <reg32 offset="1" name="1">
 806                 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
 807                 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
 808         </reg32>
 809 </domain>
 810
 811 <domain name="CP_SET_BIN_DATA5" width="32">
 812         <reg32 offset="0" name="0">
 813                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 814                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 815                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 816                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 817         </reg32>
 818         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 819         <reg32 offset="1" name="1">
 820                 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
 821         </reg32>
 822         <reg32 offset="2" name="2">
 823                 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
 824         </reg32>
 825         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 826         <reg32 offset="3" name="3">
 827                 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
 828         </reg32>
 829         <reg32 offset="4" name="4">
 830                 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
 831         </reg32>
 832         <!-- what is this new address? -->
 833         <reg32 offset="5" name="5">
 834                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 835         </reg32>
 836         <reg32 offset="6" name="6">
 837                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 838         </reg32>
 839 </domain>
 840
 841 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
 842         <doc>
 843                 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
 844                 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
 845                 for Vulkan where these values aren't known when the command
 846                 stream is recorded.
 847         </doc>
 848         <reg32 offset="0" name="0">
 849                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 850                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 851                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 852                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 853         </reg32>
 854         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 855         <reg32 offset="1" name="1">
 856                 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
 857         </reg32>
 858         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 859         <reg32 offset="2" name="2">
 860                 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
 861         </reg32>
 862         <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
 863         <reg32 offset="3" name="3">
 864                 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
 865         </reg32>
 866 </domain>
 867
 868 <domain name="CP_REG_RMW" width="32">
 869         <doc>
 870                 Modifies DST_REG using two sources that can either be registers
 871                 or immediates. If SRC1_ADD is set, then do the following:
 872
 873                         $dst = (($dst &amp; $src0) rot $rotate) + $src1
 874
 875                 Otherwise:
 876
 877                         $dst = (($dst &amp; $src0) rot $rotate) | $src1
 878
 879                 Here "rot" means rotate left.
 880         </doc>
 881         <reg32 offset="0" name="0">
 882                 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
 883                 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
 884                 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
 885                 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
 886                 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
 887         </reg32>
 888         <reg32 offset="1" name="1">
 889                 <bitfield name="SRC0" low="0" high="31" type="uint"/>
 890         </reg32>
 891         <reg32 offset="2" name="2">
 892                 <bitfield name="SRC1" low="0" high="31" type="uint"/>
 893         </reg32>
 894 </domain>
 895
 896 <domain name="CP_REG_TO_MEM" width="32">
 897         <reg32 offset="0" name="0">
 898                 <bitfield name="REG" low="0" high="15" type="hex"/>
 899                 <!-- number of registers/dwords copied is max(CNT, 1). -->
 900                 <bitfield name="CNT" low="18" high="29" type="uint"/>
 901                 <bitfield name="64B" pos="30" type="boolean"/>
 902                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 903         </reg32>
 904         <reg32 offset="1" name="1">
 905                 <bitfield name="DEST" low="0" high="31"/>
 906         </reg32>
 907         <reg32 offset="2" name="2" variants="A5XX-">
 908                 <bitfield name="DEST_HI" low="0" high="31"/>
 909         </reg32>
 910 </domain>
 911
 912 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
 913         <doc>
 914                 Like CP_REG_TO_MEM, but the memory address to write to can be
 915                 offsetted using either one or two registers or scratch
 916                 registers.
 917         </doc>
 918         <reg32 offset="0" name="0">
 919                 <bitfield name="REG" low="0" high="15" type="hex"/>
 920                 <!-- number of registers/dwords copied is max(CNT, 1). -->
 921                 <bitfield name="CNT" low="18" high="29" type="uint"/>
 922                 <bitfield name="64B" pos="30" type="boolean"/>
 923                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 924         </reg32>
 925         <reg32 offset="1" name="1">
 926                 <bitfield name="DEST" low="0" high="31"/>
 927         </reg32>
 928         <reg32 offset="2" name="2" variants="A5XX-">
 929                 <bitfield name="DEST_HI" low="0" high="31"/>
 930         </reg32>
 931         <reg32 offset="3" name="3">
 932                 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
 933                 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
 934         </reg32>
 935         <!-- followed by an optional identical OFFSET1 dword -->
 936 </domain>
 937
 938 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
 939         <doc>
 940                 Like CP_REG_TO_MEM, but the memory address to write to can be
 941                 offsetted using a DWORD in memory.
 942         </doc>
 943         <reg32 offset="0" name="0">
 944                 <bitfield name="REG" low="0" high="15" type="hex"/>
 945                 <!-- number of registers/dwords copied is max(CNT, 1). -->
 946                 <bitfield name="CNT" low="18" high="29" type="uint"/>
 947                 <bitfield name="64B" pos="30" type="boolean"/>
 948                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 949         </reg32>
 950         <reg32 offset="1" name="1">
 951                 <bitfield name="DEST" low="0" high="31"/>
 952         </reg32>
 953         <reg32 offset="2" name="2" variants="A5XX-">
 954                 <bitfield name="DEST_HI" low="0" high="31"/>
 955         </reg32>
 956         <reg32 offset="3" name="3">
 957                 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
 958         </reg32>
 959         <reg32 offset="4" name="4">
 960                 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
 961         </reg32>
 962 </domain>
 963
 964 <domain name="CP_MEM_TO_REG" width="32">
 965         <reg32 offset="0" name="0">
 966                 <bitfield name="REG" low="0" high="15" type="hex"/>
 967                 <!-- number of registers/dwords copied is max(CNT, 1). -->
 968                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 969                 <!-- shift each DWORD left by 2 while copying -->
 970                 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
 971                 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
 972                 <bitfield name="UNK31" pos="31" type="boolean"/>
 973         </reg32>
 974         <reg32 offset="1" name="1">
 975                 <bitfield name="SRC" low="0" high="31"/>
 976         </reg32>
 977         <reg32 offset="2" name="2" variants="A5XX-">
 978                 <bitfield name="SRC_HI" low="0" high="31"/>
 979         </reg32>
 980 </domain>
 981
 982 <domain name="CP_MEM_TO_MEM" width="32">
 983         <reg32 offset="0" name="0">
 984                 <!--
 985                 not sure how many src operands we have, but the low
 986                 bits negate the n'th src argument.
 987                  -->
 988                 <bitfield name="NEG_A" pos="0" type="boolean"/>
 989                 <bitfield name="NEG_B" pos="1" type="boolean"/>
 990                 <bitfield name="NEG_C" pos="2" type="boolean"/>
 991
 992                 <!-- if set treat src/dst as 64bit values -->
 993                 <bitfield name="DOUBLE" pos="29" type="boolean"/>
 994                 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
 995                 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
 996                 <!-- some other kind of wait -->
 997                 <bitfield name="UNK31" pos="31" type="boolean"/>
 998         </reg32>
 999         <!--
1000         followed by sequence of addresses.. the first is the
1001         destination and the rest are N src addresses which are
1002         summed (after being negated if NEG_x bit set) allowing
1003         to do things like 'result += end - start' (which turns
1004         out to be useful for queries and accumulating results
1005         across multiple tiles)
1006          -->
1007 </domain>
1008
1009 <domain name="CP_MEMCPY" width="32">
1010         <reg32 offset="0" name="0">
1011                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1012         </reg32>
1013         <reg32 offset="1" name="1">
1014                 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1015         </reg32>
1016         <reg32 offset="2" name="2">
1017                 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1018         </reg32>
1019         <reg32 offset="3" name="3">
1020                 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1021         </reg32>
1022         <reg32 offset="4" name="4">
1023                 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1024         </reg32>
1025 </domain>
1026
1027 <domain name="CP_REG_TO_SCRATCH" width="32">
1028         <reg32 offset="0" name="0">
1029                 <bitfield name="REG" low="0" high="17" type="hex"/>
1030                 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1031                 <!-- number of registers/dwords copied is CNT + 1. -->
1032                 <bitfield name="CNT" low="24" high="26" type="uint"/>
1033         </reg32>
1034 </domain>
1035
1036 <domain name="CP_SCRATCH_TO_REG" width="32">
1037         <reg32 offset="0" name="0">
1038                 <bitfield name="REG" low="0" high="17" type="hex"/>
1039                 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1040                 <bitfield name="UNK18" pos="18" type="boolean"/>
1041                 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1042                 <!-- number of registers/dwords copied is CNT + 1. -->
1043                 <bitfield name="CNT" low="24" high="26" type="uint"/>
1044         </reg32>
1045 </domain>
1046
1047 <domain name="CP_SCRATCH_WRITE" width="32">
1048         <reg32 offset="0" name="0">
1049                 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1050         </reg32>
1051         <!-- followed by one or more DWORDs to write to scratch registers -->
1052 </domain>
1053
1054 <domain name="CP_MEM_WRITE" width="32">
1055         <reg32 offset="0" name="0">
1056                 <bitfield name="ADDR_LO" low="0" high="31"/>
1057         </reg32>
1058         <reg32 offset="1" name="1">
1059                 <bitfield name="ADDR_HI" low="0" high="31"/>
1060         </reg32>
1061         <!-- followed by the DWORDs to write -->
1062 </domain>
1063
1064 <enum name="cp_cond_function">
1065         <value value="0" name="WRITE_ALWAYS"/>
1066         <value value="1" name="WRITE_LT"/>
1067         <value value="2" name="WRITE_LE"/>
1068         <value value="3" name="WRITE_EQ"/>
1069         <value value="4" name="WRITE_NE"/>
1070         <value value="5" name="WRITE_GE"/>
1071         <value value="6" name="WRITE_GT"/>
1072 </enum>
1073
1074 <domain name="CP_COND_WRITE" width="32">
1075         <reg32 offset="0" name="0">
1076                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1077                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1078                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1079         </reg32>
1080         <reg32 offset="1" name="1">
1081                 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1082         </reg32>
1083         <reg32 offset="2" name="2">
1084                 <bitfield name="REF" low="0" high="31"/>
1085         </reg32>
1086         <reg32 offset="3" name="3">
1087                 <bitfield name="MASK" low="0" high="31"/>
1088         </reg32>
1089         <reg32 offset="4" name="4">
1090                 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1091         </reg32>
1092         <reg32 offset="5" name="5">
1093                 <bitfield name="WRITE_DATA" low="0" high="31"/>
1094         </reg32>
1095 </domain>
1096
1097 <domain name="CP_COND_WRITE5" width="32">
1098         <reg32 offset="0" name="0">
1099                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1100                 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1101                 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1102                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1103                 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1104                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1105         </reg32>
1106         <reg32 offset="1" name="1">
1107                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1108         </reg32>
1109         <reg32 offset="2" name="2">
1110                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1111         </reg32>
1112         <reg32 offset="3" name="3">
1113                 <bitfield name="REF" low="0" high="31"/>
1114         </reg32>
1115         <reg32 offset="4" name="4">
1116                 <bitfield name="MASK" low="0" high="31"/>
1117         </reg32>
1118         <reg32 offset="5" name="5">
1119                 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1120         </reg32>
1121         <reg32 offset="6" name="6">
1122                 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1123         </reg32>
1124         <reg32 offset="7" name="7">
1125                 <bitfield name="WRITE_DATA" low="0" high="31"/>
1126         </reg32>
1127 </domain>
1128
1129 <domain name="CP_WAIT_MEM_GTE" width="32">
1130         <doc>
1131                 Wait until a memory value is greater than or equal to the
1132                 reference, using signed comparison.
1133         </doc>
1134         <reg32 offset="0" name="0">
1135                 <!-- Reserved for flags, presumably? Unused in FW -->
1136                 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1137         </reg32>
1138         <reg32 offset="1" name="1">
1139                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1140         </reg32>
1141         <reg32 offset="2" name="2">
1142                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1143         </reg32>
1144         <reg32 offset="3" name="3">
1145                 <bitfield name="REF" low="0" high="31"/>
1146         </reg32>
1147 </domain>
1148
1149 <domain name="CP_WAIT_REG_MEM" width="32">
1150         <doc>
1151                 This uses the same internal comparison as CP_COND_WRITE,
1152                 but waits until the comparison is true instead. It busy-loops in
1153                 the CP for the given number of cycles before trying again.
1154         </doc>
1155         <reg32 offset="0" name="0">
1156                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1157                 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1158                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1159                 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1160                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1161         </reg32>
1162         <reg32 offset="1" name="1">
1163                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1164         </reg32>
1165         <reg32 offset="2" name="2">
1166                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1167         </reg32>
1168         <reg32 offset="3" name="3">
1169                 <bitfield name="REF" low="0" high="31"/>
1170         </reg32>
1171         <reg32 offset="4" name="4">
1172                 <bitfield name="MASK" low="0" high="31"/>
1173         </reg32>
1174         <reg32 offset="5" name="5">
1175                 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1176         </reg32>
1177 </domain>
1178
1179 <domain name="CP_WAIT_TWO_REGS" width="32">
1180         <doc>
1181                 Waits for REG0 to not be 0 or REG1 to not equal REF
1182         </doc>
1183         <reg32 offset="0" name="0">
1184                 <bitfield name="REG0" low="0" high="17" type="hex"/>
1185         </reg32>
1186         <reg32 offset="1" name="1">
1187                 <bitfield name="REG1" low="0" high="17" type="hex"/>
1188         </reg32>
1189         <reg32 offset="2" name="2">
1190                 <bitfield name="REF" low="0" high="31" type="uint"/>
1191         </reg32>
1192 </domain>
1193
1194 <domain name="CP_DISPATCH_COMPUTE" width="32">
1195         <reg32 offset="0" name="0"/>
1196         <reg32 offset="1" name="1">
1197                 <bitfield name="X" low="0" high="31"/>
1198         </reg32>
1199         <reg32 offset="2" name="2">
1200                 <bitfield name="Y" low="0" high="31"/>
1201         </reg32>
1202         <reg32 offset="3" name="3">
1203                 <bitfield name="Z" low="0" high="31"/>
1204         </reg32>
1205 </domain>
1206
1207 <domain name="CP_SET_RENDER_MODE" width="32">
1208         <enum name="render_mode_cmd">
1209                 <value value="1" name="BYPASS"/>
1210                 <value value="2" name="BINNING"/>
1211                 <value value="3" name="GMEM"/>
1212                 <value value="5" name="BLIT2D"/>
1213                 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1214                 <value value="7" name="BLIT2DSCALE"/>
1215                 <!-- 8 set before going back to BYPASS exiting 2D -->
1216                 <value value="8" name="END2D"/>
1217         </enum>
1218         <reg32 offset="0" name="0">
1219                 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1220                 <!--
1221                 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1222                 0x21xx range.. possibly (at least some) a5xx variants have a
1223                 2d core?
1224                  -->
1225         </reg32>
1226         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1227         <reg32 offset="1" name="1">
1228                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1229         </reg32>
1230         <reg32 offset="2" name="2">
1231                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1232         </reg32>
1233         <reg32 offset="3" name="3">
1234                 <!--
1235                 set when in GMEM.. maybe indicates GMEM contents need to be
1236                 preserved on ctx switch?
1237                  -->
1238                 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1239                 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1240         </reg32>
1241         <reg32 offset="4" name="4"/>
1242         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1243         <reg32 offset="5" name="5">
1244                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1245         </reg32>
1246         <reg32 offset="6" name="6">
1247                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1248         </reg32>
1249         <reg32 offset="7" name="7">
1250                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1251         </reg32>
1252 </domain>
1253
1254 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1255 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1256         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1257         <reg32 offset="0" name="0">
1258                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1259         </reg32>
1260         <reg32 offset="1" name="1">
1261                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1262         </reg32>
1263         <reg32 offset="2" name="2">
1264         </reg32>
1265         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1266         <reg32 offset="3" name="3">
1267                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1268         </reg32>
1269         <reg32 offset="4" name="4"/>
1270         <reg32 offset="5" name="5">
1271                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1272         </reg32>
1273         <reg32 offset="6" name="6">
1274                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1275         </reg32>
1276         <reg32 offset="7" name="7"/>
1277 </domain>
1278
1279 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1280         <reg32 offset="0" name="0">
1281         </reg32>
1282         <reg32 offset="1" name="1">
1283                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1284         </reg32>
1285         <reg32 offset="2" name="2">
1286                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1287         </reg32>
1288 </domain>
1289
1290 <domain name="CP_EVENT_WRITE" width="32">
1291         <reg32 offset="0" name="0">
1292                 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1293                 <!-- when set, write back timestamp instead of value from packet: -->
1294                 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1295         </reg32>
1296         <!--
1297         TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1298         context switch?
1299          -->
1300         <reg32 offset="1" name="1">
1301                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1302         </reg32>
1303         <reg32 offset="2" name="2">
1304                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1305         </reg32>
1306         <reg32 offset="3" name="3">
1307                 <!-- ??? -->
1308         </reg32>
1309 </domain>
1310
1311 <domain name="CP_BLIT" width="32">
1312         <enum name="cp_blit_cmd">
1313                 <value value="0" name="BLIT_OP_FILL"/>
1314                 <value value="1" name="BLIT_OP_COPY"/>
1315                 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1316         </enum>
1317         <reg32 offset="0" name="0">
1318                 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1319         </reg32>
1320         <reg32 offset="1" name="1">
1321                 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1322                 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1323         </reg32>
1324         <reg32 offset="2" name="2">
1325                 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1326                 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1327         </reg32>
1328         <reg32 offset="3" name="3">
1329                 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1330                 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1331         </reg32>
1332         <reg32 offset="4" name="4">
1333                 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1334                 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1335         </reg32>
1336 </domain>
1337
1338 <domain name="CP_EXEC_CS" width="32">
1339         <reg32 offset="0" name="0">
1340         </reg32>
1341         <reg32 offset="1" name="1">
1342                 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1343         </reg32>
1344         <reg32 offset="2" name="2">
1345                 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1346         </reg32>
1347         <reg32 offset="3" name="3">
1348                 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1349         </reg32>
1350 </domain>
1351
1352 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1353         <reg32 offset="0" name="0">
1354         </reg32>
1355         <stripe variants="A4XX">
1356                 <reg32 offset="1" name="1">
1357                         <bitfield name="ADDR" low="0" high="31"/>
1358                 </reg32>
1359                 <reg32 offset="2" name="2">
1360                         <!-- localsize is value minus one: -->
1361                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1362                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1363                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1364                 </reg32>
1365         </stripe>
1366         <stripe variants="A5XX-">
1367                 <reg32 offset="1" name="1">
1368                         <bitfield name="ADDR_LO" low="0" high="31"/>
1369                 </reg32>
1370                 <reg32 offset="2" name="2">
1371                         <bitfield name="ADDR_HI" low="0" high="31"/>
1372                 </reg32>
1373                 <reg32 offset="3" name="3">
1374                         <!-- localsize is value minus one: -->
1375                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1376                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1377                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1378                 </reg32>
1379         </stripe>
1380 </domain>
1381
1382 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1383         <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1384         <enum name="a6xx_render_mode">
1385                 <value value="1" name="RM6_BYPASS"/>
1386                 <value value="2" name="RM6_BINNING"/>
1387                 <value value="4" name="RM6_GMEM"/>
1388                 <value value="5" name="RM6_BLIT2D"/>
1389                 <value value="6" name="RM6_RESOLVE"/>
1390                 <value value="7" name="RM6_YIELD"/>
1391                 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1392
1393                 <!--
1394                         These values come from a6xx_set_marker() in the
1395                         downstream kernel, and they can only be set by the kernel
1396                 -->
1397                 <value value="0xd" name="RM6_IB1LIST_START"/>
1398                 <value value="0xe" name="RM6_IB1LIST_END"/>
1399                 <!-- IFPC - inter-frame power collapse -->
1400                 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1401                 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1402         </enum>
1403         <reg32 offset="0" name="0">
1404                 <bitfield name="MARKER" low="0" high="3"/>
1405                 <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1406         </reg32>
1407 </domain>
1408
1409 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1410         <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1411         <enum name="pseudo_reg">
1412                 <value value="0" name="SMMU_INFO"/>
1413                 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1414                 <value value="2" name="SECURE_SAVE_ADDR"/>
1415                 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1416                 <value value="4" name="COUNTER"/>
1417         </enum>
1418         <array offset="0" name="" stride="3" length="100">
1419                 <reg32 offset="0" name="0">
1420                         <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1421                 </reg32>
1422                 <reg32 offset="1" name="1">
1423                         <bitfield name="LO" low="0" high="31"/>
1424                 </reg32>
1425                 <reg32 offset="2" name="2">
1426                         <bitfield name="HI" low="0" high="31"/>
1427                 </reg32>
1428         </array>
1429 </domain>
1430
1431 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1432         <doc>
1433                 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1434                 So:
1435
1436                         opcode: CP_REG_TEST (39) (2 dwords)
1437                                 { REG = 0xc10 | BIT = 0 }
1438                                        0000: 70b90001 00000c10
1439                         opcode: CP_COND_REG_EXEC (47) (3 dwords)
1440                                        0000: 70c70002 10000000 00000004
1441                         opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1442
1443                 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1444                 offset 0x0c10 is 1
1445         </doc>
1446         <reg32 offset="0" name="0">
1447                 <!-- the register to test -->
1448                 <bitfield name="REG" low="0" high="11"/>
1449                 <!-- the bit to test -->
1450                 <bitfield name="BIT" low="20" high="24" type="uint"/>
1451                 <!-- execute CP_WAIT_FOR_ME beforehand -->
1452                 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1453         </reg32>
1454 </domain>
1455
1456 <!-- I *think* this existed at least as far back as a4xx -->
1457 <domain name="CP_COND_REG_EXEC" width="32">
1458         <enum name="compare_mode">
1459                 <!-- use the predicate bit set by CP_REG_TEST -->
1460                 <value value="1" name="PRED_TEST"/>
1461                 <!-- compare two registers directly for equality -->
1462                 <value value="2" name="REG_COMPARE"/>
1463                 <!-- test if certain render modes are set via CP_SET_MARKER -->
1464                 <value value="3" name="RENDER_MODE" variants="A6XX-"/>
1465         </enum>
1466         <reg32 offset="0" name="0">
1467                 <bitfield name="REG0" low="0" high="17" type="hex"/>
1468
1469                 <!--
1470                         Note: these bits have the same meaning, and use the same
1471                         internal mechanism as the bits in CP_SET_DRAW_STATE.
1472                         When RENDER_MODE is selected, they're used as
1473                         a bitmask of which modes pass the test.
1474                 -->
1475
1476                 <!-- RM6_BINNING -->
1477                 <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
1478                 <!-- all others -->
1479                 <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
1480                 <!-- RM6_BYPASS -->
1481                 <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
1482
1483                 <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1484         </reg32>
1485
1486         <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1487
1488         <reg32 offset="1" name="1">
1489                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1490         </reg32>
1491 </domain>
1492
1493 <domain name="CP_COND_EXEC" width="32">
1494         <doc>
1495                 Executes the following DWORDs of commands if the dword at ADDR0
1496                 is not equal to 0 and the dword at ADDR1 is less than REF
1497                 (signed comparison).
1498         </doc>
1499         <reg32 offset="0" name="0">
1500                 <bitfield name="ADDR0_LO" low="0" high="31"/>
1501         </reg32>
1502         <reg32 offset="1" name="1">
1503                 <bitfield name="ADDR0_HI" low="0" high="31"/>
1504         </reg32>
1505         <reg32 offset="2" name="2">
1506                 <bitfield name="ADDR1_LO" low="0" high="31"/>
1507         </reg32>
1508         <reg32 offset="3" name="3">
1509                 <bitfield name="ADDR1_HI" low="0" high="31"/>
1510         </reg32>
1511         <reg32 offset="4" name="4">
1512                 <bitfield name="REF" low="0" high="31"/>
1513         </reg32>
1514         <reg32 offset="5" name="5">
1515                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1516         </reg32>
1517 </domain>
1518
1519 <domain name="CP_SET_CTXSWITCH_IB" width="32">
1520         <doc>
1521                 Used by the userspace driver to set various IB's which are
1522                 executed during context save/restore for handling
1523                 state that isn't restored by the
1524                 context switch routine itself.
1525         </doc>
1526         <enum name="ctxswitch_ib">
1527                 <value name="RESTORE_IB" value="0">
1528                         <doc>Executed unconditionally when switching back to the context.</doc>
1529                 </value>
1530                 <value name="YIELD_RESTORE_IB" value="1">
1531                         <doc>
1532                                 Executed when switching back after switching
1533                                 away during execution of
1534                                 a CP_SET_MARKER packet with RM6_YIELD as the
1535                                 payload *and* the normal save routine was
1536                                 bypassed for a shorter one. I think this is
1537                                 connected to the "skipsaverestore" bit set by
1538                                 the kernel when preempting.
1539                         </doc>
1540                 </value>
1541                 <value name="SAVE_IB" value="2">
1542                         <doc>
1543                                 Executed when switching away from the context,
1544                                 except for context switches initiated via
1545                                 CP_YIELD.
1546                         </doc>
1547                 </value>
1548                 <value name="RB_SAVE_IB" value="3">
1549                         <doc>
1550                                 This can only be set by the RB (i.e. the kernel)
1551                                 and executes with protected mode off, but
1552                                 is otherwise similar to SAVE_IB.
1553                         </doc>
1554                 </value>
1555         </enum>
1556         <reg32 offset="0" name="0">
1557                 <bitfield name="ADDR_LO" low="0" high="31"/>
1558         </reg32>
1559         <reg32 offset="1" name="1">
1560                 <bitfield name="ADDR_HI" low="0" high="31"/>
1561         </reg32>
1562         <reg32 offset="2" name="2">
1563                 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
1564                 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1565         </reg32>
1566 </domain>
1567
1568 <domain name="CP_REG_WRITE" width="32">
1569         <enum name="reg_tracker">
1570                 <doc>
1571                         Keep shadow copies of these registers and only set them
1572                         when drawing, avoiding redundant writes:
1573                         - VPC_CNTL_0
1574                         - HLSQ_CONTROL_1_REG
1575                         - HLSQ_UNKNOWN_B980
1576                 </doc>
1577                 <value name="TRACK_CNTL_REG" value="0x1"/>
1578                 <doc>
1579                         Track RB_RENDER_CNTL, and insert a WFI in the following
1580                         situation:
1581                         - There is a write that disables binning
1582                         - There was a draw with binning left enabled, but in
1583                           BYPASS mode
1584                         Presumably this is a hang workaround?
1585                 </doc>
1586                 <value name="TRACK_RENDER_CNTL" value="0x2"/>
1587                 <doc>
1588                         Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
1589                         the data to write is 0. Used by the Vulkan blob with
1590                         PC_UNKNOWN_9B07, but this isn't predicated on particular
1591                         register(s) like the others.
1592                 </doc>
1593                 <value name="UNK_EVENT_WRITE" value="0x4"/>
1594         </enum>
1595         <reg32 offset="0" name="0">
1596                 <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
1597         </reg32>
1598 </domain>
1599
1600 </database>
1601