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freedreno/drm: convert ring_pool to child_pool
[mesa.git] / src / freedreno / registers / adreno_pm4.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
6 <enum name="vgt_event_type">
7 <value name="VS_DEALLOC" value="0"/>
8 <value name="PS_DEALLOC" value="1"/>
9 <value name="VS_DONE_TS" value="2"/>
10 <value name="PS_DONE_TS" value="3"/>
11 <value name="CACHE_FLUSH_TS" value="4"/>
12 <value name="CONTEXT_DONE" value="5"/>
13 <value name="CACHE_FLUSH" value="6"/>
14 <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
15 <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
16 <value name="VIZQUERY_END" value="8"/>
17 <value name="SC_WAIT_WC" value="9"/>
18 <value name="RST_PIX_CNT" value="13"/>
19 <value name="RST_VTX_CNT" value="14"/>
20 <value name="TILE_FLUSH" value="15"/>
21 <value name="STAT_EVENT" value="16"/>
22 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
23 <value name="ZPASS_DONE" value="21"/>
24 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
25 <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
26 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
27 <value name="VS_FETCH_DONE" value="27"/>
28 <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
29
30 <!-- a5xx events -->
31 <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
32 <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
33 <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
34 <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
35 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
36 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
37 <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
38 <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
39 <value name="BLIT" value="30" variants="A5XX,A6XX"/>
40 <value name="UNK_25" value="37" variants="A5XX"/>
41 <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
42 <value name="UNK_2C" value="44" variants="A5XX"/>
43 <value name="UNK_2D" value="45" variants="A5XX"/>
44 </enum>
45
46 <enum name="pc_di_primtype">
47 <value name="DI_PT_NONE" value="0"/>
48 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
49 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
50 <value name="DI_PT_LINELIST" value="2"/>
51 <value name="DI_PT_LINESTRIP" value="3"/>
52 <value name="DI_PT_TRILIST" value="4"/>
53 <value name="DI_PT_TRIFAN" value="5"/>
54 <value name="DI_PT_TRISTRIP" value="6"/>
55 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
56 <value name="DI_PT_RECTLIST" value="8"/>
57 <value name="DI_PT_POINTLIST" value="9"/>
58 <value name="DI_PT_LINE_ADJ" value="0xa"/>
59 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
60 <value name="DI_PT_TRI_ADJ" value="0xc"/>
61 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
62 <value name="DI_PT_PATCHES" value="0x29"/>
63 </enum>
64
65 <enum name="pc_di_src_sel">
66 <value name="DI_SRC_SEL_DMA" value="0"/>
67 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
68 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
69 <value name="DI_SRC_SEL_RESERVED" value="3"/>
70 </enum>
71
72 <enum name="pc_di_face_cull_sel">
73 <value name="DI_FACE_CULL_NONE" value="0"/>
74 <value name="DI_FACE_CULL_FETCH" value="1"/>
75 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
76 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
77 </enum>
78
79 <enum name="pc_di_index_size">
80 <value name="INDEX_SIZE_IGN" value="0"/>
81 <value name="INDEX_SIZE_16_BIT" value="0"/>
82 <value name="INDEX_SIZE_32_BIT" value="1"/>
83 <value name="INDEX_SIZE_8_BIT" value="2"/>
84 <value name="INDEX_SIZE_INVALID"/>
85 </enum>
86
87 <enum name="pc_di_vis_cull_mode">
88 <value name="IGNORE_VISIBILITY" value="0"/>
89 <value name="USE_VISIBILITY" value="1"/>
90 </enum>
91
92 <enum name="adreno_pm4_packet_type">
93 <value name="CP_TYPE0_PKT" value="0x00000000"/>
94 <value name="CP_TYPE1_PKT" value="0x40000000"/>
95 <value name="CP_TYPE2_PKT" value="0x80000000"/>
96 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
97 <value name="CP_TYPE4_PKT" value="0x40000000"/>
98 <value name="CP_TYPE7_PKT" value="0x70000000"/>
99 </enum>
100
101 <!--
102 Note that in some cases, the same packet id is recycled on a later
103 generation, so variants attribute is used to distinguish. They
104 may not be completely accurate, we would probably have to analyze
105 the pfp and me/pm4 firmware to verify the packet is actually
106 handled on a particular generation. But it is at least enough to
107 disambiguate the packet-id's that were re-used for different
108 packets starting with a5xx.
109 -->
110 <enum name="adreno_pm4_type3_packets">
111 <doc>initialize CP's micro-engine</doc>
112 <value name="CP_ME_INIT" value="0x48"/>
113 <doc>skip N 32-bit words to get to the next packet</doc>
114 <value name="CP_NOP" value="0x10"/>
115 <doc>
116 indirect buffer dispatch. prefetch parser uses this packet
117 type to determine whether to pre-fetch the IB
118 </doc>
119 <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
120 <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
121 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
122 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
123 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
124 <doc>wait for the IDLE state of the engine</doc>
125 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
126 <doc>wait until a register or memory location is a specific value</doc>
127 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
128 <doc>wait until a register location is equal to a specific value</doc>
129 <value name="CP_WAIT_REG_EQ" value="0x52"/>
130 <doc>wait until a register location is >= a specific value</doc>
131 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
132 <doc>wait until a read completes</doc>
133 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
134 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
135 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
136 <doc>register read/modify/write</doc>
137 <value name="CP_REG_RMW" value="0x21"/>
138 <doc>Set binning configuration registers</doc>
139 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
140 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
141 <doc>reads register in chip and writes to memory</doc>
142 <value name="CP_REG_TO_MEM" value="0x3e"/>
143 <doc>write N 32-bit words to memory</doc>
144 <value name="CP_MEM_WRITE" value="0x3d"/>
145 <doc>write CP_PROG_COUNTER value to memory</doc>
146 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
147 <doc>conditional execution of a sequence of packets</doc>
148 <value name="CP_COND_EXEC" value="0x44"/>
149 <doc>conditional write to memory or register</doc>
150 <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
151 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
152 <doc>generate an event that creates a write to memory when completed</doc>
153 <value name="CP_EVENT_WRITE" value="0x46"/>
154 <doc>generate a VS|PS_done event</doc>
155 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
156 <doc>generate a cache flush done event</doc>
157 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
158 <doc>generate a z_pass done event</doc>
159 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
160 <doc>
161 not sure the real name, but this seems to be what is used for
162 opencl, instead of CP_DRAW_INDX..
163 </doc>
164 <value name="CP_RUN_OPENCL" value="0x31"/>
165 <doc>initiate fetch of index buffer and draw</doc>
166 <value name="CP_DRAW_INDX" value="0x22"/>
167 <doc>draw using supplied indices in packet</doc>
168 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
169 <doc>initiate fetch of index buffer and binIDs and draw</doc>
170 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
171 <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
172 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
173 <doc>begin/end initiator for viz query extent processing</doc>
174 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
175 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
176 <value name="CP_SET_STATE" value="0x25"/>
177 <doc>load constant into chip and to memory</doc>
178 <value name="CP_SET_CONSTANT" value="0x2d"/>
179 <doc>load sequencer instruction memory (pointer-based)</doc>
180 <value name="CP_IM_LOAD" value="0x27"/>
181 <doc>load sequencer instruction memory (code embedded in packet)</doc>
182 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
183 <doc>load constants from a location in memory</doc>
184 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
185 <doc>selective invalidation of state pointers</doc>
186 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
187 <doc>dynamically changes shader instruction memory partition</doc>
188 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
189 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
190 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
191 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
192 <value name="CP_SET_BIN_SELECT" value="0x51"/>
193 <doc>updates the current context, if needed</doc>
194 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
195 <doc>generate interrupt from the command stream</doc>
196 <value name="CP_INTERRUPT" value="0x40"/>
197 <doc>copy sequencer instruction memory to system memory</doc>
198 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
199
200 <!-- For a20x -->
201 <!-- TODO handle variants..
202 <doc>
203 Program an offset that will added to the BIN_BASE value of
204 the 3D_DRAW_INDX_BIN packet
205 </doc>
206 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
207 -->
208
209 <!-- for a22x -->
210 <doc>
211 sets draw initiator flags register in PFP, gets bitwise-ORed into
212 every draw initiator
213 </doc>
214 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
215 <doc>sets the register protection mode</doc>
216 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
217
218 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
219
220 <!-- for a3xx -->
221 <doc>load high level sequencer command</doc>
222 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
223 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
224 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
225 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
226 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
227 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
228 <doc>Load a buffer with pre-fetch enabled</doc>
229 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
230 <doc>Set bin (?)</doc>
231 <value name="CP_SET_BIN" value="0x4c"/>
232
233 <doc>test 2 memory locations to dword values specified</doc>
234 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
235
236 <doc>Write register, ignoring context state for context sensitive registers</doc>
237 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
238
239 <doc>Record the real-time when this packet is processed by PFP</doc>
240 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
241
242 <!-- Used to switch GPU between secure and non-secure modes -->
243 <value name="CP_SET_SECURE_MODE" value="0x66"/>
244
245 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
246 <value name="CP_WAIT_FOR_ME" value="0x13"/>
247
248 <!-- for a4xx -->
249 <doc>
250 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
251 groups of registers. Looks like it can be used to create state
252 objects in GPU memory, and on state change only emit pointer
253 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
254 overhead:
255
256 (A4x) save PM4 stream pointers to execute upon a visible draw
257 </doc>
258 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
259 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
260 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
261 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
262 <value name="CP_DRAW_AUTO" value="0x24"/>
263
264 <value name="CP_UNKNOWN_19" value="0x19"/>
265
266 <doc>set to 1 for fastclear..:</doc>
267 <value name="CP_UNKNOWN_1A" value="0x1a"/>
268
269 <value name="CP_UNKNOWN_4E" value="0x4e"/>
270
271 <doc>
272 for A4xx
273 Write to register with address that does not fit into type-0 pkt
274 </doc>
275 <value name="CP_WIDE_REG_WRITE" value="0x74"/>
276
277 <doc>copy from ME scratch RAM to a register</doc>
278 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
279
280 <doc>Copy from REG to ME scratch RAM</doc>
281 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
282
283 <doc>Wait for memory writes to complete</doc>
284 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
285
286 <doc>Conditional execution based on register comparison</doc>
287 <value name="CP_COND_REG_EXEC" value="0x47"/>
288
289 <doc>Memory to REG copy</doc>
290 <value name="CP_MEM_TO_REG" value="0x42"/>
291
292 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
293 <value name="CP_EXEC_CS" value="0x33"/>
294
295 <doc>
296 for a5xx
297 </doc>
298 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
299 <!-- switches SMMU pagetable, used on a5xx only -->
300 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
301 <!-- for a6xx -->
302 <doc>Tells CP the current mode of GPU operation</doc>
303 <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
304 <doc>Instruct CP to set a few internal CP registers</doc>
305 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
306 <!--
307 pairs of regid and value.. seems to be used to program some TF
308 related regs:
309 -->
310 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
311 <!-- A5XX Enable yield in RB only -->
312 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
313 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
314 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
315 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
316 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
317 <!-- Enable/Disable/Defer A5x global preemption model -->
318 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
319 <!-- Enable/Disable A5x local preemption model -->
320 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
321 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
322 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
323 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
324 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
325 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
326 <!-- check if this works on earlier.. -->
327 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
328 <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
329
330 <!-- Test specified bit in specified register and set predicate -->
331 <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
332
333 <!--
334 Seems to set the mode flags which control which CP_SET_DRAW_STATE
335 packets are executed, based on their ENABLE_MASK values
336
337 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
338 packets w/ ENABLE_MASK & 0x6 to execute immediately
339 -->
340 <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
341
342 <!--
343 Seems like there are now separate blocks of state for VS vs FS/CS
344 (probably these amounts to geometry vs fragments so that geometry
345 stage of the pipeline for next draw can start while fragment stage
346 of current draw is still running. The format of the payload of the
347 packets is the same, the only difference is the offsets of the regs
348 the firmware code that handles the packet writes.
349
350 Note that for CL, starting with a6xx, the preferred # of local
351 threads is no longer the same as the max, implying that the shader
352 core can now run warps from unrelated shaders (ie.
353 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
354 CL_KERNEL_WORK_GROUP_SIZE)
355 -->
356 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
357 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
358 <!--
359 Note: For IBO state (Image/SSBOs) which have shared state across
360 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
361 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
362 interchangable.
363 -->
364 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
365
366 <!-- internal packets: -->
367 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
368 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
369 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
370 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
371 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
372 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
373 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
374 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
375
376 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
377 <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
378 <!--
379 unknown a6xx opcodes:
380
381 opcode: (null) (14) (5 dwords)
382 opcode: (null) (55) (4 dwords)
383 opcode: (null) (6d) (4 dwords)
384 -->
385 <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
386 <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
387
388 <!--
389 Seems to always have the payload:
390 00000002 00008801 00004010
391 or:
392 00000002 00008801 00004090
393 or:
394 00000002 00008801 00000010
395 00000002 00008801 00010010
396 00000002 00008801 00d64010
397 ...
398 Note set for compute shaders..
399 Is 0x8801 a register offset?
400 This appears to be a special sort of register write packet
401 more or less, but the firmware has some special handling..
402 Seems like it intercepts/modifies certain register offsets,
403 but others are treated like a normal PKT4 reg write. I
404 guess there are some registers that the fw controls certain
405 bits.
406 -->
407 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
408
409 </enum>
410
411
412 <domain name="CP_LOAD_STATE" width="32">
413 <doc>Load state, a3xx (and later?)</doc>
414 <enum name="adreno_state_block">
415 <value name="SB_VERT_TEX" value="0"/>
416 <value name="SB_VERT_MIPADDR" value="1"/>
417 <value name="SB_FRAG_TEX" value="2"/>
418 <value name="SB_FRAG_MIPADDR" value="3"/>
419 <value name="SB_VERT_SHADER" value="4"/>
420 <value name="SB_GEOM_SHADER" value="5"/>
421 <value name="SB_FRAG_SHADER" value="6"/>
422 <value name="SB_COMPUTE_SHADER" value="7"/>
423 </enum>
424 <enum name="adreno_state_type">
425 <value name="ST_SHADER" value="0"/>
426 <value name="ST_CONSTANTS" value="1"/>
427 </enum>
428 <enum name="adreno_state_src">
429 <value name="SS_DIRECT" value="0">
430 <doc>inline with the CP_LOAD_STATE packet</doc>
431 </value>
432 <value name="SS_INVALID_ALL_IC" value="2"/>
433 <value name="SS_INVALID_PART_IC" value="3"/>
434 <value name="SS_INDIRECT" value="4">
435 <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
436 </value>
437 <value name="SS_INDIRECT_TCM" value="5"/>
438 <value name="SS_INDIRECT_STM" value="6"/>
439 </enum>
440 <reg32 offset="0" name="0">
441 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
442 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
443 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
444 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
445 </reg32>
446 <reg32 offset="1" name="1">
447 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
448 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
449 </reg32>
450 </domain>
451
452 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
453 <doc>Load state, a4xx+</doc>
454 <enum name="a4xx_state_block">
455 <!--
456 unknown: 0x7 and 0xf <- seen in compute shader
457
458 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
459 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
460 the gpuaddr of the following shader constants block. DST_OFF seems
461 to specify which shader stage:
462
463 16 -> vert
464 36 -> tcs
465 56 -> tes
466 76 -> geom
467 96 -> frag
468
469 Example:
470
471 opcode: CP_LOAD_STATE4 (30) (12 dwords)
472 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
473 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
474 { EXT_SRC_ADDR_HI = 0 }
475 0000: c0264100 00000000 00000000 00000000
476 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
477
478 opcode: CP_LOAD_STATE4 (30) (4 dwords)
479 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
480 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
481 { EXT_SRC_ADDR_HI = 0 }
482 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
483 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
484 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
485
486 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
487
488 -->
489 <value name="SB4_VS_TEX" value="0x0"/>
490 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
491 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
492 <value name="SB4_GS_TEX" value="0x3"/>
493 <value name="SB4_FS_TEX" value="0x4"/>
494 <value name="SB4_CS_TEX" value="0x5"/>
495 <value name="SB4_VS_SHADER" value="0x8"/>
496 <value name="SB4_HS_SHADER" value="0x9"/>
497 <value name="SB4_DS_SHADER" value="0xa"/>
498 <value name="SB4_GS_SHADER" value="0xb"/>
499 <value name="SB4_FS_SHADER" value="0xc"/>
500 <value name="SB4_CS_SHADER" value="0xd"/>
501 <!--
502 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
503 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
504
505 Compute has it's own dedicated SSBO state, it seems, but the rest
506 of the stages share state
507 -->
508 <value name="SB4_SSBO" value="0xe"/>
509 <value name="SB4_CS_SSBO" value="0xf"/>
510 </enum>
511 <enum name="a4xx_state_type">
512 <value name="ST4_SHADER" value="0"/>
513 <value name="ST4_CONSTANTS" value="1"/>
514 <value name="ST4_UBO" value="2"/>
515 </enum>
516 <enum name="a4xx_state_src">
517 <value name="SS4_DIRECT" value="0"/>
518 <value name="SS4_INDIRECT" value="2"/>
519 </enum>
520 <reg32 offset="0" name="0">
521 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
522 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
523 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
524 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
525 </reg32>
526 <reg32 offset="1" name="1">
527 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
528 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
529 </reg32>
530 <reg32 offset="2" name="2" variants="A5XX-">
531 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
532 </reg32>
533 </domain>
534
535 <!-- looks basically same CP_LOAD_STATE4 -->
536 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
537 <doc>Load state, a6xx+</doc>
538 <enum name="a6xx_state_block">
539 <value name="SB6_VS_TEX" value="0x0"/>
540 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
541 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
542 <value name="SB6_GS_TEX" value="0x3"/>
543 <value name="SB6_FS_TEX" value="0x4"/>
544 <value name="SB6_CS_TEX" value="0x5"/>
545 <value name="SB6_VS_SHADER" value="0x8"/>
546 <value name="SB6_HS_SHADER" value="0x9"/>
547 <value name="SB6_DS_SHADER" value="0xa"/>
548 <value name="SB6_GS_SHADER" value="0xb"/>
549 <value name="SB6_FS_SHADER" value="0xc"/>
550 <value name="SB6_CS_SHADER" value="0xd"/>
551 <value name="SB6_IBO" value="0xe"/>
552 <value name="SB6_CS_IBO" value="0xf"/>
553 </enum>
554 <enum name="a6xx_state_type">
555 <value name="ST6_SHADER" value="0"/>
556 <value name="ST6_CONSTANTS" value="1"/>
557 <value name="ST6_UBO" value="2"/>
558 <value name="ST6_IBO" value="3"/>
559 </enum>
560 <enum name="a6xx_state_src">
561 <value name="SS6_DIRECT" value="0"/>
562 <value name="SS6_INDIRECT" value="2"/>
563 </enum>
564 <reg32 offset="0" name="0">
565 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
566 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
567 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
568 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
569 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
570 </reg32>
571 <reg32 offset="1" name="1">
572 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
573 </reg32>
574 <reg32 offset="2" name="2">
575 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
576 </reg32>
577 </domain>
578
579 <bitset name="vgt_draw_initiator" inline="yes">
580 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
581 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
582 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
583 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
584 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
585 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
586 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
587 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
588 </bitset>
589
590 <!-- changed on a4xx: -->
591 <enum name="a4xx_index_size">
592 <value name="INDEX4_SIZE_8_BIT" value="0"/>
593 <value name="INDEX4_SIZE_16_BIT" value="1"/>
594 <value name="INDEX4_SIZE_32_BIT" value="2"/>
595 </enum>
596
597 <enum name="a6xx_patch_type">
598 <value name="TESS_QUADS" value="0"/>
599 <value name="TESS_TRIANGLES" value="1"/>
600 <value name="TESS_ISOLINES" value="2"/>
601 </enum>
602
603 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
604 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
605 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
606 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
607 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
608 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
609 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
610 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
611 </bitset>
612
613 <domain name="CP_DRAW_INDX" width="32">
614 <reg32 offset="0" name="0">
615 <bitfield name="VIZ_QUERY" low="0" high="31"/>
616 </reg32>
617 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
618 <reg32 offset="2" name="2">
619 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
620 </reg32>
621 <reg32 offset="3" name="3">
622 <bitfield name="INDX_BASE" low="0" high="31"/>
623 </reg32>
624 <reg32 offset="4" name="4">
625 <bitfield name="INDX_SIZE" low="0" high="31"/>
626 </reg32>
627 </domain>
628
629 <domain name="CP_DRAW_INDX_2" width="32">
630 <reg32 offset="0" name="0">
631 <bitfield name="VIZ_QUERY" low="0" high="31"/>
632 </reg32>
633 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
634 <reg32 offset="2" name="2">
635 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
636 </reg32>
637 <!-- followed by NUM_INDICES indices.. -->
638 </domain>
639
640 <domain name="CP_DRAW_INDX_OFFSET" width="32">
641 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
642 <reg32 offset="1" name="1">
643 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
644 </reg32>
645 <reg32 offset="2" name="2">
646 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
647 </reg32>
648 <reg32 offset="3" name="3">
649 </reg32>
650 <reg32 offset="4" name="4">
651 <bitfield name="INDX_BASE" low="0" high="31"/>
652 </reg32>
653 <reg32 offset="5" name="5">
654 <bitfield name="INDX_SIZE" low="0" high="31"/>
655 </reg32>
656 </domain>
657
658 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
659 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
660 <reg32 offset="1" name="1">
661 <bitfield name="INDIRECT" low="0" high="31"/>
662 </reg32>
663 <stripe variants="A5XX-">
664 <reg32 offset="2" name="2">
665 <bitfield name="INDIRECT_HI" low="0" high="31"/>
666 </reg32>
667 </stripe>
668 </domain>
669
670 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
671 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
672 <stripe variants="A4XX">
673 <reg32 offset="1" name="1">
674 <bitfield name="INDX_BASE" low="0" high="31"/>
675 </reg32>
676 <reg32 offset="2" name="2">
677 <!-- max # of bytes in index buffer -->
678 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
679 </reg32>
680 <reg32 offset="3" name="3">
681 <bitfield name="INDIRECT" low="0" high="31"/>
682 </reg32>
683 </stripe>
684 <stripe variants="A5XX-">
685 <reg32 offset="1" name="1">
686 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
687 </reg32>
688 <reg32 offset="2" name="2">
689 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
690 </reg32>
691 <reg32 offset="3" name="3">
692 <!-- max # of elements in index buffer -->
693 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
694 </reg32>
695 <reg32 offset="4" name="4">
696 <bitfield name="INDIRECT_LO" low="0" high="31"/>
697 </reg32>
698 <reg32 offset="5" name="5">
699 <bitfield name="INDIRECT_HI" low="0" high="31"/>
700 </reg32>
701 </stripe>
702 </domain>
703
704 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
705 <array offset="0" name="" stride="3" length="100">
706 <reg32 offset="0" name="0">
707 <bitfield name="COUNT" low="0" high="15" type="uint"/>
708 <bitfield name="DIRTY" pos="16" type="boolean"/>
709 <bitfield name="DISABLE" pos="17" type="boolean"/>
710 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
711 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
712 <!--
713 I think this is a bitmask of states that this group applies to
714 (ie. binning/bypass/gmem)? At least starting w/ a6xx blob
715 emits different VS state at the same time, with ENABLE_MASK=0x1
716 for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
717 -->
718 <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
719 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
720 </reg32>
721 <reg32 offset="1" name="1">
722 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
723 </reg32>
724 <reg32 offset="2" name="2" variants="A5XX-">
725 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
726 </reg32>
727 </array>
728 </domain>
729
730 <domain name="CP_SET_BIN" width="32">
731 <doc>value at offset 0 always seems to be 0x00000000..</doc>
732 <reg32 offset="0" name="0"/>
733 <reg32 offset="1" name="1">
734 <bitfield name="X1" low="0" high="15" type="uint"/>
735 <bitfield name="Y1" low="16" high="31" type="uint"/>
736 </reg32>
737 <reg32 offset="2" name="2">
738 <bitfield name="X2" low="0" high="15" type="uint"/>
739 <bitfield name="Y2" low="16" high="31" type="uint"/>
740 </reg32>
741 </domain>
742
743 <domain name="CP_SET_BIN_DATA" width="32">
744 <reg32 offset="0" name="0">
745 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
746 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
747 </reg32>
748 <reg32 offset="1" name="1">
749 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
750 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
751 </reg32>
752 </domain>
753
754 <domain name="CP_SET_BIN_DATA5" width="32">
755 <reg32 offset="0" name="0">
756 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
757 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
758 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
759 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
760 </reg32>
761 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
762 <reg32 offset="1" name="1">
763 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
764 </reg32>
765 <reg32 offset="2" name="2">
766 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
767 </reg32>
768 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
769 <reg32 offset="3" name="3">
770 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
771 </reg32>
772 <reg32 offset="4" name="4">
773 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
774 </reg32>
775 <!-- what is this new address? -->
776 <reg32 offset="5" name="5">
777 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
778 </reg32>
779 <reg32 offset="6" name="6">
780 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
781 </reg32>
782 </domain>
783
784 <domain name="CP_REG_TO_MEM" width="32">
785 <reg32 offset="0" name="0">
786 <bitfield name="REG" low="0" high="15" type="hex"/>
787 <!--
788 number of regsiters/dwords copied is CNT+1.. unsure
789 about # of bits
790 -->
791 <bitfield name="CNT" low="19" high="29" type="uint"/>
792 <bitfield name="64B" pos="30" type="boolean"/>
793 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
794 </reg32>
795 <reg32 offset="1" name="1">
796 <bitfield name="DEST" low="0" high="31"/>
797 </reg32>
798 <reg32 offset="2" name="2" variants="A5XX-">
799 <bitfield name="DEST_HI" low="0" high="31"/>
800 </reg32>
801 </domain>
802
803 <domain name="CP_MEM_TO_REG" width="32">
804 <reg32 offset="0" name="0">
805 <bitfield name="REG" low="0" high="15" type="hex"/>
806 <!--
807 number of regsiters/dwords copied is CNT+1.. unsure
808 about # of bits
809 -->
810 <bitfield name="CNT" low="19" high="29" type="uint"/>
811 <bitfield name="64B" pos="30" type="boolean"/>
812 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
813 </reg32>
814 <reg32 offset="1" name="1">
815 <bitfield name="SRC" low="0" high="31"/>
816 </reg32>
817 <reg32 offset="2" name="2" variants="A5XX-">
818 <bitfield name="SRC_HI" low="0" high="31"/>
819 </reg32>
820 </domain>
821
822 <domain name="CP_MEM_TO_MEM" width="32">
823 <reg32 offset="0" name="0">
824 <!--
825 not sure how many src operands we have, but the low
826 bits negate the n'th src argument.
827 -->
828 <bitfield name="NEG_A" pos="0" type="boolean"/>
829 <bitfield name="NEG_B" pos="1" type="boolean"/>
830 <bitfield name="NEG_C" pos="2" type="boolean"/>
831
832 <!-- if set treat src/dst as 64bit values -->
833 <bitfield name="DOUBLE" pos="29" type="boolean"/>
834 </reg32>
835 <!--
836 followed by sequence of addresses.. the first is the
837 destination and the rest are N src addresses which are
838 summed (after being negated if NEG_x bit set) allowing
839 to do things like 'result += end - start' (which turns
840 out to be useful for queries and accumulating results
841 across multiple tiles)
842 -->
843 </domain>
844
845 <enum name="cp_cond_function">
846 <value value="0" name="WRITE_ALWAYS"/>
847 <value value="1" name="WRITE_LT"/>
848 <value value="2" name="WRITE_LE"/>
849 <value value="3" name="WRITE_EQ"/>
850 <value value="4" name="WRITE_NE"/>
851 <value value="5" name="WRITE_GE"/>
852 <value value="6" name="WRITE_GT"/>
853 </enum>
854
855 <domain name="CP_COND_WRITE" width="32">
856 <reg32 offset="0" name="0">
857 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
858 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
859 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
860 </reg32>
861 <reg32 offset="1" name="1">
862 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
863 </reg32>
864 <reg32 offset="2" name="2">
865 <bitfield name="REF" low="0" high="31"/>
866 </reg32>
867 <reg32 offset="3" name="3">
868 <bitfield name="MASK" low="0" high="31"/>
869 </reg32>
870 <reg32 offset="4" name="4">
871 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
872 </reg32>
873 <reg32 offset="5" name="5">
874 <bitfield name="WRITE_DATA" low="0" high="31"/>
875 </reg32>
876 </domain>
877
878 <domain name="CP_COND_WRITE5" width="32">
879 <reg32 offset="0" name="0">
880 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
881 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
882 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
883 </reg32>
884 <reg32 offset="1" name="1">
885 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
886 </reg32>
887 <reg32 offset="2" name="2">
888 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
889 </reg32>
890 <reg32 offset="3" name="3">
891 <bitfield name="REF" low="0" high="31"/>
892 </reg32>
893 <reg32 offset="4" name="4">
894 <bitfield name="MASK" low="0" high="31"/>
895 </reg32>
896 <reg32 offset="5" name="5">
897 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
898 </reg32>
899 <reg32 offset="6" name="6">
900 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
901 </reg32>
902 <reg32 offset="7" name="7">
903 <bitfield name="WRITE_DATA" low="0" high="31"/>
904 </reg32>
905 </domain>
906
907 <domain name="CP_DISPATCH_COMPUTE" width="32">
908 <reg32 offset="0" name="0"/>
909 <reg32 offset="1" name="1">
910 <bitfield name="X" low="0" high="31"/>
911 </reg32>
912 <reg32 offset="2" name="2">
913 <bitfield name="Y" low="0" high="31"/>
914 </reg32>
915 <reg32 offset="3" name="3">
916 <bitfield name="Z" low="0" high="31"/>
917 </reg32>
918 </domain>
919
920 <domain name="CP_SET_RENDER_MODE" width="32">
921 <enum name="render_mode_cmd">
922 <value value="1" name="BYPASS"/>
923 <value value="2" name="BINNING"/>
924 <value value="3" name="GMEM"/>
925 <value value="5" name="BLIT2D"/>
926 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
927 <value value="7" name="BLIT2DSCALE"/>
928 <!-- 8 set before going back to BYPASS exiting 2D -->
929 <value value="8" name="END2D"/>
930 </enum>
931 <reg32 offset="0" name="0">
932 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
933 <!--
934 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
935 0x21xx range.. possibly (at least some) a5xx variants have a
936 2d core?
937 -->
938 </reg32>
939 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
940 <reg32 offset="1" name="1">
941 <bitfield name="ADDR_0_LO" low="0" high="31"/>
942 </reg32>
943 <reg32 offset="2" name="2">
944 <bitfield name="ADDR_0_HI" low="0" high="31"/>
945 </reg32>
946 <reg32 offset="3" name="3">
947 <!--
948 set when in GMEM.. maybe indicates GMEM contents need to be
949 preserved on ctx switch?
950 -->
951 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
952 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
953 </reg32>
954 <reg32 offset="4" name="4"/>
955 <!-- second buffer looks like some cmdstream.. length in dwords: -->
956 <reg32 offset="5" name="5">
957 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
958 </reg32>
959 <reg32 offset="6" name="6">
960 <bitfield name="ADDR_1_LO" low="0" high="31"/>
961 </reg32>
962 <reg32 offset="7" name="7">
963 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
964 </reg32>
965 </domain>
966
967 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
968 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
969 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
970 <reg32 offset="0" name="0">
971 <bitfield name="ADDR_0_LO" low="0" high="31"/>
972 </reg32>
973 <reg32 offset="1" name="1">
974 <bitfield name="ADDR_0_HI" low="0" high="31"/>
975 </reg32>
976 <reg32 offset="2" name="2">
977 </reg32>
978 <!-- second buffer looks like some cmdstream.. length in dwords: -->
979 <reg32 offset="3" name="3">
980 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
981 </reg32>
982 <reg32 offset="4" name="4"/>
983 <reg32 offset="5" name="5">
984 <bitfield name="ADDR_1_LO" low="0" high="31"/>
985 </reg32>
986 <reg32 offset="6" name="6">
987 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
988 </reg32>
989 <reg32 offset="7" name="7"/>
990 </domain>
991
992 <domain name="CP_PERFCOUNTER_ACTION" width="32">
993 <reg32 offset="0" name="0">
994 </reg32>
995 <reg32 offset="1" name="1">
996 <bitfield name="ADDR_0_LO" low="0" high="31"/>
997 </reg32>
998 <reg32 offset="2" name="2">
999 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1000 </reg32>
1001 </domain>
1002
1003 <domain name="CP_EVENT_WRITE" width="32">
1004 <reg32 offset="0" name="0">
1005 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1006 <!-- when set, write back timestamp instead of value from packet: -->
1007 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1008 </reg32>
1009 <!--
1010 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1011 context switch?
1012 -->
1013 <reg32 offset="1" name="1">
1014 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1015 </reg32>
1016 <reg32 offset="2" name="2">
1017 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1018 </reg32>
1019 <reg32 offset="3" name="3">
1020 <!-- ??? -->
1021 </reg32>
1022 </domain>
1023
1024 <domain name="CP_BLIT" width="32">
1025 <enum name="cp_blit_cmd">
1026 <value value="0" name="BLIT_OP_FILL"/>
1027 <value value="1" name="BLIT_OP_COPY"/>
1028 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1029 </enum>
1030 <reg32 offset="0" name="0">
1031 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1032 </reg32>
1033 <reg32 offset="1" name="1">
1034 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1035 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1036 </reg32>
1037 <reg32 offset="2" name="2">
1038 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1039 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1040 </reg32>
1041 <reg32 offset="3" name="3">
1042 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1043 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1044 </reg32>
1045 <reg32 offset="4" name="4">
1046 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1047 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1048 </reg32>
1049 </domain>
1050
1051 <domain name="CP_EXEC_CS" width="32">
1052 <reg32 offset="0" name="0">
1053 </reg32>
1054 <reg32 offset="1" name="1">
1055 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1056 </reg32>
1057 <reg32 offset="2" name="2">
1058 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1059 </reg32>
1060 <reg32 offset="3" name="3">
1061 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1062 </reg32>
1063 </domain>
1064
1065 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1066 <reg32 offset="0" name="0">
1067 </reg32>
1068 <stripe variants="A4XX">
1069 <reg32 offset="1" name="1">
1070 <bitfield name="ADDR" low="0" high="31"/>
1071 </reg32>
1072 <reg32 offset="2" name="2">
1073 <!-- localsize is value minus one: -->
1074 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1075 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1076 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1077 </reg32>
1078 </stripe>
1079 <stripe variants="A5XX-">
1080 <reg32 offset="1" name="1">
1081 <bitfield name="ADDR_LO" low="0" high="31"/>
1082 </reg32>
1083 <reg32 offset="2" name="2">
1084 <bitfield name="ADDR_HI" low="0" high="31"/>
1085 </reg32>
1086 <reg32 offset="3" name="3">
1087 <!-- localsize is value minus one: -->
1088 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1089 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1090 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1091 </reg32>
1092 </stripe>
1093 </domain>
1094
1095 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1096 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1097 <enum name="a6xx_render_mode">
1098 <value value="1" name="RM6_BYPASS"/>
1099 <value value="2" name="RM6_BINNING"/>
1100 <value value="4" name="RM6_GMEM"/>
1101 <value value="5" name="RM6_BLIT2D"/>
1102 <value value="6" name="RM6_RESOLVE"/>
1103 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1104 </enum>
1105 <reg32 offset="0" name="0">
1106 <bitfield name="MARKER" low="0" high="3"/>
1107 <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
1108 <!-- IFPC - inter-frame power collapse -->
1109 <bitfield name="IFPC" pos="8" type="boolean"/>
1110 </reg32>
1111 </domain>
1112
1113 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1114 <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1115 <enum name="pseudo_reg">
1116 <value value="0" name="SMMU_INFO"/>
1117 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1118 <value value="2" name="SECURE_SAVE_ADDR"/>
1119 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1120 <value value="4" name="COUNTER"/>
1121 </enum>
1122 <array offset="0" name="" stride="3" length="100">
1123 <reg32 offset="0" name="0">
1124 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1125 </reg32>
1126 <reg32 offset="1" name="1">
1127 <bitfield name="LO" low="0" high="31"/>
1128 </reg32>
1129 <reg32 offset="2" name="2">
1130 <bitfield name="HI" low="0" high="31"/>
1131 </reg32>
1132 </array>
1133 </domain>
1134
1135 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1136 <doc>
1137 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1138 So:
1139
1140 opcode: CP_REG_TEST (39) (2 dwords)
1141 { REG = 0xc10 | BIT = 0 }
1142 0000: 70b90001 00000c10
1143 opcode: CP_COND_REG_EXEC (47) (3 dwords)
1144 0000: 70c70002 10000000 00000004
1145 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1146
1147 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1148 offset 0x0c10 is 1
1149 </doc>
1150 <reg32 offset="0" name="0">
1151 <!-- the register to test -->
1152 <bitfield name="REG" low="0" high="11"/>
1153 <!-- the bit to test -->
1154 <bitfield name="BIT" low="20" high="24" type="uint"/>
1155 <bitfield name="UNK25" pos="25" type="boolean"/>
1156 </reg32>
1157 </domain>
1158
1159 </database>
1160