src/freedreno/registers/adreno_pm4.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="vgt_event_type">
   7         <value name="VS_DEALLOC" value="0"/>
   8         <value name="PS_DEALLOC" value="1"/>
   9         <value name="VS_DONE_TS" value="2"/>
  10         <value name="PS_DONE_TS" value="3"/>
  11         <value name="CACHE_FLUSH_TS" value="4"/>
  12         <value name="CONTEXT_DONE" value="5"/>
  13         <value name="CACHE_FLUSH" value="6"/>
  14         <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
  15         <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
  16         <value name="VIZQUERY_END" value="8"/>
  17         <value name="SC_WAIT_WC" value="9"/>
  18         <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
  19         <value name="RST_PIX_CNT" value="13"/>
  20         <value name="RST_VTX_CNT" value="14"/>
  21         <value name="TILE_FLUSH" value="15"/>
  22         <value name="STAT_EVENT" value="16"/>
  23         <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
  24         <value name="ZPASS_DONE" value="21"/>
  25         <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
  26         <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
  27         <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
  28         <value name="VS_FETCH_DONE" value="27"/>
  29         <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
  30
  31         <!-- a5xx events -->
  32         <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
  33         <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
  34         <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
  35         <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
  36         <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
  37         <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
  38         <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
  39         <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
  40         <value name="BLIT" value="30" variants="A5XX,A6XX"/>
  41         <value name="UNK_25" value="37" variants="A5XX"/>
  42         <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
  43         <value name="UNK_2C" value="44" variants="A5XX"/>
  44         <value name="UNK_2D" value="45" variants="A5XX"/>
  45
  46         <!-- a6xx events -->
  47         <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
  48 </enum>
  49
  50 <enum name="pc_di_primtype">
  51         <value name="DI_PT_NONE" value="0"/>
  52         <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
  53         <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
  54         <value name="DI_PT_LINELIST" value="2"/>
  55         <value name="DI_PT_LINESTRIP" value="3"/>
  56         <value name="DI_PT_TRILIST" value="4"/>
  57         <value name="DI_PT_TRIFAN" value="5"/>
  58         <value name="DI_PT_TRISTRIP" value="6"/>
  59         <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
  60         <value name="DI_PT_RECTLIST" value="8"/>
  61         <value name="DI_PT_POINTLIST" value="9"/>
  62         <value name="DI_PT_LINE_ADJ" value="0xa"/>
  63         <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
  64         <value name="DI_PT_TRI_ADJ" value="0xc"/>
  65         <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
  66         <value name="DI_PT_PATCHES" value="0x29"/>
  67 </enum>
  68
  69 <enum name="pc_di_src_sel">
  70         <value name="DI_SRC_SEL_DMA" value="0"/>
  71         <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
  72         <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
  73         <value name="DI_SRC_SEL_RESERVED" value="3"/>
  74 </enum>
  75
  76 <enum name="pc_di_face_cull_sel">
  77         <value name="DI_FACE_CULL_NONE" value="0"/>
  78         <value name="DI_FACE_CULL_FETCH" value="1"/>
  79         <value name="DI_FACE_BACKFACE_CULL" value="2"/>
  80         <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
  81 </enum>
  82
  83 <enum name="pc_di_index_size">
  84         <value name="INDEX_SIZE_IGN" value="0"/>
  85         <value name="INDEX_SIZE_16_BIT" value="0"/>
  86         <value name="INDEX_SIZE_32_BIT" value="1"/>
  87         <value name="INDEX_SIZE_8_BIT" value="2"/>
  88         <value name="INDEX_SIZE_INVALID"/>
  89 </enum>
  90
  91 <enum name="pc_di_vis_cull_mode">
  92         <value name="IGNORE_VISIBILITY" value="0"/>
  93         <value name="USE_VISIBILITY" value="1"/>
  94 </enum>
  95
  96 <enum name="adreno_pm4_packet_type">
  97         <value name="CP_TYPE0_PKT" value="0x00000000"/>
  98         <value name="CP_TYPE1_PKT" value="0x40000000"/>
  99         <value name="CP_TYPE2_PKT" value="0x80000000"/>
 100         <value name="CP_TYPE3_PKT" value="0xc0000000"/>
 101         <value name="CP_TYPE4_PKT" value="0x40000000"/>
 102         <value name="CP_TYPE7_PKT" value="0x70000000"/>
 103 </enum>
 104
 105 <!--
 106    Note that in some cases, the same packet id is recycled on a later
 107    generation, so variants attribute is used to distinguish.   They
 108    may not be completely accurate, we would probably have to analyze
 109    the pfp and me/pm4 firmware to verify the packet is actually
 110    handled on a particular generation.  But it is at least enough to
 111    disambiguate the packet-id's that were re-used for different
 112    packets starting with a5xx.
 113  -->
 114 <enum name="adreno_pm4_type3_packets">
 115         <doc>initialize CP's micro-engine</doc>
 116         <value name="CP_ME_INIT" value="0x48"/>
 117         <doc>skip N 32-bit words to get to the next packet</doc>
 118         <value name="CP_NOP" value="0x10"/>
 119         <doc>
 120                 indirect buffer dispatch.  prefetch parser uses this packet
 121                 type to determine whether to pre-fetch the IB
 122         </doc>
 123         <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 124         <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 125         <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
 126         <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 127         <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 128         <doc>wait for the IDLE state of the engine</doc>
 129         <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
 130         <doc>wait until a register or memory location is a specific value</doc>
 131         <value name="CP_WAIT_REG_MEM" value="0x3c"/>
 132         <doc>wait until a register location is equal to a specific value</doc>
 133         <value name="CP_WAIT_REG_EQ" value="0x52"/>
 134         <doc>wait until a register location is >= a specific value</doc>
 135         <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
 136         <doc>wait until a read completes</doc>
 137         <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
 138         <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
 139         <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
 140         <doc>register read/modify/write</doc>
 141         <value name="CP_REG_RMW" value="0x21"/>
 142         <doc>Set binning configuration registers</doc>
 143         <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
 144         <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
 145         <doc>reads register in chip and writes to memory</doc>
 146         <value name="CP_REG_TO_MEM" value="0x3e"/>
 147         <doc>write N 32-bit words to memory</doc>
 148         <value name="CP_MEM_WRITE" value="0x3d"/>
 149         <doc>write CP_PROG_COUNTER value to memory</doc>
 150         <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
 151         <doc>conditional execution of a sequence of packets</doc>
 152         <value name="CP_COND_EXEC" value="0x44"/>
 153         <doc>conditional write to memory or register</doc>
 154         <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
 155         <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
 156         <doc>generate an event that creates a write to memory when completed</doc>
 157         <value name="CP_EVENT_WRITE" value="0x46"/>
 158         <doc>generate a VS|PS_done event</doc>
 159         <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
 160         <doc>generate a cache flush done event</doc>
 161         <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
 162         <doc>generate a z_pass done event</doc>
 163         <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
 164         <doc>
 165                 not sure the real name, but this seems to be what is used for
 166                 opencl, instead of CP_DRAW_INDX..
 167         </doc>
 168         <value name="CP_RUN_OPENCL" value="0x31"/>
 169         <doc>initiate fetch of index buffer and draw</doc>
 170         <value name="CP_DRAW_INDX" value="0x22"/>
 171         <doc>draw using supplied indices in packet</doc>
 172         <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
 173         <doc>initiate fetch of index buffer and binIDs and draw</doc>
 174         <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
 175         <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
 176         <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
 177         <doc>begin/end initiator for viz query extent processing</doc>
 178         <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
 179         <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
 180         <value name="CP_SET_STATE" value="0x25"/>
 181         <doc>load constant into chip and to memory</doc>
 182         <value name="CP_SET_CONSTANT" value="0x2d"/>
 183         <doc>load sequencer instruction memory (pointer-based)</doc>
 184         <value name="CP_IM_LOAD" value="0x27"/>
 185         <doc>load sequencer instruction memory (code embedded in packet)</doc>
 186         <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 187         <doc>load constants from a location in memory</doc>
 188         <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
 189         <doc>selective invalidation of state pointers</doc>
 190         <value name="CP_INVALIDATE_STATE" value="0x3b"/>
 191         <doc>dynamically changes shader instruction memory partition</doc>
 192         <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
 193         <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
 194         <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
 195         <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
 196         <value name="CP_SET_BIN_SELECT" value="0x51"/>
 197         <doc>updates the current context, if needed</doc>
 198         <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
 199         <doc>generate interrupt from the command stream</doc>
 200         <value name="CP_INTERRUPT" value="0x40"/>
 201         <doc>copy sequencer instruction memory to system memory</doc>
 202         <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
 203
 204         <!-- For a20x -->
 205 <!-- TODO handle variants..
 206         <doc>
 207                 Program an offset that will added to the BIN_BASE value of
 208                 the 3D_DRAW_INDX_BIN packet
 209         </doc>
 210         <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
 211  -->
 212
 213         <!-- for a22x -->
 214         <doc>
 215                 sets draw initiator flags register in PFP, gets bitwise-ORed into
 216                 every draw initiator
 217         </doc>
 218         <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
 219         <doc>sets the register protection mode</doc>
 220         <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
 221
 222         <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
 223
 224         <!-- for a3xx -->
 225         <doc>load high level sequencer command</doc>
 226         <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
 227         <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
 228         <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
 229         <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
 230         <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
 231         <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
 232         <doc>Load a buffer with pre-fetch enabled</doc>
 233         <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 234         <doc>Set bin (?)</doc>
 235         <value name="CP_SET_BIN" value="0x4c"/>
 236
 237         <doc>test 2 memory locations to dword values specified</doc>
 238         <value name="CP_TEST_TWO_MEMS" value="0x71"/>
 239
 240         <doc>Write register, ignoring context state for context sensitive registers</doc>
 241         <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
 242
 243         <doc>Record the real-time when this packet is processed by PFP</doc>
 244         <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
 245
 246         <!-- Used to switch GPU between secure and non-secure modes -->
 247         <value name="CP_SET_SECURE_MODE" value="0x66"/>
 248
 249         <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
 250         <value name="CP_WAIT_FOR_ME" value="0x13"/>
 251
 252         <!-- for a4xx -->
 253         <doc>
 254                 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
 255                 groups of registers.  Looks like it can be used to create state
 256                 objects in GPU memory, and on state change only emit pointer
 257                 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
 258                 overhead:
 259
 260                 (A4x) save PM4 stream pointers to execute upon a visible draw
 261         </doc>
 262         <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
 263         <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
 264         <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
 265         <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
 266         <value name="CP_DRAW_AUTO" value="0x24"/>
 267
 268         <value name="CP_UNKNOWN_19" value="0x19"/>
 269
 270         <doc>set to 1 for fastclear..:</doc>
 271         <value name="CP_UNKNOWN_1A" value="0x1a"/>
 272
 273         <value name="CP_UNKNOWN_4E" value="0x4e"/>
 274
 275         <doc>
 276                 for A4xx
 277                 Write to register with address that does not fit into type-0 pkt
 278         </doc>
 279         <value name="CP_WIDE_REG_WRITE" value="0x74"/>
 280
 281         <doc>copy from ME scratch RAM to a register</doc>
 282         <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
 283
 284         <doc>Copy from REG to ME scratch RAM</doc>
 285         <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
 286
 287         <doc>Wait for memory writes to complete</doc>
 288         <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
 289
 290         <doc>Conditional execution based on register comparison</doc>
 291         <value name="CP_COND_REG_EXEC" value="0x47"/>
 292
 293         <doc>Memory to REG copy</doc>
 294         <value name="CP_MEM_TO_REG" value="0x42"/>
 295
 296         <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
 297         <value name="CP_EXEC_CS" value="0x33"/>
 298
 299         <doc>
 300                 for a5xx
 301         </doc>
 302         <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 303         <!-- switches SMMU pagetable, used on a5xx only -->
 304         <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
 305         <!-- for a6xx -->
 306         <doc>Tells CP the current mode of GPU operation</doc>
 307         <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
 308         <doc>Instruct CP to set a few internal CP registers</doc>
 309         <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 310         <!--
 311         pairs of regid and value.. seems to be used to program some TF
 312         related regs:
 313          -->
 314         <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
 315         <!-- A5XX Enable yield in RB only -->
 316         <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
 317         <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
 318         <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
 319         <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
 320         <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
 321         <!-- Enable/Disable/Defer A5x global preemption model -->
 322         <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
 323         <!-- Enable/Disable A5x local preemption model -->
 324         <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
 325         <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
 326         <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
 327         <!-- Inform CP about current render mode (needed for a5xx preemption) -->
 328         <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
 329         <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
 330         <!-- check if this works on earlier.. -->
 331         <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
 332         <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
 333
 334         <!-- Test specified bit in specified register and set predicate -->
 335         <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
 336
 337         <!--
 338         Seems to set the mode flags which control which CP_SET_DRAW_STATE
 339         packets are executed, based on their ENABLE_MASK values
 340
 341         CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
 342         packets w/ ENABLE_MASK & 0x6 to execute immediately
 343          -->
 344         <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
 345
 346         <!--
 347         Seems like there are now separate blocks of state for VS vs FS/CS
 348         (probably these amounts to geometry vs fragments so that geometry
 349         stage of the pipeline for next draw can start while fragment stage
 350         of current draw is still running.  The format of the payload of the
 351         packets is the same, the only difference is the offsets of the regs
 352         the firmware code that handles the packet writes.
 353
 354         Note that for CL, starting with a6xx, the preferred # of local
 355         threads is no longer the same as the max, implying that the shader
 356         core can now run warps from unrelated shaders (ie.
 357         CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
 358         CL_KERNEL_WORK_GROUP_SIZE)
 359          -->
 360         <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
 361         <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
 362         <!--
 363         Note: For IBO state (Image/SSBOs) which have shared state across
 364         shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
 365         compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
 366         interchangable.
 367          -->
 368         <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
 369
 370         <!-- internal packets: -->
 371         <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
 372         <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
 373         <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
 374         <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
 375         <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
 376         <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
 377         <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
 378         <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
 379
 380         <!-- jmptable entry used to handle type4 packet on a5xx+: -->
 381         <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
 382 <!--
 383 unknown a6xx opcodes:
 384
 385 opcode: (null) (14) (5 dwords)
 386 opcode: (null) (55) (4 dwords)
 387 opcode: (null) (6d) (4 dwords)
 388  -->
 389         <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
 390         <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
 391
 392         <!--
 393         Seems to always have the payload:
 394           00000002 00008801 00004010
 395         or:
 396           00000002 00008801 00004090
 397         or:
 398           00000002 00008801 00000010
 399           00000002 00008801 00010010
 400           00000002 00008801 00d64010
 401           ...
 402         Note set for compute shaders..
 403         Is 0x8801 a register offset?
 404         This appears to be a special sort of register write packet
 405         more or less, but the firmware has some special handling..
 406         Seems like it intercepts/modifies certain register offsets,
 407         but others are treated like a normal PKT4 reg write.  I
 408         guess there are some registers that the fw controls certain
 409         bits.
 410          -->
 411         <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
 412
 413 </enum>
 414
 415
 416 <domain name="CP_LOAD_STATE" width="32">
 417         <doc>Load state, a3xx (and later?)</doc>
 418         <enum name="adreno_state_block">
 419                 <value name="SB_VERT_TEX" value="0"/>
 420                 <value name="SB_VERT_MIPADDR" value="1"/>
 421                 <value name="SB_FRAG_TEX" value="2"/>
 422                 <value name="SB_FRAG_MIPADDR" value="3"/>
 423                 <value name="SB_VERT_SHADER" value="4"/>
 424                 <value name="SB_GEOM_SHADER" value="5"/>
 425                 <value name="SB_FRAG_SHADER" value="6"/>
 426                 <value name="SB_COMPUTE_SHADER" value="7"/>
 427         </enum>
 428         <enum name="adreno_state_type">
 429                 <value name="ST_SHADER" value="0"/>
 430                 <value name="ST_CONSTANTS" value="1"/>
 431         </enum>
 432         <enum name="adreno_state_src">
 433                 <value name="SS_DIRECT" value="0">
 434                         <doc>inline with the CP_LOAD_STATE packet</doc>
 435                 </value>
 436                 <value name="SS_INVALID_ALL_IC" value="2"/>
 437                 <value name="SS_INVALID_PART_IC" value="3"/>
 438                 <value name="SS_INDIRECT" value="4">
 439                         <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
 440                 </value>
 441                 <value name="SS_INDIRECT_TCM" value="5"/>
 442                 <value name="SS_INDIRECT_STM" value="6"/>
 443         </enum>
 444         <reg32 offset="0" name="0">
 445                 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
 446                 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
 447                 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
 448                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 449         </reg32>
 450         <reg32 offset="1" name="1">
 451                 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
 452                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 453         </reg32>
 454 </domain>
 455
 456 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
 457         <doc>Load state, a4xx+</doc>
 458         <enum name="a4xx_state_block">
 459                 <!--
 460                 unknown: 0x7 and 0xf <- seen in compute shader
 461
 462                 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
 463                 Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
 464                 the gpuaddr of the following shader constants block.  DST_OFF seems
 465                 to specify which shader stage:
 466
 467                     16 -> vert
 468                     36 -> tcs
 469                     56 -> tes
 470                     76 -> geom
 471                     96 -> frag
 472
 473                 Example:
 474
 475 opcode: CP_LOAD_STATE4 (30) (12 dwords)
 476         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
 477         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
 478         { EXT_SRC_ADDR_HI = 0 }
 479                         0000: c0264100 00000000 00000000 00000000
 480                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
 481
 482 opcode: CP_LOAD_STATE4 (30) (4 dwords)
 483         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 484         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
 485         { EXT_SRC_ADDR_HI = 0 }
 486                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 487                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 488                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
 489
 490                 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
 491
 492                  -->
 493                 <value name="SB4_VS_TEX"    value="0x0"/>
 494                 <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 495                 <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 496                 <value name="SB4_GS_TEX"    value="0x3"/>
 497                 <value name="SB4_FS_TEX"    value="0x4"/>
 498                 <value name="SB4_CS_TEX"    value="0x5"/>
 499                 <value name="SB4_VS_SHADER" value="0x8"/>
 500                 <value name="SB4_HS_SHADER" value="0x9"/>
 501                 <value name="SB4_DS_SHADER" value="0xa"/>
 502                 <value name="SB4_GS_SHADER" value="0xb"/>
 503                 <value name="SB4_FS_SHADER" value="0xc"/>
 504                 <value name="SB4_CS_SHADER" value="0xd"/>
 505                 <!--
 506                 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
 507                 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
 508
 509                 Compute has it's own dedicated SSBO state, it seems, but the rest
 510                 of the stages share state
 511                  -->
 512                 <value name="SB4_SSBO"   value="0xe"/>
 513                 <value name="SB4_CS_SSBO"   value="0xf"/>
 514         </enum>
 515         <enum name="a4xx_state_type">
 516                 <value name="ST4_SHADER" value="0"/>
 517                 <value name="ST4_CONSTANTS" value="1"/>
 518                 <value name="ST4_UBO" value="2"/>
 519         </enum>
 520         <enum name="a4xx_state_src">
 521                 <value name="SS4_DIRECT" value="0"/>
 522                 <value name="SS4_INDIRECT" value="2"/>
 523         </enum>
 524         <reg32 offset="0" name="0">
 525                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 526                 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
 527                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
 528                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 529         </reg32>
 530         <reg32 offset="1" name="1">
 531                 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
 532                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 533         </reg32>
 534         <reg32 offset="2" name="2" variants="A5XX-">
 535                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 536         </reg32>
 537 </domain>
 538
 539 <!-- looks basically same CP_LOAD_STATE4 -->
 540 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
 541         <doc>Load state, a6xx+</doc>
 542         <enum name="a6xx_state_block">
 543                 <value name="SB6_VS_TEX"    value="0x0"/>
 544                 <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 545                 <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 546                 <value name="SB6_GS_TEX"    value="0x3"/>
 547                 <value name="SB6_FS_TEX"    value="0x4"/>
 548                 <value name="SB6_CS_TEX"    value="0x5"/>
 549                 <value name="SB6_VS_SHADER" value="0x8"/>
 550                 <value name="SB6_HS_SHADER" value="0x9"/>
 551                 <value name="SB6_DS_SHADER" value="0xa"/>
 552                 <value name="SB6_GS_SHADER" value="0xb"/>
 553                 <value name="SB6_FS_SHADER" value="0xc"/>
 554                 <value name="SB6_CS_SHADER" value="0xd"/>
 555                 <value name="SB6_IBO"       value="0xe"/>
 556                 <value name="SB6_CS_IBO"    value="0xf"/>
 557         </enum>
 558         <enum name="a6xx_state_type">
 559                 <value name="ST6_SHADER" value="0"/>
 560                 <value name="ST6_CONSTANTS" value="1"/>
 561                 <value name="ST6_UBO" value="2"/>
 562                 <value name="ST6_IBO" value="3"/>
 563         </enum>
 564         <enum name="a6xx_state_src">
 565                 <value name="SS6_DIRECT" value="0"/>
 566                 <value name="SS6_INDIRECT" value="2"/>
 567         </enum>
 568         <reg32 offset="0" name="0">
 569                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 570                 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
 571                 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
 572                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
 573                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 574         </reg32>
 575         <reg32 offset="1" name="1">
 576                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 577         </reg32>
 578         <reg32 offset="2" name="2">
 579                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 580         </reg32>
 581 </domain>
 582
 583 <bitset name="vgt_draw_initiator" inline="yes">
 584         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 585         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 586         <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
 587         <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
 588         <bitfield name="NOT_EOP" pos="12" type="boolean"/>
 589         <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
 590         <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
 591         <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
 592 </bitset>
 593
 594 <!-- changed on a4xx: -->
 595 <enum name="a4xx_index_size">
 596         <value name="INDEX4_SIZE_8_BIT" value="0"/>
 597         <value name="INDEX4_SIZE_16_BIT" value="1"/>
 598         <value name="INDEX4_SIZE_32_BIT" value="2"/>
 599 </enum>
 600
 601 <enum name="a6xx_patch_type">
 602   <value name="TESS_QUADS" value="0"/>
 603   <value name="TESS_TRIANGLES" value="1"/>
 604   <value name="TESS_ISOLINES" value="2"/>
 605 </enum>
 606
 607 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
 608         <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
 609         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 610         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 611         <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 612         <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 613         <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
 614         <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 615 </bitset>
 616
 617 <domain name="CP_DRAW_INDX" width="32">
 618         <reg32 offset="0" name="0">
 619                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 620         </reg32>
 621         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 622         <reg32 offset="2" name="2">
 623                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 624         </reg32>
 625         <reg32 offset="3" name="3">
 626                 <bitfield name="INDX_BASE" low="0" high="31"/>
 627         </reg32>
 628         <reg32 offset="4" name="4">
 629                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 630         </reg32>
 631 </domain>
 632
 633 <domain name="CP_DRAW_INDX_2" width="32">
 634         <reg32 offset="0" name="0">
 635                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 636         </reg32>
 637         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 638         <reg32 offset="2" name="2">
 639                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 640         </reg32>
 641         <!-- followed by NUM_INDICES indices.. -->
 642 </domain>
 643
 644 <domain name="CP_DRAW_INDX_OFFSET" width="32">
 645         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 646         <reg32 offset="1" name="1">
 647                 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
 648         </reg32>
 649         <reg32 offset="2" name="2">
 650                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 651         </reg32>
 652         <reg32 offset="3" name="3">
 653         </reg32>
 654         <reg32 offset="4" name="4">
 655                 <bitfield name="INDX_BASE" low="0" high="31"/>
 656         </reg32>
 657         <reg32 offset="5" name="5">
 658                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 659         </reg32>
 660 </domain>
 661
 662 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 663         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 664         <reg32 offset="1" name="1">
 665                 <bitfield name="INDIRECT" low="0" high="31"/>
 666         </reg32>
 667         <stripe variants="A5XX-">
 668                 <reg32 offset="2" name="2">
 669                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 670                 </reg32>
 671         </stripe>
 672 </domain>
 673
 674 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 675         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 676         <stripe variants="A4XX">
 677                 <reg32 offset="1" name="1">
 678                         <bitfield name="INDX_BASE" low="0" high="31"/>
 679                 </reg32>
 680                 <reg32 offset="2" name="2">
 681                         <!-- max # of bytes in index buffer -->
 682                         <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
 683                 </reg32>
 684                 <reg32 offset="3" name="3">
 685                         <bitfield name="INDIRECT" low="0" high="31"/>
 686                 </reg32>
 687         </stripe>
 688         <stripe variants="A5XX-">
 689                 <reg32 offset="1" name="1">
 690                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 691                 </reg32>
 692                 <reg32 offset="2" name="2">
 693                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 694                 </reg32>
 695                 <reg32 offset="3" name="3">
 696                         <!-- max # of elements in index buffer -->
 697                         <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
 698                 </reg32>
 699                 <reg32 offset="4" name="4">
 700                         <bitfield name="INDIRECT_LO" low="0" high="31"/>
 701                 </reg32>
 702                 <reg32 offset="5" name="5">
 703                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 704                 </reg32>
 705         </stripe>
 706 </domain>
 707
 708 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
 709         <array offset="0" name="" stride="3" length="100">
 710                 <reg32 offset="0" name="0">
 711                         <bitfield name="COUNT" low="0" high="15" type="uint"/>
 712                         <bitfield name="DIRTY" pos="16" type="boolean"/>
 713                         <bitfield name="DISABLE" pos="17" type="boolean"/>
 714                         <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 715                         <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
 716                         <!--
 717                         I think this is a bitmask of states that this group applies to
 718                         (ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
 719                         emits different VS state at the same time, with ENABLE_MASK=0x1
 720                         for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
 721                         -->
 722                         <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
 723                         <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 724                 </reg32>
 725                 <reg32 offset="1" name="1">
 726                         <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
 727                 </reg32>
 728                 <reg32 offset="2" name="2" variants="A5XX-">
 729                         <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
 730                 </reg32>
 731         </array>
 732 </domain>
 733
 734 <domain name="CP_SET_BIN" width="32">
 735         <doc>value at offset 0 always seems to be 0x00000000..</doc>
 736         <reg32 offset="0" name="0"/>
 737         <reg32 offset="1" name="1">
 738                 <bitfield name="X1" low="0" high="15" type="uint"/>
 739                 <bitfield name="Y1" low="16" high="31" type="uint"/>
 740         </reg32>
 741         <reg32 offset="2" name="2">
 742                 <bitfield name="X2" low="0" high="15" type="uint"/>
 743                 <bitfield name="Y2" low="16" high="31" type="uint"/>
 744         </reg32>
 745 </domain>
 746
 747 <domain name="CP_SET_BIN_DATA" width="32">
 748         <reg32 offset="0" name="0">
 749                 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
 750                 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
 751         </reg32>
 752         <reg32 offset="1" name="1">
 753                 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
 754                 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
 755         </reg32>
 756 </domain>
 757
 758 <domain name="CP_SET_BIN_DATA5" width="32">
 759         <reg32 offset="0" name="0">
 760                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 761                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 762                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 763                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 764         </reg32>
 765         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 766         <reg32 offset="1" name="1">
 767                 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
 768         </reg32>
 769         <reg32 offset="2" name="2">
 770                 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
 771         </reg32>
 772         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 773         <reg32 offset="3" name="3">
 774                 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
 775         </reg32>
 776         <reg32 offset="4" name="4">
 777                 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
 778         </reg32>
 779         <!-- what is this new address? -->
 780         <reg32 offset="5" name="5">
 781                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 782         </reg32>
 783         <reg32 offset="6" name="6">
 784                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 785         </reg32>
 786 </domain>
 787
 788 <domain name="CP_REG_TO_MEM" width="32">
 789         <reg32 offset="0" name="0">
 790                 <bitfield name="REG" low="0" high="15" type="hex"/>
 791                 <!--
 792                 number of regsiters/dwords copied is CNT+1.. unsure
 793                 about # of bits
 794                  -->
 795                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 796                 <bitfield name="64B" pos="30" type="boolean"/>
 797                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 798         </reg32>
 799         <reg32 offset="1" name="1">
 800                 <bitfield name="DEST" low="0" high="31"/>
 801         </reg32>
 802         <reg32 offset="2" name="2" variants="A5XX-">
 803                 <bitfield name="DEST_HI" low="0" high="31"/>
 804         </reg32>
 805 </domain>
 806
 807 <domain name="CP_MEM_TO_REG" width="32">
 808         <reg32 offset="0" name="0">
 809                 <bitfield name="REG" low="0" high="15" type="hex"/>
 810                 <!--
 811                 number of regsiters/dwords copied is CNT+1.. unsure
 812                 about # of bits
 813                  -->
 814                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 815                 <bitfield name="64B" pos="30" type="boolean"/>
 816                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 817         </reg32>
 818         <reg32 offset="1" name="1">
 819                 <bitfield name="SRC" low="0" high="31"/>
 820         </reg32>
 821         <reg32 offset="2" name="2" variants="A5XX-">
 822                 <bitfield name="SRC_HI" low="0" high="31"/>
 823         </reg32>
 824 </domain>
 825
 826 <domain name="CP_MEM_TO_MEM" width="32">
 827         <reg32 offset="0" name="0">
 828                 <!--
 829                 not sure how many src operands we have, but the low
 830                 bits negate the n'th src argument.
 831                  -->
 832                 <bitfield name="NEG_A" pos="0" type="boolean"/>
 833                 <bitfield name="NEG_B" pos="1" type="boolean"/>
 834                 <bitfield name="NEG_C" pos="2" type="boolean"/>
 835
 836                 <!-- if set treat src/dst as 64bit values -->
 837                 <bitfield name="DOUBLE" pos="29" type="boolean"/>
 838         </reg32>
 839         <!--
 840         followed by sequence of addresses.. the first is the
 841         destination and the rest are N src addresses which are
 842         summed (after being negated if NEG_x bit set) allowing
 843         to do things like 'result += end - start' (which turns
 844         out to be useful for queries and accumulating results
 845         across multiple tiles)
 846          -->
 847 </domain>
 848
 849 <enum name="cp_cond_function">
 850         <value value="0" name="WRITE_ALWAYS"/>
 851         <value value="1" name="WRITE_LT"/>
 852         <value value="2" name="WRITE_LE"/>
 853         <value value="3" name="WRITE_EQ"/>
 854         <value value="4" name="WRITE_NE"/>
 855         <value value="5" name="WRITE_GE"/>
 856         <value value="6" name="WRITE_GT"/>
 857 </enum>
 858
 859 <domain name="CP_COND_WRITE" width="32">
 860         <reg32 offset="0" name="0">
 861                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 862                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 863                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 864         </reg32>
 865         <reg32 offset="1" name="1">
 866                 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
 867         </reg32>
 868         <reg32 offset="2" name="2">
 869                 <bitfield name="REF" low="0" high="31"/>
 870         </reg32>
 871         <reg32 offset="3" name="3">
 872                 <bitfield name="MASK" low="0" high="31"/>
 873         </reg32>
 874         <reg32 offset="4" name="4">
 875                 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
 876         </reg32>
 877         <reg32 offset="5" name="5">
 878                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 879         </reg32>
 880 </domain>
 881
 882 <domain name="CP_COND_WRITE5" width="32">
 883         <reg32 offset="0" name="0">
 884                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 885                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 886                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 887         </reg32>
 888         <reg32 offset="1" name="1">
 889                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 890         </reg32>
 891         <reg32 offset="2" name="2">
 892                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 893         </reg32>
 894         <reg32 offset="3" name="3">
 895                 <bitfield name="REF" low="0" high="31"/>
 896         </reg32>
 897         <reg32 offset="4" name="4">
 898                 <bitfield name="MASK" low="0" high="31"/>
 899         </reg32>
 900         <reg32 offset="5" name="5">
 901                 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
 902         </reg32>
 903         <reg32 offset="6" name="6">
 904                 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
 905         </reg32>
 906         <reg32 offset="7" name="7">
 907                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 908         </reg32>
 909 </domain>
 910
 911 <domain name="CP_DISPATCH_COMPUTE" width="32">
 912         <reg32 offset="0" name="0"/>
 913         <reg32 offset="1" name="1">
 914                 <bitfield name="X" low="0" high="31"/>
 915         </reg32>
 916         <reg32 offset="2" name="2">
 917                 <bitfield name="Y" low="0" high="31"/>
 918         </reg32>
 919         <reg32 offset="3" name="3">
 920                 <bitfield name="Z" low="0" high="31"/>
 921         </reg32>
 922 </domain>
 923
 924 <domain name="CP_SET_RENDER_MODE" width="32">
 925         <enum name="render_mode_cmd">
 926                 <value value="1" name="BYPASS"/>
 927                 <value value="2" name="BINNING"/>
 928                 <value value="3" name="GMEM"/>
 929                 <value value="5" name="BLIT2D"/>
 930                 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
 931                 <value value="7" name="BLIT2DSCALE"/>
 932                 <!-- 8 set before going back to BYPASS exiting 2D -->
 933                 <value value="8" name="END2D"/>
 934         </enum>
 935         <reg32 offset="0" name="0">
 936                 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
 937                 <!--
 938                 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
 939                 0x21xx range.. possibly (at least some) a5xx variants have a
 940                 2d core?
 941                  -->
 942         </reg32>
 943         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 944         <reg32 offset="1" name="1">
 945                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 946         </reg32>
 947         <reg32 offset="2" name="2">
 948                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 949         </reg32>
 950         <reg32 offset="3" name="3">
 951                 <!--
 952                 set when in GMEM.. maybe indicates GMEM contents need to be
 953                 preserved on ctx switch?
 954                  -->
 955                 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
 956                 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
 957         </reg32>
 958         <reg32 offset="4" name="4"/>
 959         <!-- second buffer looks like some cmdstream.. length in dwords: -->
 960         <reg32 offset="5" name="5">
 961                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 962         </reg32>
 963         <reg32 offset="6" name="6">
 964                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
 965         </reg32>
 966         <reg32 offset="7" name="7">
 967                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 968         </reg32>
 969 </domain>
 970
 971 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
 972 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
 973         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 974         <reg32 offset="0" name="0">
 975                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 976         </reg32>
 977         <reg32 offset="1" name="1">
 978                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 979         </reg32>
 980         <reg32 offset="2" name="2">
 981         </reg32>
 982         <!-- second buffer looks like some cmdstream.. length in dwords: -->
 983         <reg32 offset="3" name="3">
 984                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 985         </reg32>
 986         <reg32 offset="4" name="4"/>
 987         <reg32 offset="5" name="5">
 988                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
 989         </reg32>
 990         <reg32 offset="6" name="6">
 991                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 992         </reg32>
 993         <reg32 offset="7" name="7"/>
 994 </domain>
 995
 996 <domain name="CP_PERFCOUNTER_ACTION" width="32">
 997         <reg32 offset="0" name="0">
 998         </reg32>
 999         <reg32 offset="1" name="1">
1000                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1001         </reg32>
1002         <reg32 offset="2" name="2">
1003                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1004         </reg32>
1005 </domain>
1006
1007 <domain name="CP_EVENT_WRITE" width="32">
1008         <reg32 offset="0" name="0">
1009                 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1010                 <!-- when set, write back timestamp instead of value from packet: -->
1011                 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1012         </reg32>
1013         <!--
1014         TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1015         context switch?
1016          -->
1017         <reg32 offset="1" name="1">
1018                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1019         </reg32>
1020         <reg32 offset="2" name="2">
1021                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1022         </reg32>
1023         <reg32 offset="3" name="3">
1024                 <!-- ??? -->
1025         </reg32>
1026 </domain>
1027
1028 <domain name="CP_BLIT" width="32">
1029         <enum name="cp_blit_cmd">
1030                 <value value="0" name="BLIT_OP_FILL"/>
1031                 <value value="1" name="BLIT_OP_COPY"/>
1032                 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1033         </enum>
1034         <reg32 offset="0" name="0">
1035                 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1036         </reg32>
1037         <reg32 offset="1" name="1">
1038                 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1039                 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1040         </reg32>
1041         <reg32 offset="2" name="2">
1042                 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1043                 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1044         </reg32>
1045         <reg32 offset="3" name="3">
1046                 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1047                 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1048         </reg32>
1049         <reg32 offset="4" name="4">
1050                 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1051                 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1052         </reg32>
1053 </domain>
1054
1055 <domain name="CP_EXEC_CS" width="32">
1056         <reg32 offset="0" name="0">
1057         </reg32>
1058         <reg32 offset="1" name="1">
1059                 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1060         </reg32>
1061         <reg32 offset="2" name="2">
1062                 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1063         </reg32>
1064         <reg32 offset="3" name="3">
1065                 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1066         </reg32>
1067 </domain>
1068
1069 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1070         <reg32 offset="0" name="0">
1071         </reg32>
1072         <stripe variants="A4XX">
1073                 <reg32 offset="1" name="1">
1074                         <bitfield name="ADDR" low="0" high="31"/>
1075                 </reg32>
1076                 <reg32 offset="2" name="2">
1077                         <!-- localsize is value minus one: -->
1078                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1079                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1080                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1081                 </reg32>
1082         </stripe>
1083         <stripe variants="A5XX-">
1084                 <reg32 offset="1" name="1">
1085                         <bitfield name="ADDR_LO" low="0" high="31"/>
1086                 </reg32>
1087                 <reg32 offset="2" name="2">
1088                         <bitfield name="ADDR_HI" low="0" high="31"/>
1089                 </reg32>
1090                 <reg32 offset="3" name="3">
1091                         <!-- localsize is value minus one: -->
1092                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1093                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1094                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1095                 </reg32>
1096         </stripe>
1097 </domain>
1098
1099 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1100         <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1101         <enum name="a6xx_render_mode">
1102                 <value value="1" name="RM6_BYPASS"/>
1103                 <value value="2" name="RM6_BINNING"/>
1104                 <value value="4" name="RM6_GMEM"/>
1105                 <value value="5" name="RM6_BLIT2D"/>
1106                 <value value="6" name="RM6_RESOLVE"/>
1107                 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1108         </enum>
1109         <reg32 offset="0" name="0">
1110                 <bitfield name="MARKER" low="0" high="3"/>
1111                 <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
1112                 <!-- IFPC - inter-frame power collapse -->
1113                 <bitfield name="IFPC" pos="8" type="boolean"/>
1114         </reg32>
1115 </domain>
1116
1117 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1118         <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1119         <enum name="pseudo_reg">
1120                 <value value="0" name="SMMU_INFO"/>
1121                 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1122                 <value value="2" name="SECURE_SAVE_ADDR"/>
1123                 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1124                 <value value="4" name="COUNTER"/>
1125         </enum>
1126         <array offset="0" name="" stride="3" length="100">
1127                 <reg32 offset="0" name="0">
1128                         <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1129                 </reg32>
1130                 <reg32 offset="1" name="1">
1131                         <bitfield name="LO" low="0" high="31"/>
1132                 </reg32>
1133                 <reg32 offset="2" name="2">
1134                         <bitfield name="HI" low="0" high="31"/>
1135                 </reg32>
1136         </array>
1137 </domain>
1138
1139 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1140         <doc>
1141                 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1142                 So:
1143
1144                         opcode: CP_REG_TEST (39) (2 dwords)
1145                                 { REG = 0xc10 | BIT = 0 }
1146                                        0000: 70b90001 00000c10
1147                         opcode: CP_COND_REG_EXEC (47) (3 dwords)
1148                                        0000: 70c70002 10000000 00000004
1149                         opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1150
1151                 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1152                 offset 0x0c10 is 1
1153         </doc>
1154         <reg32 offset="0" name="0">
1155                 <!-- the register to test -->
1156                 <bitfield name="REG" low="0" high="11"/>
1157                 <!-- the bit to test -->
1158                 <bitfield name="BIT" low="20" high="24" type="uint"/>
1159                 <bitfield name="UNK25" pos="25" type="boolean"/>
1160         </reg32>
1161 </domain>
1162
1163 <!-- I *think* this existed at least as far back as a4xx -->
1164 <domain name="CP_COND_REG_EXEC" width="32">
1165         <reg32 offset="0" name="0">
1166                 <bitfield name="UNK28" pos="28" type="boolean"/>
1167         </reg32>
1168         <reg32 offset="1" name="1">
1169                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1170         </reg32>
1171 </domain>
1172
1173 </database>
1174