src/freedreno/registers/adreno_pm4.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="vgt_event_type">
   7         <value name="VS_DEALLOC" value="0"/>
   8         <value name="PS_DEALLOC" value="1"/>
   9         <value name="VS_DONE_TS" value="2"/>
  10         <value name="PS_DONE_TS" value="3"/>
  11         <value name="CACHE_FLUSH_TS" value="4"/>
  12         <value name="CONTEXT_DONE" value="5"/>
  13         <value name="CACHE_FLUSH" value="6"/>
  14         <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
  15         <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
  16         <value name="VIZQUERY_END" value="8"/>
  17         <value name="SC_WAIT_WC" value="9"/>
  18         <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
  19         <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
  20         <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
  21         <value name="RST_PIX_CNT" value="13"/>
  22         <value name="RST_VTX_CNT" value="14"/>
  23         <value name="TILE_FLUSH" value="15"/>
  24         <value name="STAT_EVENT" value="16"/>
  25         <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
  26         <value name="ZPASS_DONE" value="21"/>
  27         <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
  28         <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
  29         <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
  30         <value name="VS_FETCH_DONE" value="27"/>
  31         <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
  32
  33         <!-- a5xx events -->
  34         <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
  35         <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
  36         <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
  37         <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
  38         <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
  39         <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
  40         <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
  41         <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
  42         <value name="BLIT" value="30" variants="A5XX,A6XX"/>
  43         <value name="UNK_25" value="37" variants="A5XX"/>
  44         <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
  45         <value name="UNK_2C" value="44" variants="A5XX"/>
  46         <value name="UNK_2D" value="45" variants="A5XX"/>
  47
  48         <!-- a6xx events -->
  49         <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
  50 </enum>
  51
  52 <enum name="pc_di_primtype">
  53         <value name="DI_PT_NONE" value="0"/>
  54         <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
  55         <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
  56         <value name="DI_PT_LINELIST" value="2"/>
  57         <value name="DI_PT_LINESTRIP" value="3"/>
  58         <value name="DI_PT_TRILIST" value="4"/>
  59         <value name="DI_PT_TRIFAN" value="5"/>
  60         <value name="DI_PT_TRISTRIP" value="6"/>
  61         <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
  62         <value name="DI_PT_RECTLIST" value="8"/>
  63         <value name="DI_PT_POINTLIST" value="9"/>
  64         <value name="DI_PT_LINE_ADJ" value="0xa"/>
  65         <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
  66         <value name="DI_PT_TRI_ADJ" value="0xc"/>
  67         <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
  68
  69         <value name="DI_PT_PATCHES0" value="0x1f"/>
  70         <value name="DI_PT_PATCHES1" value="0x20"/>
  71         <value name="DI_PT_PATCHES2" value="0x21"/>
  72         <value name="DI_PT_PATCHES3" value="0x22"/>
  73         <value name="DI_PT_PATCHES4" value="0x23"/>
  74         <value name="DI_PT_PATCHES5" value="0x24"/>
  75         <value name="DI_PT_PATCHES6" value="0x25"/>
  76         <value name="DI_PT_PATCHES7" value="0x26"/>
  77         <value name="DI_PT_PATCHES8" value="0x27"/>
  78         <value name="DI_PT_PATCHES9" value="0x28"/>
  79         <value name="DI_PT_PATCHES10" value="0x29"/>
  80         <value name="DI_PT_PATCHES11" value="0x2a"/>
  81         <value name="DI_PT_PATCHES12" value="0x2b"/>
  82         <value name="DI_PT_PATCHES13" value="0x2c"/>
  83         <value name="DI_PT_PATCHES14" value="0x2d"/>
  84         <value name="DI_PT_PATCHES15" value="0x2e"/>
  85         <value name="DI_PT_PATCHES16" value="0x2f"/>
  86         <value name="DI_PT_PATCHES17" value="0x30"/>
  87         <value name="DI_PT_PATCHES18" value="0x31"/>
  88         <value name="DI_PT_PATCHES19" value="0x32"/>
  89         <value name="DI_PT_PATCHES20" value="0x33"/>
  90         <value name="DI_PT_PATCHES21" value="0x34"/>
  91         <value name="DI_PT_PATCHES22" value="0x35"/>
  92         <value name="DI_PT_PATCHES23" value="0x36"/>
  93         <value name="DI_PT_PATCHES24" value="0x37"/>
  94         <value name="DI_PT_PATCHES25" value="0x38"/>
  95         <value name="DI_PT_PATCHES26" value="0x39"/>
  96         <value name="DI_PT_PATCHES27" value="0x3a"/>
  97         <value name="DI_PT_PATCHES28" value="0x3b"/>
  98         <value name="DI_PT_PATCHES29" value="0x3c"/>
  99         <value name="DI_PT_PATCHES30" value="0x3d"/>
 100         <value name="DI_PT_PATCHES31" value="0x3e"/>
 101 </enum>
 102
 103 <enum name="pc_di_src_sel">
 104         <value name="DI_SRC_SEL_DMA" value="0"/>
 105         <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
 106         <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
 107         <value name="DI_SRC_SEL_RESERVED" value="3"/>
 108 </enum>
 109
 110 <enum name="pc_di_face_cull_sel">
 111         <value name="DI_FACE_CULL_NONE" value="0"/>
 112         <value name="DI_FACE_CULL_FETCH" value="1"/>
 113         <value name="DI_FACE_BACKFACE_CULL" value="2"/>
 114         <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
 115 </enum>
 116
 117 <enum name="pc_di_index_size">
 118         <value name="INDEX_SIZE_IGN" value="0"/>
 119         <value name="INDEX_SIZE_16_BIT" value="0"/>
 120         <value name="INDEX_SIZE_32_BIT" value="1"/>
 121         <value name="INDEX_SIZE_8_BIT" value="2"/>
 122         <value name="INDEX_SIZE_INVALID"/>
 123 </enum>
 124
 125 <enum name="pc_di_vis_cull_mode">
 126         <value name="IGNORE_VISIBILITY" value="0"/>
 127         <value name="USE_VISIBILITY" value="1"/>
 128 </enum>
 129
 130 <enum name="adreno_pm4_packet_type">
 131         <value name="CP_TYPE0_PKT" value="0x00000000"/>
 132         <value name="CP_TYPE1_PKT" value="0x40000000"/>
 133         <value name="CP_TYPE2_PKT" value="0x80000000"/>
 134         <value name="CP_TYPE3_PKT" value="0xc0000000"/>
 135         <value name="CP_TYPE4_PKT" value="0x40000000"/>
 136         <value name="CP_TYPE7_PKT" value="0x70000000"/>
 137 </enum>
 138
 139 <!--
 140    Note that in some cases, the same packet id is recycled on a later
 141    generation, so variants attribute is used to distinguish.   They
 142    may not be completely accurate, we would probably have to analyze
 143    the pfp and me/pm4 firmware to verify the packet is actually
 144    handled on a particular generation.  But it is at least enough to
 145    disambiguate the packet-id's that were re-used for different
 146    packets starting with a5xx.
 147  -->
 148 <enum name="adreno_pm4_type3_packets">
 149         <doc>initialize CP's micro-engine</doc>
 150         <value name="CP_ME_INIT" value="0x48"/>
 151         <doc>skip N 32-bit words to get to the next packet</doc>
 152         <value name="CP_NOP" value="0x10"/>
 153         <doc>
 154                 indirect buffer dispatch.  prefetch parser uses this packet
 155                 type to determine whether to pre-fetch the IB
 156         </doc>
 157         <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 158         <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 159         <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
 160         <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 161         <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 162         <doc>wait for the IDLE state of the engine</doc>
 163         <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
 164         <doc>wait until a register or memory location is a specific value</doc>
 165         <value name="CP_WAIT_REG_MEM" value="0x3c"/>
 166         <doc>wait until a register location is equal to a specific value</doc>
 167         <value name="CP_WAIT_REG_EQ" value="0x52"/>
 168         <doc>wait until a register location is >= a specific value</doc>
 169         <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
 170         <doc>wait until a read completes</doc>
 171         <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
 172         <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
 173         <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
 174         <doc>register read/modify/write</doc>
 175         <value name="CP_REG_RMW" value="0x21"/>
 176         <doc>Set binning configuration registers</doc>
 177         <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
 178         <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
 179         <doc>reads register in chip and writes to memory</doc>
 180         <value name="CP_REG_TO_MEM" value="0x3e"/>
 181         <doc>write N 32-bit words to memory</doc>
 182         <value name="CP_MEM_WRITE" value="0x3d"/>
 183         <doc>write CP_PROG_COUNTER value to memory</doc>
 184         <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
 185         <doc>conditional execution of a sequence of packets</doc>
 186         <value name="CP_COND_EXEC" value="0x44"/>
 187         <doc>conditional write to memory or register</doc>
 188         <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
 189         <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
 190         <doc>generate an event that creates a write to memory when completed</doc>
 191         <value name="CP_EVENT_WRITE" value="0x46"/>
 192         <doc>generate a VS|PS_done event</doc>
 193         <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
 194         <doc>generate a cache flush done event</doc>
 195         <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
 196         <doc>generate a z_pass done event</doc>
 197         <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
 198         <doc>
 199                 not sure the real name, but this seems to be what is used for
 200                 opencl, instead of CP_DRAW_INDX..
 201         </doc>
 202         <value name="CP_RUN_OPENCL" value="0x31"/>
 203         <doc>initiate fetch of index buffer and draw</doc>
 204         <value name="CP_DRAW_INDX" value="0x22"/>
 205         <doc>draw using supplied indices in packet</doc>
 206         <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
 207         <doc>initiate fetch of index buffer and binIDs and draw</doc>
 208         <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
 209         <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
 210         <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
 211         <doc>begin/end initiator for viz query extent processing</doc>
 212         <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
 213         <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
 214         <value name="CP_SET_STATE" value="0x25"/>
 215         <doc>load constant into chip and to memory</doc>
 216         <value name="CP_SET_CONSTANT" value="0x2d"/>
 217         <doc>load sequencer instruction memory (pointer-based)</doc>
 218         <value name="CP_IM_LOAD" value="0x27"/>
 219         <doc>load sequencer instruction memory (code embedded in packet)</doc>
 220         <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 221         <doc>load constants from a location in memory</doc>
 222         <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
 223         <doc>selective invalidation of state pointers</doc>
 224         <value name="CP_INVALIDATE_STATE" value="0x3b"/>
 225         <doc>dynamically changes shader instruction memory partition</doc>
 226         <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
 227         <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
 228         <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
 229         <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
 230         <value name="CP_SET_BIN_SELECT" value="0x51"/>
 231         <doc>updates the current context, if needed</doc>
 232         <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
 233         <doc>generate interrupt from the command stream</doc>
 234         <value name="CP_INTERRUPT" value="0x40"/>
 235         <doc>copy sequencer instruction memory to system memory</doc>
 236         <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
 237
 238         <!-- For a20x -->
 239 <!-- TODO handle variants..
 240         <doc>
 241                 Program an offset that will added to the BIN_BASE value of
 242                 the 3D_DRAW_INDX_BIN packet
 243         </doc>
 244         <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
 245  -->
 246
 247         <!-- for a22x -->
 248         <doc>
 249                 sets draw initiator flags register in PFP, gets bitwise-ORed into
 250                 every draw initiator
 251         </doc>
 252         <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
 253         <doc>sets the register protection mode</doc>
 254         <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
 255
 256         <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
 257
 258         <!-- for a3xx -->
 259         <doc>load high level sequencer command</doc>
 260         <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
 261         <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
 262         <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
 263         <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
 264         <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
 265         <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
 266         <doc>Load a buffer with pre-fetch enabled</doc>
 267         <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 268         <doc>Set bin (?)</doc>
 269         <value name="CP_SET_BIN" value="0x4c"/>
 270
 271         <doc>test 2 memory locations to dword values specified</doc>
 272         <value name="CP_TEST_TWO_MEMS" value="0x71"/>
 273
 274         <doc>Write register, ignoring context state for context sensitive registers</doc>
 275         <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
 276
 277         <doc>Record the real-time when this packet is processed by PFP</doc>
 278         <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
 279
 280         <!-- Used to switch GPU between secure and non-secure modes -->
 281         <value name="CP_SET_SECURE_MODE" value="0x66"/>
 282
 283         <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
 284         <value name="CP_WAIT_FOR_ME" value="0x13"/>
 285
 286         <!-- for a4xx -->
 287         <doc>
 288                 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
 289                 groups of registers.  Looks like it can be used to create state
 290                 objects in GPU memory, and on state change only emit pointer
 291                 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
 292                 overhead:
 293
 294                 (A4x) save PM4 stream pointers to execute upon a visible draw
 295         </doc>
 296         <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
 297         <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
 298         <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
 299         <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
 300         <value name="CP_DRAW_AUTO" value="0x24"/>
 301
 302         <value name="CP_UNKNOWN_19" value="0x19"/>
 303
 304         <doc>set to 1 for fastclear..:</doc>
 305         <value name="CP_UNKNOWN_1A" value="0x1a"/>
 306
 307         <value name="CP_UNKNOWN_4E" value="0x4e"/>
 308
 309         <doc>
 310                 for A4xx
 311                 Write to register with address that does not fit into type-0 pkt
 312         </doc>
 313         <value name="CP_WIDE_REG_WRITE" value="0x74"/>
 314
 315         <doc>copy from ME scratch RAM to a register</doc>
 316         <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
 317
 318         <doc>Copy from REG to ME scratch RAM</doc>
 319         <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
 320
 321         <doc>Wait for memory writes to complete</doc>
 322         <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
 323
 324         <doc>Conditional execution based on register comparison</doc>
 325         <value name="CP_COND_REG_EXEC" value="0x47"/>
 326
 327         <doc>Memory to REG copy</doc>
 328         <value name="CP_MEM_TO_REG" value="0x42"/>
 329
 330         <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
 331         <value name="CP_EXEC_CS" value="0x33"/>
 332
 333         <doc>
 334                 for a5xx
 335         </doc>
 336         <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 337         <!-- switches SMMU pagetable, used on a5xx only -->
 338         <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
 339         <!-- for a6xx -->
 340         <doc>Tells CP the current mode of GPU operation</doc>
 341         <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
 342         <doc>Instruct CP to set a few internal CP registers</doc>
 343         <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 344         <!--
 345         pairs of regid and value.. seems to be used to program some TF
 346         related regs:
 347          -->
 348         <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
 349         <!-- A5XX Enable yield in RB only -->
 350         <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
 351         <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
 352         <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
 353         <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
 354         <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
 355         <!-- Enable/Disable/Defer A5x global preemption model -->
 356         <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
 357         <!-- Enable/Disable A5x local preemption model -->
 358         <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
 359         <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
 360         <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
 361         <!-- Inform CP about current render mode (needed for a5xx preemption) -->
 362         <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
 363         <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
 364         <!-- check if this works on earlier.. -->
 365         <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
 366         <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
 367
 368         <!-- Test specified bit in specified register and set predicate -->
 369         <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
 370
 371         <!--
 372         Seems to set the mode flags which control which CP_SET_DRAW_STATE
 373         packets are executed, based on their ENABLE_MASK values
 374
 375         CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
 376         packets w/ ENABLE_MASK & 0x6 to execute immediately
 377          -->
 378         <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
 379
 380         <!--
 381         Seems like there are now separate blocks of state for VS vs FS/CS
 382         (probably these amounts to geometry vs fragments so that geometry
 383         stage of the pipeline for next draw can start while fragment stage
 384         of current draw is still running.  The format of the payload of the
 385         packets is the same, the only difference is the offsets of the regs
 386         the firmware code that handles the packet writes.
 387
 388         Note that for CL, starting with a6xx, the preferred # of local
 389         threads is no longer the same as the max, implying that the shader
 390         core can now run warps from unrelated shaders (ie.
 391         CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
 392         CL_KERNEL_WORK_GROUP_SIZE)
 393          -->
 394         <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
 395         <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
 396         <!--
 397         Note: For IBO state (Image/SSBOs) which have shared state across
 398         shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
 399         compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
 400         interchangable.
 401          -->
 402         <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
 403
 404         <!-- internal packets: -->
 405         <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
 406         <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
 407         <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
 408         <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
 409         <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
 410         <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
 411         <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
 412         <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
 413
 414         <!-- jmptable entry used to handle type4 packet on a5xx+: -->
 415         <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
 416 <!--
 417 unknown a6xx opcodes:
 418
 419 opcode: (null) (14) (5 dwords)
 420 opcode: (null) (55) (4 dwords)
 421 opcode: (null) (6d) (4 dwords)
 422  -->
 423         <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
 424         <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
 425
 426         <!--
 427         Seems to always have the payload:
 428           00000002 00008801 00004010
 429         or:
 430           00000002 00008801 00004090
 431         or:
 432           00000002 00008801 00000010
 433           00000002 00008801 00010010
 434           00000002 00008801 00d64010
 435           ...
 436         Note set for compute shaders..
 437         Is 0x8801 a register offset?
 438         This appears to be a special sort of register write packet
 439         more or less, but the firmware has some special handling..
 440         Seems like it intercepts/modifies certain register offsets,
 441         but others are treated like a normal PKT4 reg write.  I
 442         guess there are some registers that the fw controls certain
 443         bits.
 444          -->
 445         <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
 446
 447 </enum>
 448
 449
 450 <domain name="CP_LOAD_STATE" width="32">
 451         <doc>Load state, a3xx (and later?)</doc>
 452         <enum name="adreno_state_block">
 453                 <value name="SB_VERT_TEX" value="0"/>
 454                 <value name="SB_VERT_MIPADDR" value="1"/>
 455                 <value name="SB_FRAG_TEX" value="2"/>
 456                 <value name="SB_FRAG_MIPADDR" value="3"/>
 457                 <value name="SB_VERT_SHADER" value="4"/>
 458                 <value name="SB_GEOM_SHADER" value="5"/>
 459                 <value name="SB_FRAG_SHADER" value="6"/>
 460                 <value name="SB_COMPUTE_SHADER" value="7"/>
 461         </enum>
 462         <enum name="adreno_state_type">
 463                 <value name="ST_SHADER" value="0"/>
 464                 <value name="ST_CONSTANTS" value="1"/>
 465         </enum>
 466         <enum name="adreno_state_src">
 467                 <value name="SS_DIRECT" value="0">
 468                         <doc>inline with the CP_LOAD_STATE packet</doc>
 469                 </value>
 470                 <value name="SS_INVALID_ALL_IC" value="2"/>
 471                 <value name="SS_INVALID_PART_IC" value="3"/>
 472                 <value name="SS_INDIRECT" value="4">
 473                         <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
 474                 </value>
 475                 <value name="SS_INDIRECT_TCM" value="5"/>
 476                 <value name="SS_INDIRECT_STM" value="6"/>
 477         </enum>
 478         <reg32 offset="0" name="0">
 479                 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
 480                 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
 481                 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
 482                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 483         </reg32>
 484         <reg32 offset="1" name="1">
 485                 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
 486                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 487         </reg32>
 488 </domain>
 489
 490 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
 491         <doc>Load state, a4xx+</doc>
 492         <enum name="a4xx_state_block">
 493                 <!--
 494                 unknown: 0x7 and 0xf <- seen in compute shader
 495
 496                 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
 497                 Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
 498                 the gpuaddr of the following shader constants block.  DST_OFF seems
 499                 to specify which shader stage:
 500
 501                     16 -> vert
 502                     36 -> tcs
 503                     56 -> tes
 504                     76 -> geom
 505                     96 -> frag
 506
 507                 Example:
 508
 509 opcode: CP_LOAD_STATE4 (30) (12 dwords)
 510         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
 511         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
 512         { EXT_SRC_ADDR_HI = 0 }
 513                         0000: c0264100 00000000 00000000 00000000
 514                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
 515
 516 opcode: CP_LOAD_STATE4 (30) (4 dwords)
 517         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
 518         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
 519         { EXT_SRC_ADDR_HI = 0 }
 520                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 521                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
 522                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
 523
 524                 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
 525
 526                  -->
 527                 <value name="SB4_VS_TEX"    value="0x0"/>
 528                 <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 529                 <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 530                 <value name="SB4_GS_TEX"    value="0x3"/>
 531                 <value name="SB4_FS_TEX"    value="0x4"/>
 532                 <value name="SB4_CS_TEX"    value="0x5"/>
 533                 <value name="SB4_VS_SHADER" value="0x8"/>
 534                 <value name="SB4_HS_SHADER" value="0x9"/>
 535                 <value name="SB4_DS_SHADER" value="0xa"/>
 536                 <value name="SB4_GS_SHADER" value="0xb"/>
 537                 <value name="SB4_FS_SHADER" value="0xc"/>
 538                 <value name="SB4_CS_SHADER" value="0xd"/>
 539                 <!--
 540                 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
 541                 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
 542
 543                 Compute has it's own dedicated SSBO state, it seems, but the rest
 544                 of the stages share state
 545                  -->
 546                 <value name="SB4_SSBO"   value="0xe"/>
 547                 <value name="SB4_CS_SSBO"   value="0xf"/>
 548         </enum>
 549         <enum name="a4xx_state_type">
 550                 <value name="ST4_SHADER" value="0"/>
 551                 <value name="ST4_CONSTANTS" value="1"/>
 552                 <value name="ST4_UBO" value="2"/>
 553         </enum>
 554         <enum name="a4xx_state_src">
 555                 <value name="SS4_DIRECT" value="0"/>
 556                 <value name="SS4_INDIRECT" value="2"/>
 557         </enum>
 558         <reg32 offset="0" name="0">
 559                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 560                 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
 561                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
 562                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 563         </reg32>
 564         <reg32 offset="1" name="1">
 565                 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
 566                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 567         </reg32>
 568         <reg32 offset="2" name="2" variants="A5XX-">
 569                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 570         </reg32>
 571 </domain>
 572
 573 <!-- looks basically same CP_LOAD_STATE4 -->
 574 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
 575         <doc>Load state, a6xx+</doc>
 576         <enum name="a6xx_state_block">
 577                 <value name="SB6_VS_TEX"    value="0x0"/>
 578                 <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
 579                 <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
 580                 <value name="SB6_GS_TEX"    value="0x3"/>
 581                 <value name="SB6_FS_TEX"    value="0x4"/>
 582                 <value name="SB6_CS_TEX"    value="0x5"/>
 583                 <value name="SB6_VS_SHADER" value="0x8"/>
 584                 <value name="SB6_HS_SHADER" value="0x9"/>
 585                 <value name="SB6_DS_SHADER" value="0xa"/>
 586                 <value name="SB6_GS_SHADER" value="0xb"/>
 587                 <value name="SB6_FS_SHADER" value="0xc"/>
 588                 <value name="SB6_CS_SHADER" value="0xd"/>
 589                 <value name="SB6_IBO"       value="0xe"/>
 590                 <value name="SB6_CS_IBO"    value="0xf"/>
 591         </enum>
 592         <enum name="a6xx_state_type">
 593                 <value name="ST6_SHADER" value="0"/>
 594                 <value name="ST6_CONSTANTS" value="1"/>
 595                 <value name="ST6_UBO" value="2"/>
 596                 <value name="ST6_IBO" value="3"/>
 597         </enum>
 598         <enum name="a6xx_state_src">
 599                 <value name="SS6_DIRECT" value="0"/>
 600                 <value name="SS6_INDIRECT" value="2"/>
 601         </enum>
 602         <reg32 offset="0" name="0">
 603                 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
 604                 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
 605                 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
 606                 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
 607                 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
 608         </reg32>
 609         <reg32 offset="1" name="1">
 610                 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
 611         </reg32>
 612         <reg32 offset="2" name="2">
 613                 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
 614         </reg32>
 615 </domain>
 616
 617 <bitset name="vgt_draw_initiator" inline="yes">
 618         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 619         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 620         <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
 621         <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
 622         <bitfield name="NOT_EOP" pos="12" type="boolean"/>
 623         <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
 624         <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
 625         <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
 626 </bitset>
 627
 628 <!-- changed on a4xx: -->
 629 <enum name="a4xx_index_size">
 630         <value name="INDEX4_SIZE_8_BIT" value="0"/>
 631         <value name="INDEX4_SIZE_16_BIT" value="1"/>
 632         <value name="INDEX4_SIZE_32_BIT" value="2"/>
 633 </enum>
 634
 635 <enum name="a6xx_patch_type">
 636   <value name="TESS_QUADS" value="0"/>
 637   <value name="TESS_TRIANGLES" value="1"/>
 638   <value name="TESS_ISOLINES" value="2"/>
 639 </enum>
 640
 641 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
 642         <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
 643         <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
 644         <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
 645         <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 646         <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 647         <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
 648         <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
 649         <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 650 </bitset>
 651
 652 <domain name="CP_DRAW_INDX" width="32">
 653         <reg32 offset="0" name="0">
 654                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 655         </reg32>
 656         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 657         <reg32 offset="2" name="2">
 658                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 659         </reg32>
 660         <reg32 offset="3" name="3">
 661                 <bitfield name="INDX_BASE" low="0" high="31"/>
 662         </reg32>
 663         <reg32 offset="4" name="4">
 664                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 665         </reg32>
 666 </domain>
 667
 668 <domain name="CP_DRAW_INDX_2" width="32">
 669         <reg32 offset="0" name="0">
 670                 <bitfield name="VIZ_QUERY" low="0" high="31"/>
 671         </reg32>
 672         <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
 673         <reg32 offset="2" name="2">
 674                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 675         </reg32>
 676         <!-- followed by NUM_INDICES indices.. -->
 677 </domain>
 678
 679 <domain name="CP_DRAW_INDX_OFFSET" width="32">
 680         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 681         <reg32 offset="1" name="1">
 682                 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
 683         </reg32>
 684         <reg32 offset="2" name="2">
 685                 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
 686         </reg32>
 687         <reg32 offset="3" name="3">
 688         </reg32>
 689
 690         <stripe variants="A5XX-">
 691                 <reg32 offset="4" name="4">
 692                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 693                 </reg32>
 694                 <reg32 offset="5" name="5">
 695                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 696                 </reg32>
 697                 <reg32 offset="6" name="6">
 698                         <bitfield name="INDX_SIZE" low="0" high="31"/>
 699                 </reg32>
 700         </stripe>
 701
 702         <reg32 offset="4" name="4">
 703                 <bitfield name="INDX_BASE" low="0" high="31"/>
 704         </reg32>
 705
 706         <reg32 offset="5" name="5">
 707                 <bitfield name="INDX_SIZE" low="0" high="31"/>
 708         </reg32>
 709 </domain>
 710
 711 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 712         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 713         <reg32 offset="1" name="1">
 714                 <bitfield name="INDIRECT" low="0" high="31"/>
 715         </reg32>
 716         <stripe variants="A5XX-">
 717                 <reg32 offset="2" name="2">
 718                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 719                 </reg32>
 720         </stripe>
 721 </domain>
 722
 723 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 724         <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
 725         <stripe variants="A4XX">
 726                 <reg32 offset="1" name="1">
 727                         <bitfield name="INDX_BASE" low="0" high="31"/>
 728                 </reg32>
 729                 <reg32 offset="2" name="2">
 730                         <!-- max # of bytes in index buffer -->
 731                         <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
 732                 </reg32>
 733                 <reg32 offset="3" name="3">
 734                         <bitfield name="INDIRECT" low="0" high="31"/>
 735                 </reg32>
 736         </stripe>
 737         <stripe variants="A5XX-">
 738                 <reg32 offset="1" name="1">
 739                         <bitfield name="INDX_BASE_LO" low="0" high="31"/>
 740                 </reg32>
 741                 <reg32 offset="2" name="2">
 742                         <bitfield name="INDX_BASE_HI" low="0" high="31"/>
 743                 </reg32>
 744                 <reg32 offset="3" name="3">
 745                         <!-- max # of elements in index buffer -->
 746                         <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
 747                 </reg32>
 748                 <reg32 offset="4" name="4">
 749                         <bitfield name="INDIRECT_LO" low="0" high="31"/>
 750                 </reg32>
 751                 <reg32 offset="5" name="5">
 752                         <bitfield name="INDIRECT_HI" low="0" high="31"/>
 753                 </reg32>
 754         </stripe>
 755 </domain>
 756
 757 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
 758         <array offset="0" name="" stride="3" length="100">
 759                 <reg32 offset="0" name="0">
 760                         <bitfield name="COUNT" low="0" high="15" type="uint"/>
 761                         <bitfield name="DIRTY" pos="16" type="boolean"/>
 762                         <bitfield name="DISABLE" pos="17" type="boolean"/>
 763                         <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 764                         <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
 765                         <!--
 766                         I think this is a bitmask of states that this group applies to
 767                         (ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
 768                         emits different VS state at the same time, with ENABLE_MASK=0x1
 769                         for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
 770                         -->
 771                         <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
 772                         <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 773                 </reg32>
 774                 <reg32 offset="1" name="1">
 775                         <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
 776                 </reg32>
 777                 <reg32 offset="2" name="2" variants="A5XX-">
 778                         <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
 779                 </reg32>
 780         </array>
 781 </domain>
 782
 783 <domain name="CP_SET_BIN" width="32">
 784         <doc>value at offset 0 always seems to be 0x00000000..</doc>
 785         <reg32 offset="0" name="0"/>
 786         <reg32 offset="1" name="1">
 787                 <bitfield name="X1" low="0" high="15" type="uint"/>
 788                 <bitfield name="Y1" low="16" high="31" type="uint"/>
 789         </reg32>
 790         <reg32 offset="2" name="2">
 791                 <bitfield name="X2" low="0" high="15" type="uint"/>
 792                 <bitfield name="Y2" low="16" high="31" type="uint"/>
 793         </reg32>
 794 </domain>
 795
 796 <domain name="CP_SET_BIN_DATA" width="32">
 797         <reg32 offset="0" name="0">
 798                 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
 799                 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
 800         </reg32>
 801         <reg32 offset="1" name="1">
 802                 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
 803                 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
 804         </reg32>
 805 </domain>
 806
 807 <domain name="CP_SET_BIN_DATA5" width="32">
 808         <reg32 offset="0" name="0">
 809                 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
 810                 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 811                 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
 812                 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
 813         </reg32>
 814         <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
 815         <reg32 offset="1" name="1">
 816                 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
 817         </reg32>
 818         <reg32 offset="2" name="2">
 819                 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
 820         </reg32>
 821         <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
 822         <reg32 offset="3" name="3">
 823                 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
 824         </reg32>
 825         <reg32 offset="4" name="4">
 826                 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
 827         </reg32>
 828         <!-- what is this new address? -->
 829         <reg32 offset="5" name="5">
 830                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 831         </reg32>
 832         <reg32 offset="6" name="6">
 833                 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
 834         </reg32>
 835 </domain>
 836
 837 <domain name="CP_REG_TO_MEM" width="32">
 838         <reg32 offset="0" name="0">
 839                 <bitfield name="REG" low="0" high="15" type="hex"/>
 840                 <!--
 841                 number of regsiters/dwords copied is CNT+1.. unsure
 842                 about # of bits
 843                  -->
 844                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 845                 <bitfield name="64B" pos="30" type="boolean"/>
 846                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 847         </reg32>
 848         <reg32 offset="1" name="1">
 849                 <bitfield name="DEST" low="0" high="31"/>
 850         </reg32>
 851         <reg32 offset="2" name="2" variants="A5XX-">
 852                 <bitfield name="DEST_HI" low="0" high="31"/>
 853         </reg32>
 854 </domain>
 855
 856 <domain name="CP_MEM_TO_REG" width="32">
 857         <reg32 offset="0" name="0">
 858                 <bitfield name="REG" low="0" high="15" type="hex"/>
 859                 <!--
 860                 number of regsiters/dwords copied is CNT+1.. unsure
 861                 about # of bits
 862                  -->
 863                 <bitfield name="CNT" low="19" high="29" type="uint"/>
 864                 <bitfield name="64B" pos="30" type="boolean"/>
 865                 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 866         </reg32>
 867         <reg32 offset="1" name="1">
 868                 <bitfield name="SRC" low="0" high="31"/>
 869         </reg32>
 870         <reg32 offset="2" name="2" variants="A5XX-">
 871                 <bitfield name="SRC_HI" low="0" high="31"/>
 872         </reg32>
 873 </domain>
 874
 875 <domain name="CP_MEM_TO_MEM" width="32">
 876         <reg32 offset="0" name="0">
 877                 <!--
 878                 not sure how many src operands we have, but the low
 879                 bits negate the n'th src argument.
 880                  -->
 881                 <bitfield name="NEG_A" pos="0" type="boolean"/>
 882                 <bitfield name="NEG_B" pos="1" type="boolean"/>
 883                 <bitfield name="NEG_C" pos="2" type="boolean"/>
 884
 885                 <!-- if set treat src/dst as 64bit values -->
 886                 <bitfield name="DOUBLE" pos="29" type="boolean"/>
 887         </reg32>
 888         <!--
 889         followed by sequence of addresses.. the first is the
 890         destination and the rest are N src addresses which are
 891         summed (after being negated if NEG_x bit set) allowing
 892         to do things like 'result += end - start' (which turns
 893         out to be useful for queries and accumulating results
 894         across multiple tiles)
 895          -->
 896 </domain>
 897
 898 <enum name="cp_cond_function">
 899         <value value="0" name="WRITE_ALWAYS"/>
 900         <value value="1" name="WRITE_LT"/>
 901         <value value="2" name="WRITE_LE"/>
 902         <value value="3" name="WRITE_EQ"/>
 903         <value value="4" name="WRITE_NE"/>
 904         <value value="5" name="WRITE_GE"/>
 905         <value value="6" name="WRITE_GT"/>
 906 </enum>
 907
 908 <domain name="CP_COND_WRITE" width="32">
 909         <reg32 offset="0" name="0">
 910                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 911                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 912                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 913         </reg32>
 914         <reg32 offset="1" name="1">
 915                 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
 916         </reg32>
 917         <reg32 offset="2" name="2">
 918                 <bitfield name="REF" low="0" high="31"/>
 919         </reg32>
 920         <reg32 offset="3" name="3">
 921                 <bitfield name="MASK" low="0" high="31"/>
 922         </reg32>
 923         <reg32 offset="4" name="4">
 924                 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
 925         </reg32>
 926         <reg32 offset="5" name="5">
 927                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 928         </reg32>
 929 </domain>
 930
 931 <domain name="CP_COND_WRITE5" width="32">
 932         <reg32 offset="0" name="0">
 933                 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 934                 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 935                 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 936         </reg32>
 937         <reg32 offset="1" name="1">
 938                 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 939         </reg32>
 940         <reg32 offset="2" name="2">
 941                 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 942         </reg32>
 943         <reg32 offset="3" name="3">
 944                 <bitfield name="REF" low="0" high="31"/>
 945         </reg32>
 946         <reg32 offset="4" name="4">
 947                 <bitfield name="MASK" low="0" high="31"/>
 948         </reg32>
 949         <reg32 offset="5" name="5">
 950                 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
 951         </reg32>
 952         <reg32 offset="6" name="6">
 953                 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
 954         </reg32>
 955         <reg32 offset="7" name="7">
 956                 <bitfield name="WRITE_DATA" low="0" high="31"/>
 957         </reg32>
 958 </domain>
 959
 960 <domain name="CP_DISPATCH_COMPUTE" width="32">
 961         <reg32 offset="0" name="0"/>
 962         <reg32 offset="1" name="1">
 963                 <bitfield name="X" low="0" high="31"/>
 964         </reg32>
 965         <reg32 offset="2" name="2">
 966                 <bitfield name="Y" low="0" high="31"/>
 967         </reg32>
 968         <reg32 offset="3" name="3">
 969                 <bitfield name="Z" low="0" high="31"/>
 970         </reg32>
 971 </domain>
 972
 973 <domain name="CP_SET_RENDER_MODE" width="32">
 974         <enum name="render_mode_cmd">
 975                 <value value="1" name="BYPASS"/>
 976                 <value value="2" name="BINNING"/>
 977                 <value value="3" name="GMEM"/>
 978                 <value value="5" name="BLIT2D"/>
 979                 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
 980                 <value value="7" name="BLIT2DSCALE"/>
 981                 <!-- 8 set before going back to BYPASS exiting 2D -->
 982                 <value value="8" name="END2D"/>
 983         </enum>
 984         <reg32 offset="0" name="0">
 985                 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
 986                 <!--
 987                 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
 988                 0x21xx range.. possibly (at least some) a5xx variants have a
 989                 2d core?
 990                  -->
 991         </reg32>
 992         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 993         <reg32 offset="1" name="1">
 994                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
 995         </reg32>
 996         <reg32 offset="2" name="2">
 997                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
 998         </reg32>
 999         <reg32 offset="3" name="3">
1000                 <!--
1001                 set when in GMEM.. maybe indicates GMEM contents need to be
1002                 preserved on ctx switch?
1003                  -->
1004                 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1005                 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1006         </reg32>
1007         <reg32 offset="4" name="4"/>
1008         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1009         <reg32 offset="5" name="5">
1010                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1011         </reg32>
1012         <reg32 offset="6" name="6">
1013                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1014         </reg32>
1015         <reg32 offset="7" name="7">
1016                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1017         </reg32>
1018 </domain>
1019
1020 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1021 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1022         <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1023         <reg32 offset="0" name="0">
1024                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1025         </reg32>
1026         <reg32 offset="1" name="1">
1027                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1028         </reg32>
1029         <reg32 offset="2" name="2">
1030         </reg32>
1031         <!-- second buffer looks like some cmdstream.. length in dwords: -->
1032         <reg32 offset="3" name="3">
1033                 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1034         </reg32>
1035         <reg32 offset="4" name="4"/>
1036         <reg32 offset="5" name="5">
1037                 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1038         </reg32>
1039         <reg32 offset="6" name="6">
1040                 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1041         </reg32>
1042         <reg32 offset="7" name="7"/>
1043 </domain>
1044
1045 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1046         <reg32 offset="0" name="0">
1047         </reg32>
1048         <reg32 offset="1" name="1">
1049                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1050         </reg32>
1051         <reg32 offset="2" name="2">
1052                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1053         </reg32>
1054 </domain>
1055
1056 <domain name="CP_EVENT_WRITE" width="32">
1057         <reg32 offset="0" name="0">
1058                 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1059                 <!-- when set, write back timestamp instead of value from packet: -->
1060                 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1061         </reg32>
1062         <!--
1063         TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1064         context switch?
1065          -->
1066         <reg32 offset="1" name="1">
1067                 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1068         </reg32>
1069         <reg32 offset="2" name="2">
1070                 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1071         </reg32>
1072         <reg32 offset="3" name="3">
1073                 <!-- ??? -->
1074         </reg32>
1075 </domain>
1076
1077 <domain name="CP_BLIT" width="32">
1078         <enum name="cp_blit_cmd">
1079                 <value value="0" name="BLIT_OP_FILL"/>
1080                 <value value="1" name="BLIT_OP_COPY"/>
1081                 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1082         </enum>
1083         <reg32 offset="0" name="0">
1084                 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1085         </reg32>
1086         <reg32 offset="1" name="1">
1087                 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1088                 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1089         </reg32>
1090         <reg32 offset="2" name="2">
1091                 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1092                 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1093         </reg32>
1094         <reg32 offset="3" name="3">
1095                 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1096                 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1097         </reg32>
1098         <reg32 offset="4" name="4">
1099                 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1100                 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1101         </reg32>
1102 </domain>
1103
1104 <domain name="CP_EXEC_CS" width="32">
1105         <reg32 offset="0" name="0">
1106         </reg32>
1107         <reg32 offset="1" name="1">
1108                 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1109         </reg32>
1110         <reg32 offset="2" name="2">
1111                 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1112         </reg32>
1113         <reg32 offset="3" name="3">
1114                 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1115         </reg32>
1116 </domain>
1117
1118 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1119         <reg32 offset="0" name="0">
1120         </reg32>
1121         <stripe variants="A4XX">
1122                 <reg32 offset="1" name="1">
1123                         <bitfield name="ADDR" low="0" high="31"/>
1124                 </reg32>
1125                 <reg32 offset="2" name="2">
1126                         <!-- localsize is value minus one: -->
1127                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1128                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1129                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1130                 </reg32>
1131         </stripe>
1132         <stripe variants="A5XX-">
1133                 <reg32 offset="1" name="1">
1134                         <bitfield name="ADDR_LO" low="0" high="31"/>
1135                 </reg32>
1136                 <reg32 offset="2" name="2">
1137                         <bitfield name="ADDR_HI" low="0" high="31"/>
1138                 </reg32>
1139                 <reg32 offset="3" name="3">
1140                         <!-- localsize is value minus one: -->
1141                         <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1142                         <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1143                         <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1144                 </reg32>
1145         </stripe>
1146 </domain>
1147
1148 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1149         <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1150         <enum name="a6xx_render_mode">
1151                 <value value="1" name="RM6_BYPASS"/>
1152                 <value value="2" name="RM6_BINNING"/>
1153                 <value value="4" name="RM6_GMEM"/>
1154                 <value value="5" name="RM6_BLIT2D"/>
1155                 <value value="6" name="RM6_RESOLVE"/>
1156                 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1157         </enum>
1158         <reg32 offset="0" name="0">
1159                 <bitfield name="MARKER" low="0" high="3"/>
1160                 <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
1161                 <!-- IFPC - inter-frame power collapse -->
1162                 <bitfield name="IFPC" pos="8" type="boolean"/>
1163         </reg32>
1164 </domain>
1165
1166 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1167         <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1168         <enum name="pseudo_reg">
1169                 <value value="0" name="SMMU_INFO"/>
1170                 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1171                 <value value="2" name="SECURE_SAVE_ADDR"/>
1172                 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1173                 <value value="4" name="COUNTER"/>
1174         </enum>
1175         <array offset="0" name="" stride="3" length="100">
1176                 <reg32 offset="0" name="0">
1177                         <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1178                 </reg32>
1179                 <reg32 offset="1" name="1">
1180                         <bitfield name="LO" low="0" high="31"/>
1181                 </reg32>
1182                 <reg32 offset="2" name="2">
1183                         <bitfield name="HI" low="0" high="31"/>
1184                 </reg32>
1185         </array>
1186 </domain>
1187
1188 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1189         <doc>
1190                 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1191                 So:
1192
1193                         opcode: CP_REG_TEST (39) (2 dwords)
1194                                 { REG = 0xc10 | BIT = 0 }
1195                                        0000: 70b90001 00000c10
1196                         opcode: CP_COND_REG_EXEC (47) (3 dwords)
1197                                        0000: 70c70002 10000000 00000004
1198                         opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1199
1200                 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1201                 offset 0x0c10 is 1
1202         </doc>
1203         <reg32 offset="0" name="0">
1204                 <!-- the register to test -->
1205                 <bitfield name="REG" low="0" high="11"/>
1206                 <!-- the bit to test -->
1207                 <bitfield name="BIT" low="20" high="24" type="uint"/>
1208                 <bitfield name="UNK25" pos="25" type="boolean"/>
1209         </reg32>
1210 </domain>
1211
1212 <!-- I *think* this existed at least as far back as a4xx -->
1213 <domain name="CP_COND_REG_EXEC" width="32">
1214         <reg32 offset="0" name="0">
1215                 <bitfield name="UNK28" pos="28" type="boolean"/>
1216         </reg32>
1217         <reg32 offset="1" name="1">
1218                 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1219         </reg32>
1220 </domain>
1221
1222 </database>
1223