4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-02-11 18:35:20)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2019-04-25 18:25:51)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 147695 bytes, from 2019-04-25 18:26:07)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
23 Copyright (C) 2013-2019 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
65 CACHE_FLUSH_AND_INV_TS_EVENT
= 20,
67 CACHE_FLUSH_AND_INV_EVENT
= 22,
68 PERFCOUNTER_START
= 23,
69 PERFCOUNTER_STOP
= 24,
76 PC_CCU_INVALIDATE_DEPTH
= 24,
77 PC_CCU_INVALIDATE_COLOR
= 25,
89 DI_PT_POINTLIST_PSIZE
= 1,
99 DI_PT_LINESTRIP_ADJ
= 11,
101 DI_PT_TRISTRIP_ADJ
= 13,
106 DI_SRC_SEL_IMMEDIATE
= 1,
107 DI_SRC_SEL_AUTO_INDEX
= 2,
108 DI_SRC_SEL_RESERVED
= 3,
111 enum pc_di_face_cull_sel
{
112 DI_FACE_CULL_NONE
= 0,
113 DI_FACE_CULL_FETCH
= 1,
114 DI_FACE_BACKFACE_CULL
= 2,
115 DI_FACE_FRONTFACE_CULL
= 3,
118 enum pc_di_index_size
{
120 INDEX_SIZE_16_BIT
= 0,
121 INDEX_SIZE_32_BIT
= 1,
122 INDEX_SIZE_8_BIT
= 2,
123 INDEX_SIZE_INVALID
= 0,
126 enum pc_di_vis_cull_mode
{
127 IGNORE_VISIBILITY
= 0,
131 enum adreno_pm4_packet_type
{
133 CP_TYPE1_PKT
= 0x40000000,
134 CP_TYPE2_PKT
= 0x80000000,
135 CP_TYPE3_PKT
= 0xc0000000,
136 CP_TYPE4_PKT
= 0x40000000,
137 CP_TYPE7_PKT
= 0x70000000,
140 enum adreno_pm4_type3_packets
{
143 CP_PREEMPT_ENABLE
= 28,
144 CP_PREEMPT_TOKEN
= 30,
145 CP_INDIRECT_BUFFER
= 63,
146 CP_INDIRECT_BUFFER_PFD
= 55,
147 CP_WAIT_FOR_IDLE
= 38,
148 CP_WAIT_REG_MEM
= 60,
150 CP_WAIT_REG_GTE
= 83,
151 CP_WAIT_UNTIL_READ
= 92,
152 CP_WAIT_IB_PFD_COMPLETE
= 93,
154 CP_SET_BIN_DATA
= 47,
155 CP_SET_BIN_DATA5
= 47,
158 CP_MEM_WRITE_CNTR
= 79,
163 CP_EVENT_WRITE_SHD
= 88,
164 CP_EVENT_WRITE_CFL
= 89,
165 CP_EVENT_WRITE_ZPD
= 91,
169 CP_DRAW_INDX_BIN
= 52,
170 CP_DRAW_INDX_2_BIN
= 53,
173 CP_SET_CONSTANT
= 45,
175 CP_IM_LOAD_IMMEDIATE
= 43,
176 CP_LOAD_CONSTANT_CONTEXT
= 46,
177 CP_INVALIDATE_STATE
= 59,
178 CP_SET_SHADER_BASES
= 74,
179 CP_SET_BIN_MASK
= 80,
180 CP_SET_BIN_SELECT
= 81,
181 CP_CONTEXT_UPDATE
= 94,
184 CP_SET_DRAW_INIT_FLAGS
= 75,
185 CP_SET_PROTECTED_MODE
= 95,
186 CP_BOOTSTRAP_UCODE
= 111,
189 CP_COND_INDIRECT_BUFFER_PFE
= 58,
190 CP_COND_INDIRECT_BUFFER_PFD
= 50,
191 CP_INDIRECT_BUFFER_PFE
= 63,
193 CP_TEST_TWO_MEMS
= 113,
194 CP_REG_WR_NO_CTXT
= 120,
195 CP_RECORD_PFP_TIMESTAMP
= 17,
196 CP_SET_SECURE_MODE
= 102,
198 CP_SET_DRAW_STATE
= 67,
199 CP_DRAW_INDX_OFFSET
= 56,
200 CP_DRAW_INDIRECT
= 40,
201 CP_DRAW_INDX_INDIRECT
= 41,
206 CP_WIDE_REG_WRITE
= 116,
207 CP_SCRATCH_TO_REG
= 77,
208 CP_REG_TO_SCRATCH
= 74,
209 CP_WAIT_MEM_WRITES
= 18,
210 CP_COND_REG_EXEC
= 71,
212 CP_EXEC_CS_INDIRECT
= 65,
214 CP_PERFCOUNTER_ACTION
= 80,
215 CP_SMMU_TABLE_UPDATE
= 83,
217 CP_SET_PSEUDO_REG
= 86,
218 CP_CONTEXT_REG_BUNCH
= 92,
219 CP_YIELD_ENABLE
= 28,
220 CP_SKIP_IB2_ENABLE_GLOBAL
= 29,
221 CP_SKIP_IB2_ENABLE_LOCAL
= 35,
222 CP_SET_SUBDRAW_SIZE
= 53,
223 CP_SET_VISIBILITY_OVERRIDE
= 100,
224 CP_PREEMPT_ENABLE_GLOBAL
= 105,
225 CP_PREEMPT_ENABLE_LOCAL
= 106,
226 CP_CONTEXT_SWITCH_YIELD
= 107,
227 CP_SET_RENDER_MODE
= 108,
228 CP_COMPUTE_CHECKPOINT
= 110,
233 CP_LOAD_STATE6_GEOM
= 50,
234 CP_LOAD_STATE6_FRAG
= 52,
236 IN_IB_PREFETCH_END
= 23,
237 IN_SUBBLK_PREFETCH
= 31,
238 IN_INSTR_PREFETCH
= 32,
240 IN_CONST_PREFETCH
= 73,
241 IN_INCR_UPDT_STATE
= 85,
242 IN_INCR_UPDT_CONST
= 86,
243 IN_INCR_UPDT_INSTR
= 87,
250 enum adreno_state_block
{
258 SB_COMPUTE_SHADER
= 7,
261 enum adreno_state_type
{
266 enum adreno_state_src
{
268 SS_INVALID_ALL_IC
= 2,
269 SS_INVALID_PART_IC
= 3,
275 enum a4xx_state_block
{
292 enum a4xx_state_type
{
297 enum a4xx_state_src
{
302 enum a6xx_state_block
{
319 enum a6xx_state_type
{
325 enum a6xx_state_src
{
330 enum a4xx_index_size
{
331 INDEX4_SIZE_8_BIT
= 0,
332 INDEX4_SIZE_16_BIT
= 1,
333 INDEX4_SIZE_32_BIT
= 2,
336 enum cp_cond_function
{
346 enum render_mode_cmd
{
361 enum a6xx_render_mode
{
367 RM6_BLIT2DSCALE
= 12,
372 NON_SECURE_SAVE_ADDR
= 1,
373 SECURE_SAVE_ADDR
= 2,
374 NON_PRIV_SAVE_ADDR
= 3,
378 #define REG_CP_LOAD_STATE_0 0x00000000
379 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
380 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
381 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val
)
383 return ((val
) << CP_LOAD_STATE_0_DST_OFF__SHIFT
) & CP_LOAD_STATE_0_DST_OFF__MASK
;
385 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
386 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
387 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val
)
389 return ((val
) << CP_LOAD_STATE_0_STATE_SRC__SHIFT
) & CP_LOAD_STATE_0_STATE_SRC__MASK
;
391 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
392 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
393 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val
)
395 return ((val
) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT
) & CP_LOAD_STATE_0_STATE_BLOCK__MASK
;
397 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
398 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
399 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val
)
401 return ((val
) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT
) & CP_LOAD_STATE_0_NUM_UNIT__MASK
;
404 #define REG_CP_LOAD_STATE_1 0x00000001
405 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
406 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
407 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val
)
409 return ((val
) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT
) & CP_LOAD_STATE_1_STATE_TYPE__MASK
;
411 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
412 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
413 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val
)
415 assert(!(val
& 0x3));
416 return ((val
>> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT
) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK
;
419 #define REG_CP_LOAD_STATE4_0 0x00000000
420 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
421 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
422 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val
)
424 return ((val
) << CP_LOAD_STATE4_0_DST_OFF__SHIFT
) & CP_LOAD_STATE4_0_DST_OFF__MASK
;
426 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
427 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
428 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val
)
430 return ((val
) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT
) & CP_LOAD_STATE4_0_STATE_SRC__MASK
;
432 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
433 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
434 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val
)
436 return ((val
) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT
) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK
;
438 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
439 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
440 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val
)
442 return ((val
) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT
) & CP_LOAD_STATE4_0_NUM_UNIT__MASK
;
445 #define REG_CP_LOAD_STATE4_1 0x00000001
446 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
447 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
448 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val
)
450 return ((val
) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT
) & CP_LOAD_STATE4_1_STATE_TYPE__MASK
;
452 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
453 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
454 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val
)
456 assert(!(val
& 0x3));
457 return ((val
>> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT
) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK
;
460 #define REG_CP_LOAD_STATE4_2 0x00000002
461 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
462 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
463 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val
)
465 return ((val
) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT
) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK
;
468 #define REG_CP_LOAD_STATE6_0 0x00000000
469 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
470 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
471 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val
)
473 return ((val
) << CP_LOAD_STATE6_0_DST_OFF__SHIFT
) & CP_LOAD_STATE6_0_DST_OFF__MASK
;
475 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
476 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
477 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val
)
479 return ((val
) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT
) & CP_LOAD_STATE6_0_STATE_TYPE__MASK
;
481 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
482 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
483 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val
)
485 return ((val
) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT
) & CP_LOAD_STATE6_0_STATE_SRC__MASK
;
487 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
488 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
489 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val
)
491 return ((val
) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT
) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK
;
493 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
494 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
495 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val
)
497 return ((val
) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT
) & CP_LOAD_STATE6_0_NUM_UNIT__MASK
;
500 #define REG_CP_LOAD_STATE6_1 0x00000001
501 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
502 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
503 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val
)
505 assert(!(val
& 0x3));
506 return ((val
>> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT
) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK
;
509 #define REG_CP_LOAD_STATE6_2 0x00000002
510 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
511 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
512 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val
)
514 return ((val
) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT
) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK
;
517 #define REG_CP_DRAW_INDX_0 0x00000000
518 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
519 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
520 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val
)
522 return ((val
) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT
) & CP_DRAW_INDX_0_VIZ_QUERY__MASK
;
525 #define REG_CP_DRAW_INDX_1 0x00000001
526 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
527 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
528 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val
)
530 return ((val
) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_1_PRIM_TYPE__MASK
;
532 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
533 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
534 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val
)
536 return ((val
) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK
;
538 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
539 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
540 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val
)
542 return ((val
) << CP_DRAW_INDX_1_VIS_CULL__SHIFT
) & CP_DRAW_INDX_1_VIS_CULL__MASK
;
544 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
545 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
546 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val
)
548 return ((val
) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_1_INDEX_SIZE__MASK
;
550 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
551 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
552 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
553 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
554 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
555 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val
)
557 return ((val
) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK
;
560 #define REG_CP_DRAW_INDX_2 0x00000002
561 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
562 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
563 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val
)
565 return ((val
) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_2_NUM_INDICES__MASK
;
568 #define REG_CP_DRAW_INDX_3 0x00000003
569 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
570 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
571 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val
)
573 return ((val
) << CP_DRAW_INDX_3_INDX_BASE__SHIFT
) & CP_DRAW_INDX_3_INDX_BASE__MASK
;
576 #define REG_CP_DRAW_INDX_4 0x00000004
577 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
578 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
579 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val
)
581 return ((val
) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT
) & CP_DRAW_INDX_4_INDX_SIZE__MASK
;
584 #define REG_CP_DRAW_INDX_2_0 0x00000000
585 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
586 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
587 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val
)
589 return ((val
) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT
) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK
;
592 #define REG_CP_DRAW_INDX_2_1 0x00000001
593 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
594 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
595 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val
)
597 return ((val
) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK
;
599 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
600 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
601 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val
)
603 return ((val
) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK
;
605 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
606 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
607 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val
)
609 return ((val
) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT
) & CP_DRAW_INDX_2_1_VIS_CULL__MASK
;
611 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
612 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
613 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val
)
615 return ((val
) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK
;
617 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
618 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
619 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
620 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
621 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
622 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val
)
624 return ((val
) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK
;
627 #define REG_CP_DRAW_INDX_2_2 0x00000002
628 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
629 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
630 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val
)
632 return ((val
) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK
;
635 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
636 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
637 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
638 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val
)
640 return ((val
) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK
;
642 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
643 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
644 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val
)
646 return ((val
) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK
;
648 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
649 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
650 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val
)
652 return ((val
) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT
) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK
;
654 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
655 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
656 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val
)
658 return ((val
) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK
;
660 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
661 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
662 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val
)
664 return ((val
) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK
;
667 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
668 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
669 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
670 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val
)
672 return ((val
) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK
;
675 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
676 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
677 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
678 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val
)
680 return ((val
) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK
;
683 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
685 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
686 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
687 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
688 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val
)
690 return ((val
) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT
) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK
;
693 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
694 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
695 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
696 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val
)
698 return ((val
) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT
) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK
;
701 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
702 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
703 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
704 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val
)
706 return ((val
) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT
) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK
;
708 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
709 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
710 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val
)
712 return ((val
) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT
) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK
;
714 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
715 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
716 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val
)
718 return ((val
) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT
) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK
;
720 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
721 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
722 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val
)
724 return ((val
) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT
) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK
;
726 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
727 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
728 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val
)
730 return ((val
) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT
) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK
;
733 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
734 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
735 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
736 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val
)
738 return ((val
) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT
) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK
;
742 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
743 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
744 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
745 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val
)
747 return ((val
) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT
) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK
;
750 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
751 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
752 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
753 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val
)
755 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK
;
757 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
758 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
759 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val
)
761 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK
;
763 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
764 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
765 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val
)
767 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK
;
769 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
770 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
771 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val
)
773 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK
;
775 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
776 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
777 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val
)
779 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK
;
783 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
784 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
785 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
786 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val
)
788 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK
;
791 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
792 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
793 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
794 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val
)
796 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK
;
799 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
800 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
801 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
802 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val
)
804 return ((val
) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT
) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK
;
808 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
809 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
810 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
811 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val
)
813 return ((val
) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT
) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK
;
816 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
817 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
818 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
819 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val
)
821 return ((val
) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT
) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK
;
824 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
825 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
826 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
827 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val
)
829 return ((val
) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT
) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK
;
832 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
833 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
834 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
835 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val
)
837 return ((val
) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT
) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK
;
840 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
841 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
842 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
843 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val
)
845 return ((val
) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT
) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK
;
848 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0
) { return 0x00000000 + 0x3*i0
; }
850 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0
) { return 0x00000000 + 0x3*i0
; }
851 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
852 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
853 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val
)
855 return ((val
) << CP_SET_DRAW_STATE__0_COUNT__SHIFT
) & CP_SET_DRAW_STATE__0_COUNT__MASK
;
857 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
858 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
859 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
860 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
861 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
862 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
863 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val
)
865 return ((val
) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT
) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK
;
867 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
868 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
869 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val
)
871 return ((val
) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT
) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK
;
874 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0
) { return 0x00000001 + 0x3*i0
; }
875 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
876 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
877 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val
)
879 return ((val
) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT
) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK
;
882 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0
) { return 0x00000002 + 0x3*i0
; }
883 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
884 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
885 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val
)
887 return ((val
) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT
) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK
;
890 #define REG_CP_SET_BIN_0 0x00000000
892 #define REG_CP_SET_BIN_1 0x00000001
893 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
894 #define CP_SET_BIN_1_X1__SHIFT 0
895 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val
)
897 return ((val
) << CP_SET_BIN_1_X1__SHIFT
) & CP_SET_BIN_1_X1__MASK
;
899 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
900 #define CP_SET_BIN_1_Y1__SHIFT 16
901 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val
)
903 return ((val
) << CP_SET_BIN_1_Y1__SHIFT
) & CP_SET_BIN_1_Y1__MASK
;
906 #define REG_CP_SET_BIN_2 0x00000002
907 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
908 #define CP_SET_BIN_2_X2__SHIFT 0
909 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val
)
911 return ((val
) << CP_SET_BIN_2_X2__SHIFT
) & CP_SET_BIN_2_X2__MASK
;
913 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
914 #define CP_SET_BIN_2_Y2__SHIFT 16
915 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val
)
917 return ((val
) << CP_SET_BIN_2_Y2__SHIFT
) & CP_SET_BIN_2_Y2__MASK
;
920 #define REG_CP_SET_BIN_DATA_0 0x00000000
921 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
922 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
923 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val
)
925 return ((val
) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT
) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK
;
928 #define REG_CP_SET_BIN_DATA_1 0x00000001
929 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
930 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
931 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val
)
933 return ((val
) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT
) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK
;
936 #define REG_CP_SET_BIN_DATA5_0 0x00000000
937 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
938 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
939 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val
)
941 return ((val
) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT
) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK
;
943 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
944 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
945 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val
)
947 return ((val
) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT
) & CP_SET_BIN_DATA5_0_VSC_N__MASK
;
950 #define REG_CP_SET_BIN_DATA5_1 0x00000001
951 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
952 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
953 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val
)
955 return ((val
) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT
) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK
;
958 #define REG_CP_SET_BIN_DATA5_2 0x00000002
959 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
960 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
961 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val
)
963 return ((val
) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT
) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK
;
966 #define REG_CP_SET_BIN_DATA5_3 0x00000003
967 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
968 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
969 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val
)
971 return ((val
) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT
) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK
;
974 #define REG_CP_SET_BIN_DATA5_4 0x00000004
975 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
976 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
977 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val
)
979 return ((val
) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT
) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK
;
982 #define REG_CP_SET_BIN_DATA5_5 0x00000005
983 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
984 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
985 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val
)
987 return ((val
) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT
) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK
;
990 #define REG_CP_SET_BIN_DATA5_6 0x00000006
991 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
992 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
993 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val
)
995 return ((val
) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT
) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK
;
998 #define REG_CP_REG_TO_MEM_0 0x00000000
999 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
1000 #define CP_REG_TO_MEM_0_REG__SHIFT 0
1001 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val
)
1003 return ((val
) << CP_REG_TO_MEM_0_REG__SHIFT
) & CP_REG_TO_MEM_0_REG__MASK
;
1005 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
1006 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
1007 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val
)
1009 return ((val
) << CP_REG_TO_MEM_0_CNT__SHIFT
) & CP_REG_TO_MEM_0_CNT__MASK
;
1011 #define CP_REG_TO_MEM_0_64B 0x40000000
1012 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1014 #define REG_CP_REG_TO_MEM_1 0x00000001
1015 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1016 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
1017 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val
)
1019 return ((val
) << CP_REG_TO_MEM_1_DEST__SHIFT
) & CP_REG_TO_MEM_1_DEST__MASK
;
1022 #define REG_CP_REG_TO_MEM_2 0x00000002
1023 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1024 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1025 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val
)
1027 return ((val
) << CP_REG_TO_MEM_2_DEST_HI__SHIFT
) & CP_REG_TO_MEM_2_DEST_HI__MASK
;
1030 #define REG_CP_MEM_TO_REG_0 0x00000000
1031 #define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
1032 #define CP_MEM_TO_REG_0_REG__SHIFT 0
1033 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val
)
1035 return ((val
) << CP_MEM_TO_REG_0_REG__SHIFT
) & CP_MEM_TO_REG_0_REG__MASK
;
1037 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1038 #define CP_MEM_TO_REG_0_CNT__SHIFT 19
1039 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val
)
1041 return ((val
) << CP_MEM_TO_REG_0_CNT__SHIFT
) & CP_MEM_TO_REG_0_CNT__MASK
;
1043 #define CP_MEM_TO_REG_0_64B 0x40000000
1044 #define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
1046 #define REG_CP_MEM_TO_REG_1 0x00000001
1047 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1048 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
1049 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val
)
1051 return ((val
) << CP_MEM_TO_REG_1_SRC__SHIFT
) & CP_MEM_TO_REG_1_SRC__MASK
;
1054 #define REG_CP_MEM_TO_REG_2 0x00000002
1055 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1056 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1057 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val
)
1059 return ((val
) << CP_MEM_TO_REG_2_SRC_HI__SHIFT
) & CP_MEM_TO_REG_2_SRC_HI__MASK
;
1062 #define REG_CP_MEM_TO_MEM_0 0x00000000
1063 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1064 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1065 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1066 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1068 #define REG_CP_COND_WRITE_0 0x00000000
1069 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1070 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1071 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val
)
1073 return ((val
) << CP_COND_WRITE_0_FUNCTION__SHIFT
) & CP_COND_WRITE_0_FUNCTION__MASK
;
1075 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1076 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1078 #define REG_CP_COND_WRITE_1 0x00000001
1079 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1080 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1081 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val
)
1083 return ((val
) << CP_COND_WRITE_1_POLL_ADDR__SHIFT
) & CP_COND_WRITE_1_POLL_ADDR__MASK
;
1086 #define REG_CP_COND_WRITE_2 0x00000002
1087 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1088 #define CP_COND_WRITE_2_REF__SHIFT 0
1089 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val
)
1091 return ((val
) << CP_COND_WRITE_2_REF__SHIFT
) & CP_COND_WRITE_2_REF__MASK
;
1094 #define REG_CP_COND_WRITE_3 0x00000003
1095 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1096 #define CP_COND_WRITE_3_MASK__SHIFT 0
1097 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val
)
1099 return ((val
) << CP_COND_WRITE_3_MASK__SHIFT
) & CP_COND_WRITE_3_MASK__MASK
;
1102 #define REG_CP_COND_WRITE_4 0x00000004
1103 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1104 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1105 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val
)
1107 return ((val
) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT
) & CP_COND_WRITE_4_WRITE_ADDR__MASK
;
1110 #define REG_CP_COND_WRITE_5 0x00000005
1111 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1112 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1113 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val
)
1115 return ((val
) << CP_COND_WRITE_5_WRITE_DATA__SHIFT
) & CP_COND_WRITE_5_WRITE_DATA__MASK
;
1118 #define REG_CP_COND_WRITE5_0 0x00000000
1119 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1120 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1121 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val
)
1123 return ((val
) << CP_COND_WRITE5_0_FUNCTION__SHIFT
) & CP_COND_WRITE5_0_FUNCTION__MASK
;
1125 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1126 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1128 #define REG_CP_COND_WRITE5_1 0x00000001
1129 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1130 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1131 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val
)
1133 return ((val
) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT
) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK
;
1136 #define REG_CP_COND_WRITE5_2 0x00000002
1137 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1138 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1139 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val
)
1141 return ((val
) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT
) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK
;
1144 #define REG_CP_COND_WRITE5_3 0x00000003
1145 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1146 #define CP_COND_WRITE5_3_REF__SHIFT 0
1147 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val
)
1149 return ((val
) << CP_COND_WRITE5_3_REF__SHIFT
) & CP_COND_WRITE5_3_REF__MASK
;
1152 #define REG_CP_COND_WRITE5_4 0x00000004
1153 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1154 #define CP_COND_WRITE5_4_MASK__SHIFT 0
1155 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val
)
1157 return ((val
) << CP_COND_WRITE5_4_MASK__SHIFT
) & CP_COND_WRITE5_4_MASK__MASK
;
1160 #define REG_CP_COND_WRITE5_5 0x00000005
1161 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1162 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1163 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val
)
1165 return ((val
) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT
) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK
;
1168 #define REG_CP_COND_WRITE5_6 0x00000006
1169 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1170 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1171 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val
)
1173 return ((val
) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT
) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK
;
1176 #define REG_CP_COND_WRITE5_7 0x00000007
1177 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1178 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1179 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val
)
1181 return ((val
) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT
) & CP_COND_WRITE5_7_WRITE_DATA__MASK
;
1184 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1186 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1187 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1188 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1189 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val
)
1191 return ((val
) << CP_DISPATCH_COMPUTE_1_X__SHIFT
) & CP_DISPATCH_COMPUTE_1_X__MASK
;
1194 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1195 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1196 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1197 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val
)
1199 return ((val
) << CP_DISPATCH_COMPUTE_2_Y__SHIFT
) & CP_DISPATCH_COMPUTE_2_Y__MASK
;
1202 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1203 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1204 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1205 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val
)
1207 return ((val
) << CP_DISPATCH_COMPUTE_3_Z__SHIFT
) & CP_DISPATCH_COMPUTE_3_Z__MASK
;
1210 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1211 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1212 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1213 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val
)
1215 return ((val
) << CP_SET_RENDER_MODE_0_MODE__SHIFT
) & CP_SET_RENDER_MODE_0_MODE__MASK
;
1218 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1219 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1220 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1221 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val
)
1223 return ((val
) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT
) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK
;
1226 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1227 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1228 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1229 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val
)
1231 return ((val
) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT
) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK
;
1234 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1235 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1236 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1238 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1240 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1241 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1242 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1243 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val
)
1245 return ((val
) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT
) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK
;
1248 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1249 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1250 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1251 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val
)
1253 return ((val
) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT
) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK
;
1256 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1257 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1258 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1259 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val
)
1261 return ((val
) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT
) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK
;
1264 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1265 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1266 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1267 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val
)
1269 return ((val
) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT
) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK
;
1272 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1273 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1274 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1275 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val
)
1277 return ((val
) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT
) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK
;
1280 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1282 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1283 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1284 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1285 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val
)
1287 return ((val
) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT
) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK
;
1290 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1292 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1293 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1294 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1295 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val
)
1297 return ((val
) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT
) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK
;
1300 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1301 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1302 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1303 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val
)
1305 return ((val
) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT
) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK
;
1308 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1310 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1312 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1313 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1314 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
1315 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val
)
1317 return ((val
) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT
) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK
;
1320 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1321 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1322 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
1323 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val
)
1325 return ((val
) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT
) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK
;
1328 #define REG_CP_EVENT_WRITE_0 0x00000000
1329 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1330 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1331 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val
)
1333 return ((val
) << CP_EVENT_WRITE_0_EVENT__SHIFT
) & CP_EVENT_WRITE_0_EVENT__MASK
;
1335 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1337 #define REG_CP_EVENT_WRITE_1 0x00000001
1338 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1339 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1340 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val
)
1342 return ((val
) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT
) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK
;
1345 #define REG_CP_EVENT_WRITE_2 0x00000002
1346 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1347 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1348 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val
)
1350 return ((val
) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT
) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK
;
1353 #define REG_CP_EVENT_WRITE_3 0x00000003
1355 #define REG_CP_BLIT_0 0x00000000
1356 #define CP_BLIT_0_OP__MASK 0x0000000f
1357 #define CP_BLIT_0_OP__SHIFT 0
1358 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val
)
1360 return ((val
) << CP_BLIT_0_OP__SHIFT
) & CP_BLIT_0_OP__MASK
;
1363 #define REG_CP_BLIT_1 0x00000001
1364 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1365 #define CP_BLIT_1_SRC_X1__SHIFT 0
1366 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val
)
1368 return ((val
) << CP_BLIT_1_SRC_X1__SHIFT
) & CP_BLIT_1_SRC_X1__MASK
;
1370 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1371 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1372 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val
)
1374 return ((val
) << CP_BLIT_1_SRC_Y1__SHIFT
) & CP_BLIT_1_SRC_Y1__MASK
;
1377 #define REG_CP_BLIT_2 0x00000002
1378 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1379 #define CP_BLIT_2_SRC_X2__SHIFT 0
1380 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val
)
1382 return ((val
) << CP_BLIT_2_SRC_X2__SHIFT
) & CP_BLIT_2_SRC_X2__MASK
;
1384 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1385 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1386 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val
)
1388 return ((val
) << CP_BLIT_2_SRC_Y2__SHIFT
) & CP_BLIT_2_SRC_Y2__MASK
;
1391 #define REG_CP_BLIT_3 0x00000003
1392 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1393 #define CP_BLIT_3_DST_X1__SHIFT 0
1394 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val
)
1396 return ((val
) << CP_BLIT_3_DST_X1__SHIFT
) & CP_BLIT_3_DST_X1__MASK
;
1398 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1399 #define CP_BLIT_3_DST_Y1__SHIFT 16
1400 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val
)
1402 return ((val
) << CP_BLIT_3_DST_Y1__SHIFT
) & CP_BLIT_3_DST_Y1__MASK
;
1405 #define REG_CP_BLIT_4 0x00000004
1406 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
1407 #define CP_BLIT_4_DST_X2__SHIFT 0
1408 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val
)
1410 return ((val
) << CP_BLIT_4_DST_X2__SHIFT
) & CP_BLIT_4_DST_X2__MASK
;
1412 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
1413 #define CP_BLIT_4_DST_Y2__SHIFT 16
1414 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val
)
1416 return ((val
) << CP_BLIT_4_DST_Y2__SHIFT
) & CP_BLIT_4_DST_Y2__MASK
;
1419 #define REG_CP_EXEC_CS_0 0x00000000
1421 #define REG_CP_EXEC_CS_1 0x00000001
1422 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1423 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1424 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val
)
1426 return ((val
) << CP_EXEC_CS_1_NGROUPS_X__SHIFT
) & CP_EXEC_CS_1_NGROUPS_X__MASK
;
1429 #define REG_CP_EXEC_CS_2 0x00000002
1430 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1431 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1432 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val
)
1434 return ((val
) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT
) & CP_EXEC_CS_2_NGROUPS_Y__MASK
;
1437 #define REG_CP_EXEC_CS_3 0x00000003
1438 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1439 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1440 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val
)
1442 return ((val
) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT
) & CP_EXEC_CS_3_NGROUPS_Z__MASK
;
1445 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
1448 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1449 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
1450 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
1451 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val
)
1453 return ((val
) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT
) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK
;
1456 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1457 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
1458 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
1459 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val
)
1461 return ((val
) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT
) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK
;
1463 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
1464 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
1465 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val
)
1467 return ((val
) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT
) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK
;
1469 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
1470 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
1471 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val
)
1473 return ((val
) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT
) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK
;
1477 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1478 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1479 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
1480 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val
)
1482 return ((val
) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT
) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK
;
1485 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1486 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1487 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
1488 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val
)
1490 return ((val
) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT
) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK
;
1493 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
1494 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1495 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
1496 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val
)
1498 return ((val
) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT
) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK
;
1500 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1501 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
1502 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val
)
1504 return ((val
) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT
) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK
;
1506 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1507 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
1508 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val
)
1510 return ((val
) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT
) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK
;
1513 #define REG_A2XX_CP_SET_MARKER_0 0x00000000
1514 #define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
1515 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
1516 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val
)
1518 return ((val
) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT
) & A2XX_CP_SET_MARKER_0_MARKER__MASK
;
1520 #define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
1521 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
1522 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val
)
1524 return ((val
) << A2XX_CP_SET_MARKER_0_MODE__SHIFT
) & A2XX_CP_SET_MARKER_0_MODE__MASK
;
1526 #define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
1528 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0
) { return 0x00000000 + 0x3*i0
; }
1530 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0
) { return 0x00000000 + 0x3*i0
; }
1531 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
1532 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
1533 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val
)
1535 return ((val
) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT
) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK
;
1538 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0
) { return 0x00000001 + 0x3*i0
; }
1539 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
1540 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
1541 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val
)
1543 return ((val
) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT
) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK
;
1546 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0
) { return 0x00000002 + 0x3*i0
; }
1547 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
1548 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
1549 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val
)
1551 return ((val
) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT
) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK
;
1554 #define REG_A2XX_CP_REG_TEST_0 0x00000000
1555 #define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
1556 #define A2XX_CP_REG_TEST_0_REG__SHIFT 0
1557 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val
)
1559 return ((val
) << A2XX_CP_REG_TEST_0_REG__SHIFT
) & A2XX_CP_REG_TEST_0_REG__MASK
;
1561 #define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
1562 #define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
1563 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val
)
1565 return ((val
) << A2XX_CP_REG_TEST_0_BIT__SHIFT
) & A2XX_CP_REG_TEST_0_BIT__MASK
;
1567 #define A2XX_CP_REG_TEST_0_UNK25 0x02000000
1570 #endif /* ADRENO_PM4_XML */