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turnip: Make sure we include the build id.
[mesa.git] / src / freedreno / registers / hdmi / hdmi.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5 <import file="freedreno_copyright.xml"/>
6
7 <!--
8 NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear
9 to have the same HDMI block (or maybe a newer version?) but for
10 some reason duplicate the code under drivers/video/msm/mdss
11 -->
12
13 <domain name="HDMI" width="32">
14 <enum name="hdmi_hdcp_key_state">
15 <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
16 <value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/>
17 <value name="HDCP_KEYS_STATE_CHECKING" value="2"/>
18 <value name="HDCP_KEYS_STATE_VALID" value="3"/>
19 <value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/>
20 <value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/>
21 <value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/>
22 <value name="HDCP_KEYS_STATE_RESERVED" value="7"/>
23 </enum>
24 <enum name="hdmi_ddc_read_write">
25 <value name="DDC_WRITE" value="0"/>
26 <value name="DDC_READ" value="1"/>
27 </enum>
28 <enum name="hdmi_acr_cts">
29 <value name="ACR_NONE" value="0"/>
30 <value name="ACR_32" value="1"/>
31 <value name="ACR_44" value="2"/>
32 <value name="ACR_48" value="3"/>
33 </enum>
34
35 <reg32 offset="0x00000" name="CTRL">
36 <bitfield name="ENABLE" pos="0" type="boolean"/>
37 <bitfield name="HDMI" pos="1" type="boolean"/>
38 <bitfield name="ENCRYPTED" pos="2" type="boolean"/>
39 </reg32>
40 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
41 <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
42 </reg32>
43 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
44 <!--
45 Guessing on order of bitfields from these comments:
46 /* AUDIO_PRIORITY | SOURCE */
47 acr_pck_ctrl_reg |= 0x80000100;
48 /* N_MULTIPLE(multiplier) */
49 acr_pck_ctrl_reg |= (multiplier & 7) << 16;
50 /* SEND | CONT */
51 acr_pck_ctrl_reg |= 0x00000003;
52 -->
53 <bitfield name="CONT" pos="0" type="boolean"/>
54 <bitfield name="SEND" pos="1" type="boolean"/>
55 <bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/>
56 <bitfield name="SOURCE" pos="8" type="boolean"/>
57 <bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/>
58 <bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
59 </reg32>
60 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
61 <!--
62 Guessing on the order of bits from:
63 /* GC packet enable (every frame) */
64 /* HDMI_VBI_PKT_CTRL[0x0028] */
65 hdmi_msm_rmw32or(0x0028, 3 << 4);
66 /* HDMI_VBI_PKT_CTRL[0x0028] */
67 /* ISRC Send + Continuous */
68 hdmi_msm_rmw32or(0x0028, 3 << 8);
69 /* HDMI_VBI_PKT_CTRL[0x0028] */
70 /* ACP send, s/w source */
71 hdmi_msm_rmw32or(0x0028, 3 << 12);
72 -->
73 <bitfield name="GC_ENABLE" pos="4" type="boolean"/>
74 <bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
75 <bitfield name="ISRC_SEND" pos="8" type="boolean"/>
76 <bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
77 <bitfield name="ACP_SEND" pos="12" type="boolean"/>
78 <bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
79 </reg32>
80 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
81 <!--
82 Guessing on the order of these flags, from this comment:
83 /* Set these flags */
84 /* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
85 | AUDIO_INFO_SEND */
86 audio_info_ctrl_reg |= 0x000000F0;
87 /* 0x3 for AVI InfFrame enable (every frame) */
88 HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
89 -->
90 <bitfield name="AVI_SEND" pos="0" type="boolean"/>
91 <bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame -->
92 <bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
93 <bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame -->
94 <bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
95 <bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
96 </reg32>
97 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
98 <bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
99 <bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/>
100 <bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/>
101 <bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/>
102 </reg32>
103 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
104 <!--
105 0x0034 GEN_PKT_CTRL
106 GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
107 1 = Enable Generic0 Packet Transmission
108 GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
109 1 = Send Generic0 Packet on every frame
110 GENERIC0_UPDATE 2 NUM
111 GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
112 1 = Enable Generic1 Packet Transmission
113 GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
114 1 = Send Generic1 Packet on every frame
115 GENERIC0_LINE 21:16 NUM
116 GENERIC1_LINE 29:24 NUM
117
118 GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
119 Setup HDMI TX generic packet control
120 Enable this packet to transmit every frame
121 Enable this packet to transmit every frame
122 Enable HDMI TX engine to transmit Generic packet 0
123 HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
124 -->
125 <bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
126 <bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
127 <bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
128 <bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
129 <bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
130 <bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/>
131 <bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/>
132 </reg32>
133 <reg32 offset="0x00040" name="GC">
134 <bitfield name="MUTE" pos="0" type="boolean"/>
135 </reg32>
136 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
137 <bitfield name="OVERRIDE" pos="0" type="boolean"/>
138 <bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
139 </reg32>
140
141 <!--
142 AVI_INFO appears to be the infoframe in a slightly weird order..
143 starts with PB0 (checksum), and ends with version..
144 -->
145 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
146
147 <reg32 offset="0x00084" name="GENERIC0_HDR"/>
148 <reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
149
150 <reg32 offset="0x000a4" name="GENERIC1_HDR"/>
151 <reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
152
153 <!--
154 TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
155 -->
156 <array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
157 <reg32 offset="0" name="0">
158 <bitfield name="CTS" low="12" high="31" type="uint"/>
159 </reg32>
160 <reg32 offset="4" name="1">
161 <!-- not sure the actual # of bits.. -->
162 <bitfield name="N" low="0" high="31" type="uint"/>
163 </reg32>
164 </array>
165
166 <reg32 offset="0x000e4" name="AUDIO_INFO0">
167 <bitfield name="CHECKSUM" low="0" high="7"/>
168 <bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
169 </reg32>
170 <reg32 offset="0x000e8" name="AUDIO_INFO1">
171 <bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
172 <bitfield name="LSV" low="11" high="14"/> <!-- Level Shift -->
173 <bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag -->
174 </reg32>
175 <reg32 offset="0x00110" name="HDCP_CTRL">
176 <bitfield name="ENABLE" pos="0" type="boolean"/>
177 <bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
178 </reg32>
179 <reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
180 <bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
181 </reg32>
182 <reg32 offset="0x00118" name="HDCP_INT_CTRL">
183 <bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
184 <bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
185 <bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
186 <bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
187 <bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
188 <bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
189 <bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
190 <bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
191 <bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
192 <bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
193 <bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
194 <bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
195 <bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
196 </reg32>
197 <reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
198 <bitfield name="AN_0_READY" pos="8" type="boolean"/>
199 <bitfield name="AN_1_READY" pos="9" type="boolean"/>
200 <bitfield name="RI_MATCHES" pos="12" type="boolean"/>
201 <bitfield name="V_MATCHES" pos="20" type="boolean"/>
202 <bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/>
203 </reg32>
204 <reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
205 <bitfield name="DISABLE" pos="0" type="boolean"/>
206 </reg32>
207 <reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
208 <bitfield name="FAILED_ACK" pos="0" type="boolean"/>
209 </reg32>
210 <reg32 offset="0x00128" name="HDCP_DDC_STATUS">
211 <bitfield name="XFER_REQ" pos="4" type="boolean"/>
212 <bitfield name="XFER_DONE" pos="10" type="boolean"/>
213 <bitfield name="ABORTED" pos="12" type="boolean"/>
214 <bitfield name="TIMEOUT" pos="13" type="boolean"/>
215 <bitfield name="NACK0" pos="14" type="boolean"/>
216 <bitfield name="NACK1" pos="15" type="boolean"/>
217 <bitfield name="FAILED" pos="16" type="boolean"/>
218 </reg32>
219
220 <reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
221 <reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
222
223 <reg32 offset="0x00130" name="HDCP_RESET">
224 <bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
225 </reg32>
226
227 <reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
228 <reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
229 <reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
230 <reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
231 <reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
232 <reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
233 <reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
234 <reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
235 <reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
236 <reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
237 <reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
238 <reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
239 <reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
240 <reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
241
242 <reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
243 <reg32 offset="0x00170" name="VENSPEC_INFO1"/>
244 <reg32 offset="0x00174" name="VENSPEC_INFO2"/>
245 <reg32 offset="0x00178" name="VENSPEC_INFO3"/>
246 <reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
247 <reg32 offset="0x00180" name="VENSPEC_INFO5"/>
248 <reg32 offset="0x00184" name="VENSPEC_INFO6"/>
249
250 <reg32 offset="0x001d0" name="AUDIO_CFG">
251 <bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
252 <bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/>
253 </reg32>
254
255 <reg32 offset="0x00208" name="USEC_REFTIMER"/>
256 <reg32 offset="0x0020c" name="DDC_CTRL">
257 <!--
258 0x020C HDMI_DDC_CTRL
259 [21:20] TRANSACTION_CNT
260 Number of transactions to be done in current transfer.
261 * 0x0: transaction0 only
262 * 0x1: transaction0, transaction1
263 * 0x2: transaction0, transaction1, transaction2
264 * 0x3: transaction0, transaction1, transaction2, transaction3
265 [3] SW_STATUS_RESET
266 Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
267 ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
268 STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
269 [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
270 data) at start of transfer. This sequence is sent after GO is
271 written to 1, before the first transaction only.
272 [1] SOFT_RESET Write 1 to reset DDC controller
273 [0] GO WRITE ONLY. Write 1 to start DDC transfer.
274 -->
275 <bitfield name="GO" pos="0" type="boolean"/>
276 <bitfield name="SOFT_RESET" pos="1" type="boolean"/>
277 <bitfield name="SEND_RESET" pos="2" type="boolean"/>
278 <bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
279 <bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/>
280 </reg32>
281 <reg32 offset="0x00210" name="DDC_ARBITRATION">
282 <bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
283 </reg32>
284 <reg32 offset="0x00214" name="DDC_INT_CTRL">
285 <!--
286 HDMI_DDC_INT_CTRL[0x0214]
287 [2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
288 interrupt.
289 [1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
290 Write 1 to clear interrupt.
291 [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
292 -->
293 <bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
294 <bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
295 <bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
296 </reg32>
297 <reg32 offset="0x00218" name="DDC_SW_STATUS">
298 <bitfield name="NACK0" pos="12" type="boolean"/>
299 <bitfield name="NACK1" pos="13" type="boolean"/>
300 <bitfield name="NACK2" pos="14" type="boolean"/>
301 <bitfield name="NACK3" pos="15" type="boolean"/>
302 </reg32>
303 <reg32 offset="0x0021c" name="DDC_HW_STATUS">
304 <bitfield name="DONE" pos="3" type="boolean"/>
305 </reg32>
306 <reg32 offset="0x00220" name="DDC_SPEED">
307 <!--
308 0x0220 HDMI_DDC_SPEED
309 [31:16] PRESCALE prescale = (m * xtal_frequency) /
310 (desired_i2c_speed), where m is multiply
311 factor, default: m = 1
312 [1:0] THRESHOLD Select threshold to use to determine whether value
313 sampled on SDA is a 1 or 0. Specified in terms of the ratio
314 between the number of sampled ones and the total number of times
315 SDA is sampled.
316 * 0x0: >0
317 * 0x1: 1/4 of total samples
318 * 0x2: 1/2 of total samples
319 * 0x3: 3/4 of total samples */
320 -->
321 <bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
322 <bitfield name="PRESCALE" low="16" high="31" type="uint"/>
323 </reg32>
324 <reg32 offset="0x00224" name="DDC_SETUP">
325 <!--
326 * 0x0224 HDMI_DDC_SETUP
327 * Setting 31:24 bits : Time units to wait before timeout
328 * when clock is being stalled by external sink device
329 -->
330 <bitfield name="TIMEOUT" low="24" high="31" type="uint"/>
331 </reg32>
332 <!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
333 <array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
334 <reg32 offset="0" name="REG">
335 <!--
336 0x0228 HDMI_DDC_TRANS0
337 [23:16] CNT0 Byte count for first transaction (excluding the first
338 byte, which is usually the address).
339 [13] STOP0 Determines whether a stop bit will be sent after the first
340 transaction
341 * 0: NO STOP
342 * 1: STOP
343 [12] START0 Determines whether a start bit will be sent before the
344 first transaction
345 * 0: NO START
346 * 1: START
347 [8] STOP_ON_NACK0 Determines whether the current transfer will stop
348 if a NACK is received during the first transaction (current
349 transaction always stops).
350 * 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
351 * 1: STOP ALL TRANSACTIONS, SEND STOP BIT
352 [0] RW0 Read/write indicator for first transaction - set to 0 for
353 write, 1 for read. This bit only controls HDMI_DDC behaviour -
354 the R/W bit in the transaction is programmed into the DDC buffer
355 as the LSB of the address byte.
356 * 0: WRITE
357 * 1: READ
358 -->
359 <bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
360 <bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
361 <bitfield name="START" pos="12" type="boolean"/>
362 <bitfield name="STOP" pos="13" type="boolean"/>
363 <bitfield name="CNT" low="16" high="23" type="uint"/>
364 </reg32>
365 </array>
366 <reg32 offset="0x00238" name="DDC_DATA">
367 <!--
368 0x0238 HDMI_DDC_DATA
369 [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
370 1 while writing HDMI_DDC_DATA.
371 [23:16] INDEX Use to set index into DDC buffer for next read or
372 current write, or to read index of current read or next write.
373 Writable only when INDEX_WRITE=1.
374 [15:8] DATA Use to fill or read the DDC buffer
375 [0] DATA_RW Select whether buffer access will be a read or write.
376 For writes, address auto-increments on write to HDMI_DDC_DATA.
377 For reads, address autoincrements on reads to HDMI_DDC_DATA.
378 * 0: Write
379 * 1: Read
380 -->
381 <bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
382 <bitfield name="DATA" low="8" high="15" type="uint"/>
383 <bitfield name="INDEX" low="16" high="23" type="uint"/>
384 <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
385 </reg32>
386
387 <reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
388 <reg32 offset="0x00240" name="HDCP_SHA_STATUS">
389 <bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
390 <bitfield name="COMP_DONE" pos="4" type="boolean"/>
391 </reg32>
392 <reg32 offset="0x00244" name="HDCP_SHA_DATA">
393 <bitfield name="DONE" pos="0" type="boolean"/>
394 </reg32>
395
396 <reg32 offset="0x00250" name="HPD_INT_STATUS">
397 <bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
398 <bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
399 </reg32>
400 <reg32 offset="0x00254" name="HPD_INT_CTRL">
401 <!-- (this useful comment was removed in df6b645.. git archaeology is fun)
402 HPD_INT_CTRL[0x0254]
403 31:10 Reserved
404 9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask.
405 When programmed to 1,
406 RCV_PLUGIN_DET_INT will toggle
407 the interrupt line
408 8:6 Reserved
409 5 RX_INT_EN Panel RX interrupt enable
410 0: Disable
411 1: Enable
412 4 RX_INT_ACK WRITE ONLY. Panel RX interrupt
413 ack
414 3 Reserved
415 2 INT_EN Panel interrupt control
416 0: Disable
417 1: Enable
418 1 INT_POLARITY Panel interrupt polarity
419 0: generate interrupt on disconnect
420 1: generate interrupt on connect
421 0 INT_ACK WRITE ONLY. Panel interrupt ack
422 -->
423 <bitfield name="INT_ACK" pos="0" type="boolean"/>
424 <bitfield name="INT_CONNECT" pos="1" type="boolean"/>
425 <bitfield name="INT_EN" pos="2" type="boolean"/>
426 <bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
427 <bitfield name="RX_INT_EN" pos="5" type="boolean"/>
428 <bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
429 </reg32>
430 <reg32 offset="0x00258" name="HPD_CTRL">
431 <bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
432 <bitfield name="ENABLE" pos="28" type="boolean"/>
433 </reg32>
434 <reg32 offset="0x0027c" name="DDC_REF">
435 <!--
436 0x027C HDMI_DDC_REF
437 [16] REFTIMER_ENABLE Enable the timer
438 * 0: Disable
439 * 1: Enable
440 [15:0] REFTIMER Value to set the register in order to generate
441 DDC strobe. This register counts on HDCP application clock
442
443 /* Enable reference timer
444 * 27 micro-seconds */
445 HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
446 -->
447 <bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
448 <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
449 </reg32>
450
451 <reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
452 <reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
453
454 <reg32 offset="0x0028c" name="CEC_CTRL"/>
455 <reg32 offset="0x00290" name="CEC_WR_DATA"/>
456 <reg32 offset="0x00294" name="CEC_CEC_RETRANSMIT"/>
457 <reg32 offset="0x00298" name="CEC_STATUS"/>
458 <reg32 offset="0x0029c" name="CEC_INT"/>
459 <reg32 offset="0x002a0" name="CEC_ADDR"/>
460 <reg32 offset="0x002a4" name="CEC_TIME"/>
461 <reg32 offset="0x002a8" name="CEC_REFTIMER"/>
462 <reg32 offset="0x002ac" name="CEC_RD_DATA"/>
463 <reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
464
465 <reg32 offset="0x002b4" name="ACTIVE_HSYNC">
466 <bitfield name="START" low="0" high="12" type="uint"/>
467 <bitfield name="END" low="16" high="27" type="uint"/>
468 </reg32>
469 <reg32 offset="0x002b8" name="ACTIVE_VSYNC">
470 <bitfield name="START" low="0" high="12" type="uint"/>
471 <bitfield name="END" low="16" high="28" type="uint"/>
472 </reg32>
473 <reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
474 <!-- interlaced, frame 2 -->
475 <bitfield name="START" low="0" high="12" type="uint"/>
476 <bitfield name="END" low="16" high="28" type="uint"/>
477 </reg32>
478 <reg32 offset="0x002c0" name="TOTAL">
479 <bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
480 <bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
481 </reg32>
482 <reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
483 <!-- interlaced, frame 2 -->
484 <bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
485 </reg32>
486 <reg32 offset="0x002c8" name="FRAME_CTRL">
487 <bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
488 <bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
489 <bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
490 <bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
491 </reg32>
492 <reg32 offset="0x002cc" name="AUD_INT">
493 <!--
494 HDMI_AUD_INT[0x02CC]
495 [3] AUD_SAM_DROP_MASK [R/W]
496 [2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
497 [1] AUD_FIFO_URUN_MASK [R/W]
498 [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
499 -->
500 <bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
501 <bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
502 <bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq -->
503 <bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq -->
504 </reg32>
505 <reg32 offset="0x002d4" name="PHY_CTRL">
506 <!--
507 in hdmi_phy_reset() it appears to be toggling SW_RESET/
508 SW_RESET_PLL based on the value of the bit above, so
509 I'm guessing the bit above is a polarit bit
510 -->
511 <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
512 <bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
513 <bitfield name="SW_RESET" pos="2" type="boolean"/>
514 <bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
515 </reg32>
516 <reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
517 <reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
518 <reg32 offset="0x002e4" name="VERSION"/>
519 <reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
520 <reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
521 <reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
522 <reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
523 <reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
524
525 </domain>
526
527 <domain name="HDMI_8x60" width="32">
528 <reg32 offset="0x00000" name="PHY_REG0">
529 <bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/>
530 </reg32>
531 <reg32 offset="0x00004" name="PHY_REG1">
532 <bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/>
533 <bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
534 </reg32>
535 <reg32 offset="0x00008" name="PHY_REG2">
536 <bitfield name="PD_DESER" pos="0" type="boolean"/>
537 <bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
538 <bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
539 <bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
540 <bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
541 <bitfield name="PD_PLL" pos="5" type="boolean"/>
542 <bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
543 <bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
544 </reg32>
545 <reg32 offset="0x0000c" name="PHY_REG3">
546 <bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
547 </reg32>
548 <reg32 offset="0x00010" name="PHY_REG4"/>
549 <reg32 offset="0x00014" name="PHY_REG5"/>
550 <reg32 offset="0x00018" name="PHY_REG6"/>
551 <reg32 offset="0x0001c" name="PHY_REG7"/>
552 <reg32 offset="0x00020" name="PHY_REG8"/>
553 <reg32 offset="0x00024" name="PHY_REG9"/>
554 <reg32 offset="0x00028" name="PHY_REG10"/>
555 <reg32 offset="0x0002c" name="PHY_REG11"/>
556 <reg32 offset="0x00030" name="PHY_REG12">
557 <bitfield name="RETIMING_EN" pos="0" type="boolean"/>
558 <bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
559 <bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
560 </reg32>
561 </domain>
562
563 <domain name="HDMI_8960" width="32">
564 <!--
565 some of the bitfields may be same as 8x60.. but no helpful comments
566 in msm_dss_io_8960.c
567 -->
568 <reg32 offset="0x00000" name="PHY_REG0"/>
569 <reg32 offset="0x00004" name="PHY_REG1"/>
570 <reg32 offset="0x00008" name="PHY_REG2"/>
571 <reg32 offset="0x0000c" name="PHY_REG3"/>
572 <reg32 offset="0x00010" name="PHY_REG4"/>
573 <reg32 offset="0x00014" name="PHY_REG5"/>
574 <reg32 offset="0x00018" name="PHY_REG6"/>
575 <reg32 offset="0x0001c" name="PHY_REG7"/>
576 <reg32 offset="0x00020" name="PHY_REG8"/>
577 <reg32 offset="0x00024" name="PHY_REG9"/>
578 <reg32 offset="0x00028" name="PHY_REG10"/>
579 <reg32 offset="0x0002c" name="PHY_REG11"/>
580 <reg32 offset="0x00030" name="PHY_REG12">
581 <bitfield name="SW_RESET" pos="5" type="boolean"/>
582 <bitfield name="PWRDN_B" pos="7" type="boolean"/>
583 </reg32>
584 <reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
585 <reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
586 <reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
587 <reg32 offset="0x00040" name="PHY_REG13"/>
588 <reg32 offset="0x00044" name="PHY_REG14"/>
589 <reg32 offset="0x00048" name="PHY_REG15"/>
590 </domain>
591
592 <domain name="HDMI_8960_PHY_PLL" width="32">
593 <reg32 offset="0x00000" name="REFCLK_CFG"/>
594 <reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
595 <reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
596 <reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
597 <reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
598 <reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
599 <reg32 offset="0x00018" name="PWRDN_B">
600 <bitfield name="PD_PLL" pos="1" type="boolean"/>
601 <bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
602 </reg32>
603 <reg32 offset="0x0001c" name="SDM_CFG0"/>
604 <reg32 offset="0x00020" name="SDM_CFG1"/>
605 <reg32 offset="0x00024" name="SDM_CFG2"/>
606 <reg32 offset="0x00028" name="SDM_CFG3"/>
607 <reg32 offset="0x0002c" name="SDM_CFG4"/>
608 <reg32 offset="0x00030" name="SSC_CFG0"/>
609 <reg32 offset="0x00034" name="SSC_CFG1"/>
610 <reg32 offset="0x00038" name="SSC_CFG2"/>
611 <reg32 offset="0x0003c" name="SSC_CFG3"/>
612 <reg32 offset="0x00040" name="LOCKDET_CFG0"/>
613 <reg32 offset="0x00044" name="LOCKDET_CFG1"/>
614 <reg32 offset="0x00048" name="LOCKDET_CFG2"/>
615 <reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
616 <reg32 offset="0x00050" name="VCOCAL_CFG1"/>
617 <reg32 offset="0x00054" name="VCOCAL_CFG2"/>
618 <reg32 offset="0x00058" name="VCOCAL_CFG3"/>
619 <reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
620 <reg32 offset="0x00060" name="VCOCAL_CFG5"/>
621 <reg32 offset="0x00064" name="VCOCAL_CFG6"/>
622 <reg32 offset="0x00068" name="VCOCAL_CFG7"/>
623 <reg32 offset="0x0006c" name="DEBUG_SEL"/>
624 <reg32 offset="0x00070" name="MISC0"/>
625 <reg32 offset="0x00074" name="MISC1"/>
626 <reg32 offset="0x00078" name="MISC2"/>
627 <reg32 offset="0x0007c" name="MISC3"/>
628 <reg32 offset="0x00080" name="MISC4"/>
629 <reg32 offset="0x00084" name="MISC5"/>
630 <reg32 offset="0x00088" name="MISC6"/>
631 <reg32 offset="0x0008c" name="DEBUG_BUS0"/>
632 <reg32 offset="0x00090" name="DEBUG_BUS1"/>
633 <reg32 offset="0x00094" name="DEBUG_BUS2"/>
634 <reg32 offset="0x00098" name="STATUS0">
635 <bitfield name="PLL_LOCK" pos="0" type="boolean"/>
636 </reg32>
637 <reg32 offset="0x0009c" name="STATUS1"/>
638 </domain>
639
640 <domain name="HDMI_8x74" width="32">
641 <!--
642 seems to be all mdp5+ have same?
643 -->
644 <reg32 offset="0x00000" name="ANA_CFG0"/>
645 <reg32 offset="0x00004" name="ANA_CFG1"/>
646 <reg32 offset="0x00010" name="PD_CTRL0"/>
647 <reg32 offset="0x00014" name="PD_CTRL1"/>
648 <reg32 offset="0x00034" name="BIST_CFG0"/>
649 <reg32 offset="0x0003c" name="BIST_PATN0"/>
650 <reg32 offset="0x00040" name="BIST_PATN1"/>
651 <reg32 offset="0x00044" name="BIST_PATN2"/>
652 <reg32 offset="0x00048" name="BIST_PATN3"/>
653 </domain>
654
655 <domain name="HDMI_28nm_PHY_PLL" width="32">
656 <reg32 offset="0x00000" name="REFCLK_CFG"/>
657 <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
658 <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
659 <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
660 <reg32 offset="0x00010" name="VREG_CFG"/>
661 <reg32 offset="0x00014" name="PWRGEN_CFG"/>
662 <reg32 offset="0x00018" name="DMUX_CFG"/>
663 <reg32 offset="0x0001C" name="AMUX_CFG"/>
664 <reg32 offset="0x00020" name="GLB_CFG">
665 <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
666 <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
667 <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
668 <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
669 </reg32>
670 <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
671 <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
672 <reg32 offset="0x0002C" name="LPFR_CFG"/>
673 <reg32 offset="0x00030" name="LPFC1_CFG"/>
674 <reg32 offset="0x00034" name="LPFC2_CFG"/>
675 <reg32 offset="0x00038" name="SDM_CFG0"/>
676 <reg32 offset="0x0003C" name="SDM_CFG1"/>
677 <reg32 offset="0x00040" name="SDM_CFG2"/>
678 <reg32 offset="0x00044" name="SDM_CFG3"/>
679 <reg32 offset="0x00048" name="SDM_CFG4"/>
680 <reg32 offset="0x0004C" name="SSC_CFG0"/>
681 <reg32 offset="0x00050" name="SSC_CFG1"/>
682 <reg32 offset="0x00054" name="SSC_CFG2"/>
683 <reg32 offset="0x00058" name="SSC_CFG3"/>
684 <reg32 offset="0x0005C" name="LKDET_CFG0"/>
685 <reg32 offset="0x00060" name="LKDET_CFG1"/>
686 <reg32 offset="0x00064" name="LKDET_CFG2"/>
687 <reg32 offset="0x00068" name="TEST_CFG">
688 <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
689 </reg32>
690 <reg32 offset="0x0006C" name="CAL_CFG0"/>
691 <reg32 offset="0x00070" name="CAL_CFG1"/>
692 <reg32 offset="0x00074" name="CAL_CFG2"/>
693 <reg32 offset="0x00078" name="CAL_CFG3"/>
694 <reg32 offset="0x0007C" name="CAL_CFG4"/>
695 <reg32 offset="0x00080" name="CAL_CFG5"/>
696 <reg32 offset="0x00084" name="CAL_CFG6"/>
697 <reg32 offset="0x00088" name="CAL_CFG7"/>
698 <reg32 offset="0x0008C" name="CAL_CFG8"/>
699 <reg32 offset="0x00090" name="CAL_CFG9"/>
700 <reg32 offset="0x00094" name="CAL_CFG10"/>
701 <reg32 offset="0x00098" name="CAL_CFG11"/>
702 <reg32 offset="0x0009C" name="EFUSE_CFG"/>
703 <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
704 </domain>
705
706 <domain name="HDMI_8996_PHY" width="32">
707 <reg32 offset="0x00000" name="CFG"/>
708 <reg32 offset="0x00004" name="PD_CTL"/>
709 <reg32 offset="0x00008" name="MODE"/>
710 <reg32 offset="0x0000C" name="MISR_CLEAR"/>
711 <reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
712 <reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
713 <reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
714 <reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
715 <reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
716 <reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
717 <reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
718 <reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
719 <reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
720 <reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
721 <reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
722 <reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
723 <reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
724 <reg32 offset="0x00044" name="TXCAL_CFG0"/>
725 <reg32 offset="0x00048" name="TXCAL_CFG1"/>
726 <reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
727 <reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
728 <reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
729 <reg32 offset="0x00058" name="CLOCK"/>
730 <reg32 offset="0x0005C" name="MISC1"/>
731 <reg32 offset="0x00060" name="MISC2"/>
732 <reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
733 <reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
734 <reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
735 <reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
736 <reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
737 <reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
738 <reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
739 <reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
740 <reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
741 <reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
742 <reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
743 <reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
744 <reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
745 <reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
746 <reg32 offset="0x0009C" name="STATUS"/>
747 <reg32 offset="0x000A0" name="MISC3_STATUS"/>
748 <reg32 offset="0x000A4" name="MISC4_STATUS"/>
749 <reg32 offset="0x000A8" name="DEBUG_BUS0"/>
750 <reg32 offset="0x000AC" name="DEBUG_BUS1"/>
751 <reg32 offset="0x000B0" name="DEBUG_BUS2"/>
752 <reg32 offset="0x000B4" name="DEBUG_BUS3"/>
753 <reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
754 <reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
755 <reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
756 <reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
757 </domain>
758
759 <domain name="HDMI_PHY_QSERDES_COM" width="32">
760 <reg32 offset="0x00000" name="ATB_SEL1"/>
761 <reg32 offset="0x00004" name="ATB_SEL2"/>
762 <reg32 offset="0x00008" name="FREQ_UPDATE"/>
763 <reg32 offset="0x0000C" name="BG_TIMER"/>
764 <reg32 offset="0x00010" name="SSC_EN_CENTER"/>
765 <reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
766 <reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
767 <reg32 offset="0x0001C" name="SSC_PER1"/>
768 <reg32 offset="0x00020" name="SSC_PER2"/>
769 <reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
770 <reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
771 <reg32 offset="0x0002C" name="POST_DIV"/>
772 <reg32 offset="0x00030" name="POST_DIV_MUX"/>
773 <reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
774 <reg32 offset="0x00038" name="CLK_ENABLE1"/>
775 <reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
776 <reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
777 <reg32 offset="0x00044" name="PLL_EN"/>
778 <reg32 offset="0x00048" name="PLL_IVCO"/>
779 <reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
780 <reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
781 <reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
782 <reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
783 <reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
784 <reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
785 <reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
786 <reg32 offset="0x00064" name="CMN_RSVD0"/>
787 <reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
788 <reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
789 <reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
790 <reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
791 <reg32 offset="0x00070" name="BG_TRIM"/>
792 <reg32 offset="0x00074" name="CLK_EP_DIV"/>
793 <reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
794 <reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
795 <reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
796 <reg32 offset="0x00080" name="CMN_RSVD1"/>
797 <reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
798 <reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
799 <reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
800 <reg32 offset="0x0008C" name="CMN_RSVD2"/>
801 <reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
802 <reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
803 <reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
804 <reg32 offset="0x00098" name="CMN_RSVD3"/>
805 <reg32 offset="0x0009C" name="PLL_CNTRL"/>
806 <reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
807 <reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
808 <reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
809 <reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
810 <reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
811 <reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
812 <reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
813 <reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
814 <reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
815 <reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
816 <reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
817 <reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
818 <reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
819 <reg32 offset="0x000D0" name="DEC_START_MODE0"/>
820 <reg32 offset="0x000D4" name="DEC_START_MODE1"/>
821 <reg32 offset="0x000D8" name="DEC_START_MODE2"/>
822 <reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
823 <reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
824 <reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
825 <reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
826 <reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
827 <reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
828 <reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
829 <reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
830 <reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
831 <reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
832 <reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
833 <reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
834 <reg32 offset="0x000FC" name="CMN_RSVD4"/>
835 <reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
836 <reg32 offset="0x00104" name="INTEGLOOP_EN"/>
837 <reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
838 <reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
839 <reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
840 <reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
841 <reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
842 <reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
843 <reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
844 <reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
845 <reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
846 <reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
847 <reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
848 <reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
849 <reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
850 <reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
851 <reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
852 <reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
853 <reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
854 <reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
855 <reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
856 <reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
857 <reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
858 <reg32 offset="0x0014C" name="SAR"/>
859 <reg32 offset="0x00150" name="SAR_CLK"/>
860 <reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
861 <reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
862 <reg32 offset="0x0015C" name="CMN_STATUS"/>
863 <reg32 offset="0x00160" name="RESET_SM_STATUS"/>
864 <reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
865 <reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
866 <reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
867 <reg32 offset="0x00170" name="BG_CTRL"/>
868 <reg32 offset="0x00174" name="CLK_SELECT"/>
869 <reg32 offset="0x00178" name="HSCLK_SEL"/>
870 <reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
871 <reg32 offset="0x00180" name="PLL_ANALOG"/>
872 <reg32 offset="0x00184" name="CORECLK_DIV"/>
873 <reg32 offset="0x00188" name="SW_RESET"/>
874 <reg32 offset="0x0018C" name="CORE_CLK_EN"/>
875 <reg32 offset="0x00190" name="C_READY_STATUS"/>
876 <reg32 offset="0x00194" name="CMN_CONFIG"/>
877 <reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
878 <reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
879 <reg32 offset="0x001A0" name="DEBUG_BUS0"/>
880 <reg32 offset="0x001A4" name="DEBUG_BUS1"/>
881 <reg32 offset="0x001A8" name="DEBUG_BUS2"/>
882 <reg32 offset="0x001AC" name="DEBUG_BUS3"/>
883 <reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
884 <reg32 offset="0x001B4" name="CMN_MISC1"/>
885 <reg32 offset="0x001B8" name="CMN_MISC2"/>
886 <reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
887 <reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
888 <reg32 offset="0x001C4" name="CMN_RSVD5"/>
889 </domain>
890
891
892 <domain name="HDMI_PHY_QSERDES_TX_LX" width="32">
893 <reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
894 <reg32 offset="0x00004" name="BIST_INVERT"/>
895 <reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
896 <reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
897 <reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
898 <reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
899 <reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
900 <reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
901 <reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
902 <reg32 offset="0x00024" name="HP_PD_ENABLES"/>
903 <reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
904 <reg32 offset="0x0002C" name="TX_DRV_LVL"/>
905 <reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
906 <reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
907 <reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
908 <reg32 offset="0x0003C" name="TX_BAND"/>
909 <reg32 offset="0x00040" name="SLEW_CNTL"/>
910 <reg32 offset="0x00044" name="INTERFACE_SELECT"/>
911 <reg32 offset="0x00048" name="LPB_EN"/>
912 <reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
913 <reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
914 <reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
915 <reg32 offset="0x00058" name="PERL_LENGTH1"/>
916 <reg32 offset="0x0005C" name="PERL_LENGTH2"/>
917 <reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
918 <reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
919 <reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
920 <reg32 offset="0x0006C" name="TX_POL_INV"/>
921 <reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
922 <reg32 offset="0x00074" name="BIST_PATTERN1"/>
923 <reg32 offset="0x00078" name="BIST_PATTERN2"/>
924 <reg32 offset="0x0007C" name="BIST_PATTERN3"/>
925 <reg32 offset="0x00080" name="BIST_PATTERN4"/>
926 <reg32 offset="0x00084" name="BIST_PATTERN5"/>
927 <reg32 offset="0x00088" name="BIST_PATTERN6"/>
928 <reg32 offset="0x0008C" name="BIST_PATTERN7"/>
929 <reg32 offset="0x00090" name="BIST_PATTERN8"/>
930 <reg32 offset="0x00094" name="LANE_MODE"/>
931 <reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
932 <reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
933 <reg32 offset="0x000A0" name="ATB_SEL1"/>
934 <reg32 offset="0x000A4" name="ATB_SEL2"/>
935 <reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
936 <reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
937 <reg32 offset="0x000B0" name="PRBS_SEED1"/>
938 <reg32 offset="0x000B4" name="PRBS_SEED2"/>
939 <reg32 offset="0x000B8" name="PRBS_SEED3"/>
940 <reg32 offset="0x000BC" name="PRBS_SEED4"/>
941 <reg32 offset="0x000C0" name="RESET_GEN"/>
942 <reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
943 <reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
944 <reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
945 <reg32 offset="0x000D0" name="PWM_CTRL"/>
946 <reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
947 <reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
948 <reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
949 <reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
950 <reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
951 <reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
952 <reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
953 <reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
954 <reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
955 <reg32 offset="0x000F8" name="VMODE_CTRL1"/>
956 <reg32 offset="0x000FC" name="VMODE_CTRL2"/>
957 <reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
958 <reg32 offset="0x00104" name="BIST_STATUS"/>
959 <reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
960 <reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
961 <reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
962 </domain>
963
964 </database>