2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "adreno_pm4.xml.h"
31 #include "adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WAIT_MEM_WRITES
)
163 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
164 if (flushes
& TU_CMD_FLAG_WAIT_FOR_IDLE
)
166 if (flushes
& TU_CMD_FLAG_WAIT_FOR_ME
)
167 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
170 /* "Normal" cache flushes, that don't require any special handling */
173 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
176 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
177 cmd_buffer
->state
.cache
.flush_bits
= 0;
180 /* Renderpass cache flushes */
183 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
186 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
187 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
190 /* Cache flushes for things that use the color/depth read/write path (i.e.
191 * blits and draws). This deals with changing CCU state as well as the usual
196 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
198 enum tu_cmd_ccu_state ccu_state
)
200 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
202 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
204 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
205 * the CCU may also contain data that we haven't flushed out yet, so we
206 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
207 * emit a WFI as it isn't pipelined.
209 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
210 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
212 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
213 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
214 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
215 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
216 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
221 TU_CMD_FLAG_WAIT_FOR_IDLE
;
222 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
223 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
224 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
225 TU_CMD_FLAG_WAIT_FOR_IDLE
);
228 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
229 cmd_buffer
->state
.cache
.flush_bits
= 0;
231 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
232 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
234 A6XX_RB_CCU_CNTL(.offset
=
235 ccu_state
== TU_CMD_CCU_GMEM
?
236 phys_dev
->ccu_offset_gmem
:
237 phys_dev
->ccu_offset_bypass
,
238 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
239 cmd_buffer
->state
.ccu_state
= ccu_state
;
244 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
245 const struct tu_subpass
*subpass
,
248 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
250 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
251 if (a
== VK_ATTACHMENT_UNUSED
) {
253 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
254 A6XX_RB_DEPTH_BUFFER_PITCH(0),
255 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
256 A6XX_RB_DEPTH_BUFFER_BASE(0),
257 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
260 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
263 A6XX_GRAS_LRZ_BUFFER_BASE(0),
264 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
265 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
267 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
272 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
273 const struct tu_render_pass_attachment
*attachment
=
274 &cmd
->state
.pass
->attachments
[a
];
275 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
277 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
278 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
279 tu_cs_image_ref(cs
, iview
, 0);
280 tu_cs_emit(cs
, attachment
->gmem_offset
);
283 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
285 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
286 tu_cs_image_flag_ref(cs
, iview
, 0);
289 A6XX_GRAS_LRZ_BUFFER_BASE(0),
290 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
291 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
293 if (attachment
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
||
294 attachment
->format
== VK_FORMAT_S8_UINT
) {
296 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
297 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
298 if (attachment
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
) {
299 tu_cs_image_stencil_ref(cs
, iview
, 0);
300 tu_cs_emit(cs
, attachment
->gmem_offset_stencil
);
302 tu_cs_image_ref(cs
, iview
, 0);
303 tu_cs_emit(cs
, attachment
->gmem_offset
);
307 A6XX_RB_STENCIL_INFO(0));
312 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
313 const struct tu_subpass
*subpass
,
316 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
318 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
319 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
320 if (a
== VK_ATTACHMENT_UNUSED
)
323 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
325 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
326 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
327 tu_cs_image_ref(cs
, iview
, 0);
328 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
331 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
333 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
334 tu_cs_image_flag_ref(cs
, iview
, 0);
338 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
340 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
342 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
346 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
348 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
349 bool msaa_disable
= samples
== MSAA_ONE
;
352 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
353 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
354 .msaa_disable
= msaa_disable
));
357 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
358 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
359 .msaa_disable
= msaa_disable
));
362 A6XX_RB_RAS_MSAA_CNTL(samples
),
363 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
364 .msaa_disable
= msaa_disable
));
367 A6XX_RB_MSAA_CNTL(samples
));
371 tu6_emit_bin_size(struct tu_cs
*cs
,
372 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
375 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
380 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
384 /* no flag for RB_BIN_CONTROL2... */
386 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
391 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
392 const struct tu_subpass
*subpass
,
396 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
398 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
400 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
402 uint32_t mrts_ubwc_enable
= 0;
403 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
404 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
405 if (a
== VK_ATTACHMENT_UNUSED
)
408 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
409 if (iview
->ubwc_enabled
)
410 mrts_ubwc_enable
|= 1 << i
;
413 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
415 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
416 if (a
!= VK_ATTACHMENT_UNUSED
) {
417 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
418 if (iview
->ubwc_enabled
)
419 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
422 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
423 * in order to set it correctly for the different subpasses. However,
424 * that means the packets we're emitting also happen during binning. So
425 * we need to guard the write on !BINNING at CP execution time.
427 tu_cs_reserve(cs
, 3 + 4);
428 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
429 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
430 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
431 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
434 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
435 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
436 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
437 tu_cs_emit(cs
, cntl
);
441 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
444 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
446 /* Avoid assertion fails with an empty render area at (0, 0) where the
447 * subtraction below wraps around. Empty render areas should be forced to
448 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
449 * an empty scissor here works, and the blob seems to force sysmem too as
450 * it sets something wrong (non-empty) for the scissor.
452 if (render_area
->extent
.width
== 0 ||
453 render_area
->extent
.height
== 0)
456 uint32_t x1
= render_area
->offset
.x
;
457 uint32_t y1
= render_area
->offset
.y
;
458 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
459 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
462 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
463 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
464 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
465 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
469 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
470 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
474 tu6_emit_window_scissor(struct tu_cs
*cs
,
481 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
482 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
485 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
486 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
490 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
493 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
496 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
499 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
502 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
506 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
508 uint32_t enable_mask
;
510 case TU_DRAW_STATE_PROGRAM
:
511 case TU_DRAW_STATE_VI
:
512 case TU_DRAW_STATE_FS_CONST
:
513 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
514 * when resources would actually be used in the binning shader.
515 * Presumably the overhead of prefetching the resources isn't
518 case TU_DRAW_STATE_DESC_SETS_LOAD
:
519 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
520 CP_SET_DRAW_STATE__0_SYSMEM
;
522 case TU_DRAW_STATE_PROGRAM_BINNING
:
523 case TU_DRAW_STATE_VI_BINNING
:
524 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
526 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
527 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
529 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
530 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
533 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
534 CP_SET_DRAW_STATE__0_SYSMEM
|
535 CP_SET_DRAW_STATE__0_BINNING
;
539 /* We need to reload the descriptors every time the descriptor sets
540 * change. However, the commands we send only depend on the pipeline
541 * because the whole point is to cache descriptors which are used by the
542 * pipeline. There's a problem here, in that the firmware has an
543 * "optimization" which skips executing groups that are set to the same
544 * value as the last draw. This means that if the descriptor sets change
545 * but not the pipeline, we'd try to re-execute the same buffer which
546 * the firmware would ignore and we wouldn't pre-load the new
547 * descriptors. Set the DIRTY bit to avoid this optimization
549 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
550 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
552 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
554 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
555 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
556 tu_cs_emit_qw(cs
, state
.iova
);
560 use_hw_binning(struct tu_cmd_buffer
*cmd
)
562 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
564 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
565 * with non-hw binning GMEM rendering. this is required because some of the
566 * XFB commands need to only be executed once
568 if (cmd
->state
.xfb_used
)
571 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
574 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
577 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
581 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
583 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
586 /* can't fit attachments into gmem */
587 if (!cmd
->state
.pass
->gmem_pixels
)
590 if (cmd
->state
.framebuffer
->layers
> 1)
593 /* Use sysmem for empty render areas */
594 if (cmd
->state
.render_area
.extent
.width
== 0 ||
595 cmd
->state
.render_area
.extent
.height
== 0)
605 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
607 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
609 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
611 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
612 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
614 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
615 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
617 const uint32_t x1
= fb
->tile0
.width
* tx
;
618 const uint32_t y1
= fb
->tile0
.height
* ty
;
619 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
620 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
621 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
622 tu6_emit_window_offset(cs
, x1
, y1
);
624 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
626 if (use_hw_binning(cmd
)) {
627 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
629 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
632 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
633 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
634 CP_SET_BIN_DATA5_0_VSC_N(slot
));
635 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
636 tu_cs_emit(cs
, pipe
* 4);
637 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
639 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
642 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
645 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
648 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
654 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
659 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
660 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
661 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
663 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
667 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
669 const struct tu_subpass
*subpass
)
671 if (subpass
->resolve_attachments
) {
672 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
675 * End-of-subpass multisample resolves are treated as color
676 * attachment writes for the purposes of synchronization. That is,
677 * they are considered to execute in the
678 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
679 * their writes are synchronized with
680 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
681 * rendering within a subpass and any resolve operations at the end
682 * of the subpass occurs automatically, without need for explicit
683 * dependencies or pipeline barriers. However, if the resolve
684 * attachment is also used in a different subpass, an explicit
685 * dependency is needed.
687 * We use the CP_BLIT path for sysmem resolves, which is really a
688 * transfer command, so we have to manually flush similar to the gmem
689 * resolve case. However, a flush afterwards isn't needed because of the
690 * last sentence and the fact that we're in sysmem mode.
692 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
693 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
695 /* Wait for the flushes to land before using the 2D engine */
698 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
699 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
700 if (a
== VK_ATTACHMENT_UNUSED
)
703 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
704 subpass
->color_attachments
[i
].attachment
);
710 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
712 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
713 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
715 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
716 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
717 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
718 CP_SET_DRAW_STATE__0_GROUP_ID(0));
719 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
720 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
722 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
725 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
726 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
728 tu6_emit_blit_scissor(cmd
, cs
, true);
730 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
731 if (pass
->attachments
[a
].gmem_offset
>= 0)
732 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
735 if (subpass
->resolve_attachments
) {
736 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
737 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
738 if (a
!= VK_ATTACHMENT_UNUSED
)
739 tu_store_gmem_attachment(cmd
, cs
, a
,
740 subpass
->color_attachments
[i
].attachment
);
746 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
748 struct tu_device
*dev
= cmd
->device
;
749 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
751 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
753 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
762 .gfx_shared_const
= true,
763 .cs_shared_const
= true,
764 .gfx_bindless
= 0x1f,
765 .cs_bindless
= 0x1f));
769 cmd
->state
.cache
.pending_flush_bits
&=
770 ~(TU_CMD_FLAG_WAIT_FOR_IDLE
| TU_CMD_FLAG_CACHE_INVALIDATE
);
773 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
774 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
775 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
790 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
791 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
792 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
795 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
798 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
799 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
813 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
814 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
816 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
817 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
819 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
821 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
822 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
824 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
826 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
851 /* we don't use this yet.. probably best to disable.. */
852 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
853 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
854 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
855 CP_SET_DRAW_STATE__0_GROUP_ID(0));
856 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
857 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
860 A6XX_SP_HS_CTRL_REG0(0));
863 A6XX_SP_GS_CTRL_REG0(0));
866 A6XX_GRAS_LRZ_CNTL(0));
869 A6XX_RB_LRZ_CNTL(0));
872 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
873 .bo_offset
= gb_offset(border_color
)));
875 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
876 .bo_offset
= gb_offset(border_color
)));
879 * use vsc pitches from the largest values used so far with this device
880 * if there hasn't been overflow, there will already be a scratch bo
881 * allocated for these sizes
883 * if overflow is detected, the stream size is increased by 2x
885 mtx_lock(&dev
->vsc_pitch_mtx
);
887 struct tu6_global
*global
= dev
->global_bo
.map
;
889 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
890 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
892 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
893 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
895 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
896 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
898 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
899 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
901 mtx_unlock(&dev
->vsc_pitch_mtx
);
903 struct tu_bo
*vsc_bo
;
904 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
905 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
907 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
910 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
912 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
914 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
915 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
917 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
919 tu_cs_sanity_check(cs
);
923 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
925 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
928 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
929 .height
= fb
->tile0
.height
));
932 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
933 .ny
= fb
->tile_count
.height
));
935 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
936 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
939 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
940 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
943 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
944 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
948 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
950 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
951 const uint32_t used_pipe_count
=
952 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
954 for (int i
= 0; i
< used_pipe_count
; i
++) {
955 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
956 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
957 CP_COND_WRITE5_0_WRITE_MEMORY
);
958 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
959 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
960 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
961 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
962 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
963 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
965 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
966 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
967 CP_COND_WRITE5_0_WRITE_MEMORY
);
968 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
969 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
970 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
971 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
972 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
973 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
976 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
980 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
982 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
983 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
985 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
987 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
988 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
990 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
993 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
999 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1001 update_vsc_pipe(cmd
, cs
);
1004 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1007 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1009 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1010 tu_cs_emit(cs
, UNK_2C
);
1013 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1016 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1018 /* emit IB to binning drawcmds: */
1019 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1021 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1022 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1023 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1024 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1025 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1026 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1028 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1029 tu_cs_emit(cs
, UNK_2D
);
1031 /* This flush is probably required because the VSC, which produces the
1032 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1033 * visibility stream (without caching) to do draw skipping. The
1034 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1035 * submitted are finished before reading the VSC regs (in
1036 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1039 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1043 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1045 emit_vsc_overflow_test(cmd
, cs
);
1047 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1048 tu_cs_emit(cs
, 0x0);
1050 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1051 tu_cs_emit(cs
, 0x0);
1054 static struct tu_draw_state
1055 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1056 const struct tu_subpass
*subpass
,
1059 /* note: we can probably emit input attachments just once for the whole
1060 * renderpass, this would avoid emitting both sysmem/gmem versions
1062 * emit two texture descriptors for each input, as a workaround for
1063 * d24s8/d32s8, which can be sampled as both float (depth) and integer (stencil)
1064 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1066 * TODO: a smarter workaround
1069 if (!subpass
->input_count
)
1070 return (struct tu_draw_state
) {};
1072 struct tu_cs_memory texture
;
1073 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1074 A6XX_TEX_CONST_DWORDS
, &texture
);
1075 assert(result
== VK_SUCCESS
);
1077 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1078 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1079 if (a
== VK_ATTACHMENT_UNUSED
)
1082 struct tu_image_view
*iview
=
1083 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1084 const struct tu_render_pass_attachment
*att
=
1085 &cmd
->state
.pass
->attachments
[a
];
1086 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1087 uint32_t gmem_offset
= att
->gmem_offset
;
1088 uint32_t cpp
= att
->cpp
;
1090 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1092 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1093 /* note this works because spec says fb and input attachments
1094 * must use identity swizzle
1096 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1097 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1098 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1099 if (cmd
->device
->physical_device
->limited_z24s8
) {
1100 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT
) |
1101 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W
) |
1102 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1103 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1104 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1106 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_Z24_UINT_S8_UINT
) |
1107 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1108 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1109 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1110 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1114 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
) {
1115 dst
[0] &= ~A6XX_TEX_CONST_0_FMT__MASK
;
1116 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_UINT
);
1117 dst
[2] &= ~(A6XX_TEX_CONST_2_PITCHALIGN__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
1118 dst
[2] |= A6XX_TEX_CONST_2_PITCH(iview
->stencil_PITCH
<< 6);
1120 dst
[4] = iview
->stencil_base_addr
;
1121 dst
[5] = (dst
[5] & 0xffff) | iview
->stencil_base_addr
>> 32;
1124 gmem_offset
= att
->gmem_offset_stencil
;
1130 /* patched for gmem */
1131 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1132 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1134 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1135 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* cpp
);
1137 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ gmem_offset
;
1138 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1139 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1144 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1146 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1147 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1148 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1149 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1150 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1151 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1152 tu_cs_emit_qw(&cs
, texture
.iova
);
1154 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1155 tu_cs_emit_qw(&cs
, texture
.iova
);
1157 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1159 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1165 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1167 struct tu_cs
*cs
= &cmd
->draw_cs
;
1169 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1170 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1171 tu_emit_input_attachments(cmd
, subpass
, true));
1172 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1173 tu_emit_input_attachments(cmd
, subpass
, false));
1177 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1178 const VkRenderPassBeginInfo
*info
)
1180 struct tu_cs
*cs
= &cmd
->draw_cs
;
1182 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1184 tu6_emit_blit_scissor(cmd
, cs
, true);
1186 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1187 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1189 tu6_emit_blit_scissor(cmd
, cs
, false);
1191 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1192 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1194 tu_cond_exec_end(cs
);
1196 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1198 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1199 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1201 tu_cond_exec_end(cs
);
1205 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1207 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1209 assert(fb
->width
> 0 && fb
->height
> 0);
1210 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1211 tu6_emit_window_offset(cs
, 0, 0);
1213 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1215 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1217 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1218 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1220 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1221 tu_cs_emit(cs
, 0x0);
1223 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1225 /* enable stream-out, with sysmem there is only one pass: */
1226 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1228 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1229 tu_cs_emit(cs
, 0x1);
1231 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1232 tu_cs_emit(cs
, 0x0);
1234 tu_cs_sanity_check(cs
);
1238 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1240 /* Do any resolves of the last subpass. These are handled in the
1241 * tile_store_ib in the gmem path.
1243 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1245 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1247 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1248 tu_cs_emit(cs
, 0x0);
1250 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1252 tu_cs_sanity_check(cs
);
1256 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1258 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1260 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1264 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1265 tu_cs_emit(cs
, 0x0);
1267 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1269 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1270 if (use_hw_binning(cmd
)) {
1271 /* enable stream-out during binning pass: */
1272 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1274 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1275 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1277 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1279 tu6_emit_binning_pass(cmd
, cs
);
1281 /* and disable stream-out for draw pass: */
1282 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1284 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1285 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1288 A6XX_VFD_MODE_CNTL(0));
1290 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1292 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1294 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1295 tu_cs_emit(cs
, 0x1);
1297 /* no binning pass, so enable stream-out for draw pass:: */
1298 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1300 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1303 tu_cs_sanity_check(cs
);
1307 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1309 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1311 if (use_hw_binning(cmd
)) {
1312 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1313 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1316 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1318 tu_cs_sanity_check(cs
);
1322 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1324 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1327 A6XX_GRAS_LRZ_CNTL(0));
1329 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1331 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1333 tu_cs_sanity_check(cs
);
1337 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1339 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1341 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1344 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1345 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1346 uint32_t tx1
= px
* fb
->pipe0
.width
;
1347 uint32_t ty1
= py
* fb
->pipe0
.height
;
1348 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1349 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1351 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1352 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1353 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1354 tu6_render_tile(cmd
, &cmd
->cs
);
1360 tu6_tile_render_end(cmd
, &cmd
->cs
);
1364 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1366 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1368 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1370 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1374 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1376 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1377 struct tu_cs sub_cs
;
1380 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1381 if (result
!= VK_SUCCESS
) {
1382 cmd
->record_result
= result
;
1386 /* emit to tile-store sub_cs */
1387 tu6_emit_tile_store(cmd
, &sub_cs
);
1389 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1393 tu_create_cmd_buffer(struct tu_device
*device
,
1394 struct tu_cmd_pool
*pool
,
1395 VkCommandBufferLevel level
,
1396 VkCommandBuffer
*pCommandBuffer
)
1398 struct tu_cmd_buffer
*cmd_buffer
;
1400 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1401 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1402 if (cmd_buffer
== NULL
)
1403 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1405 cmd_buffer
->device
= device
;
1406 cmd_buffer
->pool
= pool
;
1407 cmd_buffer
->level
= level
;
1410 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1411 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1414 /* Init the pool_link so we can safely call list_del when we destroy
1415 * the command buffer
1417 list_inithead(&cmd_buffer
->pool_link
);
1418 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1421 tu_bo_list_init(&cmd_buffer
->bo_list
);
1422 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1423 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1424 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1425 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1427 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1429 list_inithead(&cmd_buffer
->upload
.list
);
1435 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1437 list_del(&cmd_buffer
->pool_link
);
1439 tu_cs_finish(&cmd_buffer
->cs
);
1440 tu_cs_finish(&cmd_buffer
->draw_cs
);
1441 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1442 tu_cs_finish(&cmd_buffer
->sub_cs
);
1444 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1445 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1449 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1451 cmd_buffer
->record_result
= VK_SUCCESS
;
1453 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1454 tu_cs_reset(&cmd_buffer
->cs
);
1455 tu_cs_reset(&cmd_buffer
->draw_cs
);
1456 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1457 tu_cs_reset(&cmd_buffer
->sub_cs
);
1459 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1460 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1462 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1464 return cmd_buffer
->record_result
;
1468 tu_AllocateCommandBuffers(VkDevice _device
,
1469 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1470 VkCommandBuffer
*pCommandBuffers
)
1472 TU_FROM_HANDLE(tu_device
, device
, _device
);
1473 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1475 VkResult result
= VK_SUCCESS
;
1478 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1480 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1481 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1482 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1484 list_del(&cmd_buffer
->pool_link
);
1485 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1487 result
= tu_reset_cmd_buffer(cmd_buffer
);
1488 cmd_buffer
->level
= pAllocateInfo
->level
;
1490 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1492 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1493 &pCommandBuffers
[i
]);
1495 if (result
!= VK_SUCCESS
)
1499 if (result
!= VK_SUCCESS
) {
1500 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1503 /* From the Vulkan 1.0.66 spec:
1505 * "vkAllocateCommandBuffers can be used to create multiple
1506 * command buffers. If the creation of any of those command
1507 * buffers fails, the implementation must destroy all
1508 * successfully created command buffer objects from this
1509 * command, set all entries of the pCommandBuffers array to
1510 * NULL and return the error."
1512 memset(pCommandBuffers
, 0,
1513 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1520 tu_FreeCommandBuffers(VkDevice device
,
1521 VkCommandPool commandPool
,
1522 uint32_t commandBufferCount
,
1523 const VkCommandBuffer
*pCommandBuffers
)
1525 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1526 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1529 if (cmd_buffer
->pool
) {
1530 list_del(&cmd_buffer
->pool_link
);
1531 list_addtail(&cmd_buffer
->pool_link
,
1532 &cmd_buffer
->pool
->free_cmd_buffers
);
1534 tu_cmd_buffer_destroy(cmd_buffer
);
1540 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1541 VkCommandBufferResetFlags flags
)
1543 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1544 return tu_reset_cmd_buffer(cmd_buffer
);
1547 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1551 tu_cache_init(struct tu_cache_state
*cache
)
1553 cache
->flush_bits
= 0;
1554 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1558 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1559 const VkCommandBufferBeginInfo
*pBeginInfo
)
1561 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1562 VkResult result
= VK_SUCCESS
;
1564 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1565 /* If the command buffer has already been resetted with
1566 * vkResetCommandBuffer, no need to do it again.
1568 result
= tu_reset_cmd_buffer(cmd_buffer
);
1569 if (result
!= VK_SUCCESS
)
1573 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1574 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1576 tu_cache_init(&cmd_buffer
->state
.cache
);
1577 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1578 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1580 tu_cs_begin(&cmd_buffer
->cs
);
1581 tu_cs_begin(&cmd_buffer
->draw_cs
);
1582 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1584 /* setup initial configuration into command buffer */
1585 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1586 switch (cmd_buffer
->queue_family_index
) {
1587 case TU_QUEUE_GENERAL
:
1588 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1593 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1594 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1595 assert(pBeginInfo
->pInheritanceInfo
);
1596 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1597 cmd_buffer
->state
.subpass
=
1598 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1600 /* When executing in the middle of another command buffer, the CCU
1603 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1607 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1612 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1613 * rendering can skip over unused state), so we need to collect all the
1614 * bindings together into a single state emit at draw time.
1617 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1618 uint32_t firstBinding
,
1619 uint32_t bindingCount
,
1620 const VkBuffer
*pBuffers
,
1621 const VkDeviceSize
*pOffsets
)
1623 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1625 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1627 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1628 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1630 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1631 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1633 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1636 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1640 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1642 VkDeviceSize offset
,
1643 VkIndexType indexType
)
1645 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1646 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1650 uint32_t index_size
, index_shift
, restart_index
;
1652 switch (indexType
) {
1653 case VK_INDEX_TYPE_UINT16
:
1654 index_size
= INDEX4_SIZE_16_BIT
;
1656 restart_index
= 0xffff;
1658 case VK_INDEX_TYPE_UINT32
:
1659 index_size
= INDEX4_SIZE_32_BIT
;
1661 restart_index
= 0xffffffff;
1663 case VK_INDEX_TYPE_UINT8_EXT
:
1664 index_size
= INDEX4_SIZE_8_BIT
;
1666 restart_index
= 0xff;
1669 unreachable("invalid VkIndexType");
1672 /* initialize/update the restart index */
1673 if (cmd
->state
.index_size
!= index_size
)
1674 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1676 assert(buf
->size
>= offset
);
1678 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1679 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1680 cmd
->state
.index_size
= index_size
;
1682 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1686 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1687 VkPipelineBindPoint pipelineBindPoint
,
1688 VkPipelineLayout _layout
,
1690 uint32_t descriptorSetCount
,
1691 const VkDescriptorSet
*pDescriptorSets
,
1692 uint32_t dynamicOffsetCount
,
1693 const uint32_t *pDynamicOffsets
)
1695 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1696 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1697 unsigned dyn_idx
= 0;
1699 struct tu_descriptor_state
*descriptors_state
=
1700 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1702 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1703 unsigned idx
= i
+ firstSet
;
1704 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1706 descriptors_state
->sets
[idx
] = set
;
1708 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1709 /* update the contents of the dynamic descriptor set */
1710 unsigned src_idx
= j
;
1711 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1712 assert(dyn_idx
< dynamicOffsetCount
);
1715 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1717 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1718 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1720 /* Patch the storage/uniform descriptors right away. */
1721 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1722 /* Note: we can assume here that the addition won't roll over and
1723 * change the SIZE field.
1725 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1730 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1731 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1732 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1739 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1740 if (set
->buffers
[j
]) {
1741 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1742 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1746 if (set
->size
> 0) {
1747 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1748 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1751 assert(dyn_idx
== dynamicOffsetCount
);
1753 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1754 uint64_t addr
[MAX_SETS
+ 1] = {};
1755 struct tu_cs
*cs
, state_cs
;
1757 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1758 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1760 addr
[i
] = set
->va
| 3;
1763 if (layout
->dynamic_offset_count
) {
1764 /* allocate and fill out dynamic descriptor set */
1765 struct tu_cs_memory dynamic_desc_set
;
1766 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1767 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1768 assert(result
== VK_SUCCESS
);
1770 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1771 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1772 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1775 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1776 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1777 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1778 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1780 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1781 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1784 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1786 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1787 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1788 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1790 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1794 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1795 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1796 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1797 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1798 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1800 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1801 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1802 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1803 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1807 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1808 uint32_t firstBinding
,
1809 uint32_t bindingCount
,
1810 const VkBuffer
*pBuffers
,
1811 const VkDeviceSize
*pOffsets
,
1812 const VkDeviceSize
*pSizes
)
1814 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1815 struct tu_cs
*cs
= &cmd
->draw_cs
;
1817 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1818 * presumably there isn't any benefit using a draw state when the
1819 * condition is (SYSMEM | BINNING)
1821 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1822 CP_COND_REG_EXEC_0_SYSMEM
|
1823 CP_COND_REG_EXEC_0_BINNING
);
1825 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1826 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1827 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1828 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1829 uint32_t idx
= i
+ firstBinding
;
1831 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1834 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1835 uint32_t offset
= iova
& 0x1f;
1836 iova
&= ~(uint64_t) 0x1f;
1838 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1839 tu_cs_emit_qw(cs
, iova
);
1840 tu_cs_emit(cs
, size
+ offset
);
1842 cmd
->state
.streamout_offset
[idx
] = offset
;
1844 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1847 tu_cond_exec_end(cs
);
1851 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1852 uint32_t firstCounterBuffer
,
1853 uint32_t counterBufferCount
,
1854 const VkBuffer
*pCounterBuffers
,
1855 const VkDeviceSize
*pCounterBufferOffsets
)
1857 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1858 struct tu_cs
*cs
= &cmd
->draw_cs
;
1860 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1861 CP_COND_REG_EXEC_0_SYSMEM
|
1862 CP_COND_REG_EXEC_0_BINNING
);
1864 /* TODO: only update offset for active buffers */
1865 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1866 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1868 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1869 uint32_t idx
= firstCounterBuffer
+ i
;
1870 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1872 if (!pCounterBuffers
[i
])
1875 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1877 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1879 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1880 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1881 CP_MEM_TO_REG_0_UNK31
|
1882 CP_MEM_TO_REG_0_CNT(1));
1883 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1886 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1887 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1888 CP_REG_RMW_0_SRC1_ADD
);
1889 tu_cs_emit_qw(cs
, 0xffffffff);
1890 tu_cs_emit_qw(cs
, offset
);
1894 tu_cond_exec_end(cs
);
1897 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1898 uint32_t firstCounterBuffer
,
1899 uint32_t counterBufferCount
,
1900 const VkBuffer
*pCounterBuffers
,
1901 const VkDeviceSize
*pCounterBufferOffsets
)
1903 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1904 struct tu_cs
*cs
= &cmd
->draw_cs
;
1906 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1907 CP_COND_REG_EXEC_0_SYSMEM
|
1908 CP_COND_REG_EXEC_0_BINNING
);
1910 /* TODO: only flush buffers that need to be flushed */
1911 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1912 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1913 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1914 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1915 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1918 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1919 uint32_t idx
= firstCounterBuffer
+ i
;
1920 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1922 if (!pCounterBuffers
[i
])
1925 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1927 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1929 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1930 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1931 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1932 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1934 CP_MEM_TO_REG_0_UNK31
|
1935 CP_MEM_TO_REG_0_CNT(1));
1936 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1939 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1940 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1941 CP_REG_RMW_0_SRC1_ADD
);
1942 tu_cs_emit_qw(cs
, 0xffffffff);
1943 tu_cs_emit_qw(cs
, -offset
);
1946 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1947 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1948 CP_REG_TO_MEM_0_CNT(1));
1949 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1952 tu_cond_exec_end(cs
);
1954 cmd
->state
.xfb_used
= true;
1958 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1959 VkPipelineLayout layout
,
1960 VkShaderStageFlags stageFlags
,
1963 const void *pValues
)
1965 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1966 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1967 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1970 /* Flush everything which has been made available but we haven't actually
1974 tu_flush_all_pending(struct tu_cache_state
*cache
)
1976 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1977 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1981 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1983 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1985 /* We currently flush CCU at the end of the command buffer, like
1986 * what the blob does. There's implicit synchronization around every
1987 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1988 * know yet if this command buffer will be the last in the submit so we
1989 * have to defensively flush everything else.
1991 * TODO: We could definitely do better than this, since these flushes
1992 * aren't required by Vulkan, but we'd need kernel support to do that.
1993 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1994 * wouldn't have to do any flushes here, and when submitting multiple
1995 * command buffers there wouldn't be any unnecessary flushes in between.
1997 if (cmd_buffer
->state
.pass
) {
1998 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1999 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
2001 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
2002 cmd_buffer
->state
.cache
.flush_bits
|=
2003 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
2004 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
2005 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
2008 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
2009 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2011 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2012 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2013 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2016 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2017 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2018 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2021 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2022 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2023 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2026 tu_cs_end(&cmd_buffer
->cs
);
2027 tu_cs_end(&cmd_buffer
->draw_cs
);
2028 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2030 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2032 return cmd_buffer
->record_result
;
2036 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2040 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2041 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
2043 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2044 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2050 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2051 VkPipelineBindPoint pipelineBindPoint
,
2052 VkPipeline _pipeline
)
2054 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2055 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2057 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2058 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2059 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2062 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2063 cmd
->state
.compute_pipeline
= pipeline
;
2064 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2068 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2070 cmd
->state
.pipeline
= pipeline
;
2071 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2073 struct tu_cs
*cs
= &cmd
->draw_cs
;
2074 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2077 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2078 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2079 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2080 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2081 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2082 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2083 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2084 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2085 for_each_bit(i
, mask
)
2086 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2088 /* If the new pipeline requires more VBs than we had previously set up, we
2089 * need to re-emit them in SDS. If it requires the same set or fewer, we
2090 * can just re-use the old SDS.
2092 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2093 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2095 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2096 * so the dynamic state ib must be updated when pipeline changes
2098 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2099 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2101 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2102 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2104 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2109 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2110 uint32_t firstViewport
,
2111 uint32_t viewportCount
,
2112 const VkViewport
*pViewports
)
2114 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2115 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2117 assert(firstViewport
== 0 && viewportCount
== 1);
2119 tu6_emit_viewport(&cs
, pViewports
);
2123 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2124 uint32_t firstScissor
,
2125 uint32_t scissorCount
,
2126 const VkRect2D
*pScissors
)
2128 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2129 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2131 assert(firstScissor
== 0 && scissorCount
== 1);
2133 tu6_emit_scissor(&cs
, pScissors
);
2137 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2139 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2140 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2142 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2143 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2145 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2149 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2150 float depthBiasConstantFactor
,
2151 float depthBiasClamp
,
2152 float depthBiasSlopeFactor
)
2154 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2155 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2157 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2161 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2162 const float blendConstants
[4])
2164 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2165 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2167 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2168 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2172 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2173 float minDepthBounds
,
2174 float maxDepthBounds
)
2176 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2177 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2179 tu_cs_emit_regs(&cs
,
2180 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2181 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2185 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2187 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2188 *value
= (*value
& 0xff00) | (mask
& 0xff);
2189 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2190 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2194 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2195 VkStencilFaceFlags faceMask
,
2196 uint32_t compareMask
)
2198 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2199 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2201 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2203 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2207 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2208 VkStencilFaceFlags faceMask
,
2211 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2212 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2214 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2216 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2220 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2221 VkStencilFaceFlags faceMask
,
2224 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2225 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2227 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2229 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2233 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2234 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2236 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2237 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2239 assert(pSampleLocationsInfo
);
2241 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2245 tu_flush_for_access(struct tu_cache_state
*cache
,
2246 enum tu_cmd_access_mask src_mask
,
2247 enum tu_cmd_access_mask dst_mask
)
2249 enum tu_cmd_flush_bits flush_bits
= 0;
2251 if (src_mask
& TU_ACCESS_HOST_WRITE
) {
2252 /* Host writes are always visible to CP, so only invalidate GPU caches */
2253 cache
->pending_flush_bits
|= TU_CMD_FLAG_GPU_INVALIDATE
;
2256 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2257 /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
2260 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2263 if (src_mask
& TU_ACCESS_CP_WRITE
) {
2264 /* Flush the CP write queue. However a WFI shouldn't be necessary as
2265 * WAIT_MEM_WRITES should cover it.
2267 cache
->pending_flush_bits
|=
2268 TU_CMD_FLAG_WAIT_MEM_WRITES
|
2269 TU_CMD_FLAG_GPU_INVALIDATE
|
2270 TU_CMD_FLAG_WAIT_FOR_ME
;
2273 #define SRC_FLUSH(domain, flush, invalidate) \
2274 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2275 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2276 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2279 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2280 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2281 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2285 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2286 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2287 flush_bits |= TU_CMD_FLAG_##flush; \
2288 cache->pending_flush_bits |= \
2289 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2292 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2293 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2295 #undef SRC_INCOHERENT_FLUSH
2297 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2298 * drains the queue before signalling completion to the host.
2300 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
|
2301 TU_ACCESS_HOST_READ
| TU_ACCESS_HOST_WRITE
)) {
2302 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2305 #define DST_FLUSH(domain, flush, invalidate) \
2306 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2307 TU_ACCESS_##domain##_WRITE)) { \
2308 flush_bits |= cache->pending_flush_bits & \
2309 (TU_CMD_FLAG_##invalidate | \
2310 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2313 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2314 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2315 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2319 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2320 if (dst_mask & (TU_ACCESS_##domain##_INCOHERENT_READ | \
2321 TU_ACCESS_##domain##_INCOHERENT_WRITE)) { \
2322 flush_bits |= TU_CMD_FLAG_##invalidate | \
2323 (cache->pending_flush_bits & \
2324 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2327 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2328 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2330 #undef DST_INCOHERENT_FLUSH
2332 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2333 flush_bits
|= cache
->pending_flush_bits
&
2334 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_IDLE
);
2337 if (dst_mask
& TU_ACCESS_WFM_READ
) {
2338 flush_bits
|= cache
->pending_flush_bits
&
2339 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_ME
);
2342 cache
->flush_bits
|= flush_bits
;
2343 cache
->pending_flush_bits
&= ~flush_bits
;
2346 static enum tu_cmd_access_mask
2347 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2349 enum tu_cmd_access_mask mask
= 0;
2351 /* If the GPU writes a buffer that is then read by an indirect draw
2352 * command, we theoretically need to emit a WFI to wait for any cache
2353 * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
2354 * complete. Waiting for the WFI to complete is performed as part of the
2355 * draw by the firmware, so we just need to execute the WFI.
2357 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2358 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2361 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2362 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
|
2363 VK_ACCESS_MEMORY_READ_BIT
)) {
2364 mask
|= TU_ACCESS_WFI_READ
;
2368 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2369 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2370 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP */
2371 VK_ACCESS_MEMORY_READ_BIT
)) {
2372 mask
|= TU_ACCESS_SYSMEM_READ
;
2376 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
|
2377 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2378 mask
|= TU_ACCESS_CP_WRITE
;
2382 (VK_ACCESS_HOST_READ_BIT
|
2383 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2384 mask
|= TU_ACCESS_HOST_READ
;
2388 (VK_ACCESS_HOST_WRITE_BIT
|
2389 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2390 mask
|= TU_ACCESS_HOST_WRITE
;
2394 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2395 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2396 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2397 /* TODO: Is there a no-cache bit for textures so that we can ignore
2400 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2401 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2402 VK_ACCESS_MEMORY_READ_BIT
)) {
2403 mask
|= TU_ACCESS_UCHE_READ
;
2407 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2408 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2409 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2410 mask
|= TU_ACCESS_UCHE_WRITE
;
2413 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2414 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2415 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2416 * can ignore CCU and pretend that color attachments and transfers use
2421 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2422 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2423 VK_ACCESS_MEMORY_READ_BIT
)) {
2425 mask
|= TU_ACCESS_SYSMEM_READ
;
2427 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2431 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2432 VK_ACCESS_MEMORY_READ_BIT
)) {
2434 mask
|= TU_ACCESS_SYSMEM_READ
;
2436 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2440 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2441 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2443 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2445 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2450 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2451 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2453 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2455 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2459 /* When the dst access is a transfer read/write, it seems we sometimes need
2460 * to insert a WFI after any flushes, to guarantee that the flushes finish
2461 * before the 2D engine starts. However the opposite (i.e. a WFI after
2462 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2463 * the blob doesn't emit such a WFI.
2467 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2468 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2470 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2472 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2474 mask
|= TU_ACCESS_WFI_READ
;
2478 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2479 VK_ACCESS_MEMORY_READ_BIT
)) {
2480 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2488 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2489 uint32_t commandBufferCount
,
2490 const VkCommandBuffer
*pCmdBuffers
)
2492 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2495 assert(commandBufferCount
> 0);
2497 /* Emit any pending flushes. */
2498 if (cmd
->state
.pass
) {
2499 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2500 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2502 tu_flush_all_pending(&cmd
->state
.cache
);
2503 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2506 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2507 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2509 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2510 if (result
!= VK_SUCCESS
) {
2511 cmd
->record_result
= result
;
2515 if (secondary
->usage_flags
&
2516 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2517 assert(tu_cs_is_empty(&secondary
->cs
));
2519 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2520 if (result
!= VK_SUCCESS
) {
2521 cmd
->record_result
= result
;
2525 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2526 &secondary
->draw_epilogue_cs
);
2527 if (result
!= VK_SUCCESS
) {
2528 cmd
->record_result
= result
;
2532 if (secondary
->has_tess
)
2533 cmd
->has_tess
= true;
2535 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2536 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2538 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2539 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2540 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2543 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2546 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2548 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2550 /* After executing secondary command buffers, there may have been arbitrary
2551 * flushes executed, so when we encounter a pipeline barrier with a
2552 * srcMask, we have to assume that we need to invalidate. Therefore we need
2553 * to re-initialize the cache with all pending invalidate bits set.
2555 if (cmd
->state
.pass
) {
2556 tu_cache_init(&cmd
->state
.renderpass_cache
);
2558 tu_cache_init(&cmd
->state
.cache
);
2563 tu_CreateCommandPool(VkDevice _device
,
2564 const VkCommandPoolCreateInfo
*pCreateInfo
,
2565 const VkAllocationCallbacks
*pAllocator
,
2566 VkCommandPool
*pCmdPool
)
2568 TU_FROM_HANDLE(tu_device
, device
, _device
);
2569 struct tu_cmd_pool
*pool
;
2571 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2572 VK_OBJECT_TYPE_COMMAND_POOL
);
2574 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2577 pool
->alloc
= *pAllocator
;
2579 pool
->alloc
= device
->vk
.alloc
;
2581 list_inithead(&pool
->cmd_buffers
);
2582 list_inithead(&pool
->free_cmd_buffers
);
2584 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2586 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2592 tu_DestroyCommandPool(VkDevice _device
,
2593 VkCommandPool commandPool
,
2594 const VkAllocationCallbacks
*pAllocator
)
2596 TU_FROM_HANDLE(tu_device
, device
, _device
);
2597 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2602 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2603 &pool
->cmd_buffers
, pool_link
)
2605 tu_cmd_buffer_destroy(cmd_buffer
);
2608 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2609 &pool
->free_cmd_buffers
, pool_link
)
2611 tu_cmd_buffer_destroy(cmd_buffer
);
2614 vk_object_free(&device
->vk
, pAllocator
, pool
);
2618 tu_ResetCommandPool(VkDevice device
,
2619 VkCommandPool commandPool
,
2620 VkCommandPoolResetFlags flags
)
2622 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2625 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2628 result
= tu_reset_cmd_buffer(cmd_buffer
);
2629 if (result
!= VK_SUCCESS
)
2637 tu_TrimCommandPool(VkDevice device
,
2638 VkCommandPool commandPool
,
2639 VkCommandPoolTrimFlags flags
)
2641 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2646 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2647 &pool
->free_cmd_buffers
, pool_link
)
2649 tu_cmd_buffer_destroy(cmd_buffer
);
2654 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2655 const struct tu_subpass_barrier
*barrier
,
2658 /* Note: we don't know until the end of the subpass whether we'll use
2659 * sysmem, so assume sysmem here to be safe.
2661 struct tu_cache_state
*cache
=
2662 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2663 enum tu_cmd_access_mask src_flags
=
2664 vk2tu_access(barrier
->src_access_mask
, false);
2665 enum tu_cmd_access_mask dst_flags
=
2666 vk2tu_access(barrier
->dst_access_mask
, false);
2668 if (barrier
->incoherent_ccu_color
)
2669 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2670 if (barrier
->incoherent_ccu_depth
)
2671 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2673 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2677 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2678 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2679 VkSubpassContents contents
)
2681 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2682 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2683 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2685 cmd
->state
.pass
= pass
;
2686 cmd
->state
.subpass
= pass
->subpasses
;
2687 cmd
->state
.framebuffer
= fb
;
2688 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2690 tu_cmd_prepare_tile_store_ib(cmd
);
2692 /* Note: because this is external, any flushes will happen before draw_cs
2693 * gets called. However deferred flushes could have to happen later as part
2696 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2697 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2698 cmd
->state
.cache
.pending_flush_bits
;
2699 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2701 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2703 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2704 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2705 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2706 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2708 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2710 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2711 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2712 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2713 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2716 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2720 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2721 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2722 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2724 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2725 pSubpassBeginInfo
->contents
);
2729 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2731 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2732 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2733 struct tu_cs
*cs
= &cmd
->draw_cs
;
2735 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2737 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2739 if (subpass
->resolve_attachments
) {
2740 tu6_emit_blit_scissor(cmd
, cs
, true);
2742 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2743 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2744 if (a
== VK_ATTACHMENT_UNUSED
)
2747 tu_store_gmem_attachment(cmd
, cs
, a
,
2748 subpass
->color_attachments
[i
].attachment
);
2750 if (pass
->attachments
[a
].gmem_offset
< 0)
2754 * check if the resolved attachment is needed by later subpasses,
2755 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2757 tu_finishme("missing GMEM->GMEM resolve path\n");
2758 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2762 tu_cond_exec_end(cs
);
2764 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2766 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2768 tu_cond_exec_end(cs
);
2770 /* Handle dependencies for the next subpass */
2771 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2773 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2774 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2775 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2776 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2777 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2779 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2783 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2784 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2785 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2787 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2791 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2792 struct tu_descriptor_state
*descriptors_state
,
2793 gl_shader_stage type
,
2794 uint32_t *push_constants
)
2796 const struct tu_program_descriptor_linkage
*link
=
2797 &pipeline
->program
.link
[type
];
2798 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2800 if (link
->push_consts
.count
> 0) {
2801 unsigned num_units
= link
->push_consts
.count
;
2802 unsigned offset
= link
->push_consts
.lo
;
2803 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2804 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2805 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2806 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2807 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2808 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2811 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2812 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2815 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2816 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2817 uint32_t offset
= state
->range
[i
].start
;
2819 /* and even if the start of the const buffer is before
2820 * first_immediate, the end may not be:
2822 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2827 /* things should be aligned to vec4: */
2828 debug_assert((state
->range
[i
].offset
% 16) == 0);
2829 debug_assert((size
% 16) == 0);
2830 debug_assert((offset
% 16) == 0);
2832 /* Dig out the descriptor from the descriptor state and read the VA from
2835 assert(state
->range
[i
].ubo
.bindless
);
2836 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2837 descriptors_state
->dynamic_descriptors
:
2838 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2839 unsigned block
= state
->range
[i
].ubo
.block
;
2840 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2841 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2844 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2845 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2846 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2847 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2848 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2849 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2850 tu_cs_emit_qw(cs
, va
+ offset
);
2854 static struct tu_draw_state
2855 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2856 const struct tu_pipeline
*pipeline
,
2857 struct tu_descriptor_state
*descriptors_state
,
2858 gl_shader_stage type
)
2861 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2863 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2865 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2868 static struct tu_draw_state
2869 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2870 const struct tu_pipeline
*pipeline
)
2873 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2876 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2877 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2878 const VkDeviceSize offset
= buf
->bo_offset
+
2879 cmd
->state
.vb
.offsets
[binding
];
2881 tu_cs_emit_regs(&cs
,
2882 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2883 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2887 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2889 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2893 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2894 uint32_t draw_count
)
2896 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2897 * Still not sure what to do here, so just allocate a reasonably large
2898 * BO and hope for the best for now. */
2902 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2903 * which includes both the per-vertex outputs and per-patch outputs
2904 * build_primitive_map in ir3 calculates this stride
2906 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2907 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2908 return num_patches
* pipeline
->tess
.param_stride
;
2912 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2913 uint32_t draw_count
)
2915 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2916 * Still not sure what to do here, so just allocate a reasonably large
2917 * BO and hope for the best for now. */
2921 /* Each distinct patch gets its own tess factor output. */
2922 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2923 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2924 uint32_t factor_stride
;
2925 switch (pipeline
->tess
.patch_type
) {
2926 case IR3_TESS_ISOLINES
:
2929 case IR3_TESS_TRIANGLES
:
2932 case IR3_TESS_QUADS
:
2936 unreachable("bad tessmode");
2938 return factor_stride
* num_patches
;
2942 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2943 uint32_t draw_count
,
2944 const struct tu_pipeline
*pipeline
,
2945 struct tu_draw_state
*state
,
2946 uint64_t *factor_iova
)
2949 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 16, &cs
);
2950 if (result
!= VK_SUCCESS
)
2953 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2954 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2955 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2956 if (tess_bo_size
> 0) {
2957 struct tu_bo
*tess_bo
;
2958 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2959 if (result
!= VK_SUCCESS
)
2962 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2963 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2964 uint64_t tess_factor_iova
= tess_bo
->iova
;
2965 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2967 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2968 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2969 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2970 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2971 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2972 CP_LOAD_STATE6_0_NUM_UNIT(1));
2973 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2974 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2975 tu_cs_emit_qw(&cs
, tess_param_iova
);
2976 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2978 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2979 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2980 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2981 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2982 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2983 CP_LOAD_STATE6_0_NUM_UNIT(1));
2984 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2985 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2986 tu_cs_emit_qw(&cs
, tess_param_iova
);
2987 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2989 *factor_iova
= tess_factor_iova
;
2991 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2996 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2999 /* note: draw_count is 0 for indirect */
3000 uint32_t draw_count
)
3002 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3005 struct tu_descriptor_state
*descriptors_state
=
3006 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3008 tu_emit_cache_flush_renderpass(cmd
, cs
);
3012 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
3013 .primitive_restart
=
3014 pipeline
->ia
.primitive_restart
&& indexed
,
3015 .tess_upper_left_domain_origin
=
3016 pipeline
->tess
.upper_left_domain_origin
));
3018 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3019 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
3020 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
3021 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
3022 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
3023 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
3024 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
3025 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
3026 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
3027 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
3028 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3031 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3032 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3035 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
3036 struct tu_draw_state tess_consts
= {};
3038 uint64_t tess_factor_iova
= 0;
3040 cmd
->has_tess
= true;
3041 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
, &tess_factor_iova
);
3042 if (result
!= VK_SUCCESS
)
3045 /* this sequence matches what the blob does before every tess draw
3046 * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
3047 * before writing to it
3051 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
3052 tu_cs_emit_qw(cs
, tess_factor_iova
);
3054 tu_cs_emit_pkt7(cs
, CP_SET_SUBDRAW_SIZE
, 1);
3055 tu_cs_emit(cs
, draw_count
);
3058 /* for the first draw in a renderpass, re-emit all the draw states
3060 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3061 * used, then draw states must be re-emitted. note however this only happens
3062 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3064 * the two input attachment states are excluded because secondary command
3065 * buffer doesn't have a state ib to restore it, and not re-emitting them
3066 * is OK since CmdClearAttachments won't disable/overwrite them
3068 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3069 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3071 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
3072 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
3073 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3074 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
3075 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
3076 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
3077 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
3078 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
3079 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3080 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3081 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3082 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3083 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3084 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
3085 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3086 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3087 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3089 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3090 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3091 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3092 cmd
->state
.dynamic_state
[i
] :
3093 pipeline
->dynamic_state
[i
]));
3097 /* emit draw states that were just updated
3098 * note we eventually don't want to have to emit anything here
3100 uint32_t draw_state_count
=
3102 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3103 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
3104 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3107 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3109 /* We may need to re-emit tess consts if the current draw call is
3110 * sufficiently larger than the last draw call. */
3112 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3113 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3114 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3115 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3116 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3117 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3118 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3120 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3121 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3122 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3123 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3124 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3127 tu_cs_sanity_check(cs
);
3129 /* There are too many graphics dirty bits to list here, so just list the
3130 * bits to preserve instead. The only things not emitted here are
3131 * compute-related state.
3133 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3138 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3140 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3141 uint32_t initiator
=
3142 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3143 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3144 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3145 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3147 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3148 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3150 switch (pipeline
->tess
.patch_type
) {
3151 case IR3_TESS_TRIANGLES
:
3152 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3153 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3155 case IR3_TESS_ISOLINES
:
3156 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3157 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3160 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3162 case IR3_TESS_QUADS
:
3163 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3164 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3172 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3174 const struct tu_program_descriptor_linkage
*link
=
3175 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3176 const struct ir3_const_state
*const_state
= &link
->const_state
;
3178 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3181 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3182 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3183 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3184 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3186 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3187 assert(const_state
->offsets
.driver_param
!= 0);
3189 return const_state
->offsets
.driver_param
;
3192 static struct tu_draw_state
3193 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3194 uint32_t vertex_offset
,
3195 uint32_t first_instance
)
3197 uint32_t offset
= vs_params_offset(cmd
);
3200 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3201 if (result
!= VK_SUCCESS
) {
3202 cmd
->record_result
= result
;
3203 return (struct tu_draw_state
) {};
3206 /* TODO: don't make a new draw state when it doesn't change */
3208 tu_cs_emit_regs(&cs
,
3209 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3210 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3213 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3214 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3215 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3216 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3217 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3218 CP_LOAD_STATE6_0_NUM_UNIT(1));
3223 tu_cs_emit(&cs
, vertex_offset
);
3224 tu_cs_emit(&cs
, first_instance
);
3228 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3229 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3233 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3234 uint32_t vertexCount
,
3235 uint32_t instanceCount
,
3236 uint32_t firstVertex
,
3237 uint32_t firstInstance
)
3239 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3240 struct tu_cs
*cs
= &cmd
->draw_cs
;
3242 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3244 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3246 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3247 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3248 tu_cs_emit(cs
, instanceCount
);
3249 tu_cs_emit(cs
, vertexCount
);
3253 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3254 uint32_t indexCount
,
3255 uint32_t instanceCount
,
3256 uint32_t firstIndex
,
3257 int32_t vertexOffset
,
3258 uint32_t firstInstance
)
3260 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3261 struct tu_cs
*cs
= &cmd
->draw_cs
;
3263 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3265 tu6_draw_common(cmd
, cs
, true, indexCount
);
3267 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3268 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3269 tu_cs_emit(cs
, instanceCount
);
3270 tu_cs_emit(cs
, indexCount
);
3271 tu_cs_emit(cs
, firstIndex
);
3272 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3273 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3276 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
3277 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
3278 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
3279 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
3280 * before draw opcodes that don't need it.
3283 draw_wfm(struct tu_cmd_buffer
*cmd
)
3285 cmd
->state
.renderpass_cache
.flush_bits
|=
3286 cmd
->state
.renderpass_cache
.pending_flush_bits
& TU_CMD_FLAG_WAIT_FOR_ME
;
3287 cmd
->state
.renderpass_cache
.pending_flush_bits
&= ~TU_CMD_FLAG_WAIT_FOR_ME
;
3291 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3293 VkDeviceSize offset
,
3297 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3298 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3299 struct tu_cs
*cs
= &cmd
->draw_cs
;
3301 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3303 /* The latest known a630_sqe.fw fails to wait for WFI before reading the
3304 * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
3305 * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
3307 * TODO: There may be newer a630_sqe.fw released in the future which fixes
3308 * this, if so we should detect it and avoid this workaround.
3310 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3313 tu6_draw_common(cmd
, cs
, false, 0);
3315 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3316 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3317 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3318 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3319 tu_cs_emit(cs
, drawCount
);
3320 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3321 tu_cs_emit(cs
, stride
);
3323 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3327 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3329 VkDeviceSize offset
,
3333 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3334 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3335 struct tu_cs
*cs
= &cmd
->draw_cs
;
3337 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3339 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3342 tu6_draw_common(cmd
, cs
, true, 0);
3344 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3345 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3346 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3347 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3348 tu_cs_emit(cs
, drawCount
);
3349 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3350 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3351 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3352 tu_cs_emit(cs
, stride
);
3354 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3358 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer
,
3360 VkDeviceSize offset
,
3361 VkBuffer countBuffer
,
3362 VkDeviceSize countBufferOffset
,
3366 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3367 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3368 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3369 struct tu_cs
*cs
= &cmd
->draw_cs
;
3371 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3373 /* It turns out that the firmware we have for a650 only partially fixed the
3374 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
3375 * before reading indirect parameters. It waits for WFI's before reading
3376 * the draw parameters, but after reading the indirect count :(.
3380 tu6_draw_common(cmd
, cs
, false, 0);
3382 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 8);
3383 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3384 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT
) |
3385 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3386 tu_cs_emit(cs
, drawCount
);
3387 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3388 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3389 tu_cs_emit(cs
, stride
);
3391 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3392 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3396 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer
,
3398 VkDeviceSize offset
,
3399 VkBuffer countBuffer
,
3400 VkDeviceSize countBufferOffset
,
3404 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3405 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3406 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3407 struct tu_cs
*cs
= &cmd
->draw_cs
;
3409 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3413 tu6_draw_common(cmd
, cs
, true, 0);
3415 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 11);
3416 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3417 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED
) |
3418 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3419 tu_cs_emit(cs
, drawCount
);
3420 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3421 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3422 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3423 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3424 tu_cs_emit(cs
, stride
);
3426 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3427 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3430 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3431 uint32_t instanceCount
,
3432 uint32_t firstInstance
,
3433 VkBuffer _counterBuffer
,
3434 VkDeviceSize counterBufferOffset
,
3435 uint32_t counterOffset
,
3436 uint32_t vertexStride
)
3438 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3439 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3440 struct tu_cs
*cs
= &cmd
->draw_cs
;
3442 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
3443 * Plus, for the common case where the counter buffer is written by
3444 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
3445 * complete which means we need a WAIT_FOR_ME anyway.
3449 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3451 tu6_draw_common(cmd
, cs
, false, 0);
3453 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3454 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3455 tu_cs_emit(cs
, instanceCount
);
3456 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3457 tu_cs_emit(cs
, counterOffset
);
3458 tu_cs_emit(cs
, vertexStride
);
3460 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3463 struct tu_dispatch_info
3466 * Determine the layout of the grid (in block units) to be used.
3471 * A starting offset for the grid. If unaligned is set, the offset
3472 * must still be aligned.
3474 uint32_t offsets
[3];
3476 * Whether it's an unaligned compute dispatch.
3481 * Indirect compute parameters resource.
3483 struct tu_buffer
*indirect
;
3484 uint64_t indirect_offset
;
3488 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3489 const struct tu_dispatch_info
*info
)
3491 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3492 const struct tu_program_descriptor_linkage
*link
=
3493 &pipeline
->program
.link
[type
];
3494 const struct ir3_const_state
*const_state
= &link
->const_state
;
3495 uint32_t offset
= const_state
->offsets
.driver_param
;
3497 if (link
->constlen
<= offset
)
3500 if (!info
->indirect
) {
3501 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3502 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3503 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3504 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3505 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3506 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3507 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3510 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3511 (link
->constlen
- offset
) * 4);
3512 /* push constants */
3513 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3514 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3515 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3516 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3517 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3518 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3522 for (i
= 0; i
< num_consts
; i
++)
3523 tu_cs_emit(cs
, driver_params
[i
]);
3525 tu_finishme("Indirect driver params");
3530 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3531 const struct tu_dispatch_info
*info
)
3533 struct tu_cs
*cs
= &cmd
->cs
;
3534 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3535 struct tu_descriptor_state
*descriptors_state
=
3536 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3538 /* TODO: We could probably flush less if we add a compute_flush_bits
3541 tu_emit_cache_flush(cmd
, cs
);
3543 /* note: no reason to have this in a separate IB */
3544 tu_cs_emit_state_ib(cs
,
3545 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3547 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3549 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3550 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3552 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3554 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3555 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3557 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3558 const uint32_t *num_groups
= info
->blocks
;
3560 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3561 .localsizex
= local_size
[0] - 1,
3562 .localsizey
= local_size
[1] - 1,
3563 .localsizez
= local_size
[2] - 1),
3564 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3565 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3566 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3567 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3568 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3569 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3572 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3573 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3574 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3576 if (info
->indirect
) {
3577 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3579 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3580 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3582 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3583 tu_cs_emit(cs
, 0x00000000);
3584 tu_cs_emit_qw(cs
, iova
);
3586 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3587 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3588 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3590 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3591 tu_cs_emit(cs
, 0x00000000);
3592 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3593 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3594 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3601 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3609 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3610 struct tu_dispatch_info info
= {};
3616 info
.offsets
[0] = base_x
;
3617 info
.offsets
[1] = base_y
;
3618 info
.offsets
[2] = base_z
;
3619 tu_dispatch(cmd_buffer
, &info
);
3623 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3628 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3632 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3634 VkDeviceSize offset
)
3636 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3637 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3638 struct tu_dispatch_info info
= {};
3640 info
.indirect
= buffer
;
3641 info
.indirect_offset
= offset
;
3643 tu_dispatch(cmd_buffer
, &info
);
3647 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3649 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3651 tu_cs_end(&cmd_buffer
->draw_cs
);
3652 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3654 if (use_sysmem_rendering(cmd_buffer
))
3655 tu_cmd_render_sysmem(cmd_buffer
);
3657 tu_cmd_render_tiles(cmd_buffer
);
3659 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3661 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3662 tu_cs_begin(&cmd_buffer
->draw_cs
);
3663 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3664 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3666 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3667 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3668 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3670 cmd_buffer
->state
.pass
= NULL
;
3671 cmd_buffer
->state
.subpass
= NULL
;
3672 cmd_buffer
->state
.framebuffer
= NULL
;
3676 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3677 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3679 tu_CmdEndRenderPass(commandBuffer
);
3682 struct tu_barrier_info
3684 uint32_t eventCount
;
3685 const VkEvent
*pEvents
;
3686 VkPipelineStageFlags srcStageMask
;
3690 tu_barrier(struct tu_cmd_buffer
*cmd
,
3691 uint32_t memoryBarrierCount
,
3692 const VkMemoryBarrier
*pMemoryBarriers
,
3693 uint32_t bufferMemoryBarrierCount
,
3694 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3695 uint32_t imageMemoryBarrierCount
,
3696 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3697 const struct tu_barrier_info
*info
)
3699 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3700 VkAccessFlags srcAccessMask
= 0;
3701 VkAccessFlags dstAccessMask
= 0;
3703 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3704 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3705 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3708 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3709 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3710 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3713 enum tu_cmd_access_mask src_flags
= 0;
3714 enum tu_cmd_access_mask dst_flags
= 0;
3716 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3717 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3718 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3719 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3720 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3721 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3722 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3723 /* The underlying memory for this image may have been used earlier
3724 * within the same queue submission for a different image, which
3725 * means that there may be old, stale cache entries which are in the
3726 * "wrong" location, which could cause problems later after writing
3727 * to the image. We don't want these entries being flushed later and
3728 * overwriting the actual image, so we need to flush the CCU.
3730 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3732 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3733 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3736 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3737 * so we have to use the sysmem flushes.
3739 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3741 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3742 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3744 struct tu_cache_state
*cache
=
3745 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3746 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3748 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3749 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3751 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3753 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3754 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3755 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3756 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3757 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3758 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3759 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3764 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3765 VkPipelineStageFlags srcStageMask
,
3766 VkPipelineStageFlags dstStageMask
,
3767 VkDependencyFlags dependencyFlags
,
3768 uint32_t memoryBarrierCount
,
3769 const VkMemoryBarrier
*pMemoryBarriers
,
3770 uint32_t bufferMemoryBarrierCount
,
3771 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3772 uint32_t imageMemoryBarrierCount
,
3773 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3775 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3776 struct tu_barrier_info info
;
3778 info
.eventCount
= 0;
3779 info
.pEvents
= NULL
;
3780 info
.srcStageMask
= srcStageMask
;
3782 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3783 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3784 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3788 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3789 VkPipelineStageFlags stageMask
, unsigned value
)
3791 struct tu_cs
*cs
= &cmd
->cs
;
3793 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3794 assert(!cmd
->state
.pass
);
3796 tu_emit_cache_flush(cmd
, cs
);
3798 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3800 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3801 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3803 VkPipelineStageFlags top_of_pipe_flags
=
3804 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3805 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3807 if (!(stageMask
& ~top_of_pipe_flags
)) {
3808 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3809 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3810 tu_cs_emit(cs
, value
);
3812 /* Use a RB_DONE_TS event to wait for everything to complete. */
3813 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3814 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3815 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3816 tu_cs_emit(cs
, value
);
3821 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3823 VkPipelineStageFlags stageMask
)
3825 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3826 TU_FROM_HANDLE(tu_event
, event
, _event
);
3828 write_event(cmd
, event
, stageMask
, 1);
3832 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3834 VkPipelineStageFlags stageMask
)
3836 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3837 TU_FROM_HANDLE(tu_event
, event
, _event
);
3839 write_event(cmd
, event
, stageMask
, 0);
3843 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3844 uint32_t eventCount
,
3845 const VkEvent
*pEvents
,
3846 VkPipelineStageFlags srcStageMask
,
3847 VkPipelineStageFlags dstStageMask
,
3848 uint32_t memoryBarrierCount
,
3849 const VkMemoryBarrier
*pMemoryBarriers
,
3850 uint32_t bufferMemoryBarrierCount
,
3851 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3852 uint32_t imageMemoryBarrierCount
,
3853 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3855 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3856 struct tu_barrier_info info
;
3858 info
.eventCount
= eventCount
;
3859 info
.pEvents
= pEvents
;
3860 info
.srcStageMask
= 0;
3862 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3863 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3864 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3868 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)