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radv: do not use VK_TRUE/VK_FALSE
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 assert(bo_info->handle != 0);
66
67 for (uint32_t i = 0; i < list->count; ++i) {
68 if (list->bo_infos[i].handle == bo_info->handle) {
69 assert(list->bo_infos[i].presumed == bo_info->presumed);
70 list->bo_infos[i].flags |= bo_info->flags;
71 return i;
72 }
73 }
74
75 /* grow list->bo_infos if needed */
76 if (list->count == list->capacity) {
77 uint32_t new_capacity = MAX2(2 * list->count, 16);
78 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
79 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
80 if (!new_bo_infos)
81 return TU_BO_LIST_FAILED;
82 list->bo_infos = new_bo_infos;
83 list->capacity = new_capacity;
84 }
85
86 list->bo_infos[list->count] = *bo_info;
87 return list->count++;
88 }
89
90 uint32_t
91 tu_bo_list_add(struct tu_bo_list *list,
92 const struct tu_bo *bo,
93 uint32_t flags)
94 {
95 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
96 .flags = flags,
97 .handle = bo->gem_handle,
98 .presumed = bo->iova,
99 });
100 }
101
102 VkResult
103 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
104 {
105 for (uint32_t i = 0; i < other->count; i++) {
106 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
107 return VK_ERROR_OUT_OF_HOST_MEMORY;
108 }
109
110 return VK_SUCCESS;
111 }
112
113 static VkResult
114 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
115 const struct tu_device *dev)
116 {
117 const uint32_t gmem_size = dev->physical_device->gmem_size;
118 uint32_t offset = 0;
119
120 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
121 /* 16KB-aligned */
122 offset = align(offset, 0x4000);
123
124 tiling->gmem_offsets[i] = offset;
125 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
126 tiling->buffer_cpp[i];
127 }
128
129 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
130 }
131
132 static void
133 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
134 const struct tu_device *dev)
135 {
136 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
137 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
138 const uint32_t max_tile_width = 1024; /* A6xx */
139
140 tiling->tile0.offset = (VkOffset2D) {
141 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
142 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
143 };
144
145 const uint32_t ra_width =
146 tiling->render_area.extent.width +
147 (tiling->render_area.offset.x - tiling->tile0.offset.x);
148 const uint32_t ra_height =
149 tiling->render_area.extent.height +
150 (tiling->render_area.offset.y - tiling->tile0.offset.y);
151
152 /* start from 1 tile */
153 tiling->tile_count = (VkExtent2D) {
154 .width = 1,
155 .height = 1,
156 };
157 tiling->tile0.extent = (VkExtent2D) {
158 .width = align(ra_width, tile_align_w),
159 .height = align(ra_height, tile_align_h),
160 };
161
162 /* do not exceed max tile width */
163 while (tiling->tile0.extent.width > max_tile_width) {
164 tiling->tile_count.width++;
165 tiling->tile0.extent.width =
166 align(ra_width / tiling->tile_count.width, tile_align_w);
167 }
168
169 /* do not exceed gmem size */
170 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
171 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
172 tiling->tile_count.width++;
173 tiling->tile0.extent.width =
174 align(ra_width / tiling->tile_count.width, tile_align_w);
175 } else {
176 tiling->tile_count.height++;
177 tiling->tile0.extent.height =
178 align(ra_height / tiling->tile_count.height, tile_align_h);
179 }
180 }
181 }
182
183 static void
184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
185 const struct tu_device *dev)
186 {
187 const uint32_t max_pipe_count = 32; /* A6xx */
188
189 /* start from 1 tile per pipe */
190 tiling->pipe0 = (VkExtent2D) {
191 .width = 1,
192 .height = 1,
193 };
194 tiling->pipe_count = tiling->tile_count;
195
196 /* do not exceed max pipe count vertically */
197 while (tiling->pipe_count.height > max_pipe_count) {
198 tiling->pipe0.height += 2;
199 tiling->pipe_count.height =
200 (tiling->tile_count.height + tiling->pipe0.height - 1) /
201 tiling->pipe0.height;
202 }
203
204 /* do not exceed max pipe count */
205 while (tiling->pipe_count.width * tiling->pipe_count.height >
206 max_pipe_count) {
207 tiling->pipe0.width += 1;
208 tiling->pipe_count.width =
209 (tiling->tile_count.width + tiling->pipe0.width - 1) /
210 tiling->pipe0.width;
211 }
212 }
213
214 static void
215 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
216 const struct tu_device *dev)
217 {
218 const uint32_t max_pipe_count = 32; /* A6xx */
219 const uint32_t used_pipe_count =
220 tiling->pipe_count.width * tiling->pipe_count.height;
221 const VkExtent2D last_pipe = {
222 .width = tiling->tile_count.width % tiling->pipe0.width,
223 .height = tiling->tile_count.height % tiling->pipe0.height,
224 };
225
226 assert(used_pipe_count <= max_pipe_count);
227 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
228
229 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
230 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
231 const uint32_t pipe_x = tiling->pipe0.width * x;
232 const uint32_t pipe_y = tiling->pipe0.height * y;
233 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
234 ? last_pipe.width
235 : tiling->pipe0.width;
236 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
237 ? last_pipe.height
238 : tiling->pipe0.height;
239 const uint32_t n = tiling->pipe_count.width * y + x;
240
241 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
242 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
243 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
244 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
245 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
246 }
247 }
248
249 memset(tiling->pipe_config + used_pipe_count, 0,
250 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
251 }
252
253 static void
254 tu_tiling_config_update(struct tu_tiling_config *tiling,
255 const struct tu_device *dev,
256 const uint32_t *buffer_cpp,
257 uint32_t buffer_count,
258 const VkRect2D *render_area)
259 {
260 /* see if there is any real change */
261 const bool ra_changed =
262 render_area &&
263 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
264 const bool buf_changed = tiling->buffer_count != buffer_count ||
265 memcmp(tiling->buffer_cpp, buffer_cpp,
266 sizeof(*buffer_cpp) * buffer_count);
267 if (!ra_changed && !buf_changed)
268 return;
269
270 if (ra_changed)
271 tiling->render_area = *render_area;
272
273 if (buf_changed) {
274 memcpy(tiling->buffer_cpp, buffer_cpp,
275 sizeof(*buffer_cpp) * buffer_count);
276 tiling->buffer_count = buffer_count;
277 }
278
279 tu_tiling_config_update_tile_layout(tiling, dev);
280 tu_tiling_config_update_pipe_layout(tiling, dev);
281 tu_tiling_config_update_pipes(tiling, dev);
282 }
283
284 static void
285 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
286 const struct tu_device *dev,
287 uint32_t tx,
288 uint32_t ty,
289 struct tu_tile *tile)
290 {
291 /* find the pipe and the slot for tile (tx, ty) */
292 const uint32_t px = tx / tiling->pipe0.width;
293 const uint32_t py = ty / tiling->pipe0.height;
294 const uint32_t sx = tx - tiling->pipe0.width * px;
295 const uint32_t sy = ty - tiling->pipe0.height * py;
296
297 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
298 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
299 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
300
301 /* convert to 1D indices */
302 tile->pipe = tiling->pipe_count.width * py + px;
303 tile->slot = tiling->pipe0.width * sy + sx;
304
305 /* get the blit area for the tile */
306 tile->begin = (VkOffset2D) {
307 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
308 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
309 };
310 tile->end.x =
311 (tx == tiling->tile_count.width - 1)
312 ? tiling->render_area.offset.x + tiling->render_area.extent.width
313 : tile->begin.x + tiling->tile0.extent.width;
314 tile->end.y =
315 (ty == tiling->tile_count.height - 1)
316 ? tiling->render_area.offset.y + tiling->render_area.extent.height
317 : tile->begin.y + tiling->tile0.extent.height;
318 }
319
320 enum a3xx_msaa_samples
321 tu_msaa_samples(uint32_t samples)
322 {
323 switch (samples) {
324 case 1:
325 return MSAA_ONE;
326 case 2:
327 return MSAA_TWO;
328 case 4:
329 return MSAA_FOUR;
330 case 8:
331 return MSAA_EIGHT;
332 default:
333 assert(!"invalid sample count");
334 return MSAA_ONE;
335 }
336 }
337
338 static enum a4xx_index_size
339 tu6_index_size(VkIndexType type)
340 {
341 switch (type) {
342 case VK_INDEX_TYPE_UINT16:
343 return INDEX4_SIZE_16_BIT;
344 case VK_INDEX_TYPE_UINT32:
345 return INDEX4_SIZE_32_BIT;
346 default:
347 unreachable("invalid VkIndexType");
348 return INDEX4_SIZE_8_BIT;
349 }
350 }
351
352 static void
353 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
354 {
355 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
356 }
357
358 void
359 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
360 struct tu_cs *cs,
361 enum vgt_event_type event,
362 bool need_seqno)
363 {
364 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
365 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
366 if (need_seqno) {
367 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
368 tu_cs_emit(cs, ++cmd->scratch_seqno);
369 }
370 }
371
372 static void
373 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
374 {
375 tu6_emit_event_write(cmd, cs, 0x31, false);
376 }
377
378 static void
379 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
380 {
381 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
382 }
383
384 static void
385 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
386 {
387 if (cmd->wait_for_idle) {
388 tu_cs_emit_wfi(cs);
389 cmd->wait_for_idle = false;
390 }
391 }
392
393 static void
394 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
395 {
396 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
397 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
398 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
399 if (iview->image->ubwc_size) {
400 tu_cs_emit_qw(cs, va);
401 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
402 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
403 } else {
404 tu_cs_emit_qw(cs, 0);
405 tu_cs_emit(cs, 0);
406 }
407 }
408
409 static void
410 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
411 {
412 const struct tu_framebuffer *fb = cmd->state.framebuffer;
413 const struct tu_subpass *subpass = cmd->state.subpass;
414 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
415
416 const uint32_t a = subpass->depth_stencil_attachment.attachment;
417 if (a == VK_ATTACHMENT_UNUSED) {
418 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
419 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
422 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
423 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
424 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
425
426 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
427 tu_cs_emit(cs,
428 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
429
430 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
431 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
432 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
433 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
434 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
435 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
436
437 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
438 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
439
440 return;
441 }
442
443 const struct tu_image_view *iview = fb->attachments[a].attachment;
444 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
445
446 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
447 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
448 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
449 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layer_size));
450 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
451 tu_cs_emit(cs, tiling->gmem_offsets[subpass->color_count]);
452
453 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
454 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
455
456 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
457 tu6_emit_flag_buffer(cs, iview);
458
459 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
460 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
461 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
462 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
463 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
464 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
465
466 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
467 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
468
469 /* enable zs? */
470 }
471
472 static void
473 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
474 {
475 const struct tu_framebuffer *fb = cmd->state.framebuffer;
476 const struct tu_subpass *subpass = cmd->state.subpass;
477 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
478 unsigned char mrt_comp[MAX_RTS] = { 0 };
479 unsigned srgb_cntl = 0;
480
481 for (uint32_t i = 0; i < subpass->color_count; ++i) {
482 uint32_t a = subpass->color_attachments[i].attachment;
483 if (a == VK_ATTACHMENT_UNUSED)
484 continue;
485
486 const struct tu_image_view *iview = fb->attachments[a].attachment;
487 const enum a6xx_tile_mode tile_mode =
488 tu6_get_image_tile_mode(iview->image, iview->base_mip);
489
490 mrt_comp[i] = 0xf;
491
492 if (vk_format_is_srgb(iview->vk_format))
493 srgb_cntl |= (1 << i);
494
495 const struct tu_native_format *format =
496 tu6_get_native_format(iview->vk_format);
497 assert(format && format->rb >= 0);
498
499 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
500 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
501 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
502 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
503 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
504 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layer_size));
505 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
506 tu_cs_emit(
507 cs, tiling->gmem_offsets[i]); /* RB_MRT[i].BASE_GMEM */
508
509 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
510 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
511 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
512 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
513
514 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
515 tu6_emit_flag_buffer(cs, iview);
516 }
517
518 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
519 tu_cs_emit(cs, srgb_cntl);
520
521 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
522 tu_cs_emit(cs, srgb_cntl);
523
524 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
525 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
526 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
527 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
528 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
529 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
530 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
531 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
532 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
533
534 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
535 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
536 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
537 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
538 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
539 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
540 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
541 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
542 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
543 }
544
545 static void
546 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
547 {
548 const struct tu_subpass *subpass = cmd->state.subpass;
549 const enum a3xx_msaa_samples samples =
550 tu_msaa_samples(subpass->max_sample_count);
551
552 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
553 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
554 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
555 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
556
557 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
558 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
559 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
560 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
561
562 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
563 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
564 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
565 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
566
567 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
568 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
569 }
570
571 static void
572 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
573 {
574 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
575 const uint32_t bin_w = tiling->tile0.extent.width;
576 const uint32_t bin_h = tiling->tile0.extent.height;
577
578 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
579 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
580 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
581
582 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
583 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
584 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
585
586 /* no flag for RB_BIN_CONTROL2... */
587 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
588 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
589 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
590 }
591
592 static void
593 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
594 struct tu_cs *cs,
595 bool binning)
596 {
597 uint32_t cntl = 0;
598 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
599 if (binning)
600 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
601
602 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
603 tu_cs_emit(cs, 0x2);
604 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
605 tu_cs_emit(cs, cntl);
606 }
607
608 static void
609 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
610 {
611 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
612 const uint32_t x1 = render_area->offset.x;
613 const uint32_t y1 = render_area->offset.y;
614 const uint32_t x2 = x1 + render_area->extent.width - 1;
615 const uint32_t y2 = y1 + render_area->extent.height - 1;
616
617 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
618 tu_cs_emit(cs,
619 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
620 tu_cs_emit(cs,
621 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
622 }
623
624 static void
625 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
626 struct tu_cs *cs,
627 const struct tu_image_view *iview,
628 uint32_t gmem_offset,
629 uint32_t blit_info)
630 {
631 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
632 tu_cs_emit(cs, blit_info);
633
634 const struct tu_native_format *format =
635 tu6_get_native_format(iview->vk_format);
636 assert(format && format->rb >= 0);
637
638 enum a6xx_tile_mode tile_mode =
639 tu6_get_image_tile_mode(iview->image, iview->base_mip);
640 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
641 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
642 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
643 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
644 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
645 COND(iview->image->ubwc_size, A6XX_RB_BLIT_DST_INFO_FLAGS));
646 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
647 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
648 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layer_size));
649
650 if (iview->image->ubwc_size) {
651 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
652 tu6_emit_flag_buffer(cs, iview);
653 }
654
655 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
656 tu_cs_emit(cs, gmem_offset);
657 }
658
659 static void
660 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
661 struct tu_cs *cs,
662 const struct tu_image_view *iview,
663 uint32_t gmem_offset,
664 const VkClearValue *clear_value)
665 {
666 const struct tu_native_format *format =
667 tu6_get_native_format(iview->vk_format);
668 assert(format && format->rb >= 0);
669
670 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
671 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
672
673 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
674 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
675
676 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
677 tu_cs_emit(cs, gmem_offset);
678
679 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
680 tu_cs_emit(cs, 0);
681
682 uint32_t clear_vals[4] = { 0 };
683 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
684
685 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
686 tu_cs_emit(cs, clear_vals[0]);
687 tu_cs_emit(cs, clear_vals[1]);
688 tu_cs_emit(cs, clear_vals[2]);
689 tu_cs_emit(cs, clear_vals[3]);
690 }
691
692 static void
693 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
694 {
695 tu6_emit_marker(cmd, cs);
696 tu6_emit_event_write(cmd, cs, BLIT, false);
697 tu6_emit_marker(cmd, cs);
698 }
699
700 static void
701 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
702 struct tu_cs *cs,
703 uint32_t x1,
704 uint32_t y1,
705 uint32_t x2,
706 uint32_t y2)
707 {
708 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
709 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
710 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
711 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
712 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
713
714 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
715 tu_cs_emit(
716 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
717 tu_cs_emit(
718 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
719 }
720
721 static void
722 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
723 struct tu_cs *cs,
724 uint32_t x1,
725 uint32_t y1)
726 {
727 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
728 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
729
730 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
731 tu_cs_emit(cs,
732 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
733
734 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
735 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
736
737 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
738 tu_cs_emit(
739 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
740 }
741
742 static void
743 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
744 struct tu_cs *cs,
745 const struct tu_tile *tile)
746 {
747 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
748 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
749
750 tu6_emit_marker(cmd, cs);
751 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
752 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
753 tu6_emit_marker(cmd, cs);
754
755 const uint32_t x1 = tile->begin.x;
756 const uint32_t y1 = tile->begin.y;
757 const uint32_t x2 = tile->end.x - 1;
758 const uint32_t y2 = tile->end.y - 1;
759 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
760 tu6_emit_window_offset(cmd, cs, x1, y1);
761
762 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
763 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
764
765 if (false) {
766 /* hw binning? */
767 } else {
768 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
769 tu_cs_emit(cs, 0x1);
770
771 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
772 tu_cs_emit(cs, 0x0);
773 }
774 }
775
776 static void
777 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
778 struct tu_cs *cs,
779 uint32_t a,
780 uint32_t gmem_index)
781 {
782 const struct tu_framebuffer *fb = cmd->state.framebuffer;
783 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
784 const struct tu_attachment_state *attachments = cmd->state.attachments;
785
786 const struct tu_image_view *iview = fb->attachments[a].attachment;
787 const struct tu_attachment_state *att = attachments + a;
788 if (att->pending_clear_aspects) {
789 tu6_emit_blit_clear(cmd, cs, iview,
790 tiling->gmem_offsets[gmem_index],
791 &att->clear_value);
792 } else {
793 tu6_emit_blit_info(cmd, cs, iview,
794 tiling->gmem_offsets[gmem_index],
795 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
796 }
797
798 tu6_emit_blit(cmd, cs);
799 }
800
801 static void
802 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
803 {
804 const struct tu_subpass *subpass = cmd->state.subpass;
805
806 tu6_emit_blit_scissor(cmd, cs);
807
808 for (uint32_t i = 0; i < subpass->color_count; ++i) {
809 const uint32_t a = subpass->color_attachments[i].attachment;
810 if (a != VK_ATTACHMENT_UNUSED)
811 tu6_emit_tile_load_attachment(cmd, cs, a, i);
812 }
813
814 const uint32_t a = subpass->depth_stencil_attachment.attachment;
815 if (a != VK_ATTACHMENT_UNUSED)
816 tu6_emit_tile_load_attachment(cmd, cs, a, subpass->color_count);
817 }
818
819 static void
820 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
821 struct tu_cs *cs,
822 uint32_t a,
823 uint32_t gmem_index)
824 {
825 const struct tu_framebuffer *fb = cmd->state.framebuffer;
826 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
827
828 if (a == VK_ATTACHMENT_UNUSED)
829 return;
830
831 tu6_emit_blit_info(cmd, cs, fb->attachments[a].attachment,
832 tiling->gmem_offsets[gmem_index], 0);
833 tu6_emit_blit(cmd, cs);
834 }
835
836 static void
837 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
838 {
839 const struct tu_subpass *subpass = cmd->state.subpass;
840
841 if (false) {
842 /* hw binning? */
843 }
844
845 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
846 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
847 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
848 CP_SET_DRAW_STATE__0_GROUP_ID(0));
849 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
850 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
851
852 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
853 tu_cs_emit(cs, 0x0);
854
855 tu6_emit_marker(cmd, cs);
856 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
857 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
858 tu6_emit_marker(cmd, cs);
859
860 tu6_emit_blit_scissor(cmd, cs);
861
862 for (uint32_t i = 0; i < subpass->color_count; ++i) {
863 tu6_emit_store_attachment(cmd, cs,
864 subpass->color_attachments[i].attachment,
865 i);
866 if (subpass->resolve_attachments) {
867 tu6_emit_store_attachment(cmd, cs,
868 subpass->resolve_attachments[i].attachment,
869 i);
870 }
871 }
872
873 tu6_emit_store_attachment(cmd, cs,
874 subpass->depth_stencil_attachment.attachment,
875 subpass->color_count);
876 }
877
878 static void
879 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
880 {
881 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
882 tu_cs_emit(cs, restart_index);
883 }
884
885 static void
886 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
887 {
888 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
889 if (result != VK_SUCCESS) {
890 cmd->record_result = result;
891 return;
892 }
893
894 tu6_emit_cache_flush(cmd, cs);
895
896 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
897
898 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
899 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
900 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
901 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
902 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
903 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
904 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
905 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
906 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
907
908 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
909 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
910 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
911 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
912 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
913 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
914 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
915 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
916 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
917 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
919 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
920 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
921 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
922
923 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
924
925 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
926 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
928
929 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
940 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
941
942 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
943 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
944
945 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
946 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
947
948 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
949 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
950
951 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
952 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
953 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
954
955 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
956 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
959
960 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
961
962 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
963 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
965 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
970 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
972 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
974 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
975 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
976 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
977 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
978 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
983
984 tu6_emit_marker(cmd, cs);
985
986 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
987
988 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
989
990 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
991
992 /* we don't use this yet.. probably best to disable.. */
993 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
994 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
995 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
996 CP_SET_DRAW_STATE__0_GROUP_ID(0));
997 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
998 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
999
1000 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1001 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1002 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1003 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1004
1005 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1006 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1007 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1008
1009 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1010 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1011
1012 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1013 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1014
1015 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1016 tu_cs_emit(cs, 0x00000000);
1017 tu_cs_emit(cs, 0x00000000);
1018 tu_cs_emit(cs, 0x00000000);
1019
1020 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1021 tu_cs_emit(cs, 0x00000000);
1022 tu_cs_emit(cs, 0x00000000);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025 tu_cs_emit(cs, 0x00000000);
1026 tu_cs_emit(cs, 0x00000000);
1027
1028 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1029 tu_cs_emit(cs, 0x00000000);
1030 tu_cs_emit(cs, 0x00000000);
1031 tu_cs_emit(cs, 0x00000000);
1032 tu_cs_emit(cs, 0x00000000);
1033 tu_cs_emit(cs, 0x00000000);
1034 tu_cs_emit(cs, 0x00000000);
1035
1036 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1037 tu_cs_emit(cs, 0x00000000);
1038 tu_cs_emit(cs, 0x00000000);
1039 tu_cs_emit(cs, 0x00000000);
1040
1041 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1042 tu_cs_emit(cs, 0x00000000);
1043
1044 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1045 tu_cs_emit(cs, 0x00000000);
1046
1047 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1048 tu_cs_emit(cs, 0x00000000);
1049
1050 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1051 tu_cs_emit(cs, 0x00000000);
1052
1053 tu_cs_sanity_check(cs);
1054 }
1055
1056 static void
1057 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1058 {
1059 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1060 if (result != VK_SUCCESS) {
1061 cmd->record_result = result;
1062 return;
1063 }
1064
1065 tu6_emit_lrz_flush(cmd, cs);
1066
1067 /* lrz clear? */
1068
1069 tu6_emit_cache_flush(cmd, cs);
1070
1071 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1072 tu_cs_emit(cs, 0x0);
1073
1074 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1075 tu6_emit_wfi(cmd, cs);
1076 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1077 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1078
1079 tu6_emit_zs(cmd, cs);
1080 tu6_emit_mrt(cmd, cs);
1081 tu6_emit_msaa(cmd, cs);
1082
1083 if (false) {
1084 /* hw binning? */
1085 } else {
1086 tu6_emit_bin_size(cmd, cs, 0x6000000);
1087 /* no draws */
1088 }
1089
1090 tu6_emit_render_cntl(cmd, cs, false);
1091
1092 tu_cs_sanity_check(cs);
1093 }
1094
1095 static void
1096 tu6_render_tile(struct tu_cmd_buffer *cmd,
1097 struct tu_cs *cs,
1098 const struct tu_tile *tile)
1099 {
1100 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1101 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1102 if (result != VK_SUCCESS) {
1103 cmd->record_result = result;
1104 return;
1105 }
1106
1107 tu6_emit_tile_select(cmd, cs, tile);
1108 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1109
1110 tu_cs_emit_call(cs, &cmd->draw_cs);
1111 cmd->wait_for_idle = true;
1112
1113 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1114
1115 tu_cs_sanity_check(cs);
1116 }
1117
1118 static void
1119 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1120 {
1121 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1122 if (result != VK_SUCCESS) {
1123 cmd->record_result = result;
1124 return;
1125 }
1126
1127 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1128 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1129
1130 tu6_emit_lrz_flush(cmd, cs);
1131
1132 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1133
1134 tu_cs_sanity_check(cs);
1135 }
1136
1137 static void
1138 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1139 {
1140 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1141
1142 tu6_render_begin(cmd, &cmd->cs);
1143
1144 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1145 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1146 struct tu_tile tile;
1147 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1148 tu6_render_tile(cmd, &cmd->cs, &tile);
1149 }
1150 }
1151
1152 tu6_render_end(cmd, &cmd->cs);
1153 }
1154
1155 static void
1156 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1157 {
1158 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1159 const struct tu_subpass *subpass = cmd->state.subpass;
1160 struct tu_attachment_state *attachments = cmd->state.attachments;
1161 struct tu_cs sub_cs;
1162
1163 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1164 tile_load_space, &sub_cs);
1165 if (result != VK_SUCCESS) {
1166 cmd->record_result = result;
1167 return;
1168 }
1169
1170 /* emit to tile-load sub_cs */
1171 tu6_emit_tile_load(cmd, &sub_cs);
1172
1173 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1174
1175 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1176 const uint32_t a = subpass->color_attachments[i].attachment;
1177 if (a != VK_ATTACHMENT_UNUSED)
1178 attachments[a].pending_clear_aspects = 0;
1179 }
1180 }
1181
1182 static void
1183 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1184 {
1185 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1186 struct tu_cs sub_cs;
1187
1188 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1189 tile_store_space, &sub_cs);
1190 if (result != VK_SUCCESS) {
1191 cmd->record_result = result;
1192 return;
1193 }
1194
1195 /* emit to tile-store sub_cs */
1196 tu6_emit_tile_store(cmd, &sub_cs);
1197
1198 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1199 }
1200
1201 static void
1202 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1203 const VkRect2D *render_area)
1204 {
1205 const struct tu_device *dev = cmd->device;
1206 const struct tu_render_pass *pass = cmd->state.pass;
1207 const struct tu_subpass *subpass = cmd->state.subpass;
1208 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1209
1210 uint32_t buffer_cpp[MAX_RTS + 2];
1211 uint32_t buffer_count = 0;
1212
1213 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1214 const uint32_t a = subpass->color_attachments[i].attachment;
1215 if (a == VK_ATTACHMENT_UNUSED) {
1216 buffer_cpp[buffer_count++] = 0;
1217 continue;
1218 }
1219
1220 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1221 buffer_cpp[buffer_count++] =
1222 vk_format_get_blocksize(att->format) * att->samples;
1223 }
1224
1225 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1226 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1227 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1228
1229 /* TODO */
1230 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1231
1232 buffer_cpp[buffer_count++] =
1233 vk_format_get_blocksize(att->format) * att->samples;
1234 }
1235
1236 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1237 render_area);
1238 }
1239
1240 const struct tu_dynamic_state default_dynamic_state = {
1241 .viewport =
1242 {
1243 .count = 0,
1244 },
1245 .scissor =
1246 {
1247 .count = 0,
1248 },
1249 .line_width = 1.0f,
1250 .depth_bias =
1251 {
1252 .bias = 0.0f,
1253 .clamp = 0.0f,
1254 .slope = 0.0f,
1255 },
1256 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1257 .depth_bounds =
1258 {
1259 .min = 0.0f,
1260 .max = 1.0f,
1261 },
1262 .stencil_compare_mask =
1263 {
1264 .front = ~0u,
1265 .back = ~0u,
1266 },
1267 .stencil_write_mask =
1268 {
1269 .front = ~0u,
1270 .back = ~0u,
1271 },
1272 .stencil_reference =
1273 {
1274 .front = 0u,
1275 .back = 0u,
1276 },
1277 };
1278
1279 static void UNUSED /* FINISHME */
1280 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1281 const struct tu_dynamic_state *src)
1282 {
1283 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1284 uint32_t copy_mask = src->mask;
1285 uint32_t dest_mask = 0;
1286
1287 tu_use_args(cmd_buffer); /* FINISHME */
1288
1289 /* Make sure to copy the number of viewports/scissors because they can
1290 * only be specified at pipeline creation time.
1291 */
1292 dest->viewport.count = src->viewport.count;
1293 dest->scissor.count = src->scissor.count;
1294 dest->discard_rectangle.count = src->discard_rectangle.count;
1295
1296 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1297 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1298 src->viewport.count * sizeof(VkViewport))) {
1299 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1300 src->viewport.count);
1301 dest_mask |= TU_DYNAMIC_VIEWPORT;
1302 }
1303 }
1304
1305 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1306 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1307 src->scissor.count * sizeof(VkRect2D))) {
1308 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1309 src->scissor.count);
1310 dest_mask |= TU_DYNAMIC_SCISSOR;
1311 }
1312 }
1313
1314 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1315 if (dest->line_width != src->line_width) {
1316 dest->line_width = src->line_width;
1317 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1318 }
1319 }
1320
1321 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1322 if (memcmp(&dest->depth_bias, &src->depth_bias,
1323 sizeof(src->depth_bias))) {
1324 dest->depth_bias = src->depth_bias;
1325 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1326 }
1327 }
1328
1329 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1330 if (memcmp(&dest->blend_constants, &src->blend_constants,
1331 sizeof(src->blend_constants))) {
1332 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1333 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1334 }
1335 }
1336
1337 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1338 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1339 sizeof(src->depth_bounds))) {
1340 dest->depth_bounds = src->depth_bounds;
1341 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1342 }
1343 }
1344
1345 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1346 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1347 sizeof(src->stencil_compare_mask))) {
1348 dest->stencil_compare_mask = src->stencil_compare_mask;
1349 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1350 }
1351 }
1352
1353 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1354 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1355 sizeof(src->stencil_write_mask))) {
1356 dest->stencil_write_mask = src->stencil_write_mask;
1357 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1358 }
1359 }
1360
1361 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1362 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1363 sizeof(src->stencil_reference))) {
1364 dest->stencil_reference = src->stencil_reference;
1365 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1366 }
1367 }
1368
1369 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1370 if (memcmp(&dest->discard_rectangle.rectangles,
1371 &src->discard_rectangle.rectangles,
1372 src->discard_rectangle.count * sizeof(VkRect2D))) {
1373 typed_memcpy(dest->discard_rectangle.rectangles,
1374 src->discard_rectangle.rectangles,
1375 src->discard_rectangle.count);
1376 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1377 }
1378 }
1379 }
1380
1381 static VkResult
1382 tu_create_cmd_buffer(struct tu_device *device,
1383 struct tu_cmd_pool *pool,
1384 VkCommandBufferLevel level,
1385 VkCommandBuffer *pCommandBuffer)
1386 {
1387 struct tu_cmd_buffer *cmd_buffer;
1388 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1389 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1390 if (cmd_buffer == NULL)
1391 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1392
1393 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1394 cmd_buffer->device = device;
1395 cmd_buffer->pool = pool;
1396 cmd_buffer->level = level;
1397
1398 if (pool) {
1399 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1400 cmd_buffer->queue_family_index = pool->queue_family_index;
1401
1402 } else {
1403 /* Init the pool_link so we can safely call list_del when we destroy
1404 * the command buffer
1405 */
1406 list_inithead(&cmd_buffer->pool_link);
1407 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1408 }
1409
1410 tu_bo_list_init(&cmd_buffer->bo_list);
1411 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1412 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1413 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1414 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1415
1416 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1417
1418 list_inithead(&cmd_buffer->upload.list);
1419
1420 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1421 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1422
1423 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1424 if (result != VK_SUCCESS)
1425 return result;
1426
1427 return VK_SUCCESS;
1428 }
1429
1430 static void
1431 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1432 {
1433 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1434
1435 list_del(&cmd_buffer->pool_link);
1436
1437 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1438 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1439
1440 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1441 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1442 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1443 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1444
1445 tu_bo_list_destroy(&cmd_buffer->bo_list);
1446 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1447 }
1448
1449 static VkResult
1450 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1451 {
1452 cmd_buffer->wait_for_idle = true;
1453
1454 cmd_buffer->record_result = VK_SUCCESS;
1455
1456 tu_bo_list_reset(&cmd_buffer->bo_list);
1457 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1458 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1459 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1460 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1461
1462 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1463 cmd_buffer->descriptors[i].dirty = 0;
1464 cmd_buffer->descriptors[i].valid = 0;
1465 cmd_buffer->descriptors[i].push_dirty = false;
1466 }
1467
1468 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1469
1470 return cmd_buffer->record_result;
1471 }
1472
1473 static VkResult
1474 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1475 const VkRenderPassBeginInfo *info)
1476 {
1477 struct tu_cmd_state *state = &cmd_buffer->state;
1478 const struct tu_framebuffer *fb = state->framebuffer;
1479 const struct tu_render_pass *pass = state->pass;
1480
1481 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1482 const struct tu_image_view *iview = fb->attachments[i].attachment;
1483 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1484 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1485 }
1486
1487 if (pass->attachment_count == 0) {
1488 state->attachments = NULL;
1489 return VK_SUCCESS;
1490 }
1491
1492 state->attachments =
1493 vk_alloc(&cmd_buffer->pool->alloc,
1494 pass->attachment_count * sizeof(state->attachments[0]), 8,
1495 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1496 if (state->attachments == NULL) {
1497 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1498 return cmd_buffer->record_result;
1499 }
1500
1501 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1502 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1503 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1504 VkImageAspectFlags clear_aspects = 0;
1505
1506 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1507 /* color attachment */
1508 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1509 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1510 }
1511 } else {
1512 /* depthstencil attachment */
1513 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1514 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1515 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1516 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1517 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1518 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1519 }
1520 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1521 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1522 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1523 }
1524 }
1525
1526 state->attachments[i].pending_clear_aspects = clear_aspects;
1527 state->attachments[i].cleared_views = 0;
1528 if (clear_aspects && info) {
1529 assert(info->clearValueCount > i);
1530 state->attachments[i].clear_value = info->pClearValues[i];
1531 }
1532
1533 state->attachments[i].current_layout = att->initial_layout;
1534 }
1535
1536 return VK_SUCCESS;
1537 }
1538
1539 VkResult
1540 tu_AllocateCommandBuffers(VkDevice _device,
1541 const VkCommandBufferAllocateInfo *pAllocateInfo,
1542 VkCommandBuffer *pCommandBuffers)
1543 {
1544 TU_FROM_HANDLE(tu_device, device, _device);
1545 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1546
1547 VkResult result = VK_SUCCESS;
1548 uint32_t i;
1549
1550 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1551
1552 if (!list_is_empty(&pool->free_cmd_buffers)) {
1553 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1554 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1555
1556 list_del(&cmd_buffer->pool_link);
1557 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1558
1559 result = tu_reset_cmd_buffer(cmd_buffer);
1560 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1561 cmd_buffer->level = pAllocateInfo->level;
1562
1563 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1564 } else {
1565 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1566 &pCommandBuffers[i]);
1567 }
1568 if (result != VK_SUCCESS)
1569 break;
1570 }
1571
1572 if (result != VK_SUCCESS) {
1573 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1574 pCommandBuffers);
1575
1576 /* From the Vulkan 1.0.66 spec:
1577 *
1578 * "vkAllocateCommandBuffers can be used to create multiple
1579 * command buffers. If the creation of any of those command
1580 * buffers fails, the implementation must destroy all
1581 * successfully created command buffer objects from this
1582 * command, set all entries of the pCommandBuffers array to
1583 * NULL and return the error."
1584 */
1585 memset(pCommandBuffers, 0,
1586 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1587 }
1588
1589 return result;
1590 }
1591
1592 void
1593 tu_FreeCommandBuffers(VkDevice device,
1594 VkCommandPool commandPool,
1595 uint32_t commandBufferCount,
1596 const VkCommandBuffer *pCommandBuffers)
1597 {
1598 for (uint32_t i = 0; i < commandBufferCount; i++) {
1599 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1600
1601 if (cmd_buffer) {
1602 if (cmd_buffer->pool) {
1603 list_del(&cmd_buffer->pool_link);
1604 list_addtail(&cmd_buffer->pool_link,
1605 &cmd_buffer->pool->free_cmd_buffers);
1606 } else
1607 tu_cmd_buffer_destroy(cmd_buffer);
1608 }
1609 }
1610 }
1611
1612 VkResult
1613 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1614 VkCommandBufferResetFlags flags)
1615 {
1616 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1617 return tu_reset_cmd_buffer(cmd_buffer);
1618 }
1619
1620 VkResult
1621 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1622 const VkCommandBufferBeginInfo *pBeginInfo)
1623 {
1624 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1625 VkResult result = VK_SUCCESS;
1626
1627 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1628 /* If the command buffer has already been resetted with
1629 * vkResetCommandBuffer, no need to do it again.
1630 */
1631 result = tu_reset_cmd_buffer(cmd_buffer);
1632 if (result != VK_SUCCESS)
1633 return result;
1634 }
1635
1636 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1637 cmd_buffer->usage_flags = pBeginInfo->flags;
1638
1639 tu_cs_begin(&cmd_buffer->cs);
1640 tu_cs_begin(&cmd_buffer->draw_cs);
1641
1642 cmd_buffer->marker_seqno = 0;
1643 cmd_buffer->scratch_seqno = 0;
1644
1645 /* setup initial configuration into command buffer */
1646 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1647 switch (cmd_buffer->queue_family_index) {
1648 case TU_QUEUE_GENERAL:
1649 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1650 break;
1651 default:
1652 break;
1653 }
1654 }
1655
1656 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1657
1658 return VK_SUCCESS;
1659 }
1660
1661 void
1662 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1663 uint32_t firstBinding,
1664 uint32_t bindingCount,
1665 const VkBuffer *pBuffers,
1666 const VkDeviceSize *pOffsets)
1667 {
1668 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1669
1670 assert(firstBinding + bindingCount <= MAX_VBS);
1671
1672 for (uint32_t i = 0; i < bindingCount; i++) {
1673 cmd->state.vb.buffers[firstBinding + i] =
1674 tu_buffer_from_handle(pBuffers[i]);
1675 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1676 }
1677
1678 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1679 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1680 }
1681
1682 void
1683 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1684 VkBuffer buffer,
1685 VkDeviceSize offset,
1686 VkIndexType indexType)
1687 {
1688 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1689 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1690
1691 /* initialize/update the restart index */
1692 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1693 struct tu_cs *draw_cs = &cmd->draw_cs;
1694 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1695 if (result != VK_SUCCESS) {
1696 cmd->record_result = result;
1697 return;
1698 }
1699
1700 tu6_emit_restart_index(
1701 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1702
1703 tu_cs_sanity_check(draw_cs);
1704 }
1705
1706 /* track the BO */
1707 if (cmd->state.index_buffer != buf)
1708 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1709
1710 cmd->state.index_buffer = buf;
1711 cmd->state.index_offset = offset;
1712 cmd->state.index_type = indexType;
1713 }
1714
1715 void
1716 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1717 VkPipelineBindPoint pipelineBindPoint,
1718 VkPipelineLayout _layout,
1719 uint32_t firstSet,
1720 uint32_t descriptorSetCount,
1721 const VkDescriptorSet *pDescriptorSets,
1722 uint32_t dynamicOffsetCount,
1723 const uint32_t *pDynamicOffsets)
1724 {
1725 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1726 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1727 unsigned dyn_idx = 0;
1728
1729 struct tu_descriptor_state *descriptors_state =
1730 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1731
1732 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1733 unsigned idx = i + firstSet;
1734 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1735
1736 descriptors_state->sets[idx] = set;
1737 descriptors_state->valid |= (1u << idx);
1738
1739 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1740 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1741 assert(dyn_idx < dynamicOffsetCount);
1742
1743 descriptors_state->dynamic_buffers[idx] =
1744 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1745 }
1746 }
1747
1748 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1749 }
1750
1751 void
1752 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1753 VkPipelineLayout layout,
1754 VkShaderStageFlags stageFlags,
1755 uint32_t offset,
1756 uint32_t size,
1757 const void *pValues)
1758 {
1759 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1760 memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1761 }
1762
1763 VkResult
1764 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1765 {
1766 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1767
1768 if (cmd_buffer->scratch_seqno) {
1769 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1770 MSM_SUBMIT_BO_WRITE);
1771 }
1772
1773 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1774 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1775 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1776 }
1777
1778 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1779 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1780 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1781 }
1782
1783 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1784 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1785 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1786 }
1787
1788 tu_cs_end(&cmd_buffer->cs);
1789 tu_cs_end(&cmd_buffer->draw_cs);
1790
1791 assert(!cmd_buffer->state.attachments);
1792
1793 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1794
1795 return cmd_buffer->record_result;
1796 }
1797
1798 void
1799 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1800 VkPipelineBindPoint pipelineBindPoint,
1801 VkPipeline _pipeline)
1802 {
1803 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1804 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1805
1806 switch (pipelineBindPoint) {
1807 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1808 cmd->state.pipeline = pipeline;
1809 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1810 break;
1811 case VK_PIPELINE_BIND_POINT_COMPUTE:
1812 cmd->state.compute_pipeline = pipeline;
1813 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
1814 break;
1815 default:
1816 unreachable("unrecognized pipeline bind point");
1817 break;
1818 }
1819
1820 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
1821 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1822 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
1823 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
1824 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1825 }
1826 }
1827
1828 void
1829 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1830 uint32_t firstViewport,
1831 uint32_t viewportCount,
1832 const VkViewport *pViewports)
1833 {
1834 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1835 struct tu_cs *draw_cs = &cmd->draw_cs;
1836
1837 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1838 if (result != VK_SUCCESS) {
1839 cmd->record_result = result;
1840 return;
1841 }
1842
1843 assert(firstViewport == 0 && viewportCount == 1);
1844 tu6_emit_viewport(draw_cs, pViewports);
1845
1846 tu_cs_sanity_check(draw_cs);
1847 }
1848
1849 void
1850 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1851 uint32_t firstScissor,
1852 uint32_t scissorCount,
1853 const VkRect2D *pScissors)
1854 {
1855 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1856 struct tu_cs *draw_cs = &cmd->draw_cs;
1857
1858 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1859 if (result != VK_SUCCESS) {
1860 cmd->record_result = result;
1861 return;
1862 }
1863
1864 assert(firstScissor == 0 && scissorCount == 1);
1865 tu6_emit_scissor(draw_cs, pScissors);
1866
1867 tu_cs_sanity_check(draw_cs);
1868 }
1869
1870 void
1871 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1872 {
1873 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1874
1875 cmd->state.dynamic.line_width = lineWidth;
1876
1877 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1878 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1879 }
1880
1881 void
1882 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1883 float depthBiasConstantFactor,
1884 float depthBiasClamp,
1885 float depthBiasSlopeFactor)
1886 {
1887 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1888 struct tu_cs *draw_cs = &cmd->draw_cs;
1889
1890 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1891 if (result != VK_SUCCESS) {
1892 cmd->record_result = result;
1893 return;
1894 }
1895
1896 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1897 depthBiasSlopeFactor);
1898
1899 tu_cs_sanity_check(draw_cs);
1900 }
1901
1902 void
1903 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1904 const float blendConstants[4])
1905 {
1906 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1907 struct tu_cs *draw_cs = &cmd->draw_cs;
1908
1909 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1910 if (result != VK_SUCCESS) {
1911 cmd->record_result = result;
1912 return;
1913 }
1914
1915 tu6_emit_blend_constants(draw_cs, blendConstants);
1916
1917 tu_cs_sanity_check(draw_cs);
1918 }
1919
1920 void
1921 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1922 float minDepthBounds,
1923 float maxDepthBounds)
1924 {
1925 }
1926
1927 void
1928 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1929 VkStencilFaceFlags faceMask,
1930 uint32_t compareMask)
1931 {
1932 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1933
1934 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1935 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1936 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1937 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1938
1939 /* the front/back compare masks must be updated together */
1940 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1941 }
1942
1943 void
1944 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1945 VkStencilFaceFlags faceMask,
1946 uint32_t writeMask)
1947 {
1948 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1949
1950 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1951 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1952 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1953 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1954
1955 /* the front/back write masks must be updated together */
1956 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1957 }
1958
1959 void
1960 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1961 VkStencilFaceFlags faceMask,
1962 uint32_t reference)
1963 {
1964 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1965
1966 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1967 cmd->state.dynamic.stencil_reference.front = reference;
1968 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1969 cmd->state.dynamic.stencil_reference.back = reference;
1970
1971 /* the front/back references must be updated together */
1972 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1973 }
1974
1975 void
1976 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1977 uint32_t commandBufferCount,
1978 const VkCommandBuffer *pCmdBuffers)
1979 {
1980 }
1981
1982 VkResult
1983 tu_CreateCommandPool(VkDevice _device,
1984 const VkCommandPoolCreateInfo *pCreateInfo,
1985 const VkAllocationCallbacks *pAllocator,
1986 VkCommandPool *pCmdPool)
1987 {
1988 TU_FROM_HANDLE(tu_device, device, _device);
1989 struct tu_cmd_pool *pool;
1990
1991 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1992 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1993 if (pool == NULL)
1994 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1995
1996 if (pAllocator)
1997 pool->alloc = *pAllocator;
1998 else
1999 pool->alloc = device->alloc;
2000
2001 list_inithead(&pool->cmd_buffers);
2002 list_inithead(&pool->free_cmd_buffers);
2003
2004 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2005
2006 *pCmdPool = tu_cmd_pool_to_handle(pool);
2007
2008 return VK_SUCCESS;
2009 }
2010
2011 void
2012 tu_DestroyCommandPool(VkDevice _device,
2013 VkCommandPool commandPool,
2014 const VkAllocationCallbacks *pAllocator)
2015 {
2016 TU_FROM_HANDLE(tu_device, device, _device);
2017 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2018
2019 if (!pool)
2020 return;
2021
2022 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2023 &pool->cmd_buffers, pool_link)
2024 {
2025 tu_cmd_buffer_destroy(cmd_buffer);
2026 }
2027
2028 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2029 &pool->free_cmd_buffers, pool_link)
2030 {
2031 tu_cmd_buffer_destroy(cmd_buffer);
2032 }
2033
2034 vk_free2(&device->alloc, pAllocator, pool);
2035 }
2036
2037 VkResult
2038 tu_ResetCommandPool(VkDevice device,
2039 VkCommandPool commandPool,
2040 VkCommandPoolResetFlags flags)
2041 {
2042 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2043 VkResult result;
2044
2045 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2046 pool_link)
2047 {
2048 result = tu_reset_cmd_buffer(cmd_buffer);
2049 if (result != VK_SUCCESS)
2050 return result;
2051 }
2052
2053 return VK_SUCCESS;
2054 }
2055
2056 void
2057 tu_TrimCommandPool(VkDevice device,
2058 VkCommandPool commandPool,
2059 VkCommandPoolTrimFlags flags)
2060 {
2061 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2062
2063 if (!pool)
2064 return;
2065
2066 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2067 &pool->free_cmd_buffers, pool_link)
2068 {
2069 tu_cmd_buffer_destroy(cmd_buffer);
2070 }
2071 }
2072
2073 void
2074 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2075 const VkRenderPassBeginInfo *pRenderPassBegin,
2076 VkSubpassContents contents)
2077 {
2078 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2079 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2080 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2081 VkResult result;
2082
2083 cmd_buffer->state.pass = pass;
2084 cmd_buffer->state.subpass = pass->subpasses;
2085 cmd_buffer->state.framebuffer = framebuffer;
2086
2087 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2088 if (result != VK_SUCCESS)
2089 return;
2090
2091 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2092 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2093 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2094 }
2095
2096 void
2097 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2098 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2099 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2100 {
2101 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2102 pSubpassBeginInfo->contents);
2103 }
2104
2105 void
2106 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2107 {
2108 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2109
2110 tu_cmd_render_tiles(cmd);
2111
2112 cmd->state.subpass++;
2113
2114 tu_cmd_update_tiling_config(cmd, NULL);
2115 tu_cmd_prepare_tile_load_ib(cmd);
2116 tu_cmd_prepare_tile_store_ib(cmd);
2117 }
2118
2119 void
2120 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2121 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2122 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2123 {
2124 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2125 }
2126
2127 struct tu_draw_info
2128 {
2129 /**
2130 * Number of vertices.
2131 */
2132 uint32_t count;
2133
2134 /**
2135 * Index of the first vertex.
2136 */
2137 int32_t vertex_offset;
2138
2139 /**
2140 * First instance id.
2141 */
2142 uint32_t first_instance;
2143
2144 /**
2145 * Number of instances.
2146 */
2147 uint32_t instance_count;
2148
2149 /**
2150 * First index (indexed draws only).
2151 */
2152 uint32_t first_index;
2153
2154 /**
2155 * Whether it's an indexed draw.
2156 */
2157 bool indexed;
2158
2159 /**
2160 * Indirect draw parameters resource.
2161 */
2162 struct tu_buffer *indirect;
2163 uint64_t indirect_offset;
2164 uint32_t stride;
2165
2166 /**
2167 * Draw count parameters resource.
2168 */
2169 struct tu_buffer *count_buffer;
2170 uint64_t count_buffer_offset;
2171 };
2172
2173 enum tu_draw_state_group_id
2174 {
2175 TU_DRAW_STATE_PROGRAM,
2176 TU_DRAW_STATE_PROGRAM_BINNING,
2177 TU_DRAW_STATE_VI,
2178 TU_DRAW_STATE_VI_BINNING,
2179 TU_DRAW_STATE_VP,
2180 TU_DRAW_STATE_RAST,
2181 TU_DRAW_STATE_DS,
2182 TU_DRAW_STATE_BLEND,
2183 TU_DRAW_STATE_VS_CONST,
2184 TU_DRAW_STATE_FS_CONST,
2185 TU_DRAW_STATE_VS_TEX,
2186 TU_DRAW_STATE_FS_TEX,
2187 TU_DRAW_STATE_FS_IBO,
2188
2189 TU_DRAW_STATE_COUNT,
2190 };
2191
2192 struct tu_draw_state_group
2193 {
2194 enum tu_draw_state_group_id id;
2195 uint32_t enable_mask;
2196 struct tu_cs_entry ib;
2197 };
2198
2199 static struct tu_sampler*
2200 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2201 const struct tu_descriptor_map *map, unsigned i)
2202 {
2203 assert(descriptors_state->valid & (1 << map->set[i]));
2204
2205 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2206 assert(map->binding[i] < set->layout->binding_count);
2207
2208 const struct tu_descriptor_set_binding_layout *layout =
2209 &set->layout->binding[map->binding[i]];
2210
2211 switch (layout->type) {
2212 case VK_DESCRIPTOR_TYPE_SAMPLER:
2213 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2214 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2215 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2216 default:
2217 unreachable("unimplemented descriptor type");
2218 break;
2219 }
2220 }
2221
2222 static uint32_t*
2223 texture_ptr(struct tu_descriptor_state *descriptors_state,
2224 const struct tu_descriptor_map *map, unsigned i)
2225 {
2226 assert(descriptors_state->valid & (1 << map->set[i]));
2227
2228 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2229 assert(map->binding[i] < set->layout->binding_count);
2230
2231 const struct tu_descriptor_set_binding_layout *layout =
2232 &set->layout->binding[map->binding[i]];
2233
2234 switch (layout->type) {
2235 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2236 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2237 return &set->mapped_ptr[layout->offset / 4];
2238 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2239 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2240 return &set->mapped_ptr[layout->offset / 4];
2241 default:
2242 unreachable("unimplemented descriptor type");
2243 break;
2244 }
2245 }
2246
2247 static uint64_t
2248 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2249 const struct tu_descriptor_map *map,
2250 unsigned i)
2251 {
2252 assert(descriptors_state->valid & (1 << map->set[i]));
2253
2254 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2255 assert(map->binding[i] < set->layout->binding_count);
2256
2257 const struct tu_descriptor_set_binding_layout *layout =
2258 &set->layout->binding[map->binding[i]];
2259
2260 switch (layout->type) {
2261 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2262 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2263 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2264 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2265 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2266 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2267 set->mapped_ptr[layout->offset / 4];
2268 default:
2269 unreachable("unimplemented descriptor type");
2270 break;
2271 }
2272 }
2273
2274 static inline uint32_t
2275 tu6_stage2opcode(gl_shader_stage type)
2276 {
2277 switch (type) {
2278 case MESA_SHADER_VERTEX:
2279 case MESA_SHADER_TESS_CTRL:
2280 case MESA_SHADER_TESS_EVAL:
2281 case MESA_SHADER_GEOMETRY:
2282 return CP_LOAD_STATE6_GEOM;
2283 case MESA_SHADER_FRAGMENT:
2284 case MESA_SHADER_COMPUTE:
2285 case MESA_SHADER_KERNEL:
2286 return CP_LOAD_STATE6_FRAG;
2287 default:
2288 unreachable("bad shader type");
2289 }
2290 }
2291
2292 static inline enum a6xx_state_block
2293 tu6_stage2shadersb(gl_shader_stage type)
2294 {
2295 switch (type) {
2296 case MESA_SHADER_VERTEX:
2297 return SB6_VS_SHADER;
2298 case MESA_SHADER_FRAGMENT:
2299 return SB6_FS_SHADER;
2300 case MESA_SHADER_COMPUTE:
2301 case MESA_SHADER_KERNEL:
2302 return SB6_CS_SHADER;
2303 default:
2304 unreachable("bad shader type");
2305 return ~0;
2306 }
2307 }
2308
2309 static void
2310 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2311 struct tu_descriptor_state *descriptors_state,
2312 gl_shader_stage type,
2313 uint32_t *push_constants)
2314 {
2315 const struct tu_program_descriptor_linkage *link =
2316 &pipeline->program.link[type];
2317 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2318
2319 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2320 if (state->range[i].start < state->range[i].end) {
2321 uint32_t size = state->range[i].end - state->range[i].start;
2322 uint32_t offset = state->range[i].start;
2323
2324 /* and even if the start of the const buffer is before
2325 * first_immediate, the end may not be:
2326 */
2327 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2328
2329 if (size == 0)
2330 continue;
2331
2332 /* things should be aligned to vec4: */
2333 debug_assert((state->range[i].offset % 16) == 0);
2334 debug_assert((size % 16) == 0);
2335 debug_assert((offset % 16) == 0);
2336
2337 if (i == 0) {
2338 /* push constants */
2339 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2340 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2341 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2342 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2343 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2344 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2345 tu_cs_emit(cs, 0);
2346 tu_cs_emit(cs, 0);
2347 for (unsigned i = 0; i < size / 4; i++)
2348 tu_cs_emit(cs, push_constants[i + offset / 4]);
2349 continue;
2350 }
2351
2352 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2353
2354 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2355 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2356 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2357 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2358 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2359 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2360 tu_cs_emit_qw(cs, va + offset);
2361 }
2362 }
2363 }
2364
2365 static void
2366 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2367 struct tu_descriptor_state *descriptors_state,
2368 gl_shader_stage type)
2369 {
2370 const struct tu_program_descriptor_linkage *link =
2371 &pipeline->program.link[type];
2372
2373 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2374 uint32_t anum = align(num, 2);
2375 uint32_t i;
2376
2377 if (!num)
2378 return;
2379
2380 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2381 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2382 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2383 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2384 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2385 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2386 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2387 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2388
2389 for (i = 0; i < num; i++)
2390 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2391
2392 for (; i < anum; i++) {
2393 tu_cs_emit(cs, 0xffffffff);
2394 tu_cs_emit(cs, 0xffffffff);
2395 }
2396 }
2397
2398 static struct tu_cs_entry
2399 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2400 const struct tu_pipeline *pipeline,
2401 struct tu_descriptor_state *descriptors_state,
2402 gl_shader_stage type)
2403 {
2404 struct tu_cs cs;
2405 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2406
2407 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2408 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2409
2410 return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2411 }
2412
2413 static VkResult
2414 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2415 gl_shader_stage type,
2416 struct tu_cs_entry *entry,
2417 bool *needs_border)
2418 {
2419 struct tu_device *device = cmd->device;
2420 struct tu_cs *draw_state = &cmd->draw_state;
2421 struct tu_descriptor_state *descriptors_state =
2422 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2423 const struct tu_program_descriptor_linkage *link =
2424 &cmd->state.pipeline->program.link[type];
2425 VkResult result;
2426
2427 if (link->texture_map.num == 0 && link->sampler_map.num == 0) {
2428 *entry = (struct tu_cs_entry) {};
2429 return VK_SUCCESS;
2430 }
2431
2432 /* allocate and fill texture state */
2433 struct ts_cs_memory tex_const;
2434 result = tu_cs_alloc(device, draw_state, link->texture_map.num, A6XX_TEX_CONST_DWORDS, &tex_const);
2435 if (result != VK_SUCCESS)
2436 return result;
2437
2438 for (unsigned i = 0; i < link->texture_map.num; i++) {
2439 memcpy(&tex_const.map[A6XX_TEX_CONST_DWORDS*i],
2440 texture_ptr(descriptors_state, &link->texture_map, i),
2441 A6XX_TEX_CONST_DWORDS*4);
2442 }
2443
2444 /* allocate and fill sampler state */
2445 struct ts_cs_memory tex_samp;
2446 result = tu_cs_alloc(device, draw_state, link->sampler_map.num, A6XX_TEX_SAMP_DWORDS, &tex_samp);
2447 if (result != VK_SUCCESS)
2448 return result;
2449
2450 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2451 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2452 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS*i], sampler->state, sizeof(sampler->state));
2453 *needs_border |= sampler->needs_border;
2454 }
2455
2456 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2457 enum a6xx_state_block sb;
2458
2459 switch (type) {
2460 case MESA_SHADER_VERTEX:
2461 sb = SB6_VS_TEX;
2462 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2463 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2464 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2465 break;
2466 case MESA_SHADER_FRAGMENT:
2467 sb = SB6_FS_TEX;
2468 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2469 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2470 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2471 break;
2472 case MESA_SHADER_COMPUTE:
2473 sb = SB6_CS_TEX;
2474 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2475 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2476 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2477 break;
2478 default:
2479 unreachable("bad state block");
2480 }
2481
2482 struct tu_cs cs;
2483 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2484 if (result != VK_SUCCESS)
2485 return result;
2486
2487 /* output sampler state: */
2488 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2489 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2490 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2491 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2492 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2493 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2494 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2495
2496 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2497 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2498
2499 /* emit texture state: */
2500 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2501 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2502 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2503 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2504 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2505 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2506 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2507
2508 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2509 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2510
2511 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2512 tu_cs_emit(&cs, link->texture_map.num);
2513
2514 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2515 return VK_SUCCESS;
2516 }
2517
2518 static struct tu_cs_entry
2519 tu6_emit_ibo(struct tu_device *device, struct tu_cs *draw_state,
2520 const struct tu_pipeline *pipeline,
2521 struct tu_descriptor_state *descriptors_state,
2522 gl_shader_stage type)
2523 {
2524 const struct tu_program_descriptor_linkage *link =
2525 &pipeline->program.link[type];
2526
2527 uint32_t size = link->image_mapping.num_ibo * A6XX_TEX_CONST_DWORDS;
2528 if (!size)
2529 return (struct tu_cs_entry) {};
2530
2531 struct tu_cs cs;
2532 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2533
2534 for (unsigned i = 0; i < link->image_mapping.num_ibo; i++) {
2535 unsigned idx = link->image_mapping.ibo_to_image[i];
2536
2537 if (idx & IBO_SSBO) {
2538 idx &= ~IBO_SSBO;
2539
2540 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, idx);
2541 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2542 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2543
2544 tu_cs_emit(&cs, A6XX_IBO_0_FMT(TFMT6_32_UINT));
2545 tu_cs_emit(&cs,
2546 A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2547 A6XX_IBO_1_HEIGHT(sz >> 15));
2548 tu_cs_emit(&cs,
2549 A6XX_IBO_2_UNK4 |
2550 A6XX_IBO_2_UNK31 |
2551 A6XX_IBO_2_TYPE(A6XX_TEX_1D));
2552 tu_cs_emit(&cs, 0);
2553 tu_cs_emit_qw(&cs, va);
2554 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2555 tu_cs_emit(&cs, 0);
2556 } else {
2557 tu_finishme("Emit images");
2558 }
2559 }
2560
2561 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2562
2563 uint64_t ibo_addr = entry.bo->iova + entry.offset;
2564
2565 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2566
2567 /* emit texture state: */
2568 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6, 3);
2569 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2570 CP_LOAD_STATE6_0_STATE_TYPE(type == MESA_SHADER_COMPUTE ?
2571 ST6_IBO : ST6_SHADER) |
2572 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2573 CP_LOAD_STATE6_0_STATE_BLOCK(type == MESA_SHADER_COMPUTE ?
2574 SB6_CS_SHADER : SB6_IBO) |
2575 CP_LOAD_STATE6_0_NUM_UNIT(link->image_mapping.num_ibo));
2576 tu_cs_emit_qw(&cs, ibo_addr); /* SRC_ADDR_LO/HI */
2577
2578 tu_cs_emit_pkt4(&cs,
2579 type == MESA_SHADER_COMPUTE ?
2580 REG_A6XX_SP_IBO_LO : REG_A6XX_SP_CS_IBO_LO, 2);
2581 tu_cs_emit_qw(&cs, ibo_addr); /* SRC_ADDR_LO/HI */
2582
2583 return tu_cs_end_sub_stream(draw_state, &cs);
2584 }
2585
2586 struct PACKED bcolor_entry {
2587 uint32_t fp32[4];
2588 uint16_t ui16[4];
2589 int16_t si16[4];
2590 uint16_t fp16[4];
2591 uint16_t rgb565;
2592 uint16_t rgb5a1;
2593 uint16_t rgba4;
2594 uint8_t __pad0[2];
2595 uint8_t ui8[4];
2596 int8_t si8[4];
2597 uint32_t rgb10a2;
2598 uint32_t z24; /* also s8? */
2599 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
2600 uint8_t __pad1[56];
2601 } border_color[] = {
2602 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
2603 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
2604 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
2605 .fp32[3] = 0x3f800000,
2606 .ui16[3] = 0xffff,
2607 .si16[3] = 0x7fff,
2608 .fp16[3] = 0x3c00,
2609 .rgb5a1 = 0x8000,
2610 .rgba4 = 0xf000,
2611 .ui8[3] = 0xff,
2612 .si8[3] = 0x7f,
2613 .rgb10a2 = 0xc0000000,
2614 .srgb[3] = 0x3c00,
2615 },
2616 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
2617 .fp32[3] = 1,
2618 .fp16[3] = 1,
2619 },
2620 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
2621 .fp32[0 ... 3] = 0x3f800000,
2622 .ui16[0 ... 3] = 0xffff,
2623 .si16[0 ... 3] = 0x7fff,
2624 .fp16[0 ... 3] = 0x3c00,
2625 .rgb565 = 0xffff,
2626 .rgb5a1 = 0xffff,
2627 .rgba4 = 0xffff,
2628 .ui8[0 ... 3] = 0xff,
2629 .si8[0 ... 3] = 0x7f,
2630 .rgb10a2 = 0xffffffff,
2631 .z24 = 0xffffff,
2632 .srgb[0 ... 3] = 0x3c00,
2633 },
2634 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
2635 .fp32[0 ... 3] = 1,
2636 .fp16[0 ... 3] = 1,
2637 },
2638 };
2639
2640 static VkResult
2641 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2642 struct tu_cs *cs)
2643 {
2644 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
2645
2646 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2647 struct tu_descriptor_state *descriptors_state =
2648 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2649 const struct tu_descriptor_map *vs_sampler =
2650 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
2651 const struct tu_descriptor_map *fs_sampler =
2652 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
2653 struct ts_cs_memory ptr;
2654
2655 VkResult result = tu_cs_alloc(cmd->device, &cmd->draw_state,
2656 vs_sampler->num + fs_sampler->num, 128 / 4,
2657 &ptr);
2658 if (result != VK_SUCCESS)
2659 return result;
2660
2661 for (unsigned i = 0; i < vs_sampler->num; i++) {
2662 struct tu_sampler *sampler = sampler_ptr(descriptors_state, vs_sampler, i);
2663 memcpy(ptr.map, &border_color[sampler->border], 128);
2664 ptr.map += 128 / 4;
2665 }
2666
2667 for (unsigned i = 0; i < fs_sampler->num; i++) {
2668 struct tu_sampler *sampler = sampler_ptr(descriptors_state, fs_sampler, i);
2669 memcpy(ptr.map, &border_color[sampler->border], 128);
2670 ptr.map += 128 / 4;
2671 }
2672
2673 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2674 tu_cs_emit_qw(cs, ptr.iova);
2675 return VK_SUCCESS;
2676 }
2677
2678 static VkResult
2679 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2680 struct tu_cs *cs,
2681 const struct tu_draw_info *draw)
2682 {
2683 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2684 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2685 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2686 uint32_t draw_state_group_count = 0;
2687
2688 struct tu_descriptor_state *descriptors_state =
2689 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2690
2691 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2692 if (result != VK_SUCCESS)
2693 return result;
2694
2695 /* TODO lrz */
2696
2697 uint32_t pc_primitive_cntl = 0;
2698 if (pipeline->ia.primitive_restart && draw->indexed)
2699 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2700
2701 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2702 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2703 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2704
2705 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2706 tu_cs_emit(cs, pc_primitive_cntl);
2707
2708 if (cmd->state.dirty &
2709 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2710 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2711 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2712 dynamic->line_width);
2713 }
2714
2715 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2716 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2717 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2718 dynamic->stencil_compare_mask.back);
2719 }
2720
2721 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2722 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2723 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2724 dynamic->stencil_write_mask.back);
2725 }
2726
2727 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2728 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2729 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2730 dynamic->stencil_reference.back);
2731 }
2732
2733 if (cmd->state.dirty &
2734 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2735 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2736 const uint32_t binding = pipeline->vi.bindings[i];
2737 const uint32_t stride = pipeline->vi.strides[i];
2738 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2739 const VkDeviceSize offset = buf->bo_offset +
2740 cmd->state.vb.offsets[binding] +
2741 pipeline->vi.offsets[i];
2742 const VkDeviceSize size =
2743 offset < buf->bo->size ? buf->bo->size - offset : 0;
2744
2745 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2746 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2747 tu_cs_emit(cs, size);
2748 tu_cs_emit(cs, stride);
2749 }
2750 }
2751
2752 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2753 draw_state_groups[draw_state_group_count++] =
2754 (struct tu_draw_state_group) {
2755 .id = TU_DRAW_STATE_PROGRAM,
2756 .enable_mask = 0x6,
2757 .ib = pipeline->program.state_ib,
2758 };
2759 draw_state_groups[draw_state_group_count++] =
2760 (struct tu_draw_state_group) {
2761 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2762 .enable_mask = 0x1,
2763 .ib = pipeline->program.binning_state_ib,
2764 };
2765 draw_state_groups[draw_state_group_count++] =
2766 (struct tu_draw_state_group) {
2767 .id = TU_DRAW_STATE_VI,
2768 .enable_mask = 0x6,
2769 .ib = pipeline->vi.state_ib,
2770 };
2771 draw_state_groups[draw_state_group_count++] =
2772 (struct tu_draw_state_group) {
2773 .id = TU_DRAW_STATE_VI_BINNING,
2774 .enable_mask = 0x1,
2775 .ib = pipeline->vi.binning_state_ib,
2776 };
2777 draw_state_groups[draw_state_group_count++] =
2778 (struct tu_draw_state_group) {
2779 .id = TU_DRAW_STATE_VP,
2780 .enable_mask = 0x7,
2781 .ib = pipeline->vp.state_ib,
2782 };
2783 draw_state_groups[draw_state_group_count++] =
2784 (struct tu_draw_state_group) {
2785 .id = TU_DRAW_STATE_RAST,
2786 .enable_mask = 0x7,
2787 .ib = pipeline->rast.state_ib,
2788 };
2789 draw_state_groups[draw_state_group_count++] =
2790 (struct tu_draw_state_group) {
2791 .id = TU_DRAW_STATE_DS,
2792 .enable_mask = 0x7,
2793 .ib = pipeline->ds.state_ib,
2794 };
2795 draw_state_groups[draw_state_group_count++] =
2796 (struct tu_draw_state_group) {
2797 .id = TU_DRAW_STATE_BLEND,
2798 .enable_mask = 0x7,
2799 .ib = pipeline->blend.state_ib,
2800 };
2801 }
2802
2803 if (cmd->state.dirty &
2804 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2805 bool needs_border = false;
2806 struct tu_cs_entry vs_tex, fs_tex;
2807
2808 result = tu6_emit_textures(cmd, MESA_SHADER_VERTEX, &vs_tex, &needs_border);
2809 if (result != VK_SUCCESS)
2810 return result;
2811
2812 result = tu6_emit_textures(cmd, MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
2813 if (result != VK_SUCCESS)
2814 return result;
2815
2816 draw_state_groups[draw_state_group_count++] =
2817 (struct tu_draw_state_group) {
2818 .id = TU_DRAW_STATE_VS_CONST,
2819 .enable_mask = 0x7,
2820 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2821 };
2822 draw_state_groups[draw_state_group_count++] =
2823 (struct tu_draw_state_group) {
2824 .id = TU_DRAW_STATE_FS_CONST,
2825 .enable_mask = 0x6,
2826 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2827 };
2828 draw_state_groups[draw_state_group_count++] =
2829 (struct tu_draw_state_group) {
2830 .id = TU_DRAW_STATE_VS_TEX,
2831 .enable_mask = 0x7,
2832 .ib = vs_tex,
2833 };
2834 draw_state_groups[draw_state_group_count++] =
2835 (struct tu_draw_state_group) {
2836 .id = TU_DRAW_STATE_FS_TEX,
2837 .enable_mask = 0x6,
2838 .ib = fs_tex,
2839 };
2840 draw_state_groups[draw_state_group_count++] =
2841 (struct tu_draw_state_group) {
2842 .id = TU_DRAW_STATE_FS_IBO,
2843 .enable_mask = 0x6,
2844 .ib = tu6_emit_ibo(cmd->device, &cmd->draw_state, pipeline,
2845 descriptors_state, MESA_SHADER_FRAGMENT)
2846 };
2847
2848 if (needs_border) {
2849 result = tu6_emit_border_color(cmd, cs);
2850 if (result != VK_SUCCESS)
2851 return result;
2852 }
2853 }
2854
2855 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2856 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2857 const struct tu_draw_state_group *group = &draw_state_groups[i];
2858
2859 uint32_t cp_set_draw_state =
2860 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2861 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2862 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2863 uint64_t iova;
2864 if (group->ib.size) {
2865 iova = group->ib.bo->iova + group->ib.offset;
2866 } else {
2867 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2868 iova = 0;
2869 }
2870
2871 tu_cs_emit(cs, cp_set_draw_state);
2872 tu_cs_emit_qw(cs, iova);
2873 }
2874
2875 tu_cs_sanity_check(cs);
2876
2877 /* track BOs */
2878 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2879 for (uint32_t i = 0; i < MAX_VBS; i++) {
2880 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2881 if (buf)
2882 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2883 }
2884 }
2885 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2886 unsigned i;
2887 for_each_bit(i, descriptors_state->valid) {
2888 struct tu_descriptor_set *set = descriptors_state->sets[i];
2889 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2890 if (set->descriptors[j]) {
2891 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2892 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2893 }
2894 }
2895 }
2896
2897 /* Fragment shader state overwrites compute shader state, so flag the
2898 * compute pipeline for re-emit.
2899 */
2900 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
2901 return VK_SUCCESS;
2902 }
2903
2904 static void
2905 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2906 struct tu_cs *cs,
2907 const struct tu_draw_info *draw)
2908 {
2909
2910 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2911
2912 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2913 tu_cs_emit(cs, draw->vertex_offset);
2914 tu_cs_emit(cs, draw->first_instance);
2915
2916 /* TODO hw binning */
2917 if (draw->indexed) {
2918 const enum a4xx_index_size index_size =
2919 tu6_index_size(cmd->state.index_type);
2920 const uint32_t index_bytes =
2921 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2922 const struct tu_buffer *buf = cmd->state.index_buffer;
2923 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2924 index_bytes * draw->first_index;
2925 const uint32_t size = index_bytes * draw->count;
2926
2927 const uint32_t cp_draw_indx =
2928 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2929 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2930 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2931 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2932
2933 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2934 tu_cs_emit(cs, cp_draw_indx);
2935 tu_cs_emit(cs, draw->instance_count);
2936 tu_cs_emit(cs, draw->count);
2937 tu_cs_emit(cs, 0x0); /* XXX */
2938 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2939 tu_cs_emit(cs, size);
2940 } else {
2941 const uint32_t cp_draw_indx =
2942 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2943 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2944 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2945
2946 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2947 tu_cs_emit(cs, cp_draw_indx);
2948 tu_cs_emit(cs, draw->instance_count);
2949 tu_cs_emit(cs, draw->count);
2950 }
2951 }
2952
2953 static void
2954 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2955 {
2956 struct tu_cs *cs = &cmd->draw_cs;
2957 VkResult result;
2958
2959 result = tu6_bind_draw_states(cmd, cs, draw);
2960 if (result != VK_SUCCESS) {
2961 cmd->record_result = result;
2962 return;
2963 }
2964
2965 result = tu_cs_reserve_space(cmd->device, cs, 32);
2966 if (result != VK_SUCCESS) {
2967 cmd->record_result = result;
2968 return;
2969 }
2970
2971 if (draw->indirect) {
2972 tu_finishme("indirect draw");
2973 return;
2974 }
2975
2976 /* TODO tu6_emit_marker should pick different regs depending on cs */
2977 tu6_emit_marker(cmd, cs);
2978 tu6_emit_draw_direct(cmd, cs, draw);
2979 tu6_emit_marker(cmd, cs);
2980
2981 cmd->wait_for_idle = true;
2982
2983 tu_cs_sanity_check(cs);
2984 }
2985
2986 void
2987 tu_CmdDraw(VkCommandBuffer commandBuffer,
2988 uint32_t vertexCount,
2989 uint32_t instanceCount,
2990 uint32_t firstVertex,
2991 uint32_t firstInstance)
2992 {
2993 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2994 struct tu_draw_info info = {};
2995
2996 info.count = vertexCount;
2997 info.instance_count = instanceCount;
2998 info.first_instance = firstInstance;
2999 info.vertex_offset = firstVertex;
3000
3001 tu_draw(cmd_buffer, &info);
3002 }
3003
3004 void
3005 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3006 uint32_t indexCount,
3007 uint32_t instanceCount,
3008 uint32_t firstIndex,
3009 int32_t vertexOffset,
3010 uint32_t firstInstance)
3011 {
3012 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3013 struct tu_draw_info info = {};
3014
3015 info.indexed = true;
3016 info.count = indexCount;
3017 info.instance_count = instanceCount;
3018 info.first_index = firstIndex;
3019 info.vertex_offset = vertexOffset;
3020 info.first_instance = firstInstance;
3021
3022 tu_draw(cmd_buffer, &info);
3023 }
3024
3025 void
3026 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3027 VkBuffer _buffer,
3028 VkDeviceSize offset,
3029 uint32_t drawCount,
3030 uint32_t stride)
3031 {
3032 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3033 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3034 struct tu_draw_info info = {};
3035
3036 info.count = drawCount;
3037 info.indirect = buffer;
3038 info.indirect_offset = offset;
3039 info.stride = stride;
3040
3041 tu_draw(cmd_buffer, &info);
3042 }
3043
3044 void
3045 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3046 VkBuffer _buffer,
3047 VkDeviceSize offset,
3048 uint32_t drawCount,
3049 uint32_t stride)
3050 {
3051 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3052 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3053 struct tu_draw_info info = {};
3054
3055 info.indexed = true;
3056 info.count = drawCount;
3057 info.indirect = buffer;
3058 info.indirect_offset = offset;
3059 info.stride = stride;
3060
3061 tu_draw(cmd_buffer, &info);
3062 }
3063
3064 struct tu_dispatch_info
3065 {
3066 /**
3067 * Determine the layout of the grid (in block units) to be used.
3068 */
3069 uint32_t blocks[3];
3070
3071 /**
3072 * A starting offset for the grid. If unaligned is set, the offset
3073 * must still be aligned.
3074 */
3075 uint32_t offsets[3];
3076 /**
3077 * Whether it's an unaligned compute dispatch.
3078 */
3079 bool unaligned;
3080
3081 /**
3082 * Indirect compute parameters resource.
3083 */
3084 struct tu_buffer *indirect;
3085 uint64_t indirect_offset;
3086 };
3087
3088 static void
3089 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3090 const struct tu_dispatch_info *info)
3091 {
3092 gl_shader_stage type = MESA_SHADER_COMPUTE;
3093 const struct tu_program_descriptor_linkage *link =
3094 &pipeline->program.link[type];
3095 const struct ir3_const_state *const_state = &link->const_state;
3096 uint32_t offset_dwords = const_state->offsets.driver_param;
3097
3098 if (link->constlen <= offset_dwords)
3099 return;
3100
3101 if (!info->indirect) {
3102 uint32_t driver_params[] = {
3103 info->blocks[0],
3104 info->blocks[1],
3105 info->blocks[2],
3106 pipeline->compute.local_size[0],
3107 pipeline->compute.local_size[1],
3108 pipeline->compute.local_size[2],
3109 };
3110 uint32_t num_consts = MIN2(const_state->num_driver_params,
3111 link->constlen - offset_dwords);
3112 uint32_t align_size = align(num_consts, 4);
3113
3114 /* push constants */
3115 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + align_size);
3116 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset_dwords / 4) |
3117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3118 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3119 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3120 CP_LOAD_STATE6_0_NUM_UNIT(align_size / 4));
3121 tu_cs_emit(cs, 0);
3122 tu_cs_emit(cs, 0);
3123 uint32_t i;
3124 for (i = 0; i < num_consts; i++)
3125 tu_cs_emit(cs, driver_params[i]);
3126 for (; i < align_size; i++)
3127 tu_cs_emit(cs, 0);
3128 } else {
3129 tu_finishme("Indirect driver params");
3130 }
3131 }
3132
3133 static void
3134 tu_dispatch(struct tu_cmd_buffer *cmd,
3135 const struct tu_dispatch_info *info)
3136 {
3137 struct tu_cs *cs = &cmd->cs;
3138 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3139 struct tu_descriptor_state *descriptors_state =
3140 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3141
3142 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3143 if (result != VK_SUCCESS) {
3144 cmd->record_result = result;
3145 return;
3146 }
3147
3148 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3149 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3150
3151 struct tu_cs_entry ib;
3152
3153 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3154 if (ib.size)
3155 tu_cs_emit_ib(cs, &ib);
3156
3157 tu_emit_compute_driver_params(cs, pipeline, info);
3158
3159 bool needs_border;
3160 result = tu6_emit_textures(cmd, MESA_SHADER_COMPUTE, &ib, &needs_border);
3161 if (result != VK_SUCCESS) {
3162 cmd->record_result = result;
3163 return;
3164 }
3165
3166 if (ib.size)
3167 tu_cs_emit_ib(cs, &ib);
3168
3169 if (needs_border)
3170 tu6_emit_border_color(cmd, cs);
3171
3172 ib = tu6_emit_ibo(cmd->device, &cmd->draw_state, pipeline,
3173 descriptors_state, MESA_SHADER_COMPUTE);
3174 if (ib.size)
3175 tu_cs_emit_ib(cs, &ib);
3176
3177 /* track BOs */
3178 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3179 unsigned i;
3180 for_each_bit(i, descriptors_state->valid) {
3181 struct tu_descriptor_set *set = descriptors_state->sets[i];
3182 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3183 if (set->descriptors[j]) {
3184 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3185 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3186 }
3187 }
3188 }
3189
3190 /* Compute shader state overwrites fragment shader state, so we flag the
3191 * graphics pipeline for re-emit.
3192 */
3193 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3194
3195 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3196 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3197
3198 const uint32_t *local_size = pipeline->compute.local_size;
3199 const uint32_t *num_groups = info->blocks;
3200 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
3201 tu_cs_emit(cs,
3202 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3203 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
3204 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
3205 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
3206 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
3207 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3208 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
3209 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3210 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
3211 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3212
3213 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
3214 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_X */
3215 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
3216 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
3217
3218 if (info->indirect) {
3219 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3220
3221 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3222 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3223
3224 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3225 tu_cs_emit(cs, 0x00000000);
3226 tu_cs_emit_qw(cs, iova);
3227 tu_cs_emit(cs,
3228 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3229 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3230 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3231 } else {
3232 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3233 tu_cs_emit(cs, 0x00000000);
3234 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3235 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3236 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3237 }
3238
3239 tu_cs_emit_wfi(cs);
3240
3241 tu6_emit_cache_flush(cmd, cs);
3242 }
3243
3244 void
3245 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3246 uint32_t base_x,
3247 uint32_t base_y,
3248 uint32_t base_z,
3249 uint32_t x,
3250 uint32_t y,
3251 uint32_t z)
3252 {
3253 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3254 struct tu_dispatch_info info = {};
3255
3256 info.blocks[0] = x;
3257 info.blocks[1] = y;
3258 info.blocks[2] = z;
3259
3260 info.offsets[0] = base_x;
3261 info.offsets[1] = base_y;
3262 info.offsets[2] = base_z;
3263 tu_dispatch(cmd_buffer, &info);
3264 }
3265
3266 void
3267 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3268 uint32_t x,
3269 uint32_t y,
3270 uint32_t z)
3271 {
3272 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3273 }
3274
3275 void
3276 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3277 VkBuffer _buffer,
3278 VkDeviceSize offset)
3279 {
3280 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3281 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3282 struct tu_dispatch_info info = {};
3283
3284 info.indirect = buffer;
3285 info.indirect_offset = offset;
3286
3287 tu_dispatch(cmd_buffer, &info);
3288 }
3289
3290 void
3291 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3292 {
3293 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3294
3295 tu_cs_end(&cmd_buffer->draw_cs);
3296
3297 tu_cmd_render_tiles(cmd_buffer);
3298
3299 /* discard draw_cs entries now that the tiles are rendered */
3300 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3301 tu_cs_begin(&cmd_buffer->draw_cs);
3302
3303 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3304 cmd_buffer->state.attachments = NULL;
3305
3306 cmd_buffer->state.pass = NULL;
3307 cmd_buffer->state.subpass = NULL;
3308 cmd_buffer->state.framebuffer = NULL;
3309 }
3310
3311 void
3312 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3313 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3314 {
3315 tu_CmdEndRenderPass(commandBuffer);
3316 }
3317
3318 struct tu_barrier_info
3319 {
3320 uint32_t eventCount;
3321 const VkEvent *pEvents;
3322 VkPipelineStageFlags srcStageMask;
3323 };
3324
3325 static void
3326 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3327 uint32_t memoryBarrierCount,
3328 const VkMemoryBarrier *pMemoryBarriers,
3329 uint32_t bufferMemoryBarrierCount,
3330 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3331 uint32_t imageMemoryBarrierCount,
3332 const VkImageMemoryBarrier *pImageMemoryBarriers,
3333 const struct tu_barrier_info *info)
3334 {
3335 }
3336
3337 void
3338 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3339 VkPipelineStageFlags srcStageMask,
3340 VkPipelineStageFlags destStageMask,
3341 VkBool32 byRegion,
3342 uint32_t memoryBarrierCount,
3343 const VkMemoryBarrier *pMemoryBarriers,
3344 uint32_t bufferMemoryBarrierCount,
3345 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3346 uint32_t imageMemoryBarrierCount,
3347 const VkImageMemoryBarrier *pImageMemoryBarriers)
3348 {
3349 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3350 struct tu_barrier_info info;
3351
3352 info.eventCount = 0;
3353 info.pEvents = NULL;
3354 info.srcStageMask = srcStageMask;
3355
3356 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3357 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3358 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3359 }
3360
3361 static void
3362 write_event(struct tu_cmd_buffer *cmd_buffer,
3363 struct tu_event *event,
3364 VkPipelineStageFlags stageMask,
3365 unsigned value)
3366 {
3367 }
3368
3369 void
3370 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3371 VkEvent _event,
3372 VkPipelineStageFlags stageMask)
3373 {
3374 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3375 TU_FROM_HANDLE(tu_event, event, _event);
3376
3377 write_event(cmd_buffer, event, stageMask, 1);
3378 }
3379
3380 void
3381 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3382 VkEvent _event,
3383 VkPipelineStageFlags stageMask)
3384 {
3385 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3386 TU_FROM_HANDLE(tu_event, event, _event);
3387
3388 write_event(cmd_buffer, event, stageMask, 0);
3389 }
3390
3391 void
3392 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3393 uint32_t eventCount,
3394 const VkEvent *pEvents,
3395 VkPipelineStageFlags srcStageMask,
3396 VkPipelineStageFlags dstStageMask,
3397 uint32_t memoryBarrierCount,
3398 const VkMemoryBarrier *pMemoryBarriers,
3399 uint32_t bufferMemoryBarrierCount,
3400 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3401 uint32_t imageMemoryBarrierCount,
3402 const VkImageMemoryBarrier *pImageMemoryBarriers)
3403 {
3404 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3405 struct tu_barrier_info info;
3406
3407 info.eventCount = eventCount;
3408 info.pEvents = pEvents;
3409 info.srcStageMask = 0;
3410
3411 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3412 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3413 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3414 }
3415
3416 void
3417 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3418 {
3419 /* No-op */
3420 }