2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
116 const struct tu_render_pass
*pass
)
118 const uint32_t tile_align_w
= pass
->tile_align_w
;
119 const uint32_t max_tile_width
= 1024;
121 /* note: don't offset the tiling config by render_area.offset,
122 * because binning pass can't deal with it
123 * this means we might end up with more tiles than necessary,
124 * but load/store/etc are still scissored to the render_area
126 tiling
->tile0
.offset
= (VkOffset2D
) {};
128 const uint32_t ra_width
=
129 tiling
->render_area
.extent
.width
+
130 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
131 const uint32_t ra_height
=
132 tiling
->render_area
.extent
.height
+
133 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
135 /* start from 1 tile */
136 tiling
->tile_count
= (VkExtent2D
) {
140 tiling
->tile0
.extent
= (VkExtent2D
) {
141 .width
= util_align_npot(ra_width
, tile_align_w
),
142 .height
= align(ra_height
, TILE_ALIGN_H
),
145 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
146 /* start with 2x2 tiles */
147 tiling
->tile_count
.width
= 2;
148 tiling
->tile_count
.height
= 2;
149 tiling
->tile0
.extent
.width
= util_align_npot(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
150 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), TILE_ALIGN_H
);
153 /* do not exceed max tile width */
154 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
155 tiling
->tile_count
.width
++;
156 tiling
->tile0
.extent
.width
=
157 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
160 /* will force to sysmem, don't bother trying to have a valid tile config
161 * TODO: just skip all GMEM stuff when sysmem is forced?
163 if (!pass
->gmem_pixels
)
166 /* do not exceed gmem size */
167 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pass
->gmem_pixels
) {
168 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
169 tiling
->tile_count
.width
++;
170 tiling
->tile0
.extent
.width
=
171 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
173 /* if this assert fails then layout is impossible.. */
174 assert(tiling
->tile0
.extent
.height
> TILE_ALIGN_H
);
175 tiling
->tile_count
.height
++;
176 tiling
->tile0
.extent
.height
=
177 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), TILE_ALIGN_H
);
183 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
184 const struct tu_device
*dev
)
186 const uint32_t max_pipe_count
= 32; /* A6xx */
188 /* start from 1 tile per pipe */
189 tiling
->pipe0
= (VkExtent2D
) {
193 tiling
->pipe_count
= tiling
->tile_count
;
195 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
196 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
197 tiling
->pipe0
.width
+= 1;
198 tiling
->pipe_count
.width
=
199 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
201 tiling
->pipe0
.height
+= 1;
202 tiling
->pipe_count
.height
=
203 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
209 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
210 const struct tu_device
*dev
)
212 const uint32_t max_pipe_count
= 32; /* A6xx */
213 const uint32_t used_pipe_count
=
214 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
215 const VkExtent2D last_pipe
= {
216 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
217 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
220 assert(used_pipe_count
<= max_pipe_count
);
221 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
223 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
224 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
225 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
226 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
227 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
229 : tiling
->pipe0
.width
;
230 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
232 : tiling
->pipe0
.height
;
233 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
235 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
236 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
237 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
238 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
239 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
243 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
244 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
248 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
249 const struct tu_device
*dev
,
252 struct tu_tile
*tile
)
254 /* find the pipe and the slot for tile (tx, ty) */
255 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
256 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
257 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
258 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
259 /* last pipe has different width */
260 const uint32_t pipe_width
=
261 MIN2(tiling
->pipe0
.width
,
262 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
264 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
265 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
266 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
268 /* convert to 1D indices */
269 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
270 tile
->slot
= pipe_width
* sy
+ sx
;
272 /* get the blit area for the tile */
273 tile
->begin
= (VkOffset2D
) {
274 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
275 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
278 (tx
== tiling
->tile_count
.width
- 1)
279 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
280 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
282 (ty
== tiling
->tile_count
.height
- 1)
283 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
284 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
287 enum a3xx_msaa_samples
288 tu_msaa_samples(uint32_t samples
)
300 assert(!"invalid sample count");
305 static enum a4xx_index_size
306 tu6_index_size(VkIndexType type
)
309 case VK_INDEX_TYPE_UINT16
:
310 return INDEX4_SIZE_16_BIT
;
311 case VK_INDEX_TYPE_UINT32
:
312 return INDEX4_SIZE_32_BIT
;
314 unreachable("invalid VkIndexType");
315 return INDEX4_SIZE_8_BIT
;
320 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
322 enum vgt_event_type event
,
327 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
328 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
330 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
331 seqno
= ++cmd
->scratch_seqno
;
332 tu_cs_emit(cs
, seqno
);
339 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
341 tu6_emit_event_write(cmd
, cs
, 0x31, false);
345 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
347 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
351 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
353 if (cmd
->wait_for_idle
) {
355 cmd
->wait_for_idle
= false;
360 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
361 const struct tu_subpass
*subpass
,
364 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
366 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
367 if (a
== VK_ATTACHMENT_UNUSED
) {
369 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
370 A6XX_RB_DEPTH_BUFFER_PITCH(0),
371 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
372 A6XX_RB_DEPTH_BUFFER_BASE(0),
373 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
376 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
379 A6XX_GRAS_LRZ_BUFFER_BASE(0),
380 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
381 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
383 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
388 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
389 const struct tu_render_pass_attachment
*attachment
=
390 &cmd
->state
.pass
->attachments
[a
];
391 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
393 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
394 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
395 tu_cs_image_ref(cs
, iview
, 0);
396 tu_cs_emit(cs
, attachment
->gmem_offset
);
399 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
401 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
402 tu_cs_image_flag_ref(cs
, iview
, 0);
405 A6XX_GRAS_LRZ_BUFFER_BASE(0),
406 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
407 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
409 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
410 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
411 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
412 tu_cs_image_ref(cs
, iview
, 0);
413 tu_cs_emit(cs
, attachment
->gmem_offset
);
416 A6XX_RB_STENCIL_INFO(0));
421 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
422 const struct tu_subpass
*subpass
,
425 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
427 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
428 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
429 if (a
== VK_ATTACHMENT_UNUSED
)
432 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
434 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
435 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
436 tu_cs_image_ref(cs
, iview
, 0);
437 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
440 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
442 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
443 tu_cs_image_flag_ref(cs
, iview
, 0);
447 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
449 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
452 A6XX_RB_RENDER_COMPONENTS(.dword
= subpass
->render_components
));
454 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= subpass
->render_components
));
456 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
460 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
462 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
463 bool msaa_disable
= samples
== MSAA_ONE
;
466 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
467 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
468 .msaa_disable
= msaa_disable
));
471 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
472 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
473 .msaa_disable
= msaa_disable
));
476 A6XX_RB_RAS_MSAA_CNTL(samples
),
477 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
478 .msaa_disable
= msaa_disable
));
481 A6XX_RB_MSAA_CNTL(samples
));
485 tu6_emit_bin_size(struct tu_cs
*cs
,
486 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
489 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
494 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
498 /* no flag for RB_BIN_CONTROL2... */
500 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
505 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
506 const struct tu_subpass
*subpass
,
510 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
512 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
514 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
516 uint32_t mrts_ubwc_enable
= 0;
517 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
518 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
519 if (a
== VK_ATTACHMENT_UNUSED
)
522 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
523 if (iview
->ubwc_enabled
)
524 mrts_ubwc_enable
|= 1 << i
;
527 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
529 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
530 if (a
!= VK_ATTACHMENT_UNUSED
) {
531 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
532 if (iview
->ubwc_enabled
)
533 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
536 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
537 * in order to set it correctly for the different subpasses. However,
538 * that means the packets we're emitting also happen during binning. So
539 * we need to guard the write on !BINNING at CP execution time.
541 tu_cs_reserve(cs
, 3 + 4);
542 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
543 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
544 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
545 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
548 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
549 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
550 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
551 tu_cs_emit(cs
, cntl
);
555 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
557 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
558 uint32_t x1
= render_area
->offset
.x
;
559 uint32_t y1
= render_area
->offset
.y
;
560 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
561 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
564 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
565 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
566 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
567 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
571 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
572 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
576 tu6_emit_window_scissor(struct tu_cs
*cs
,
583 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
584 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
587 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
588 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
592 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
595 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
598 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
601 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
604 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
608 use_hw_binning(struct tu_cmd_buffer
*cmd
)
610 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
612 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
615 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
618 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
622 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
624 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
627 /* can't fit attachments into gmem */
628 if (!cmd
->state
.pass
->gmem_pixels
)
631 if (cmd
->state
.framebuffer
->layers
> 1)
634 return cmd
->state
.tiling_config
.force_sysmem
;
638 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
640 const struct tu_tile
*tile
)
642 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
643 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
645 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
646 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
648 const uint32_t x1
= tile
->begin
.x
;
649 const uint32_t y1
= tile
->begin
.y
;
650 const uint32_t x2
= tile
->end
.x
- 1;
651 const uint32_t y2
= tile
->end
.y
- 1;
652 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
653 tu6_emit_window_offset(cs
, x1
, y1
);
656 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
658 if (use_hw_binning(cmd
)) {
659 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
661 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
664 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
665 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
666 A6XX_CP_REG_TEST_0_BIT(0) |
667 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
669 tu_cs_reserve(cs
, 3 + 11);
670 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
671 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
672 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
674 /* if (no overflow) */ {
675 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
676 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
677 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
678 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
679 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
680 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
682 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
685 /* use a NOP packet to skip over the 'else' side: */
686 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
688 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
692 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
695 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
698 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
704 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
709 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
710 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
711 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
713 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
717 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
719 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
720 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
722 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
723 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
724 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
725 CP_SET_DRAW_STATE__0_GROUP_ID(0));
726 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
727 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
729 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
732 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
733 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
735 tu6_emit_blit_scissor(cmd
, cs
, true);
737 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
738 if (pass
->attachments
[a
].gmem_offset
>= 0)
739 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
742 if (subpass
->resolve_attachments
) {
743 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
744 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
745 if (a
!= VK_ATTACHMENT_UNUSED
)
746 tu_store_gmem_attachment(cmd
, cs
, a
,
747 subpass
->color_attachments
[i
].attachment
);
753 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
756 A6XX_PC_RESTART_INDEX(restart_index
));
760 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
762 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
764 tu6_emit_cache_flush(cmd
, cs
);
766 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
769 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
770 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
790 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
791 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
792 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
795 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
802 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
814 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
817 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
818 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
820 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
821 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
823 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
825 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
827 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
844 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
846 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
851 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
853 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
855 /* we don't use this yet.. probably best to disable.. */
856 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
857 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
858 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
859 CP_SET_DRAW_STATE__0_GROUP_ID(0));
860 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
861 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
863 /* Set not to use streamout by default, */
864 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
865 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
867 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
871 A6XX_SP_HS_CTRL_REG0(0));
874 A6XX_SP_GS_CTRL_REG0(0));
877 A6XX_GRAS_LRZ_CNTL(0));
880 A6XX_RB_LRZ_CNTL(0));
883 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
885 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
887 tu_cs_sanity_check(cs
);
891 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
895 seqno
= tu6_emit_event_write(cmd
, cs
, RB_DONE_TS
, true);
897 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
898 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
899 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
900 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
901 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
902 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
903 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
905 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
907 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
908 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
909 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
910 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
914 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
916 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
919 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
920 .height
= tiling
->tile0
.extent
.height
),
921 A6XX_VSC_SIZE_ADDRESS(.bo
= &cmd
->vsc_data
,
922 .bo_offset
= 32 * cmd
->vsc_data_pitch
));
925 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
926 .ny
= tiling
->tile_count
.height
));
928 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
929 for (unsigned i
= 0; i
< 32; i
++)
930 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
933 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo
= &cmd
->vsc_data2
),
934 A6XX_VSC_PIPE_DATA2_PITCH(cmd
->vsc_data2_pitch
),
935 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd
->vsc_data2
.size
));
938 A6XX_VSC_PIPE_DATA_ADDRESS(.bo
= &cmd
->vsc_data
),
939 A6XX_VSC_PIPE_DATA_PITCH(cmd
->vsc_data_pitch
),
940 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd
->vsc_data
.size
));
944 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
946 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
947 const uint32_t used_pipe_count
=
948 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
950 /* Clear vsc_scratch: */
951 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
952 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
955 /* Check for overflow, write vsc_scratch if detected: */
956 for (int i
= 0; i
< used_pipe_count
; i
++) {
957 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
958 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
959 CP_COND_WRITE5_0_WRITE_MEMORY
);
960 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
961 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
962 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
963 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
964 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
965 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
967 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
968 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
969 CP_COND_WRITE5_0_WRITE_MEMORY
);
970 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
971 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
972 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
973 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
974 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
975 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
978 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
980 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
982 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
983 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
984 CP_MEM_TO_REG_0_CNT(1 - 1));
985 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
988 * This is a bit awkward, we really want a way to invert the
989 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
990 * execute cmds to use hwbinning when a bit is *not* set. This
991 * dance is to invert OVERFLOW_FLAG_REG
993 * A CP_NOP packet is used to skip executing the 'else' clause
997 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
998 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
999 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1000 A6XX_CP_REG_TEST_0_BIT(0) |
1001 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1003 tu_cs_reserve(cs
, 3 + 7);
1004 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1005 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1006 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1010 * On overflow, mirror the value to control->vsc_overflow
1011 * which CPU is checking to detect overflow (see
1012 * check_vsc_overflow())
1014 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1015 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1016 CP_REG_TO_MEM_0_CNT(0));
1017 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1019 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1020 tu_cs_emit(cs
, 0x0);
1022 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1024 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1025 tu_cs_emit(cs
, 0x1);
1030 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1032 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1033 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1035 uint32_t x1
= tiling
->tile0
.offset
.x
;
1036 uint32_t y1
= tiling
->tile0
.offset
.y
;
1037 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1038 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1040 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1042 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1043 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1045 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1046 tu_cs_emit(cs
, 0x1);
1048 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1049 tu_cs_emit(cs
, 0x1);
1054 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1056 update_vsc_pipe(cmd
, cs
);
1059 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1062 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1064 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1065 tu_cs_emit(cs
, UNK_2C
);
1068 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1071 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1073 /* emit IB to binning drawcmds: */
1074 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1076 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1077 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1078 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1079 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1080 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1081 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1083 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1084 tu_cs_emit(cs
, UNK_2D
);
1086 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1087 tu6_cache_flush(cmd
, cs
);
1091 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1093 emit_vsc_overflow_test(cmd
, cs
);
1095 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1096 tu_cs_emit(cs
, 0x0);
1098 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1099 tu_cs_emit(cs
, 0x0);
1101 cmd
->wait_for_idle
= false;
1105 tu_emit_load_clear(struct tu_cmd_buffer
*cmd
,
1106 const VkRenderPassBeginInfo
*info
)
1108 struct tu_cs
*cs
= &cmd
->draw_cs
;
1110 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1112 tu6_emit_blit_scissor(cmd
, cs
, true);
1114 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1115 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1117 tu6_emit_blit_scissor(cmd
, cs
, false);
1119 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1120 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1122 tu_cond_exec_end(cs
);
1124 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1126 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1127 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1129 tu_cond_exec_end(cs
);
1133 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1134 const struct VkRect2D
*renderArea
)
1136 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1137 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1139 assert(fb
->width
> 0 && fb
->height
> 0);
1140 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1141 tu6_emit_window_offset(cs
, 0, 0);
1143 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1145 tu6_emit_lrz_flush(cmd
, cs
);
1147 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1148 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1150 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1151 tu_cs_emit(cs
, 0x0);
1153 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1154 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1155 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1157 tu6_emit_wfi(cmd
, cs
);
1159 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
1161 /* enable stream-out, with sysmem there is only one pass: */
1163 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1165 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1166 tu_cs_emit(cs
, 0x1);
1168 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1169 tu_cs_emit(cs
, 0x0);
1171 tu_cs_sanity_check(cs
);
1175 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1177 /* Do any resolves of the last subpass. These are handled in the
1178 * tile_store_ib in the gmem path.
1180 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1181 if (subpass
->resolve_attachments
) {
1182 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
1183 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
1184 if (a
!= VK_ATTACHMENT_UNUSED
)
1185 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
1186 subpass
->color_attachments
[i
].attachment
);
1190 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1192 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1193 tu_cs_emit(cs
, 0x0);
1195 tu6_emit_lrz_flush(cmd
, cs
);
1197 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1198 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1200 tu_cs_sanity_check(cs
);
1205 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1207 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1209 tu6_emit_lrz_flush(cmd
, cs
);
1213 tu6_emit_cache_flush(cmd
, cs
);
1215 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1216 tu_cs_emit(cs
, 0x0);
1218 /* TODO: flushing with barriers instead of blindly always flushing */
1219 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1220 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1221 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1222 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1226 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_gmem
, .gmem
= 1));
1228 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1229 if (use_hw_binning(cmd
)) {
1230 /* enable stream-out during binning pass: */
1231 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1233 tu6_emit_bin_size(cs
,
1234 tiling
->tile0
.extent
.width
,
1235 tiling
->tile0
.extent
.height
,
1236 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1238 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1240 tu6_emit_binning_pass(cmd
, cs
);
1242 /* and disable stream-out for draw pass: */
1243 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1245 tu6_emit_bin_size(cs
,
1246 tiling
->tile0
.extent
.width
,
1247 tiling
->tile0
.extent
.height
,
1248 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1251 A6XX_VFD_MODE_CNTL(0));
1253 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1255 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1257 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1258 tu_cs_emit(cs
, 0x1);
1260 /* no binning pass, so enable stream-out for draw pass:: */
1261 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1263 tu6_emit_bin_size(cs
,
1264 tiling
->tile0
.extent
.width
,
1265 tiling
->tile0
.extent
.height
,
1269 tu_cs_sanity_check(cs
);
1273 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1275 const struct tu_tile
*tile
)
1277 tu6_emit_tile_select(cmd
, cs
, tile
);
1279 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1280 cmd
->wait_for_idle
= true;
1282 if (use_hw_binning(cmd
)) {
1283 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1284 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1285 A6XX_CP_REG_TEST_0_BIT(0) |
1286 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1288 tu_cs_reserve(cs
, 3 + 2);
1289 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1290 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1291 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1293 /* if (no overflow) */ {
1294 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1295 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1299 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1301 tu_cs_sanity_check(cs
);
1305 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1307 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1310 A6XX_GRAS_LRZ_CNTL(0));
1312 tu6_emit_lrz_flush(cmd
, cs
);
1314 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
, true);
1316 tu_cs_sanity_check(cs
);
1320 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1322 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1324 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1326 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1327 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1328 struct tu_tile tile
;
1329 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1330 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1334 tu6_tile_render_end(cmd
, &cmd
->cs
);
1338 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1340 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1342 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1344 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1345 cmd
->wait_for_idle
= true;
1347 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1351 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1353 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1354 struct tu_cs sub_cs
;
1357 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1358 if (result
!= VK_SUCCESS
) {
1359 cmd
->record_result
= result
;
1363 /* emit to tile-store sub_cs */
1364 tu6_emit_tile_store(cmd
, &sub_cs
);
1366 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1370 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1371 const VkRect2D
*render_area
)
1373 const struct tu_device
*dev
= cmd
->device
;
1374 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1376 tiling
->render_area
= *render_area
;
1377 tiling
->force_sysmem
= false;
1379 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
);
1380 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1381 tu_tiling_config_update_pipes(tiling
, dev
);
1384 const struct tu_dynamic_state default_dynamic_state
= {
1400 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1406 .stencil_compare_mask
=
1411 .stencil_write_mask
=
1416 .stencil_reference
=
1423 static void UNUSED
/* FINISHME */
1424 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1425 const struct tu_dynamic_state
*src
)
1427 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1428 uint32_t copy_mask
= src
->mask
;
1429 uint32_t dest_mask
= 0;
1431 tu_use_args(cmd_buffer
); /* FINISHME */
1433 /* Make sure to copy the number of viewports/scissors because they can
1434 * only be specified at pipeline creation time.
1436 dest
->viewport
.count
= src
->viewport
.count
;
1437 dest
->scissor
.count
= src
->scissor
.count
;
1438 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1440 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1441 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1442 src
->viewport
.count
* sizeof(VkViewport
))) {
1443 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1444 src
->viewport
.count
);
1445 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1449 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1450 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1451 src
->scissor
.count
* sizeof(VkRect2D
))) {
1452 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1453 src
->scissor
.count
);
1454 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1458 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1459 if (dest
->line_width
!= src
->line_width
) {
1460 dest
->line_width
= src
->line_width
;
1461 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1465 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1466 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1467 sizeof(src
->depth_bias
))) {
1468 dest
->depth_bias
= src
->depth_bias
;
1469 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1473 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1474 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1475 sizeof(src
->blend_constants
))) {
1476 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1477 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1481 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1482 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1483 sizeof(src
->depth_bounds
))) {
1484 dest
->depth_bounds
= src
->depth_bounds
;
1485 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1489 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1490 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1491 sizeof(src
->stencil_compare_mask
))) {
1492 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1493 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1497 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1498 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1499 sizeof(src
->stencil_write_mask
))) {
1500 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1501 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1505 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1506 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1507 sizeof(src
->stencil_reference
))) {
1508 dest
->stencil_reference
= src
->stencil_reference
;
1509 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1513 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1514 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1515 &src
->discard_rectangle
.rectangles
,
1516 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1517 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1518 src
->discard_rectangle
.rectangles
,
1519 src
->discard_rectangle
.count
);
1520 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1526 tu_create_cmd_buffer(struct tu_device
*device
,
1527 struct tu_cmd_pool
*pool
,
1528 VkCommandBufferLevel level
,
1529 VkCommandBuffer
*pCommandBuffer
)
1531 struct tu_cmd_buffer
*cmd_buffer
;
1532 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1533 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1534 if (cmd_buffer
== NULL
)
1535 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1537 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1538 cmd_buffer
->device
= device
;
1539 cmd_buffer
->pool
= pool
;
1540 cmd_buffer
->level
= level
;
1543 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1544 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1547 /* Init the pool_link so we can safely call list_del when we destroy
1548 * the command buffer
1550 list_inithead(&cmd_buffer
->pool_link
);
1551 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1554 tu_bo_list_init(&cmd_buffer
->bo_list
);
1555 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1556 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1557 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1558 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1560 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1562 list_inithead(&cmd_buffer
->upload
.list
);
1564 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1565 if (result
!= VK_SUCCESS
)
1566 goto fail_scratch_bo
;
1568 /* TODO: resize on overflow */
1569 cmd_buffer
->vsc_data_pitch
= device
->vsc_data_pitch
;
1570 cmd_buffer
->vsc_data2_pitch
= device
->vsc_data2_pitch
;
1571 cmd_buffer
->vsc_data
= device
->vsc_data
;
1572 cmd_buffer
->vsc_data2
= device
->vsc_data2
;
1577 list_del(&cmd_buffer
->pool_link
);
1582 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1584 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1586 list_del(&cmd_buffer
->pool_link
);
1588 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1589 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1591 tu_cs_finish(&cmd_buffer
->cs
);
1592 tu_cs_finish(&cmd_buffer
->draw_cs
);
1593 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1594 tu_cs_finish(&cmd_buffer
->sub_cs
);
1596 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1597 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1601 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1603 cmd_buffer
->wait_for_idle
= true;
1605 cmd_buffer
->record_result
= VK_SUCCESS
;
1607 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1608 tu_cs_reset(&cmd_buffer
->cs
);
1609 tu_cs_reset(&cmd_buffer
->draw_cs
);
1610 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1611 tu_cs_reset(&cmd_buffer
->sub_cs
);
1613 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1614 cmd_buffer
->descriptors
[i
].valid
= 0;
1615 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1618 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1620 return cmd_buffer
->record_result
;
1624 tu_AllocateCommandBuffers(VkDevice _device
,
1625 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1626 VkCommandBuffer
*pCommandBuffers
)
1628 TU_FROM_HANDLE(tu_device
, device
, _device
);
1629 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1631 VkResult result
= VK_SUCCESS
;
1634 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1636 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1637 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1638 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1640 list_del(&cmd_buffer
->pool_link
);
1641 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1643 result
= tu_reset_cmd_buffer(cmd_buffer
);
1644 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1645 cmd_buffer
->level
= pAllocateInfo
->level
;
1647 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1649 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1650 &pCommandBuffers
[i
]);
1652 if (result
!= VK_SUCCESS
)
1656 if (result
!= VK_SUCCESS
) {
1657 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1660 /* From the Vulkan 1.0.66 spec:
1662 * "vkAllocateCommandBuffers can be used to create multiple
1663 * command buffers. If the creation of any of those command
1664 * buffers fails, the implementation must destroy all
1665 * successfully created command buffer objects from this
1666 * command, set all entries of the pCommandBuffers array to
1667 * NULL and return the error."
1669 memset(pCommandBuffers
, 0,
1670 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1677 tu_FreeCommandBuffers(VkDevice device
,
1678 VkCommandPool commandPool
,
1679 uint32_t commandBufferCount
,
1680 const VkCommandBuffer
*pCommandBuffers
)
1682 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1683 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1686 if (cmd_buffer
->pool
) {
1687 list_del(&cmd_buffer
->pool_link
);
1688 list_addtail(&cmd_buffer
->pool_link
,
1689 &cmd_buffer
->pool
->free_cmd_buffers
);
1691 tu_cmd_buffer_destroy(cmd_buffer
);
1697 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1698 VkCommandBufferResetFlags flags
)
1700 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1701 return tu_reset_cmd_buffer(cmd_buffer
);
1705 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1706 const VkCommandBufferBeginInfo
*pBeginInfo
)
1708 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1709 VkResult result
= VK_SUCCESS
;
1711 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1712 /* If the command buffer has already been resetted with
1713 * vkResetCommandBuffer, no need to do it again.
1715 result
= tu_reset_cmd_buffer(cmd_buffer
);
1716 if (result
!= VK_SUCCESS
)
1720 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1721 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1723 tu_cs_begin(&cmd_buffer
->cs
);
1724 tu_cs_begin(&cmd_buffer
->draw_cs
);
1725 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1727 cmd_buffer
->scratch_seqno
= 0;
1729 /* setup initial configuration into command buffer */
1730 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1731 switch (cmd_buffer
->queue_family_index
) {
1732 case TU_QUEUE_GENERAL
:
1733 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1738 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1739 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1740 assert(pBeginInfo
->pInheritanceInfo
);
1741 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1742 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1745 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1751 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1752 uint32_t firstBinding
,
1753 uint32_t bindingCount
,
1754 const VkBuffer
*pBuffers
,
1755 const VkDeviceSize
*pOffsets
)
1757 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1759 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1761 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1762 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1763 tu_buffer_from_handle(pBuffers
[i
]);
1764 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1767 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1768 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1772 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1774 VkDeviceSize offset
,
1775 VkIndexType indexType
)
1777 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1778 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1780 /* initialize/update the restart index */
1781 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1782 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1784 tu6_emit_restart_index(
1785 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1787 tu_cs_sanity_check(draw_cs
);
1791 if (cmd
->state
.index_buffer
!= buf
)
1792 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1794 cmd
->state
.index_buffer
= buf
;
1795 cmd
->state
.index_offset
= offset
;
1796 cmd
->state
.index_type
= indexType
;
1800 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1801 VkPipelineBindPoint pipelineBindPoint
,
1802 VkPipelineLayout _layout
,
1804 uint32_t descriptorSetCount
,
1805 const VkDescriptorSet
*pDescriptorSets
,
1806 uint32_t dynamicOffsetCount
,
1807 const uint32_t *pDynamicOffsets
)
1809 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1810 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1811 unsigned dyn_idx
= 0;
1813 struct tu_descriptor_state
*descriptors_state
=
1814 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1816 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1817 unsigned idx
= i
+ firstSet
;
1818 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1820 descriptors_state
->sets
[idx
] = set
;
1821 descriptors_state
->valid
|= (1u << idx
);
1823 /* Note: the actual input attachment indices come from the shader
1824 * itself, so we can't generate the patched versions of these until
1825 * draw time when both the pipeline and descriptors are bound and
1826 * we're inside the render pass.
1828 unsigned dst_idx
= layout
->set
[idx
].input_attachment_start
;
1829 memcpy(&descriptors_state
->input_attachments
[dst_idx
* A6XX_TEX_CONST_DWORDS
],
1830 set
->dynamic_descriptors
,
1831 set
->layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
1833 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1834 /* Dynamic buffers come after input attachments in the descriptor set
1835 * itself, but due to how the Vulkan descriptor set binding works, we
1836 * have to put input attachments and dynamic buffers in separate
1837 * buffers in the descriptor_state and then combine them at draw
1838 * time. Binding a descriptor set only invalidates the descriptor
1839 * sets after it, but if we try to tightly pack the descriptors after
1840 * the input attachments then we could corrupt dynamic buffers in the
1841 * descriptor set before it, or we'd have to move all the dynamic
1842 * buffers over. We just put them into separate buffers to make
1843 * binding as well as the later patching of input attachments easy.
1845 unsigned src_idx
= j
+ set
->layout
->input_attachment_count
;
1846 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1847 assert(dyn_idx
< dynamicOffsetCount
);
1850 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1852 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1853 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1855 /* Patch the storage/uniform descriptors right away. */
1856 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1857 /* Note: we can assume here that the addition won't roll over and
1858 * change the SIZE field.
1860 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1865 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1866 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1867 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1875 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
)
1876 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1878 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1881 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1882 uint32_t firstBinding
,
1883 uint32_t bindingCount
,
1884 const VkBuffer
*pBuffers
,
1885 const VkDeviceSize
*pOffsets
,
1886 const VkDeviceSize
*pSizes
)
1888 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1889 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1891 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1892 uint32_t idx
= firstBinding
+ i
;
1893 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1895 if (pOffsets
[i
] != 0)
1896 cmd
->state
.streamout_reset
|= 1 << idx
;
1898 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1899 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1900 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1902 cmd
->state
.streamout_enabled
|= 1 << idx
;
1905 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1908 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1909 uint32_t firstCounterBuffer
,
1910 uint32_t counterBufferCount
,
1911 const VkBuffer
*pCounterBuffers
,
1912 const VkDeviceSize
*pCounterBufferOffsets
)
1914 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1915 /* TODO do something with counter buffer? */
1918 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1919 uint32_t firstCounterBuffer
,
1920 uint32_t counterBufferCount
,
1921 const VkBuffer
*pCounterBuffers
,
1922 const VkDeviceSize
*pCounterBufferOffsets
)
1924 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1925 /* TODO do something with counter buffer? */
1927 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1928 cmd
->state
.streamout_enabled
= 0;
1932 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1933 VkPipelineLayout layout
,
1934 VkShaderStageFlags stageFlags
,
1937 const void *pValues
)
1939 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1940 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1941 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
1945 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1947 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1949 if (cmd_buffer
->scratch_seqno
) {
1950 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
1951 MSM_SUBMIT_BO_WRITE
);
1954 if (cmd_buffer
->use_vsc_data
) {
1955 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
1956 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1957 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
1958 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1961 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
1962 MSM_SUBMIT_BO_READ
);
1964 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1965 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1966 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1969 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1970 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1971 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1974 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1975 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1976 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1979 tu_cs_end(&cmd_buffer
->cs
);
1980 tu_cs_end(&cmd_buffer
->draw_cs
);
1981 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
1983 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1985 return cmd_buffer
->record_result
;
1989 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
1990 VkPipelineBindPoint pipelineBindPoint
,
1991 VkPipeline _pipeline
)
1993 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1994 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1996 switch (pipelineBindPoint
) {
1997 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
1998 cmd
->state
.pipeline
= pipeline
;
1999 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2001 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2002 cmd
->state
.compute_pipeline
= pipeline
;
2003 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2006 unreachable("unrecognized pipeline bind point");
2010 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2011 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2012 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2013 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2014 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2019 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2020 uint32_t firstViewport
,
2021 uint32_t viewportCount
,
2022 const VkViewport
*pViewports
)
2024 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2026 assert(firstViewport
== 0 && viewportCount
== 1);
2027 cmd
->state
.dynamic
.viewport
.viewports
[0] = pViewports
[0];
2028 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2032 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2033 uint32_t firstScissor
,
2034 uint32_t scissorCount
,
2035 const VkRect2D
*pScissors
)
2037 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2039 assert(firstScissor
== 0 && scissorCount
== 1);
2040 cmd
->state
.dynamic
.scissor
.scissors
[0] = pScissors
[0];
2041 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_SCISSOR
;
2045 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2047 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2049 cmd
->state
.dynamic
.line_width
= lineWidth
;
2051 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2052 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2056 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2057 float depthBiasConstantFactor
,
2058 float depthBiasClamp
,
2059 float depthBiasSlopeFactor
)
2061 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2062 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2064 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2065 depthBiasSlopeFactor
);
2067 tu_cs_sanity_check(draw_cs
);
2071 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2072 const float blendConstants
[4])
2074 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2075 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2077 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2079 tu_cs_sanity_check(draw_cs
);
2083 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2084 float minDepthBounds
,
2085 float maxDepthBounds
)
2090 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2091 VkStencilFaceFlags faceMask
,
2092 uint32_t compareMask
)
2094 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2096 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2097 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2098 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2099 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2101 /* the front/back compare masks must be updated together */
2102 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2106 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2107 VkStencilFaceFlags faceMask
,
2110 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2112 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2113 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2114 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2115 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2117 /* the front/back write masks must be updated together */
2118 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2122 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2123 VkStencilFaceFlags faceMask
,
2126 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2128 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2129 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2130 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2131 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2133 /* the front/back references must be updated together */
2134 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2138 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2139 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2141 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2143 tu6_emit_sample_locations(&cmd
->draw_cs
, pSampleLocationsInfo
);
2147 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2148 uint32_t commandBufferCount
,
2149 const VkCommandBuffer
*pCmdBuffers
)
2151 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2154 assert(commandBufferCount
> 0);
2156 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2157 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2159 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2160 if (result
!= VK_SUCCESS
) {
2161 cmd
->record_result
= result
;
2165 if (secondary
->usage_flags
&
2166 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2167 assert(tu_cs_is_empty(&secondary
->cs
));
2169 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2170 if (result
!= VK_SUCCESS
) {
2171 cmd
->record_result
= result
;
2175 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2176 &secondary
->draw_epilogue_cs
);
2177 if (result
!= VK_SUCCESS
) {
2178 cmd
->record_result
= result
;
2182 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2183 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2185 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2186 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2187 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2190 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2193 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2197 tu_CreateCommandPool(VkDevice _device
,
2198 const VkCommandPoolCreateInfo
*pCreateInfo
,
2199 const VkAllocationCallbacks
*pAllocator
,
2200 VkCommandPool
*pCmdPool
)
2202 TU_FROM_HANDLE(tu_device
, device
, _device
);
2203 struct tu_cmd_pool
*pool
;
2205 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2206 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2208 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2211 pool
->alloc
= *pAllocator
;
2213 pool
->alloc
= device
->alloc
;
2215 list_inithead(&pool
->cmd_buffers
);
2216 list_inithead(&pool
->free_cmd_buffers
);
2218 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2220 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2226 tu_DestroyCommandPool(VkDevice _device
,
2227 VkCommandPool commandPool
,
2228 const VkAllocationCallbacks
*pAllocator
)
2230 TU_FROM_HANDLE(tu_device
, device
, _device
);
2231 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2236 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2237 &pool
->cmd_buffers
, pool_link
)
2239 tu_cmd_buffer_destroy(cmd_buffer
);
2242 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2243 &pool
->free_cmd_buffers
, pool_link
)
2245 tu_cmd_buffer_destroy(cmd_buffer
);
2248 vk_free2(&device
->alloc
, pAllocator
, pool
);
2252 tu_ResetCommandPool(VkDevice device
,
2253 VkCommandPool commandPool
,
2254 VkCommandPoolResetFlags flags
)
2256 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2259 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2262 result
= tu_reset_cmd_buffer(cmd_buffer
);
2263 if (result
!= VK_SUCCESS
)
2271 tu_TrimCommandPool(VkDevice device
,
2272 VkCommandPool commandPool
,
2273 VkCommandPoolTrimFlags flags
)
2275 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2280 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2281 &pool
->free_cmd_buffers
, pool_link
)
2283 tu_cmd_buffer_destroy(cmd_buffer
);
2288 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2289 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2290 VkSubpassContents contents
)
2292 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2293 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2294 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2296 cmd
->state
.pass
= pass
;
2297 cmd
->state
.subpass
= pass
->subpasses
;
2298 cmd
->state
.framebuffer
= fb
;
2300 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2301 tu_cmd_prepare_tile_store_ib(cmd
);
2303 tu_emit_load_clear(cmd
, pRenderPassBegin
);
2305 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2306 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2307 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2308 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2310 /* note: use_hw_binning only checks tiling config */
2311 if (use_hw_binning(cmd
))
2312 cmd
->use_vsc_data
= true;
2314 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2315 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2316 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2317 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2320 /* Flag input attachment descriptors for re-emission if necessary */
2321 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2325 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2326 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2327 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2329 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2330 pSubpassBeginInfo
->contents
);
2334 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2336 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2337 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2338 struct tu_cs
*cs
= &cmd
->draw_cs
;
2340 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2342 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2344 if (subpass
->resolve_attachments
) {
2345 tu6_emit_blit_scissor(cmd
, cs
, true);
2347 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2348 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2349 if (a
== VK_ATTACHMENT_UNUSED
)
2352 tu_store_gmem_attachment(cmd
, cs
, a
,
2353 subpass
->color_attachments
[i
].attachment
);
2355 if (pass
->attachments
[a
].gmem_offset
< 0)
2359 * check if the resolved attachment is needed by later subpasses,
2360 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2362 tu_finishme("missing GMEM->GMEM resolve path\n");
2363 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2367 tu_cond_exec_end(cs
);
2369 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2371 /* Emit flushes so that input attachments will read the correct value.
2372 * TODO: use subpass dependencies to flush or not
2374 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2375 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
2377 if (subpass
->resolve_attachments
) {
2378 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2380 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2381 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2382 if (a
== VK_ATTACHMENT_UNUSED
)
2385 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
2386 subpass
->color_attachments
[i
].attachment
);
2389 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2392 tu_cond_exec_end(cs
);
2394 /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2395 if (cmd
->state
.subpass
->input_count
)
2396 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2398 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2399 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2400 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2401 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2402 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2404 /* Flag input attachment descriptors for re-emission if necessary */
2405 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2409 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2410 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2411 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2413 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2419 * Number of vertices.
2424 * Index of the first vertex.
2426 int32_t vertex_offset
;
2429 * First instance id.
2431 uint32_t first_instance
;
2434 * Number of instances.
2436 uint32_t instance_count
;
2439 * First index (indexed draws only).
2441 uint32_t first_index
;
2444 * Whether it's an indexed draw.
2449 * Indirect draw parameters resource.
2451 struct tu_buffer
*indirect
;
2452 uint64_t indirect_offset
;
2456 * Draw count parameters resource.
2458 struct tu_buffer
*count_buffer
;
2459 uint64_t count_buffer_offset
;
2462 * Stream output parameters resource.
2464 struct tu_buffer
*streamout_buffer
;
2465 uint64_t streamout_buffer_offset
;
2468 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2469 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2470 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2472 enum tu_draw_state_group_id
2474 TU_DRAW_STATE_PROGRAM
,
2475 TU_DRAW_STATE_PROGRAM_BINNING
,
2477 TU_DRAW_STATE_VI_BINNING
,
2481 TU_DRAW_STATE_BLEND
,
2482 TU_DRAW_STATE_VS_CONST
,
2483 TU_DRAW_STATE_GS_CONST
,
2484 TU_DRAW_STATE_FS_CONST
,
2485 TU_DRAW_STATE_DESC_SETS
,
2486 TU_DRAW_STATE_DESC_SETS_GMEM
,
2487 TU_DRAW_STATE_DESC_SETS_LOAD
,
2488 TU_DRAW_STATE_VS_PARAMS
,
2490 TU_DRAW_STATE_COUNT
,
2493 struct tu_draw_state_group
2495 enum tu_draw_state_group_id id
;
2496 uint32_t enable_mask
;
2497 struct tu_cs_entry ib
;
2500 static inline uint32_t
2501 tu6_stage2opcode(gl_shader_stage type
)
2504 case MESA_SHADER_VERTEX
:
2505 case MESA_SHADER_TESS_CTRL
:
2506 case MESA_SHADER_TESS_EVAL
:
2507 case MESA_SHADER_GEOMETRY
:
2508 return CP_LOAD_STATE6_GEOM
;
2509 case MESA_SHADER_FRAGMENT
:
2510 case MESA_SHADER_COMPUTE
:
2511 case MESA_SHADER_KERNEL
:
2512 return CP_LOAD_STATE6_FRAG
;
2514 unreachable("bad shader type");
2518 static inline enum a6xx_state_block
2519 tu6_stage2shadersb(gl_shader_stage type
)
2522 case MESA_SHADER_VERTEX
:
2523 return SB6_VS_SHADER
;
2524 case MESA_SHADER_GEOMETRY
:
2525 return SB6_GS_SHADER
;
2526 case MESA_SHADER_FRAGMENT
:
2527 return SB6_FS_SHADER
;
2528 case MESA_SHADER_COMPUTE
:
2529 case MESA_SHADER_KERNEL
:
2530 return SB6_CS_SHADER
;
2532 unreachable("bad shader type");
2538 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2539 struct tu_descriptor_state
*descriptors_state
,
2540 gl_shader_stage type
,
2541 uint32_t *push_constants
)
2543 const struct tu_program_descriptor_linkage
*link
=
2544 &pipeline
->program
.link
[type
];
2545 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2547 if (link
->push_consts
.count
> 0) {
2548 unsigned num_units
= link
->push_consts
.count
;
2549 unsigned offset
= link
->push_consts
.lo
;
2550 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2551 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2552 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2553 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2554 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2555 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2558 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2559 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2562 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2563 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2564 uint32_t offset
= state
->range
[i
].start
;
2566 /* and even if the start of the const buffer is before
2567 * first_immediate, the end may not be:
2569 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2574 /* things should be aligned to vec4: */
2575 debug_assert((state
->range
[i
].offset
% 16) == 0);
2576 debug_assert((size
% 16) == 0);
2577 debug_assert((offset
% 16) == 0);
2579 /* Dig out the descriptor from the descriptor state and read the VA from
2582 assert(state
->range
[i
].bindless
);
2583 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2584 descriptors_state
->dynamic_descriptors
:
2585 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2586 unsigned block
= state
->range
[i
].block
;
2587 /* If the block in the shader here is in the dynamic descriptor set, it
2588 * is an index into the dynamic descriptor set which is combined from
2589 * dynamic descriptors and input attachments on-the-fly, and we don't
2590 * have access to it here. Instead we work backwards to get the index
2591 * into dynamic_descriptors.
2593 if (state
->range
[i
].bindless_base
== MAX_SETS
)
2594 block
-= pipeline
->layout
->input_attachment_count
;
2595 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2596 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2599 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2600 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2601 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2602 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2603 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2604 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2605 tu_cs_emit_qw(cs
, va
+ offset
);
2609 static struct tu_cs_entry
2610 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2611 const struct tu_pipeline
*pipeline
,
2612 struct tu_descriptor_state
*descriptors_state
,
2613 gl_shader_stage type
)
2616 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2618 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2620 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2624 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2625 const struct tu_draw_info
*draw
,
2626 struct tu_cs_entry
*entry
)
2628 /* TODO: fill out more than just base instance */
2629 const struct tu_program_descriptor_linkage
*link
=
2630 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2631 const struct ir3_const_state
*const_state
= &link
->const_state
;
2634 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2635 *entry
= (struct tu_cs_entry
) {};
2639 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2640 if (result
!= VK_SUCCESS
)
2643 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2644 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2645 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2646 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2647 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2648 CP_LOAD_STATE6_0_NUM_UNIT(1));
2652 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2656 tu_cs_emit(&cs
, draw
->first_instance
);
2659 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2664 tu6_emit_descriptor_sets(struct tu_cmd_buffer
*cmd
,
2665 const struct tu_pipeline
*pipeline
,
2666 VkPipelineBindPoint bind_point
,
2667 struct tu_cs_entry
*entry
,
2670 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2671 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
2672 struct tu_descriptor_state
*descriptors_state
=
2673 tu_get_descriptors_state(cmd
, bind_point
);
2674 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2675 const uint32_t *input_attachment_idx
=
2676 pipeline
->program
.input_attachment_idx
;
2677 uint32_t num_dynamic_descs
= layout
->dynamic_offset_count
+
2678 layout
->input_attachment_count
;
2679 struct ts_cs_memory dynamic_desc_set
;
2682 if (num_dynamic_descs
> 0) {
2683 /* allocate and fill out dynamic descriptor set */
2684 result
= tu_cs_alloc(draw_state
, num_dynamic_descs
,
2685 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
2686 if (result
!= VK_SUCCESS
)
2689 memcpy(dynamic_desc_set
.map
, descriptors_state
->input_attachments
,
2690 layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
2693 /* Patch input attachments to refer to GMEM instead */
2694 for (unsigned i
= 0; i
< layout
->input_attachment_count
; i
++) {
2696 &dynamic_desc_set
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2698 /* The compiler has already laid out input_attachment_idx in the
2699 * final order of input attachments, so there's no need to go
2700 * through the pipeline layout finding input attachments.
2702 unsigned attachment_idx
= input_attachment_idx
[i
];
2704 /* It's possible for the pipeline layout to include an input
2705 * attachment which doesn't actually exist for the current
2706 * subpass. Of course, this is only valid so long as the pipeline
2707 * doesn't try to actually load that attachment. Just skip
2708 * patching in that scenario to avoid out-of-bounds accesses.
2710 if (attachment_idx
>= cmd
->state
.subpass
->input_count
)
2713 uint32_t a
= cmd
->state
.subpass
->input_attachments
[attachment_idx
].attachment
;
2714 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2716 assert(att
->gmem_offset
>= 0);
2718 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2719 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2720 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2722 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2723 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2725 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
2726 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2727 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2730 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2731 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2735 memcpy(dynamic_desc_set
.map
+ layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
,
2736 descriptors_state
->dynamic_descriptors
,
2737 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
2740 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
;
2741 uint32_t hlsq_update_value
;
2742 switch (bind_point
) {
2743 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2744 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
2745 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
2746 hlsq_update_value
= 0x7c000;
2748 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2749 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2750 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2751 hlsq_update_value
= 0x3e00;
2754 unreachable("bad bind point");
2757 /* Be careful here to *not* refer to the pipeline, so that if only the
2758 * pipeline changes we don't have to emit this again (except if there are
2759 * dynamic descriptors in the pipeline layout). This means always emitting
2760 * all the valid descriptors, which means that we always have to put the
2761 * dynamic descriptor in the driver-only slot at the end
2763 uint32_t num_user_sets
= util_last_bit(descriptors_state
->valid
);
2764 uint32_t num_sets
= num_user_sets
;
2765 if (num_dynamic_descs
> 0) {
2766 num_user_sets
= MAX_SETS
;
2767 num_sets
= num_user_sets
+ 1;
2770 unsigned regs
[2] = { sp_bindless_base_reg
, hlsq_bindless_base_reg
};
2773 result
= tu_cs_begin_sub_stream(draw_state
, ARRAY_SIZE(regs
) * (1 + num_sets
* 2) + 2, &cs
);
2774 if (result
!= VK_SUCCESS
)
2778 for (unsigned i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
2779 tu_cs_emit_pkt4(&cs
, regs
[i
], num_sets
* 2);
2780 for (unsigned j
= 0; j
< num_user_sets
; j
++) {
2781 if (descriptors_state
->valid
& (1 << j
)) {
2782 /* magic | 3 copied from the blob */
2783 tu_cs_emit_qw(&cs
, descriptors_state
->sets
[j
]->va
| 3);
2785 tu_cs_emit_qw(&cs
, 0 | 3);
2788 if (num_dynamic_descs
> 0) {
2789 tu_cs_emit_qw(&cs
, dynamic_desc_set
.iova
| 3);
2793 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value
));
2796 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2801 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2803 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2805 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2806 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2811 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2813 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2814 .bo_offset
= buf
->bo_offset
));
2815 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2817 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2818 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2819 cmd
->state
.streamout_reset
&= ~(1 << i
);
2821 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2822 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2823 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2824 CP_MEM_TO_REG_0_CNT(0));
2825 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2826 ctrl_offset(flush_base
[i
].offset
));
2829 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
2831 ctrl_offset(flush_base
[i
])));
2834 if (cmd
->state
.streamout_enabled
) {
2835 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
2836 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2837 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
2838 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
2839 tu_cs_emit(cs
, tf
->ncomp
[0]);
2840 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
2841 tu_cs_emit(cs
, tf
->ncomp
[1]);
2842 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
2843 tu_cs_emit(cs
, tf
->ncomp
[2]);
2844 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
2845 tu_cs_emit(cs
, tf
->ncomp
[3]);
2846 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2847 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
2848 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
2849 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
2850 tu_cs_emit(cs
, tf
->prog
[i
]);
2853 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
2854 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2856 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2862 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2864 const struct tu_draw_info
*draw
)
2866 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2867 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2868 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2869 uint32_t draw_state_group_count
= 0;
2872 struct tu_descriptor_state
*descriptors_state
=
2873 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2878 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
2879 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
2881 if (cmd
->state
.dirty
&
2882 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2883 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2884 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2885 dynamic
->line_width
);
2888 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2889 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2890 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2891 dynamic
->stencil_compare_mask
.back
);
2894 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2895 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2896 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2897 dynamic
->stencil_write_mask
.back
);
2900 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2901 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2902 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2903 dynamic
->stencil_reference
.back
);
2906 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2907 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2908 tu6_emit_viewport(cs
, &cmd
->state
.dynamic
.viewport
.viewports
[0]);
2911 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_SCISSOR
) &&
2912 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2913 tu6_emit_scissor(cs
, &cmd
->state
.dynamic
.scissor
.scissors
[0]);
2916 if (cmd
->state
.dirty
&
2917 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
2918 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
2919 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
2920 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2921 const VkDeviceSize offset
= buf
->bo_offset
+
2922 cmd
->state
.vb
.offsets
[binding
];
2923 const VkDeviceSize size
=
2924 offset
< buf
->size
? buf
->size
- offset
: 0;
2927 A6XX_VFD_FETCH_BASE(i
, .bo
= buf
->bo
, .bo_offset
= offset
),
2928 A6XX_VFD_FETCH_SIZE(i
, size
));
2932 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2933 draw_state_groups
[draw_state_group_count
++] =
2934 (struct tu_draw_state_group
) {
2935 .id
= TU_DRAW_STATE_PROGRAM
,
2936 .enable_mask
= ENABLE_DRAW
,
2937 .ib
= pipeline
->program
.state_ib
,
2939 draw_state_groups
[draw_state_group_count
++] =
2940 (struct tu_draw_state_group
) {
2941 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2942 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2943 .ib
= pipeline
->program
.binning_state_ib
,
2945 draw_state_groups
[draw_state_group_count
++] =
2946 (struct tu_draw_state_group
) {
2947 .id
= TU_DRAW_STATE_VI
,
2948 .enable_mask
= ENABLE_DRAW
,
2949 .ib
= pipeline
->vi
.state_ib
,
2951 draw_state_groups
[draw_state_group_count
++] =
2952 (struct tu_draw_state_group
) {
2953 .id
= TU_DRAW_STATE_VI_BINNING
,
2954 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2955 .ib
= pipeline
->vi
.binning_state_ib
,
2957 draw_state_groups
[draw_state_group_count
++] =
2958 (struct tu_draw_state_group
) {
2959 .id
= TU_DRAW_STATE_VP
,
2960 .enable_mask
= ENABLE_ALL
,
2961 .ib
= pipeline
->vp
.state_ib
,
2963 draw_state_groups
[draw_state_group_count
++] =
2964 (struct tu_draw_state_group
) {
2965 .id
= TU_DRAW_STATE_RAST
,
2966 .enable_mask
= ENABLE_ALL
,
2967 .ib
= pipeline
->rast
.state_ib
,
2969 draw_state_groups
[draw_state_group_count
++] =
2970 (struct tu_draw_state_group
) {
2971 .id
= TU_DRAW_STATE_DS
,
2972 .enable_mask
= ENABLE_ALL
,
2973 .ib
= pipeline
->ds
.state_ib
,
2975 draw_state_groups
[draw_state_group_count
++] =
2976 (struct tu_draw_state_group
) {
2977 .id
= TU_DRAW_STATE_BLEND
,
2978 .enable_mask
= ENABLE_ALL
,
2979 .ib
= pipeline
->blend
.state_ib
,
2983 if (cmd
->state
.dirty
&
2984 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
2985 draw_state_groups
[draw_state_group_count
++] =
2986 (struct tu_draw_state_group
) {
2987 .id
= TU_DRAW_STATE_VS_CONST
,
2988 .enable_mask
= ENABLE_ALL
,
2989 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
2991 draw_state_groups
[draw_state_group_count
++] =
2992 (struct tu_draw_state_group
) {
2993 .id
= TU_DRAW_STATE_GS_CONST
,
2994 .enable_mask
= ENABLE_ALL
,
2995 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
)
2997 draw_state_groups
[draw_state_group_count
++] =
2998 (struct tu_draw_state_group
) {
2999 .id
= TU_DRAW_STATE_FS_CONST
,
3000 .enable_mask
= ENABLE_DRAW
,
3001 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3005 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3006 tu6_emit_streamout(cmd
, cs
);
3008 /* If there are any any dynamic descriptors, then we may need to re-emit
3009 * them after every pipeline change in case the number of input attachments
3010 * changes. We also always need to re-emit after a pipeline change if there
3011 * are any input attachments, because the input attachment index comes from
3012 * the pipeline. Finally, it can also happen that the subpass changes
3013 * without the pipeline changing, in which case the GMEM descriptors need
3014 * to be patched differently.
3016 * TODO: We could probably be clever and avoid re-emitting state on
3017 * pipeline changes if the number of input attachments is always 0. We
3018 * could also only re-emit dynamic state.
3020 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
||
3021 ((pipeline
->layout
->dynamic_offset_count
+
3022 pipeline
->layout
->input_attachment_count
> 0) &&
3023 cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) ||
3024 (pipeline
->layout
->input_attachment_count
> 0 &&
3025 cmd
->state
.dirty
& TU_CMD_DIRTY_INPUT_ATTACHMENTS
)) {
3026 struct tu_cs_entry desc_sets
, desc_sets_gmem
;
3027 bool need_gmem_desc_set
= pipeline
->layout
->input_attachment_count
> 0;
3029 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3030 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3032 if (result
!= VK_SUCCESS
)
3035 draw_state_groups
[draw_state_group_count
++] =
3036 (struct tu_draw_state_group
) {
3037 .id
= TU_DRAW_STATE_DESC_SETS
,
3038 .enable_mask
= need_gmem_desc_set
? ENABLE_NON_GMEM
: ENABLE_ALL
,
3042 if (need_gmem_desc_set
) {
3043 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3044 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3045 &desc_sets_gmem
, true);
3046 if (result
!= VK_SUCCESS
)
3049 draw_state_groups
[draw_state_group_count
++] =
3050 (struct tu_draw_state_group
) {
3051 .id
= TU_DRAW_STATE_DESC_SETS_GMEM
,
3052 .enable_mask
= CP_SET_DRAW_STATE__0_GMEM
,
3053 .ib
= desc_sets_gmem
,
3057 /* We need to reload the descriptors every time the descriptor sets
3058 * change. However, the commands we send only depend on the pipeline
3059 * because the whole point is to cache descriptors which are used by the
3060 * pipeline. There's a problem here, in that the firmware has an
3061 * "optimization" which skips executing groups that are set to the same
3062 * value as the last draw. This means that if the descriptor sets change
3063 * but not the pipeline, we'd try to re-execute the same buffer which
3064 * the firmware would ignore and we wouldn't pre-load the new
3065 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3066 * the descriptor sets change, which we emulate here by copying the
3067 * pre-prepared buffer.
3069 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3070 if (load_entry
->size
> 0) {
3071 struct tu_cs load_cs
;
3072 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3073 if (result
!= VK_SUCCESS
)
3075 tu_cs_emit_array(&load_cs
,
3076 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3077 load_entry
->size
/ 4);
3078 struct tu_cs_entry load_copy
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3080 draw_state_groups
[draw_state_group_count
++] =
3081 (struct tu_draw_state_group
) {
3082 .id
= TU_DRAW_STATE_DESC_SETS_LOAD
,
3083 /* The blob seems to not enable this for binning, even when
3084 * resources would actually be used in the binning shader.
3085 * Presumably the overhead of prefetching the resources isn't
3088 .enable_mask
= ENABLE_DRAW
,
3094 struct tu_cs_entry vs_params
;
3095 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3096 if (result
!= VK_SUCCESS
)
3099 draw_state_groups
[draw_state_group_count
++] =
3100 (struct tu_draw_state_group
) {
3101 .id
= TU_DRAW_STATE_VS_PARAMS
,
3102 .enable_mask
= ENABLE_ALL
,
3106 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3107 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3108 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3109 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3110 uint32_t cp_set_draw_state
=
3111 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3112 group
->enable_mask
|
3113 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3115 if (group
->ib
.size
) {
3116 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3118 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3122 tu_cs_emit(cs
, cp_set_draw_state
);
3123 tu_cs_emit_qw(cs
, iova
);
3126 tu_cs_sanity_check(cs
);
3129 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3130 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3131 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3133 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3136 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3138 for_each_bit(i
, descriptors_state
->valid
) {
3139 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3140 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3141 if (set
->buffers
[j
]) {
3142 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3143 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3146 if (set
->size
> 0) {
3147 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3148 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3152 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3153 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3154 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3156 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3157 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3162 /* There are too many graphics dirty bits to list here, so just list the
3163 * bits to preserve instead. The only things not emitted here are
3164 * compute-related state.
3166 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
3168 /* Fragment shader state overwrites compute shader state, so flag the
3169 * compute pipeline for re-emit.
3171 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3176 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3178 const struct tu_draw_info
*draw
)
3180 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3181 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3182 VK_SHADER_STAGE_GEOMETRY_BIT
;
3185 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3186 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3188 if (draw
->indexed
) {
3189 const enum a4xx_index_size index_size
=
3190 tu6_index_size(cmd
->state
.index_type
);
3191 const uint32_t index_bytes
=
3192 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3193 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3194 unsigned max_indicies
=
3195 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3197 const uint32_t cp_draw_indx
=
3198 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3199 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3200 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3201 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3202 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3204 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3205 tu_cs_emit(cs
, cp_draw_indx
);
3206 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3207 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3208 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3210 const uint32_t cp_draw_indx
=
3211 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3212 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3213 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3214 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3216 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3217 tu_cs_emit(cs
, cp_draw_indx
);
3218 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3221 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3225 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3227 const struct tu_draw_info
*draw
)
3230 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3231 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3232 VK_SHADER_STAGE_GEOMETRY_BIT
;
3235 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3236 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3238 /* TODO hw binning */
3239 if (draw
->indexed
) {
3240 const enum a4xx_index_size index_size
=
3241 tu6_index_size(cmd
->state
.index_type
);
3242 const uint32_t index_bytes
=
3243 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3244 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3245 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3246 index_bytes
* draw
->first_index
;
3247 const uint32_t size
= index_bytes
* draw
->count
;
3249 const uint32_t cp_draw_indx
=
3250 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3251 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3252 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3253 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3254 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3256 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3257 tu_cs_emit(cs
, cp_draw_indx
);
3258 tu_cs_emit(cs
, draw
->instance_count
);
3259 tu_cs_emit(cs
, draw
->count
);
3260 tu_cs_emit(cs
, 0x0); /* XXX */
3261 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3262 tu_cs_emit(cs
, size
);
3264 const uint32_t cp_draw_indx
=
3265 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3266 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3267 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3268 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3270 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3271 tu_cs_emit(cs
, cp_draw_indx
);
3272 tu_cs_emit(cs
, draw
->instance_count
);
3273 tu_cs_emit(cs
, draw
->count
);
3278 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3280 struct tu_cs
*cs
= &cmd
->draw_cs
;
3283 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3284 if (result
!= VK_SUCCESS
) {
3285 cmd
->record_result
= result
;
3290 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3292 tu6_emit_draw_direct(cmd
, cs
, draw
);
3294 if (cmd
->state
.streamout_enabled
) {
3295 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3296 if (cmd
->state
.streamout_enabled
& (1 << i
))
3297 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
, false);
3301 cmd
->wait_for_idle
= true;
3303 tu_cs_sanity_check(cs
);
3307 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3308 uint32_t vertexCount
,
3309 uint32_t instanceCount
,
3310 uint32_t firstVertex
,
3311 uint32_t firstInstance
)
3313 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3314 struct tu_draw_info info
= {};
3316 info
.count
= vertexCount
;
3317 info
.instance_count
= instanceCount
;
3318 info
.first_instance
= firstInstance
;
3319 info
.vertex_offset
= firstVertex
;
3321 tu_draw(cmd_buffer
, &info
);
3325 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3326 uint32_t indexCount
,
3327 uint32_t instanceCount
,
3328 uint32_t firstIndex
,
3329 int32_t vertexOffset
,
3330 uint32_t firstInstance
)
3332 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3333 struct tu_draw_info info
= {};
3335 info
.indexed
= true;
3336 info
.count
= indexCount
;
3337 info
.instance_count
= instanceCount
;
3338 info
.first_index
= firstIndex
;
3339 info
.vertex_offset
= vertexOffset
;
3340 info
.first_instance
= firstInstance
;
3342 tu_draw(cmd_buffer
, &info
);
3346 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3348 VkDeviceSize offset
,
3352 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3353 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3354 struct tu_draw_info info
= {};
3356 info
.count
= drawCount
;
3357 info
.indirect
= buffer
;
3358 info
.indirect_offset
= offset
;
3359 info
.stride
= stride
;
3361 tu_draw(cmd_buffer
, &info
);
3365 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3367 VkDeviceSize offset
,
3371 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3372 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3373 struct tu_draw_info info
= {};
3375 info
.indexed
= true;
3376 info
.count
= drawCount
;
3377 info
.indirect
= buffer
;
3378 info
.indirect_offset
= offset
;
3379 info
.stride
= stride
;
3381 tu_draw(cmd_buffer
, &info
);
3384 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3385 uint32_t instanceCount
,
3386 uint32_t firstInstance
,
3387 VkBuffer _counterBuffer
,
3388 VkDeviceSize counterBufferOffset
,
3389 uint32_t counterOffset
,
3390 uint32_t vertexStride
)
3392 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3393 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3395 struct tu_draw_info info
= {};
3397 info
.instance_count
= instanceCount
;
3398 info
.first_instance
= firstInstance
;
3399 info
.streamout_buffer
= buffer
;
3400 info
.streamout_buffer_offset
= counterBufferOffset
;
3401 info
.stride
= vertexStride
;
3403 tu_draw(cmd_buffer
, &info
);
3406 struct tu_dispatch_info
3409 * Determine the layout of the grid (in block units) to be used.
3414 * A starting offset for the grid. If unaligned is set, the offset
3415 * must still be aligned.
3417 uint32_t offsets
[3];
3419 * Whether it's an unaligned compute dispatch.
3424 * Indirect compute parameters resource.
3426 struct tu_buffer
*indirect
;
3427 uint64_t indirect_offset
;
3431 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3432 const struct tu_dispatch_info
*info
)
3434 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3435 const struct tu_program_descriptor_linkage
*link
=
3436 &pipeline
->program
.link
[type
];
3437 const struct ir3_const_state
*const_state
= &link
->const_state
;
3438 uint32_t offset
= const_state
->offsets
.driver_param
;
3440 if (link
->constlen
<= offset
)
3443 if (!info
->indirect
) {
3444 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3445 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3446 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3447 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3448 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3449 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3450 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3453 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3454 (link
->constlen
- offset
) * 4);
3455 /* push constants */
3456 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3457 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3458 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3459 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3460 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3461 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3465 for (i
= 0; i
< num_consts
; i
++)
3466 tu_cs_emit(cs
, driver_params
[i
]);
3468 tu_finishme("Indirect driver params");
3473 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3474 const struct tu_dispatch_info
*info
)
3476 struct tu_cs
*cs
= &cmd
->cs
;
3477 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3478 struct tu_descriptor_state
*descriptors_state
=
3479 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3482 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3483 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3485 struct tu_cs_entry ib
;
3487 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3489 tu_cs_emit_ib(cs
, &ib
);
3491 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3493 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) {
3494 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3495 VK_PIPELINE_BIND_POINT_COMPUTE
, &ib
,
3497 if (result
!= VK_SUCCESS
) {
3498 cmd
->record_result
= result
;
3504 for_each_bit(i
, descriptors_state
->valid
) {
3505 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3506 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3507 if (set
->buffers
[j
]) {
3508 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3509 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3513 if (set
->size
> 0) {
3514 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3515 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3521 tu_cs_emit_ib(cs
, &ib
);
3523 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
)
3524 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3527 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3529 /* Compute shader state overwrites fragment shader state, so we flag the
3530 * graphics pipeline for re-emit.
3532 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
3534 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3535 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3537 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3538 const uint32_t *num_groups
= info
->blocks
;
3540 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3541 .localsizex
= local_size
[0] - 1,
3542 .localsizey
= local_size
[1] - 1,
3543 .localsizez
= local_size
[2] - 1),
3544 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3545 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3546 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3547 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3548 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3549 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3552 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3553 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3554 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3556 if (info
->indirect
) {
3557 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3559 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3560 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3562 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3563 tu_cs_emit(cs
, 0x00000000);
3564 tu_cs_emit_qw(cs
, iova
);
3566 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3567 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3568 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3570 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3571 tu_cs_emit(cs
, 0x00000000);
3572 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3573 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3574 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3579 tu6_emit_cache_flush(cmd
, cs
);
3583 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3591 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3592 struct tu_dispatch_info info
= {};
3598 info
.offsets
[0] = base_x
;
3599 info
.offsets
[1] = base_y
;
3600 info
.offsets
[2] = base_z
;
3601 tu_dispatch(cmd_buffer
, &info
);
3605 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3610 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3614 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3616 VkDeviceSize offset
)
3618 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3619 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3620 struct tu_dispatch_info info
= {};
3622 info
.indirect
= buffer
;
3623 info
.indirect_offset
= offset
;
3625 tu_dispatch(cmd_buffer
, &info
);
3629 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3631 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3633 tu_cs_end(&cmd_buffer
->draw_cs
);
3634 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3636 if (use_sysmem_rendering(cmd_buffer
))
3637 tu_cmd_render_sysmem(cmd_buffer
);
3639 tu_cmd_render_tiles(cmd_buffer
);
3641 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3643 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3644 tu_cs_begin(&cmd_buffer
->draw_cs
);
3645 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3646 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3648 cmd_buffer
->state
.pass
= NULL
;
3649 cmd_buffer
->state
.subpass
= NULL
;
3650 cmd_buffer
->state
.framebuffer
= NULL
;
3654 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3655 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3657 tu_CmdEndRenderPass(commandBuffer
);
3660 struct tu_barrier_info
3662 uint32_t eventCount
;
3663 const VkEvent
*pEvents
;
3664 VkPipelineStageFlags srcStageMask
;
3668 tu_barrier(struct tu_cmd_buffer
*cmd
,
3669 uint32_t memoryBarrierCount
,
3670 const VkMemoryBarrier
*pMemoryBarriers
,
3671 uint32_t bufferMemoryBarrierCount
,
3672 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3673 uint32_t imageMemoryBarrierCount
,
3674 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3675 const struct tu_barrier_info
*info
)
3677 /* renderpass case is only for subpass self-dependencies
3678 * which means syncing the render output with texture cache
3679 * note: only the CACHE_INVALIDATE is needed in GMEM mode
3680 * and in sysmem mode we might not need either color/depth flush
3682 if (cmd
->state
.pass
) {
3683 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_COLOR_TS
, true);
3684 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
3685 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, CACHE_INVALIDATE
, false);
3691 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3692 VkPipelineStageFlags srcStageMask
,
3693 VkPipelineStageFlags dstStageMask
,
3694 VkDependencyFlags dependencyFlags
,
3695 uint32_t memoryBarrierCount
,
3696 const VkMemoryBarrier
*pMemoryBarriers
,
3697 uint32_t bufferMemoryBarrierCount
,
3698 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3699 uint32_t imageMemoryBarrierCount
,
3700 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3702 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3703 struct tu_barrier_info info
;
3705 info
.eventCount
= 0;
3706 info
.pEvents
= NULL
;
3707 info
.srcStageMask
= srcStageMask
;
3709 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3710 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3711 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3715 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
, unsigned value
)
3717 struct tu_cs
*cs
= &cmd
->cs
;
3719 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3721 /* TODO: any flush required before/after ? */
3723 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3724 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3725 tu_cs_emit(cs
, value
);
3729 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3731 VkPipelineStageFlags stageMask
)
3733 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3734 TU_FROM_HANDLE(tu_event
, event
, _event
);
3736 write_event(cmd
, event
, 1);
3740 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3742 VkPipelineStageFlags stageMask
)
3744 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3745 TU_FROM_HANDLE(tu_event
, event
, _event
);
3747 write_event(cmd
, event
, 0);
3751 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3752 uint32_t eventCount
,
3753 const VkEvent
*pEvents
,
3754 VkPipelineStageFlags srcStageMask
,
3755 VkPipelineStageFlags dstStageMask
,
3756 uint32_t memoryBarrierCount
,
3757 const VkMemoryBarrier
*pMemoryBarriers
,
3758 uint32_t bufferMemoryBarrierCount
,
3759 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3760 uint32_t imageMemoryBarrierCount
,
3761 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3763 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3764 struct tu_cs
*cs
= &cmd
->cs
;
3766 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3768 for (uint32_t i
= 0; i
< eventCount
; i
++) {
3769 TU_FROM_HANDLE(tu_event
, event
, pEvents
[i
]);
3771 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3773 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3774 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3775 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3776 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3777 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3778 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3779 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3784 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)