src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36 #include "tu_blit.h"
  37
  38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  39
  40 void
  41 tu_bo_list_init(struct tu_bo_list *list)
  42 {
  43    list->count = list->capacity = 0;
  44    list->bo_infos = NULL;
  45 }
  46
  47 void
  48 tu_bo_list_destroy(struct tu_bo_list *list)
  49 {
  50    free(list->bo_infos);
  51 }
  52
  53 void
  54 tu_bo_list_reset(struct tu_bo_list *list)
  55 {
  56    list->count = 0;
  57 }
  58
  59 /**
  60  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  61  */
  62 static uint32_t
  63 tu_bo_list_add_info(struct tu_bo_list *list,
  64                     const struct drm_msm_gem_submit_bo *bo_info)
  65 {
  66    assert(bo_info->handle != 0);
  67
  68    for (uint32_t i = 0; i < list->count; ++i) {
  69       if (list->bo_infos[i].handle == bo_info->handle) {
  70          assert(list->bo_infos[i].presumed == bo_info->presumed);
  71          list->bo_infos[i].flags |= bo_info->flags;
  72          return i;
  73       }
  74    }
  75
  76    /* grow list->bo_infos if needed */
  77    if (list->count == list->capacity) {
  78       uint32_t new_capacity = MAX2(2 * list->count, 16);
  79       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  80          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  81       if (!new_bo_infos)
  82          return TU_BO_LIST_FAILED;
  83       list->bo_infos = new_bo_infos;
  84       list->capacity = new_capacity;
  85    }
  86
  87    list->bo_infos[list->count] = *bo_info;
  88    return list->count++;
  89 }
  90
  91 uint32_t
  92 tu_bo_list_add(struct tu_bo_list *list,
  93                const struct tu_bo *bo,
  94                uint32_t flags)
  95 {
  96    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  97                                        .flags = flags,
  98                                        .handle = bo->gem_handle,
  99                                        .presumed = bo->iova,
 100                                     });
 101 }
 102
 103 VkResult
 104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 105 {
 106    for (uint32_t i = 0; i < other->count; i++) {
 107       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 108          return VK_ERROR_OUT_OF_HOST_MEMORY;
 109    }
 110
 111    return VK_SUCCESS;
 112 }
 113
 114 static bool
 115 is_linear_mipmapped(const struct tu_image_view *iview)
 116 {
 117    return iview->image->layout.tile_mode == TILE6_LINEAR &&
 118           iview->base_mip != iview->image->level_count - 1;
 119 }
 120
 121 static bool
 122 force_sysmem(const struct tu_cmd_buffer *cmd,
 123              const struct VkRect2D *render_area)
 124 {
 125    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 126    const struct tu_physical_device *device = cmd->device->physical_device;
 127    bool has_linear_mipmapped_store = false;
 128    const struct tu_render_pass *pass = cmd->state.pass;
 129
 130    /* Iterate over all the places we call tu6_emit_store_attachment() */
 131    for (unsigned i = 0; i < pass->subpass_count; i++) {
 132       const struct tu_subpass *subpass = &pass->subpasses[i];
 133       if (subpass->resolve_attachments) {
 134          for (unsigned i = 0; i < subpass->color_count; i++) {
 135             uint32_t a = subpass->resolve_attachments[i].attachment;
 136             if (a != VK_ATTACHMENT_UNUSED &&
 137                 cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 138                const struct tu_image_view *iview = fb->attachments[a].attachment;
 139                if (is_linear_mipmapped(iview)) {
 140                   has_linear_mipmapped_store = true;
 141                   break;
 142                }
 143             }
 144          }
 145       }
 146    }
 147
 148    for (unsigned i = 0; i < pass->attachment_count; i++) {
 149       if (pass->attachments[i].gmem_offset >= 0 &&
 150           cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 151          const struct tu_image_view *iview = fb->attachments[i].attachment;
 152          if (is_linear_mipmapped(iview)) {
 153             has_linear_mipmapped_store = true;
 154             break;
 155          }
 156       }
 157    }
 158
 159    /* Linear textures cannot have any padding between mipmap levels and their
 160     * height isn't padded, while at the same time the GMEM->MEM resolve does
 161     * not have per-pixel granularity, so if the image height isn't aligned to
 162     * the resolve granularity and the render area is tall enough, we may wind
 163     * up writing past the bottom of the image into the next miplevel or even
 164     * past the end of the image. For the last miplevel, the layout code should
 165     * insert enough padding so that the overdraw writes to the padding.  To
 166     * work around this, we force-enable sysmem rendering.
 167     */
 168    const uint32_t y2 = render_area->offset.y + render_area->extent.height;
 169    const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
 170
 171    return has_linear_mipmapped_store && aligned_y2 > fb->height;
 172 }
 173
 174 static void
 175 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 176                                     const struct tu_device *dev,
 177                                     uint32_t pixels)
 178 {
 179    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 180    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 181    const uint32_t max_tile_width = 1024; /* A6xx */
 182
 183    tiling->tile0.offset = (VkOffset2D) {
 184       .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
 185       .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
 186    };
 187
 188    const uint32_t ra_width =
 189       tiling->render_area.extent.width +
 190       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 191    const uint32_t ra_height =
 192       tiling->render_area.extent.height +
 193       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 194
 195    /* start from 1 tile */
 196    tiling->tile_count = (VkExtent2D) {
 197       .width = 1,
 198       .height = 1,
 199    };
 200    tiling->tile0.extent = (VkExtent2D) {
 201       .width = align(ra_width, tile_align_w),
 202       .height = align(ra_height, tile_align_h),
 203    };
 204
 205    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 206       /* start with 2x2 tiles */
 207       tiling->tile_count.width = 2;
 208       tiling->tile_count.height = 2;
 209       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 210       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 211    }
 212
 213    /* do not exceed max tile width */
 214    while (tiling->tile0.extent.width > max_tile_width) {
 215       tiling->tile_count.width++;
 216       tiling->tile0.extent.width =
 217          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 218    }
 219
 220    /* do not exceed gmem size */
 221    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 222       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 223          tiling->tile_count.width++;
 224          tiling->tile0.extent.width =
 225             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 226       } else {
 227          /* if this assert fails then layout is impossible.. */
 228          assert(tiling->tile0.extent.height > tile_align_h);
 229          tiling->tile_count.height++;
 230          tiling->tile0.extent.height =
 231             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 232       }
 233    }
 234 }
 235
 236 static void
 237 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 238                                     const struct tu_device *dev)
 239 {
 240    const uint32_t max_pipe_count = 32; /* A6xx */
 241
 242    /* start from 1 tile per pipe */
 243    tiling->pipe0 = (VkExtent2D) {
 244       .width = 1,
 245       .height = 1,
 246    };
 247    tiling->pipe_count = tiling->tile_count;
 248
 249    /* do not exceed max pipe count vertically */
 250    while (tiling->pipe_count.height > max_pipe_count) {
 251       tiling->pipe0.height += 2;
 252       tiling->pipe_count.height =
 253          (tiling->tile_count.height + tiling->pipe0.height - 1) /
 254          tiling->pipe0.height;
 255    }
 256
 257    /* do not exceed max pipe count */
 258    while (tiling->pipe_count.width * tiling->pipe_count.height >
 259           max_pipe_count) {
 260       tiling->pipe0.width += 1;
 261       tiling->pipe_count.width =
 262          (tiling->tile_count.width + tiling->pipe0.width - 1) /
 263          tiling->pipe0.width;
 264    }
 265 }
 266
 267 static void
 268 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 269                               const struct tu_device *dev)
 270 {
 271    const uint32_t max_pipe_count = 32; /* A6xx */
 272    const uint32_t used_pipe_count =
 273       tiling->pipe_count.width * tiling->pipe_count.height;
 274    const VkExtent2D last_pipe = {
 275       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 276       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 277    };
 278
 279    assert(used_pipe_count <= max_pipe_count);
 280    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 281
 282    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 283       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 284          const uint32_t pipe_x = tiling->pipe0.width * x;
 285          const uint32_t pipe_y = tiling->pipe0.height * y;
 286          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 287                                     ? last_pipe.width
 288                                     : tiling->pipe0.width;
 289          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 290                                     ? last_pipe.height
 291                                     : tiling->pipe0.height;
 292          const uint32_t n = tiling->pipe_count.width * y + x;
 293
 294          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 295                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 296                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 297                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 298          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 299       }
 300    }
 301
 302    memset(tiling->pipe_config + used_pipe_count, 0,
 303           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 304 }
 305
 306 static void
 307 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 308                           const struct tu_device *dev,
 309                           uint32_t tx,
 310                           uint32_t ty,
 311                           struct tu_tile *tile)
 312 {
 313    /* find the pipe and the slot for tile (tx, ty) */
 314    const uint32_t px = tx / tiling->pipe0.width;
 315    const uint32_t py = ty / tiling->pipe0.height;
 316    const uint32_t sx = tx - tiling->pipe0.width * px;
 317    const uint32_t sy = ty - tiling->pipe0.height * py;
 318
 319    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 320    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 321    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 322
 323    /* convert to 1D indices */
 324    tile->pipe = tiling->pipe_count.width * py + px;
 325    tile->slot = tiling->pipe0.width * sy + sx;
 326
 327    /* get the blit area for the tile */
 328    tile->begin = (VkOffset2D) {
 329       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 330       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 331    };
 332    tile->end.x =
 333       (tx == tiling->tile_count.width - 1)
 334          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 335          : tile->begin.x + tiling->tile0.extent.width;
 336    tile->end.y =
 337       (ty == tiling->tile_count.height - 1)
 338          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 339          : tile->begin.y + tiling->tile0.extent.height;
 340 }
 341
 342 enum a3xx_msaa_samples
 343 tu_msaa_samples(uint32_t samples)
 344 {
 345    switch (samples) {
 346    case 1:
 347       return MSAA_ONE;
 348    case 2:
 349       return MSAA_TWO;
 350    case 4:
 351       return MSAA_FOUR;
 352    case 8:
 353       return MSAA_EIGHT;
 354    default:
 355       assert(!"invalid sample count");
 356       return MSAA_ONE;
 357    }
 358 }
 359
 360 static enum a4xx_index_size
 361 tu6_index_size(VkIndexType type)
 362 {
 363    switch (type) {
 364    case VK_INDEX_TYPE_UINT16:
 365       return INDEX4_SIZE_16_BIT;
 366    case VK_INDEX_TYPE_UINT32:
 367       return INDEX4_SIZE_32_BIT;
 368    default:
 369       unreachable("invalid VkIndexType");
 370       return INDEX4_SIZE_8_BIT;
 371    }
 372 }
 373
 374 unsigned
 375 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 376                      struct tu_cs *cs,
 377                      enum vgt_event_type event,
 378                      bool need_seqno)
 379 {
 380    unsigned seqno = 0;
 381
 382    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 383    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 384    if (need_seqno) {
 385       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 386       seqno = ++cmd->scratch_seqno;
 387       tu_cs_emit(cs, seqno);
 388    }
 389
 390    return seqno;
 391 }
 392
 393 static void
 394 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 395 {
 396    tu6_emit_event_write(cmd, cs, 0x31, false);
 397 }
 398
 399 static void
 400 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 401 {
 402    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 403 }
 404
 405 static void
 406 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 407 {
 408    if (cmd->wait_for_idle) {
 409       tu_cs_emit_wfi(cs);
 410       cmd->wait_for_idle = false;
 411    }
 412 }
 413
 414 #define tu_image_view_ubwc_pitches(iview)                                \
 415    .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip),          \
 416    .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
 417
 418 static void
 419 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 420             const struct tu_subpass *subpass,
 421             struct tu_cs *cs)
 422 {
 423    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 424
 425    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 426    if (a == VK_ATTACHMENT_UNUSED) {
 427       tu_cs_emit_regs(cs,
 428                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 429                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 430                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 431                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 432                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 433
 434       tu_cs_emit_regs(cs,
 435                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 436
 437       tu_cs_emit_regs(cs,
 438                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 439                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 440                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 441
 442       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 443
 444       return;
 445    }
 446
 447    const struct tu_image_view *iview = fb->attachments[a].attachment;
 448    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 449
 450    tu_cs_emit_regs(cs,
 451                    A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
 452                    A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 453                    A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
 454                    A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
 455                    A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
 456
 457    tu_cs_emit_regs(cs,
 458                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 459
 460    tu_cs_emit_regs(cs,
 461                    A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
 462                    A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
 463
 464    tu_cs_emit_regs(cs,
 465                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 466                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 467                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 468
 469    tu_cs_emit_regs(cs,
 470                    A6XX_RB_STENCIL_INFO(0));
 471
 472    /* enable zs? */
 473 }
 474
 475 static void
 476 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 477              const struct tu_subpass *subpass,
 478              struct tu_cs *cs)
 479 {
 480    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 481    unsigned char mrt_comp[MAX_RTS] = { 0 };
 482    unsigned srgb_cntl = 0;
 483
 484    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 485       uint32_t a = subpass->color_attachments[i].attachment;
 486       if (a == VK_ATTACHMENT_UNUSED)
 487          continue;
 488
 489       const struct tu_image_view *iview = fb->attachments[a].attachment;
 490       const enum a6xx_tile_mode tile_mode =
 491          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 492
 493       mrt_comp[i] = 0xf;
 494
 495       if (vk_format_is_srgb(iview->vk_format))
 496          srgb_cntl |= (1 << i);
 497
 498       const struct tu_native_format format =
 499          tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 500
 501       tu_cs_emit_regs(cs,
 502                       A6XX_RB_MRT_BUF_INFO(i,
 503                                            .color_tile_mode = tile_mode,
 504                                            .color_format = format.fmt,
 505                                            .color_swap = format.swap),
 506                       A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
 507                       A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
 508                       A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
 509                       A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
 510
 511       tu_cs_emit_regs(cs,
 512                       A6XX_SP_FS_MRT_REG(i,
 513                                          .color_format = format.fmt,
 514                                          .color_sint = vk_format_is_sint(iview->vk_format),
 515                                          .color_uint = vk_format_is_uint(iview->vk_format)));
 516
 517       tu_cs_emit_regs(cs,
 518                       A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
 519                       A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
 520    }
 521
 522    tu_cs_emit_regs(cs,
 523                    A6XX_RB_SRGB_CNTL(srgb_cntl));
 524
 525    tu_cs_emit_regs(cs,
 526                    A6XX_SP_SRGB_CNTL(srgb_cntl));
 527
 528    tu_cs_emit_regs(cs,
 529                    A6XX_RB_RENDER_COMPONENTS(
 530                       .rt0 = mrt_comp[0],
 531                       .rt1 = mrt_comp[1],
 532                       .rt2 = mrt_comp[2],
 533                       .rt3 = mrt_comp[3],
 534                       .rt4 = mrt_comp[4],
 535                       .rt5 = mrt_comp[5],
 536                       .rt6 = mrt_comp[6],
 537                       .rt7 = mrt_comp[7]));
 538
 539    tu_cs_emit_regs(cs,
 540                    A6XX_SP_FS_RENDER_COMPONENTS(
 541                       .rt0 = mrt_comp[0],
 542                       .rt1 = mrt_comp[1],
 543                       .rt2 = mrt_comp[2],
 544                       .rt3 = mrt_comp[3],
 545                       .rt4 = mrt_comp[4],
 546                       .rt5 = mrt_comp[5],
 547                       .rt6 = mrt_comp[6],
 548                       .rt7 = mrt_comp[7]));
 549 }
 550
 551 static void
 552 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
 553               const struct tu_subpass *subpass,
 554               struct tu_cs *cs)
 555 {
 556    const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
 557    bool msaa_disable = samples == MSAA_ONE;
 558
 559    tu_cs_emit_regs(cs,
 560                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 561                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 562                                              .msaa_disable = msaa_disable));
 563
 564    tu_cs_emit_regs(cs,
 565                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 566                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 567                                             .msaa_disable = msaa_disable));
 568
 569    tu_cs_emit_regs(cs,
 570                    A6XX_RB_RAS_MSAA_CNTL(samples),
 571                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 572                                           .msaa_disable = msaa_disable));
 573
 574    tu_cs_emit_regs(cs,
 575                    A6XX_RB_MSAA_CNTL(samples));
 576 }
 577
 578 static void
 579 tu6_emit_bin_size(struct tu_cs *cs,
 580                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 581 {
 582    tu_cs_emit_regs(cs,
 583                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 584                                          .binh = bin_h,
 585                                          .dword = flags));
 586
 587    tu_cs_emit_regs(cs,
 588                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 589                                        .binh = bin_h,
 590                                        .dword = flags));
 591
 592    /* no flag for RB_BIN_CONTROL2... */
 593    tu_cs_emit_regs(cs,
 594                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 595                                         .binh = bin_h));
 596 }
 597
 598 static void
 599 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 600                      const struct tu_subpass *subpass,
 601                      struct tu_cs *cs,
 602                      bool binning)
 603 {
 604    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 605    uint32_t cntl = 0;
 606    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 607    if (binning) {
 608       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 609    } else {
 610       uint32_t mrts_ubwc_enable = 0;
 611       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 612          uint32_t a = subpass->color_attachments[i].attachment;
 613          if (a == VK_ATTACHMENT_UNUSED)
 614             continue;
 615
 616          const struct tu_image_view *iview = fb->attachments[a].attachment;
 617          if (iview->image->layout.ubwc_layer_size != 0)
 618             mrts_ubwc_enable |= 1 << i;
 619       }
 620
 621       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 622
 623       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 624       if (a != VK_ATTACHMENT_UNUSED) {
 625          const struct tu_image_view *iview = fb->attachments[a].attachment;
 626          if (iview->image->layout.ubwc_layer_size != 0)
 627             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 628       }
 629
 630       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 631        * in order to set it correctly for the different subpasses. However,
 632        * that means the packets we're emitting also happen during binning. So
 633        * we need to guard the write on !BINNING at CP execution time.
 634        */
 635       tu_cs_reserve(cs, 3 + 4);
 636       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 637       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 638                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 639       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 640    }
 641
 642    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 643    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 644    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 645    tu_cs_emit(cs, cntl);
 646 }
 647
 648 static void
 649 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 650 {
 651    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 652    uint32_t x1 = render_area->offset.x;
 653    uint32_t y1 = render_area->offset.y;
 654    uint32_t x2 = x1 + render_area->extent.width - 1;
 655    uint32_t y2 = y1 + render_area->extent.height - 1;
 656
 657    /* TODO: alignment requirement seems to be less than tile_align_w/h */
 658    if (align) {
 659       x1 = x1 & ~cmd->device->physical_device->tile_align_w;
 660       y1 = y1 & ~cmd->device->physical_device->tile_align_h;
 661       x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
 662       y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
 663    }
 664
 665    tu_cs_emit_regs(cs,
 666                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 667                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 668 }
 669
 670 static void
 671 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 672                    struct tu_cs *cs,
 673                    const struct tu_image_view *iview,
 674                    uint32_t gmem_offset,
 675                    bool resolve)
 676 {
 677    tu_cs_emit_regs(cs,
 678                    A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
 679
 680    const struct tu_native_format format =
 681       tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 682
 683    enum a6xx_tile_mode tile_mode =
 684       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 685    tu_cs_emit_regs(cs,
 686                    A6XX_RB_BLIT_DST_INFO(
 687                       .tile_mode = tile_mode,
 688                       .samples = tu_msaa_samples(iview->image->samples),
 689                       .color_format = format.fmt,
 690                       .color_swap = format.swap,
 691                       .flags = iview->image->layout.ubwc_layer_size != 0),
 692                    A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
 693                    A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 694                    A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
 695
 696    if (iview->image->layout.ubwc_layer_size) {
 697       tu_cs_emit_regs(cs,
 698                       A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
 699                       A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
 700    }
 701
 702    tu_cs_emit_regs(cs,
 703                    A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
 704 }
 705
 706 static void
 707 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 708 {
 709    tu6_emit_event_write(cmd, cs, BLIT, false);
 710 }
 711
 712 static void
 713 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 714                         struct tu_cs *cs,
 715                         uint32_t x1,
 716                         uint32_t y1,
 717                         uint32_t x2,
 718                         uint32_t y2)
 719 {
 720    tu_cs_emit_regs(cs,
 721                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 722                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 723
 724    tu_cs_emit_regs(cs,
 725                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 726                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 727 }
 728
 729 static void
 730 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 731                        struct tu_cs *cs,
 732                        uint32_t x1,
 733                        uint32_t y1)
 734 {
 735    tu_cs_emit_regs(cs,
 736                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 737
 738    tu_cs_emit_regs(cs,
 739                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 740
 741    tu_cs_emit_regs(cs,
 742                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 743
 744    tu_cs_emit_regs(cs,
 745                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 746 }
 747
 748 static bool
 749 use_hw_binning(struct tu_cmd_buffer *cmd)
 750 {
 751    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 752
 753    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 754       return false;
 755
 756    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 757       return true;
 758
 759    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 760 }
 761
 762 static bool
 763 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 764 {
 765    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 766       return true;
 767
 768    return cmd->state.tiling_config.force_sysmem;
 769 }
 770
 771 static void
 772 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 773                      struct tu_cs *cs,
 774                      const struct tu_tile *tile)
 775 {
 776    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 777    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 778
 779    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 780    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 781
 782    const uint32_t x1 = tile->begin.x;
 783    const uint32_t y1 = tile->begin.y;
 784    const uint32_t x2 = tile->end.x - 1;
 785    const uint32_t y2 = tile->end.y - 1;
 786    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 787    tu6_emit_window_offset(cmd, cs, x1, y1);
 788
 789    tu_cs_emit_regs(cs,
 790                    A6XX_VPC_SO_OVERRIDE(.so_disable = true));
 791
 792    if (use_hw_binning(cmd)) {
 793       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 794
 795       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 796       tu_cs_emit(cs, 0x0);
 797
 798       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 799       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 800                      A6XX_CP_REG_TEST_0_BIT(0) |
 801                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 802
 803       tu_cs_reserve(cs, 3 + 11);
 804       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 805       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 806       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 807
 808       /* if (no overflow) */ {
 809          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 810          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 811                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 812          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 813          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 814          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 815
 816          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 817          tu_cs_emit(cs, 0x0);
 818
 819          /* use a NOP packet to skip over the 'else' side: */
 820          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 821       } /* else */ {
 822          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 823          tu_cs_emit(cs, 0x1);
 824       }
 825
 826       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 827       tu_cs_emit(cs, 0x0);
 828
 829       tu_cs_emit_regs(cs,
 830                       A6XX_RB_UNKNOWN_8804(0));
 831
 832       tu_cs_emit_regs(cs,
 833                       A6XX_SP_TP_UNKNOWN_B304(0));
 834
 835       tu_cs_emit_regs(cs,
 836                       A6XX_GRAS_UNKNOWN_80A4(0));
 837    } else {
 838       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 839       tu_cs_emit(cs, 0x1);
 840
 841       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 842       tu_cs_emit(cs, 0x0);
 843    }
 844 }
 845
 846 static void
 847 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
 848 {
 849    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 850    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 851    const struct tu_image_view *iview = fb->attachments[a].attachment;
 852    const struct tu_render_pass_attachment *attachment =
 853       &cmd->state.pass->attachments[a];
 854
 855    if (attachment->gmem_offset < 0)
 856       return;
 857
 858    const uint32_t x1 = tiling->render_area.offset.x;
 859    const uint32_t y1 = tiling->render_area.offset.y;
 860    const uint32_t x2 = x1 + tiling->render_area.extent.width;
 861    const uint32_t y2 = y1 + tiling->render_area.extent.height;
 862    const uint32_t tile_x2 =
 863       tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
 864    const uint32_t tile_y2 =
 865       tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
 866    bool need_load =
 867       x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
 868       y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
 869
 870    if (need_load)
 871       tu_finishme("improve handling of unaligned render area");
 872
 873    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 874       need_load = true;
 875
 876    if (vk_format_has_stencil(iview->vk_format) &&
 877        attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 878       need_load = true;
 879
 880    if (need_load) {
 881       tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
 882       tu6_emit_blit(cmd, cs);
 883    }
 884 }
 885
 886 static void
 887 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 888                           uint32_t a,
 889                           const VkRenderPassBeginInfo *info)
 890 {
 891    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 892    const struct tu_image_view *iview = fb->attachments[a].attachment;
 893    const struct tu_render_pass_attachment *attachment =
 894       &cmd->state.pass->attachments[a];
 895    unsigned clear_mask = 0;
 896
 897    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
 898    if (attachment->gmem_offset < 0)
 899       return;
 900
 901    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 902       clear_mask = 0xf;
 903
 904    if (vk_format_has_stencil(iview->vk_format)) {
 905       clear_mask &= 0x1;
 906       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 907          clear_mask |= 0x2;
 908    }
 909    if (!clear_mask)
 910       return;
 911
 912    tu_clear_gmem_attachment(cmd, cs, a, clear_mask,
 913                             &info->pClearValues[a]);
 914 }
 915
 916 static void
 917 tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
 918                          struct tu_cs *cs,
 919                          uint32_t a,
 920                          uint32_t gmem_a,
 921                          bool resolve)
 922 {
 923    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
 924
 925    tu6_emit_blit_info(cmd, cs,
 926                       cmd->state.framebuffer->attachments[a].attachment,
 927                       cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
 928    tu6_emit_blit(cmd, cs);
 929
 930    tu_cond_exec_end(cs);
 931 }
 932
 933 static void
 934 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 935                         struct tu_cs *cs,
 936                         uint32_t a,
 937                         uint32_t gmem_a)
 938 {
 939    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 940    const struct tu_image_view *dst = fb->attachments[a].attachment;
 941    const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 942
 943    tu_blit(cmd, cs, &(struct tu_blit) {
 944       .dst = sysmem_attachment_surf(dst, dst->base_layer,
 945                                     &cmd->state.tiling_config.render_area),
 946       .src = sysmem_attachment_surf(src, src->base_layer,
 947                                     &cmd->state.tiling_config.render_area),
 948       .layers = fb->layers,
 949    });
 950 }
 951
 952
 953 /* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
 954 static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
 955                              struct tu_cs *cs,
 956                              uint32_t a,
 957                              uint32_t gmem_a)
 958 {
 959    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 960       return;
 961
 962    tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
 963
 964    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
 965    tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
 966    tu_cond_exec_end(cs);
 967 }
 968
 969 static void
 970 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
 971                           struct tu_cs *cs,
 972                           uint32_t a,
 973                           uint32_t gmem_a)
 974 {
 975    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 976       return;
 977
 978    tu6_emit_blit_info(cmd, cs,
 979                       cmd->state.framebuffer->attachments[a].attachment,
 980                       cmd->state.pass->attachments[gmem_a].gmem_offset, true);
 981    tu6_emit_blit(cmd, cs);
 982 }
 983
 984 static void
 985 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 986 {
 987    const struct tu_render_pass *pass = cmd->state.pass;
 988    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 989
 990    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 991    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 992                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 993                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 994    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 995    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 996
 997    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 998    tu_cs_emit(cs, 0x0);
 999
1000    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1001    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1002
1003    tu6_emit_blit_scissor(cmd, cs, true);
1004
1005    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1006       if (pass->attachments[a].gmem_offset >= 0)
1007          tu6_emit_store_attachment(cmd, cs, a, a);
1008    }
1009
1010    if (subpass->resolve_attachments) {
1011       for (unsigned i = 0; i < subpass->color_count; i++) {
1012          uint32_t a = subpass->resolve_attachments[i].attachment;
1013          if (a != VK_ATTACHMENT_UNUSED)
1014             tu6_emit_store_attachment(cmd, cs, a,
1015                                       subpass->color_attachments[i].attachment);
1016       }
1017    }
1018 }
1019
1020 static void
1021 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
1022 {
1023    tu_cs_emit_regs(cs,
1024                    A6XX_PC_RESTART_INDEX(restart_index));
1025 }
1026
1027 static void
1028 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1029 {
1030    tu6_emit_cache_flush(cmd, cs);
1031
1032    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
1033
1034    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x10000000);
1035    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1036    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1037    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
1038    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1039    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
1040    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1041    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1042    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1043
1044    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
1045    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1046    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1047    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1048    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
1049    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1050    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1051    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1052    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
1053    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1054    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1055    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1056    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1057    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
1058
1059    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
1060
1061    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1062
1063    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1064    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
1065    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1066    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1067    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1068    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1069    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1070    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1071    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1072    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1073    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1074
1075    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1076    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
1077
1078    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1079    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1080
1081    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1082                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1083
1084    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1085    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1086    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1087
1088    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1089    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1090
1091    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1092
1093    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1094
1095    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1096    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1097    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1098    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1099    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1100    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1101    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1102    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1103    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1104    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1105    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1106    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1107    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1108    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1109    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1110    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1111    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1112    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1113    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1114    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1115    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1116
1117    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1118
1119    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1120
1121    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1122
1123    /* we don't use this yet.. probably best to disable.. */
1124    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1125    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1126                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1127                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1128    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1129    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1130
1131    tu_cs_emit_regs(cs,
1132                    A6XX_VPC_SO_BUFFER_BASE(0),
1133                    A6XX_VPC_SO_BUFFER_SIZE(0));
1134
1135    tu_cs_emit_regs(cs,
1136                    A6XX_VPC_SO_FLUSH_BASE(0));
1137
1138    tu_cs_emit_regs(cs,
1139                    A6XX_VPC_SO_BUF_CNTL(0));
1140
1141    tu_cs_emit_regs(cs,
1142                    A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1143
1144    tu_cs_emit_regs(cs,
1145                    A6XX_VPC_SO_BUFFER_BASE(1, 0),
1146                    A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1147
1148    tu_cs_emit_regs(cs,
1149                    A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1150                    A6XX_VPC_SO_FLUSH_BASE(1, 0),
1151                    A6XX_VPC_SO_BUFFER_BASE(2, 0),
1152                    A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1153
1154    tu_cs_emit_regs(cs,
1155                    A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1156                    A6XX_VPC_SO_FLUSH_BASE(2, 0),
1157                    A6XX_VPC_SO_BUFFER_BASE(3, 0),
1158                    A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1159
1160    tu_cs_emit_regs(cs,
1161                    A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1162                    A6XX_VPC_SO_FLUSH_BASE(3, 0));
1163
1164    tu_cs_emit_regs(cs,
1165                    A6XX_SP_HS_CTRL_REG0(0));
1166
1167    tu_cs_emit_regs(cs,
1168                    A6XX_SP_GS_CTRL_REG0(0));
1169
1170    tu_cs_emit_regs(cs,
1171                    A6XX_GRAS_LRZ_CNTL(0));
1172
1173    tu_cs_emit_regs(cs,
1174                    A6XX_RB_LRZ_CNTL(0));
1175
1176    tu_cs_sanity_check(cs);
1177 }
1178
1179 static void
1180 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1181 {
1182    unsigned seqno;
1183
1184    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1185
1186    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1187    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1188                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
1189    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1190    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1191    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1192    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1193
1194    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1195
1196    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1197    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1198    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1199    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1200 }
1201
1202 static void
1203 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1204 {
1205    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1206
1207    tu_cs_emit_regs(cs,
1208                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1209                                      .height = tiling->tile0.extent.height),
1210                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
1211                                          .bo_offset = 32 * cmd->vsc_data_pitch));
1212
1213    tu_cs_emit_regs(cs,
1214                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1215                                       .ny = tiling->tile_count.height));
1216
1217    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1218    for (unsigned i = 0; i < 32; i++)
1219       tu_cs_emit(cs, tiling->pipe_config[i]);
1220
1221    tu_cs_emit_regs(cs,
1222                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1223                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1224                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1225
1226    tu_cs_emit_regs(cs,
1227                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1228                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1229                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1230 }
1231
1232 static void
1233 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1234 {
1235    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1236    const uint32_t used_pipe_count =
1237       tiling->pipe_count.width * tiling->pipe_count.height;
1238
1239    /* Clear vsc_scratch: */
1240    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1241    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1242    tu_cs_emit(cs, 0x0);
1243
1244    /* Check for overflow, write vsc_scratch if detected: */
1245    for (int i = 0; i < used_pipe_count; i++) {
1246       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1247       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1248             CP_COND_WRITE5_0_WRITE_MEMORY);
1249       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1250       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1251       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1252       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1253       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1254       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1255
1256       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1257       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1258             CP_COND_WRITE5_0_WRITE_MEMORY);
1259       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1260       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1261       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1262       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1263       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1264       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1265    }
1266
1267    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1268
1269    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1270
1271    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1272    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1273          CP_MEM_TO_REG_0_CNT(1 - 1));
1274    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1275
1276    /*
1277     * This is a bit awkward, we really want a way to invert the
1278     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1279     * execute cmds to use hwbinning when a bit is *not* set.  This
1280     * dance is to invert OVERFLOW_FLAG_REG
1281     *
1282     * A CP_NOP packet is used to skip executing the 'else' clause
1283     * if (b0 set)..
1284     */
1285
1286    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1287    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1288    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1289          A6XX_CP_REG_TEST_0_BIT(0) |
1290          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1291
1292    tu_cs_reserve(cs, 3 + 7);
1293    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1294    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1295    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1296
1297    /* if (b0 set) */ {
1298       /*
1299        * On overflow, mirror the value to control->vsc_overflow
1300        * which CPU is checking to detect overflow (see
1301        * check_vsc_overflow())
1302        */
1303       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1304       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1305             CP_REG_TO_MEM_0_CNT(0));
1306       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1307
1308       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1309       tu_cs_emit(cs, 0x0);
1310
1311       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1312    } /* else */ {
1313       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1314       tu_cs_emit(cs, 0x1);
1315    }
1316 }
1317
1318 static void
1319 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1320 {
1321    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1322    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1323
1324    uint32_t x1 = tiling->tile0.offset.x;
1325    uint32_t y1 = tiling->tile0.offset.y;
1326    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1327    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1328
1329    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1330
1331    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1332    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1333
1334    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1335    tu_cs_emit(cs, 0x1);
1336
1337    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1338    tu_cs_emit(cs, 0x1);
1339
1340    tu_cs_emit_wfi(cs);
1341
1342    tu_cs_emit_regs(cs,
1343                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1344
1345    update_vsc_pipe(cmd, cs);
1346
1347    tu_cs_emit_regs(cs,
1348                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1349
1350    tu_cs_emit_regs(cs,
1351                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1352
1353    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1354    tu_cs_emit(cs, UNK_2C);
1355
1356    tu_cs_emit_regs(cs,
1357                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1358
1359    tu_cs_emit_regs(cs,
1360                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1361
1362    /* emit IB to binning drawcmds: */
1363    tu_cs_emit_call(cs, &cmd->draw_cs);
1364
1365    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1366    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1367                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1368                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1369    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1370    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1371
1372    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1373    tu_cs_emit(cs, UNK_2D);
1374
1375    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1376    tu6_cache_flush(cmd, cs);
1377
1378    tu_cs_emit_wfi(cs);
1379
1380    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1381
1382    emit_vsc_overflow_test(cmd, cs);
1383
1384    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1385    tu_cs_emit(cs, 0x0);
1386
1387    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1388    tu_cs_emit(cs, 0x0);
1389
1390    tu_cs_emit_wfi(cs);
1391
1392    tu_cs_emit_regs(cs,
1393                    A6XX_RB_CCU_CNTL(.unknown = phys_dev->magic.RB_CCU_CNTL_gmem));
1394
1395    cmd->wait_for_idle = false;
1396 }
1397
1398 static void
1399 tu_emit_sysmem_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1400                                 uint32_t a,
1401                                 const VkRenderPassBeginInfo *info)
1402 {
1403    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1404    const struct tu_image_view *iview = fb->attachments[a].attachment;
1405    const struct tu_render_pass_attachment *attachment =
1406       &cmd->state.pass->attachments[a];
1407    unsigned clear_mask = 0;
1408
1409    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
1410    if (attachment->gmem_offset < 0)
1411       return;
1412
1413    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1414       clear_mask = 0xf;
1415    }
1416
1417    if (vk_format_has_stencil(iview->vk_format)) {
1418       clear_mask &= 0x1;
1419       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1420          clear_mask |= 0x2;
1421       if (clear_mask != 0x3)
1422          tu_finishme("depth/stencil only load op");
1423    }
1424
1425    if (!clear_mask)
1426       return;
1427
1428    tu_clear_sysmem_attachment(cmd, cs, a,
1429                               &info->pClearValues[a], &(struct VkClearRect) {
1430       .rect = info->renderArea,
1431       .baseArrayLayer = iview->base_layer,
1432       .layerCount = iview->layer_count,
1433    });
1434 }
1435
1436 static void
1437 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1438                    const VkRenderPassBeginInfo *info)
1439 {
1440    struct tu_cs *cs = &cmd->draw_cs;
1441
1442    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1443
1444    tu6_emit_blit_scissor(cmd, cs, true);
1445
1446    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1447       tu6_emit_load_attachment(cmd, cs, i);
1448
1449    tu6_emit_blit_scissor(cmd, cs, false);
1450
1451    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1452       tu6_emit_clear_attachment(cmd, cs, i, info);
1453
1454    tu_cond_exec_end(cs);
1455
1456    /* invalidate because reading input attachments will cache GMEM and
1457     * the cache isn''t updated when GMEM is written
1458     * TODO: is there a no-cache bit for textures?
1459     */
1460    if (cmd->state.subpass->input_count)
1461       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1462
1463    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1464
1465    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1466       tu_emit_sysmem_clear_attachment(cmd, cs, i, info);
1467
1468    tu_cond_exec_end(cs);
1469 }
1470
1471 static void
1472 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1473                         const struct VkRect2D *renderArea)
1474 {
1475    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1476    if (fb->width > 0 && fb->height > 0) {
1477       tu6_emit_window_scissor(cmd, cs,
1478                               0, 0, fb->width - 1, fb->height - 1);
1479    } else {
1480       tu6_emit_window_scissor(cmd, cs, 0, 0, 0, 0);
1481    }
1482
1483    tu6_emit_window_offset(cmd, cs, 0, 0);
1484
1485    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1486
1487    tu6_emit_lrz_flush(cmd, cs);
1488
1489    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1490    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1491
1492    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1493    tu_cs_emit(cs, 0x0);
1494
1495    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1496    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1497    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1498
1499    tu6_emit_wfi(cmd, cs);
1500    tu_cs_emit_regs(cs,
1501                    A6XX_RB_CCU_CNTL(0x10000000));
1502
1503    /* enable stream-out, with sysmem there is only one pass: */
1504    tu_cs_emit_regs(cs,
1505                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1506
1507    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1508    tu_cs_emit(cs, 0x1);
1509
1510    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1511    tu_cs_emit(cs, 0x0);
1512
1513    tu_cs_sanity_check(cs);
1514 }
1515
1516 static void
1517 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1518 {
1519    /* Do any resolves of the last subpass. These are handled in the
1520     * tile_store_ib in the gmem path.
1521     */
1522
1523    const struct tu_subpass *subpass = cmd->state.subpass;
1524    if (subpass->resolve_attachments) {
1525       for (unsigned i = 0; i < subpass->color_count; i++) {
1526          uint32_t a = subpass->resolve_attachments[i].attachment;
1527          if (a != VK_ATTACHMENT_UNUSED)
1528             tu6_emit_sysmem_resolve(cmd, cs, a,
1529                                     subpass->color_attachments[i].attachment);
1530       }
1531    }
1532
1533    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1534
1535    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1536    tu_cs_emit(cs, 0x0);
1537
1538    tu6_emit_lrz_flush(cmd, cs);
1539
1540    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1541    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1542
1543    tu_cs_sanity_check(cs);
1544 }
1545
1546
1547 static void
1548 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1549 {
1550    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1551
1552    tu6_emit_lrz_flush(cmd, cs);
1553
1554    /* lrz clear? */
1555
1556    tu6_emit_cache_flush(cmd, cs);
1557
1558    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1559    tu_cs_emit(cs, 0x0);
1560
1561    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1562    tu6_emit_wfi(cmd, cs);
1563    tu_cs_emit_regs(cs,
1564                    A6XX_RB_CCU_CNTL(phys_dev->magic.RB_CCU_CNTL_gmem));
1565
1566    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1567    if (use_hw_binning(cmd)) {
1568       tu6_emit_bin_size(cs,
1569                         tiling->tile0.extent.width,
1570                         tiling->tile0.extent.height,
1571                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1572
1573       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1574
1575       tu6_emit_binning_pass(cmd, cs);
1576
1577       tu6_emit_bin_size(cs,
1578                         tiling->tile0.extent.width,
1579                         tiling->tile0.extent.height,
1580                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1581
1582       tu_cs_emit_regs(cs,
1583                       A6XX_VFD_MODE_CNTL(0));
1584
1585       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1586
1587       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1588
1589       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1590       tu_cs_emit(cs, 0x1);
1591    } else {
1592       tu6_emit_bin_size(cs,
1593                         tiling->tile0.extent.width,
1594                         tiling->tile0.extent.height,
1595                         0x6000000);
1596    }
1597
1598    tu_cs_sanity_check(cs);
1599 }
1600
1601 static void
1602 tu6_render_tile(struct tu_cmd_buffer *cmd,
1603                 struct tu_cs *cs,
1604                 const struct tu_tile *tile)
1605 {
1606    tu6_emit_tile_select(cmd, cs, tile);
1607
1608    tu_cs_emit_call(cs, &cmd->draw_cs);
1609    cmd->wait_for_idle = true;
1610
1611    if (use_hw_binning(cmd)) {
1612       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1613       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1614                      A6XX_CP_REG_TEST_0_BIT(0) |
1615                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1616
1617       tu_cs_reserve(cs, 3 + 2);
1618       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1619       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1620       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1621
1622       /* if (no overflow) */ {
1623          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1624          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1625       }
1626    }
1627
1628    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1629
1630    tu_cs_sanity_check(cs);
1631 }
1632
1633 static void
1634 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1635 {
1636    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1637
1638    tu_cs_emit_regs(cs,
1639                    A6XX_GRAS_LRZ_CNTL(0));
1640
1641    tu6_emit_lrz_flush(cmd, cs);
1642
1643    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1644
1645    tu_cs_sanity_check(cs);
1646 }
1647
1648 static void
1649 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1650 {
1651    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1652
1653    tu6_tile_render_begin(cmd, &cmd->cs);
1654
1655    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1656       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1657          struct tu_tile tile;
1658          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1659          tu6_render_tile(cmd, &cmd->cs, &tile);
1660       }
1661    }
1662
1663    tu6_tile_render_end(cmd, &cmd->cs);
1664 }
1665
1666 static void
1667 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1668 {
1669    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1670
1671    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1672
1673    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1674    cmd->wait_for_idle = true;
1675
1676    tu6_sysmem_render_end(cmd, &cmd->cs);
1677 }
1678
1679 static void
1680 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1681 {
1682    const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1683    struct tu_cs sub_cs;
1684
1685    VkResult result =
1686       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1687    if (result != VK_SUCCESS) {
1688       cmd->record_result = result;
1689       return;
1690    }
1691
1692    /* emit to tile-store sub_cs */
1693    tu6_emit_tile_store(cmd, &sub_cs);
1694
1695    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1696 }
1697
1698 static void
1699 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1700                             const VkRect2D *render_area)
1701 {
1702    const struct tu_device *dev = cmd->device;
1703    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1704
1705    tiling->render_area = *render_area;
1706    tiling->force_sysmem = force_sysmem(cmd, render_area);
1707
1708    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1709    tu_tiling_config_update_pipe_layout(tiling, dev);
1710    tu_tiling_config_update_pipes(tiling, dev);
1711 }
1712
1713 const struct tu_dynamic_state default_dynamic_state = {
1714    .viewport =
1715      {
1716        .count = 0,
1717      },
1718    .scissor =
1719      {
1720        .count = 0,
1721      },
1722    .line_width = 1.0f,
1723    .depth_bias =
1724      {
1725        .bias = 0.0f,
1726        .clamp = 0.0f,
1727        .slope = 0.0f,
1728      },
1729    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1730    .depth_bounds =
1731      {
1732        .min = 0.0f,
1733        .max = 1.0f,
1734      },
1735    .stencil_compare_mask =
1736      {
1737        .front = ~0u,
1738        .back = ~0u,
1739      },
1740    .stencil_write_mask =
1741      {
1742        .front = ~0u,
1743        .back = ~0u,
1744      },
1745    .stencil_reference =
1746      {
1747        .front = 0u,
1748        .back = 0u,
1749      },
1750 };
1751
1752 static void UNUSED /* FINISHME */
1753 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1754                       const struct tu_dynamic_state *src)
1755 {
1756    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1757    uint32_t copy_mask = src->mask;
1758    uint32_t dest_mask = 0;
1759
1760    tu_use_args(cmd_buffer); /* FINISHME */
1761
1762    /* Make sure to copy the number of viewports/scissors because they can
1763     * only be specified at pipeline creation time.
1764     */
1765    dest->viewport.count = src->viewport.count;
1766    dest->scissor.count = src->scissor.count;
1767    dest->discard_rectangle.count = src->discard_rectangle.count;
1768
1769    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1770       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1771                  src->viewport.count * sizeof(VkViewport))) {
1772          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1773                       src->viewport.count);
1774          dest_mask |= TU_DYNAMIC_VIEWPORT;
1775       }
1776    }
1777
1778    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1779       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1780                  src->scissor.count * sizeof(VkRect2D))) {
1781          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1782                       src->scissor.count);
1783          dest_mask |= TU_DYNAMIC_SCISSOR;
1784       }
1785    }
1786
1787    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1788       if (dest->line_width != src->line_width) {
1789          dest->line_width = src->line_width;
1790          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1791       }
1792    }
1793
1794    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1795       if (memcmp(&dest->depth_bias, &src->depth_bias,
1796                  sizeof(src->depth_bias))) {
1797          dest->depth_bias = src->depth_bias;
1798          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1799       }
1800    }
1801
1802    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1803       if (memcmp(&dest->blend_constants, &src->blend_constants,
1804                  sizeof(src->blend_constants))) {
1805          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1806          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1807       }
1808    }
1809
1810    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1811       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1812                  sizeof(src->depth_bounds))) {
1813          dest->depth_bounds = src->depth_bounds;
1814          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1815       }
1816    }
1817
1818    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1819       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1820                  sizeof(src->stencil_compare_mask))) {
1821          dest->stencil_compare_mask = src->stencil_compare_mask;
1822          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1823       }
1824    }
1825
1826    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1827       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1828                  sizeof(src->stencil_write_mask))) {
1829          dest->stencil_write_mask = src->stencil_write_mask;
1830          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1831       }
1832    }
1833
1834    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1835       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1836                  sizeof(src->stencil_reference))) {
1837          dest->stencil_reference = src->stencil_reference;
1838          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1839       }
1840    }
1841
1842    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1843       if (memcmp(&dest->discard_rectangle.rectangles,
1844                  &src->discard_rectangle.rectangles,
1845                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1846          typed_memcpy(dest->discard_rectangle.rectangles,
1847                       src->discard_rectangle.rectangles,
1848                       src->discard_rectangle.count);
1849          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1850       }
1851    }
1852 }
1853
1854 static VkResult
1855 tu_create_cmd_buffer(struct tu_device *device,
1856                      struct tu_cmd_pool *pool,
1857                      VkCommandBufferLevel level,
1858                      VkCommandBuffer *pCommandBuffer)
1859 {
1860    struct tu_cmd_buffer *cmd_buffer;
1861    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1862                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1863    if (cmd_buffer == NULL)
1864       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1865
1866    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1867    cmd_buffer->device = device;
1868    cmd_buffer->pool = pool;
1869    cmd_buffer->level = level;
1870
1871    if (pool) {
1872       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1873       cmd_buffer->queue_family_index = pool->queue_family_index;
1874
1875    } else {
1876       /* Init the pool_link so we can safely call list_del when we destroy
1877        * the command buffer
1878        */
1879       list_inithead(&cmd_buffer->pool_link);
1880       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1881    }
1882
1883    tu_bo_list_init(&cmd_buffer->bo_list);
1884    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1885    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1886    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1887    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1888
1889    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1890
1891    list_inithead(&cmd_buffer->upload.list);
1892
1893    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1894    if (result != VK_SUCCESS)
1895       goto fail_scratch_bo;
1896
1897    /* TODO: resize on overflow */
1898    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1899    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1900    cmd_buffer->vsc_data = device->vsc_data;
1901    cmd_buffer->vsc_data2 = device->vsc_data2;
1902
1903    return VK_SUCCESS;
1904
1905 fail_scratch_bo:
1906    list_del(&cmd_buffer->pool_link);
1907    return result;
1908 }
1909
1910 static void
1911 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1912 {
1913    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1914
1915    list_del(&cmd_buffer->pool_link);
1916
1917    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1918       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1919
1920    tu_cs_finish(&cmd_buffer->cs);
1921    tu_cs_finish(&cmd_buffer->draw_cs);
1922    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1923    tu_cs_finish(&cmd_buffer->sub_cs);
1924
1925    tu_bo_list_destroy(&cmd_buffer->bo_list);
1926    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1927 }
1928
1929 static VkResult
1930 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1931 {
1932    cmd_buffer->wait_for_idle = true;
1933
1934    cmd_buffer->record_result = VK_SUCCESS;
1935
1936    tu_bo_list_reset(&cmd_buffer->bo_list);
1937    tu_cs_reset(&cmd_buffer->cs);
1938    tu_cs_reset(&cmd_buffer->draw_cs);
1939    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1940    tu_cs_reset(&cmd_buffer->sub_cs);
1941
1942    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1943       cmd_buffer->descriptors[i].valid = 0;
1944       cmd_buffer->descriptors[i].push_dirty = false;
1945    }
1946
1947    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1948
1949    return cmd_buffer->record_result;
1950 }
1951
1952 VkResult
1953 tu_AllocateCommandBuffers(VkDevice _device,
1954                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1955                           VkCommandBuffer *pCommandBuffers)
1956 {
1957    TU_FROM_HANDLE(tu_device, device, _device);
1958    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1959
1960    VkResult result = VK_SUCCESS;
1961    uint32_t i;
1962
1963    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1964
1965       if (!list_is_empty(&pool->free_cmd_buffers)) {
1966          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1967             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1968
1969          list_del(&cmd_buffer->pool_link);
1970          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1971
1972          result = tu_reset_cmd_buffer(cmd_buffer);
1973          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1974          cmd_buffer->level = pAllocateInfo->level;
1975
1976          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1977       } else {
1978          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1979                                        &pCommandBuffers[i]);
1980       }
1981       if (result != VK_SUCCESS)
1982          break;
1983    }
1984
1985    if (result != VK_SUCCESS) {
1986       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1987                             pCommandBuffers);
1988
1989       /* From the Vulkan 1.0.66 spec:
1990        *
1991        * "vkAllocateCommandBuffers can be used to create multiple
1992        *  command buffers. If the creation of any of those command
1993        *  buffers fails, the implementation must destroy all
1994        *  successfully created command buffer objects from this
1995        *  command, set all entries of the pCommandBuffers array to
1996        *  NULL and return the error."
1997        */
1998       memset(pCommandBuffers, 0,
1999              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2000    }
2001
2002    return result;
2003 }
2004
2005 void
2006 tu_FreeCommandBuffers(VkDevice device,
2007                       VkCommandPool commandPool,
2008                       uint32_t commandBufferCount,
2009                       const VkCommandBuffer *pCommandBuffers)
2010 {
2011    for (uint32_t i = 0; i < commandBufferCount; i++) {
2012       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2013
2014       if (cmd_buffer) {
2015          if (cmd_buffer->pool) {
2016             list_del(&cmd_buffer->pool_link);
2017             list_addtail(&cmd_buffer->pool_link,
2018                          &cmd_buffer->pool->free_cmd_buffers);
2019          } else
2020             tu_cmd_buffer_destroy(cmd_buffer);
2021       }
2022    }
2023 }
2024
2025 VkResult
2026 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
2027                       VkCommandBufferResetFlags flags)
2028 {
2029    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2030    return tu_reset_cmd_buffer(cmd_buffer);
2031 }
2032
2033 VkResult
2034 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2035                       const VkCommandBufferBeginInfo *pBeginInfo)
2036 {
2037    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2038    VkResult result = VK_SUCCESS;
2039
2040    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
2041       /* If the command buffer has already been resetted with
2042        * vkResetCommandBuffer, no need to do it again.
2043        */
2044       result = tu_reset_cmd_buffer(cmd_buffer);
2045       if (result != VK_SUCCESS)
2046          return result;
2047    }
2048
2049    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2050    cmd_buffer->usage_flags = pBeginInfo->flags;
2051
2052    tu_cs_begin(&cmd_buffer->cs);
2053    tu_cs_begin(&cmd_buffer->draw_cs);
2054    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2055
2056    cmd_buffer->scratch_seqno = 0;
2057
2058    /* setup initial configuration into command buffer */
2059    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2060       switch (cmd_buffer->queue_family_index) {
2061       case TU_QUEUE_GENERAL:
2062          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
2063          break;
2064       default:
2065          break;
2066       }
2067    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2068               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2069       assert(pBeginInfo->pInheritanceInfo);
2070       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2071       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2072    }
2073
2074    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
2075
2076    return VK_SUCCESS;
2077 }
2078
2079 void
2080 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
2081                         uint32_t firstBinding,
2082                         uint32_t bindingCount,
2083                         const VkBuffer *pBuffers,
2084                         const VkDeviceSize *pOffsets)
2085 {
2086    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2087
2088    assert(firstBinding + bindingCount <= MAX_VBS);
2089
2090    for (uint32_t i = 0; i < bindingCount; i++) {
2091       cmd->state.vb.buffers[firstBinding + i] =
2092          tu_buffer_from_handle(pBuffers[i]);
2093       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
2094    }
2095
2096    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
2097    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2098 }
2099
2100 void
2101 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
2102                       VkBuffer buffer,
2103                       VkDeviceSize offset,
2104                       VkIndexType indexType)
2105 {
2106    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2107    TU_FROM_HANDLE(tu_buffer, buf, buffer);
2108
2109    /* initialize/update the restart index */
2110    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
2111       struct tu_cs *draw_cs = &cmd->draw_cs;
2112
2113       tu6_emit_restart_index(
2114          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
2115
2116       tu_cs_sanity_check(draw_cs);
2117    }
2118
2119    /* track the BO */
2120    if (cmd->state.index_buffer != buf)
2121       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2122
2123    cmd->state.index_buffer = buf;
2124    cmd->state.index_offset = offset;
2125    cmd->state.index_type = indexType;
2126 }
2127
2128 void
2129 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
2130                          VkPipelineBindPoint pipelineBindPoint,
2131                          VkPipelineLayout _layout,
2132                          uint32_t firstSet,
2133                          uint32_t descriptorSetCount,
2134                          const VkDescriptorSet *pDescriptorSets,
2135                          uint32_t dynamicOffsetCount,
2136                          const uint32_t *pDynamicOffsets)
2137 {
2138    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2139    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
2140    unsigned dyn_idx = 0;
2141
2142    struct tu_descriptor_state *descriptors_state =
2143       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2144
2145    for (unsigned i = 0; i < descriptorSetCount; ++i) {
2146       unsigned idx = i + firstSet;
2147       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
2148
2149       descriptors_state->sets[idx] = set;
2150       descriptors_state->valid |= (1u << idx);
2151
2152       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2153          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2154          assert(dyn_idx < dynamicOffsetCount);
2155
2156          descriptors_state->dynamic_buffers[idx] =
2157          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
2158       }
2159    }
2160
2161    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
2162 }
2163
2164 void
2165 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2166                     VkPipelineLayout layout,
2167                     VkShaderStageFlags stageFlags,
2168                     uint32_t offset,
2169                     uint32_t size,
2170                     const void *pValues)
2171 {
2172    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2173    memcpy((void*) cmd->push_constants + offset, pValues, size);
2174    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2175 }
2176
2177 VkResult
2178 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2179 {
2180    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2181
2182    if (cmd_buffer->scratch_seqno) {
2183       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2184                      MSM_SUBMIT_BO_WRITE);
2185    }
2186
2187    if (cmd_buffer->use_vsc_data) {
2188       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2189                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2190       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2191                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2192    }
2193
2194    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2195       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2196                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2197    }
2198
2199    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
2200       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
2201                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2202    }
2203
2204    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2205       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2206                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2207    }
2208
2209    tu_cs_end(&cmd_buffer->cs);
2210    tu_cs_end(&cmd_buffer->draw_cs);
2211    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2212
2213    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2214
2215    return cmd_buffer->record_result;
2216 }
2217
2218 void
2219 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2220                    VkPipelineBindPoint pipelineBindPoint,
2221                    VkPipeline _pipeline)
2222 {
2223    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2224    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2225
2226    switch (pipelineBindPoint) {
2227    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2228       cmd->state.pipeline = pipeline;
2229       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2230       break;
2231    case VK_PIPELINE_BIND_POINT_COMPUTE:
2232       cmd->state.compute_pipeline = pipeline;
2233       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2234       break;
2235    default:
2236       unreachable("unrecognized pipeline bind point");
2237       break;
2238    }
2239
2240    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2241                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2242    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2243       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2244                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2245    }
2246 }
2247
2248 void
2249 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2250                   uint32_t firstViewport,
2251                   uint32_t viewportCount,
2252                   const VkViewport *pViewports)
2253 {
2254    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2255    struct tu_cs *draw_cs = &cmd->draw_cs;
2256
2257    assert(firstViewport == 0 && viewportCount == 1);
2258    tu6_emit_viewport(draw_cs, pViewports);
2259
2260    tu_cs_sanity_check(draw_cs);
2261 }
2262
2263 void
2264 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2265                  uint32_t firstScissor,
2266                  uint32_t scissorCount,
2267                  const VkRect2D *pScissors)
2268 {
2269    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2270    struct tu_cs *draw_cs = &cmd->draw_cs;
2271
2272    assert(firstScissor == 0 && scissorCount == 1);
2273    tu6_emit_scissor(draw_cs, pScissors);
2274
2275    tu_cs_sanity_check(draw_cs);
2276 }
2277
2278 void
2279 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2280 {
2281    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2282
2283    cmd->state.dynamic.line_width = lineWidth;
2284
2285    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2286    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2287 }
2288
2289 void
2290 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2291                    float depthBiasConstantFactor,
2292                    float depthBiasClamp,
2293                    float depthBiasSlopeFactor)
2294 {
2295    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2296    struct tu_cs *draw_cs = &cmd->draw_cs;
2297
2298    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2299                        depthBiasSlopeFactor);
2300
2301    tu_cs_sanity_check(draw_cs);
2302 }
2303
2304 void
2305 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2306                         const float blendConstants[4])
2307 {
2308    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2309    struct tu_cs *draw_cs = &cmd->draw_cs;
2310
2311    tu6_emit_blend_constants(draw_cs, blendConstants);
2312
2313    tu_cs_sanity_check(draw_cs);
2314 }
2315
2316 void
2317 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2318                      float minDepthBounds,
2319                      float maxDepthBounds)
2320 {
2321 }
2322
2323 void
2324 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2325                             VkStencilFaceFlags faceMask,
2326                             uint32_t compareMask)
2327 {
2328    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2329
2330    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2331       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2332    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2333       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2334
2335    /* the front/back compare masks must be updated together */
2336    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2337 }
2338
2339 void
2340 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2341                           VkStencilFaceFlags faceMask,
2342                           uint32_t writeMask)
2343 {
2344    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2345
2346    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2347       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2348    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2349       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2350
2351    /* the front/back write masks must be updated together */
2352    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2353 }
2354
2355 void
2356 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2357                           VkStencilFaceFlags faceMask,
2358                           uint32_t reference)
2359 {
2360    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2361
2362    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2363       cmd->state.dynamic.stencil_reference.front = reference;
2364    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2365       cmd->state.dynamic.stencil_reference.back = reference;
2366
2367    /* the front/back references must be updated together */
2368    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2369 }
2370
2371 void
2372 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2373                       uint32_t commandBufferCount,
2374                       const VkCommandBuffer *pCmdBuffers)
2375 {
2376    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2377    VkResult result;
2378
2379    assert(commandBufferCount > 0);
2380
2381    for (uint32_t i = 0; i < commandBufferCount; i++) {
2382       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2383
2384       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2385       if (result != VK_SUCCESS) {
2386          cmd->record_result = result;
2387          break;
2388       }
2389
2390       result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2391       if (result != VK_SUCCESS) {
2392          cmd->record_result = result;
2393          break;
2394       }
2395
2396       result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2397             &secondary->draw_epilogue_cs);
2398       if (result != VK_SUCCESS) {
2399          cmd->record_result = result;
2400          break;
2401       }
2402    }
2403    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2404 }
2405
2406 VkResult
2407 tu_CreateCommandPool(VkDevice _device,
2408                      const VkCommandPoolCreateInfo *pCreateInfo,
2409                      const VkAllocationCallbacks *pAllocator,
2410                      VkCommandPool *pCmdPool)
2411 {
2412    TU_FROM_HANDLE(tu_device, device, _device);
2413    struct tu_cmd_pool *pool;
2414
2415    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2416                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2417    if (pool == NULL)
2418       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2419
2420    if (pAllocator)
2421       pool->alloc = *pAllocator;
2422    else
2423       pool->alloc = device->alloc;
2424
2425    list_inithead(&pool->cmd_buffers);
2426    list_inithead(&pool->free_cmd_buffers);
2427
2428    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2429
2430    *pCmdPool = tu_cmd_pool_to_handle(pool);
2431
2432    return VK_SUCCESS;
2433 }
2434
2435 void
2436 tu_DestroyCommandPool(VkDevice _device,
2437                       VkCommandPool commandPool,
2438                       const VkAllocationCallbacks *pAllocator)
2439 {
2440    TU_FROM_HANDLE(tu_device, device, _device);
2441    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2442
2443    if (!pool)
2444       return;
2445
2446    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2447                             &pool->cmd_buffers, pool_link)
2448    {
2449       tu_cmd_buffer_destroy(cmd_buffer);
2450    }
2451
2452    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2453                             &pool->free_cmd_buffers, pool_link)
2454    {
2455       tu_cmd_buffer_destroy(cmd_buffer);
2456    }
2457
2458    vk_free2(&device->alloc, pAllocator, pool);
2459 }
2460
2461 VkResult
2462 tu_ResetCommandPool(VkDevice device,
2463                     VkCommandPool commandPool,
2464                     VkCommandPoolResetFlags flags)
2465 {
2466    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2467    VkResult result;
2468
2469    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2470                        pool_link)
2471    {
2472       result = tu_reset_cmd_buffer(cmd_buffer);
2473       if (result != VK_SUCCESS)
2474          return result;
2475    }
2476
2477    return VK_SUCCESS;
2478 }
2479
2480 void
2481 tu_TrimCommandPool(VkDevice device,
2482                    VkCommandPool commandPool,
2483                    VkCommandPoolTrimFlags flags)
2484 {
2485    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2486
2487    if (!pool)
2488       return;
2489
2490    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2491                             &pool->free_cmd_buffers, pool_link)
2492    {
2493       tu_cmd_buffer_destroy(cmd_buffer);
2494    }
2495 }
2496
2497 void
2498 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2499                       const VkRenderPassBeginInfo *pRenderPassBegin,
2500                       VkSubpassContents contents)
2501 {
2502    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2503    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2504    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2505
2506    cmd->state.pass = pass;
2507    cmd->state.subpass = pass->subpasses;
2508    cmd->state.framebuffer = fb;
2509
2510    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2511    tu_cmd_prepare_tile_store_ib(cmd);
2512
2513    tu_emit_load_clear(cmd, pRenderPassBegin);
2514
2515    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2516    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2517    tu6_emit_msaa(cmd, cmd->state.subpass, &cmd->draw_cs);
2518    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2519
2520    /* note: use_hw_binning only checks tiling config */
2521    if (use_hw_binning(cmd))
2522       cmd->use_vsc_data = true;
2523
2524    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2525       const struct tu_image_view *iview = fb->attachments[i].attachment;
2526       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2527                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2528    }
2529 }
2530
2531 void
2532 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2533                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2534                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2535 {
2536    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2537                          pSubpassBeginInfo->contents);
2538 }
2539
2540 void
2541 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2542 {
2543    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2544    const struct tu_render_pass *pass = cmd->state.pass;
2545    struct tu_cs *cs = &cmd->draw_cs;
2546
2547    const struct tu_subpass *subpass = cmd->state.subpass++;
2548    /* TODO:
2549     * if msaa samples change between subpasses,
2550     * attachment store is broken for some attachments
2551     */
2552    if (subpass->resolve_attachments) {
2553       tu6_emit_blit_scissor(cmd, cs, true);
2554       for (unsigned i = 0; i < subpass->color_count; i++) {
2555          uint32_t a = subpass->resolve_attachments[i].attachment;
2556          if (a != VK_ATTACHMENT_UNUSED) {
2557             tu6_emit_resolve(cmd, cs, a,
2558                              subpass->color_attachments[i].attachment);
2559          }
2560       }
2561    }
2562
2563    /* invalidate because reading input attachments will cache GMEM and
2564     * the cache isn''t updated when GMEM is written
2565     * TODO: is there a no-cache bit for textures?
2566     */
2567    if (cmd->state.subpass->input_count)
2568       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2569
2570    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2571    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2572    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2573    tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2574    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2575
2576    /* Emit flushes so that input attachments will read the correct value. This
2577     * is for sysmem only, although it shouldn't do much harm on gmem.
2578     */
2579    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2580    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2581
2582    /* TODO:
2583     * since we don't know how to do GMEM->GMEM resolve,
2584     * resolve attachments are resolved to memory then loaded to GMEM again if needed
2585     */
2586    if (subpass->resolve_attachments) {
2587       for (unsigned i = 0; i < subpass->color_count; i++) {
2588          uint32_t a = subpass->resolve_attachments[i].attachment;
2589          if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2590                tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2591                tu6_emit_predicated_blit(cmd, cs, a, a, false);
2592          }
2593       }
2594    }
2595 }
2596
2597 void
2598 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2599                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2600                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2601 {
2602    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2603 }
2604
2605 struct tu_draw_info
2606 {
2607    /**
2608     * Number of vertices.
2609     */
2610    uint32_t count;
2611
2612    /**
2613     * Index of the first vertex.
2614     */
2615    int32_t vertex_offset;
2616
2617    /**
2618     * First instance id.
2619     */
2620    uint32_t first_instance;
2621
2622    /**
2623     * Number of instances.
2624     */
2625    uint32_t instance_count;
2626
2627    /**
2628     * First index (indexed draws only).
2629     */
2630    uint32_t first_index;
2631
2632    /**
2633     * Whether it's an indexed draw.
2634     */
2635    bool indexed;
2636
2637    /**
2638     * Indirect draw parameters resource.
2639     */
2640    struct tu_buffer *indirect;
2641    uint64_t indirect_offset;
2642    uint32_t stride;
2643
2644    /**
2645     * Draw count parameters resource.
2646     */
2647    struct tu_buffer *count_buffer;
2648    uint64_t count_buffer_offset;
2649 };
2650
2651 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2652 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2653
2654 enum tu_draw_state_group_id
2655 {
2656    TU_DRAW_STATE_PROGRAM,
2657    TU_DRAW_STATE_PROGRAM_BINNING,
2658    TU_DRAW_STATE_VI,
2659    TU_DRAW_STATE_VI_BINNING,
2660    TU_DRAW_STATE_VP,
2661    TU_DRAW_STATE_RAST,
2662    TU_DRAW_STATE_DS,
2663    TU_DRAW_STATE_BLEND,
2664    TU_DRAW_STATE_VS_CONST,
2665    TU_DRAW_STATE_FS_CONST,
2666    TU_DRAW_STATE_VS_TEX,
2667    TU_DRAW_STATE_FS_TEX_SYSMEM,
2668    TU_DRAW_STATE_FS_TEX_GMEM,
2669    TU_DRAW_STATE_FS_IBO,
2670    TU_DRAW_STATE_VS_PARAMS,
2671
2672    TU_DRAW_STATE_COUNT,
2673 };
2674
2675 struct tu_draw_state_group
2676 {
2677    enum tu_draw_state_group_id id;
2678    uint32_t enable_mask;
2679    struct tu_cs_entry ib;
2680 };
2681
2682 const static struct tu_sampler*
2683 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2684             const struct tu_descriptor_map *map, unsigned i,
2685             unsigned array_index)
2686 {
2687    assert(descriptors_state->valid & (1 << map->set[i]));
2688
2689    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2690    assert(map->binding[i] < set->layout->binding_count);
2691
2692    const struct tu_descriptor_set_binding_layout *layout =
2693       &set->layout->binding[map->binding[i]];
2694
2695    if (layout->immutable_samplers_offset) {
2696       const struct tu_sampler *immutable_samplers =
2697          tu_immutable_samplers(set->layout, layout);
2698
2699       return &immutable_samplers[array_index];
2700    }
2701
2702    switch (layout->type) {
2703    case VK_DESCRIPTOR_TYPE_SAMPLER:
2704       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2705    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2706       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2707                                                    array_index *
2708                                                    (A6XX_TEX_CONST_DWORDS +
2709                                                     sizeof(struct tu_sampler) / 4)];
2710    default:
2711       unreachable("unimplemented descriptor type");
2712       break;
2713    }
2714 }
2715
2716 static void
2717 write_tex_const(struct tu_cmd_buffer *cmd,
2718                 uint32_t *dst,
2719                 struct tu_descriptor_state *descriptors_state,
2720                 const struct tu_descriptor_map *map,
2721                 unsigned i, unsigned array_index, bool is_sysmem)
2722 {
2723    assert(descriptors_state->valid & (1 << map->set[i]));
2724
2725    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2726    assert(map->binding[i] < set->layout->binding_count);
2727
2728    const struct tu_descriptor_set_binding_layout *layout =
2729       &set->layout->binding[map->binding[i]];
2730
2731    switch (layout->type) {
2732    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2733    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2734    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2735    case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2736       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2737                                    array_index * A6XX_TEX_CONST_DWORDS],
2738              A6XX_TEX_CONST_DWORDS * 4);
2739       break;
2740    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2741       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2742                                    array_index *
2743                                    (A6XX_TEX_CONST_DWORDS +
2744                                     sizeof(struct tu_sampler) / 4)],
2745              A6XX_TEX_CONST_DWORDS * 4);
2746       break;
2747    default:
2748       unreachable("unimplemented descriptor type");
2749       break;
2750    }
2751
2752    if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
2753       const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2754       uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2755                                                          array_index].attachment;
2756       const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2757
2758       assert(att->gmem_offset >= 0);
2759
2760       dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2761       dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2762       dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2763       dst[2] |=
2764          A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2765          A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2766       dst[3] = 0;
2767       dst[4] = 0x100000 + att->gmem_offset;
2768       dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2769       for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2770          dst[i] = 0;
2771
2772       if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2773          tu_finishme("patch input attachment pitch for secondary cmd buffer");
2774    }
2775 }
2776
2777 static void
2778 write_image_ibo(struct tu_cmd_buffer *cmd,
2779                 uint32_t *dst,
2780                 struct tu_descriptor_state *descriptors_state,
2781                 const struct tu_descriptor_map *map,
2782                 unsigned i, unsigned array_index)
2783 {
2784    assert(descriptors_state->valid & (1 << map->set[i]));
2785
2786    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2787    assert(map->binding[i] < set->layout->binding_count);
2788
2789    const struct tu_descriptor_set_binding_layout *layout =
2790       &set->layout->binding[map->binding[i]];
2791
2792    assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2793
2794    memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2795                                 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2796           A6XX_TEX_CONST_DWORDS * 4);
2797 }
2798
2799 static uint64_t
2800 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2801            const struct tu_descriptor_map *map,
2802            unsigned i, unsigned array_index)
2803 {
2804    assert(descriptors_state->valid & (1 << map->set[i]));
2805
2806    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2807    assert(map->binding[i] < set->layout->binding_count);
2808
2809    const struct tu_descriptor_set_binding_layout *layout =
2810       &set->layout->binding[map->binding[i]];
2811
2812    switch (layout->type) {
2813    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2814    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2815       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2816                                                 array_index];
2817    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2818    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2819       return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2820                         set->mapped_ptr[layout->offset / 4 + array_index * 2];
2821    default:
2822       unreachable("unimplemented descriptor type");
2823       break;
2824    }
2825 }
2826
2827 static inline uint32_t
2828 tu6_stage2opcode(gl_shader_stage type)
2829 {
2830    switch (type) {
2831    case MESA_SHADER_VERTEX:
2832    case MESA_SHADER_TESS_CTRL:
2833    case MESA_SHADER_TESS_EVAL:
2834    case MESA_SHADER_GEOMETRY:
2835       return CP_LOAD_STATE6_GEOM;
2836    case MESA_SHADER_FRAGMENT:
2837    case MESA_SHADER_COMPUTE:
2838    case MESA_SHADER_KERNEL:
2839       return CP_LOAD_STATE6_FRAG;
2840    default:
2841       unreachable("bad shader type");
2842    }
2843 }
2844
2845 static inline enum a6xx_state_block
2846 tu6_stage2shadersb(gl_shader_stage type)
2847 {
2848    switch (type) {
2849    case MESA_SHADER_VERTEX:
2850       return SB6_VS_SHADER;
2851    case MESA_SHADER_FRAGMENT:
2852       return SB6_FS_SHADER;
2853    case MESA_SHADER_COMPUTE:
2854    case MESA_SHADER_KERNEL:
2855       return SB6_CS_SHADER;
2856    default:
2857       unreachable("bad shader type");
2858       return ~0;
2859    }
2860 }
2861
2862 static void
2863 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2864                      struct tu_descriptor_state *descriptors_state,
2865                      gl_shader_stage type,
2866                      uint32_t *push_constants)
2867 {
2868    const struct tu_program_descriptor_linkage *link =
2869       &pipeline->program.link[type];
2870    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2871
2872    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2873       if (state->range[i].start < state->range[i].end) {
2874          uint32_t size = state->range[i].end - state->range[i].start;
2875          uint32_t offset = state->range[i].start;
2876
2877          /* and even if the start of the const buffer is before
2878           * first_immediate, the end may not be:
2879           */
2880          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2881
2882          if (size == 0)
2883             continue;
2884
2885          /* things should be aligned to vec4: */
2886          debug_assert((state->range[i].offset % 16) == 0);
2887          debug_assert((size % 16) == 0);
2888          debug_assert((offset % 16) == 0);
2889
2890          if (i == 0) {
2891             /* push constants */
2892             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2893             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2894                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2895                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2896                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2897                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2898             tu_cs_emit(cs, 0);
2899             tu_cs_emit(cs, 0);
2900             for (unsigned i = 0; i < size / 4; i++)
2901                tu_cs_emit(cs, push_constants[i + offset / 4]);
2902             continue;
2903          }
2904
2905          /* Look through the UBO map to find our UBO index, and get the VA for
2906           * that UBO.
2907           */
2908          uint64_t va = 0;
2909          uint32_t ubo_idx = i - 1;
2910          uint32_t ubo_map_base = 0;
2911          for (int j = 0; j < link->ubo_map.num; j++) {
2912             if (ubo_idx >= ubo_map_base &&
2913                 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2914                va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2915                                ubo_idx - ubo_map_base);
2916                break;
2917             }
2918             ubo_map_base += link->ubo_map.array_size[j];
2919          }
2920          assert(va);
2921
2922          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2923          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2924                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2925                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2926                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2927                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2928          tu_cs_emit_qw(cs, va + offset);
2929       }
2930    }
2931 }
2932
2933 static void
2934 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2935               struct tu_descriptor_state *descriptors_state,
2936               gl_shader_stage type)
2937 {
2938    const struct tu_program_descriptor_linkage *link =
2939       &pipeline->program.link[type];
2940
2941    uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2942    uint32_t anum = align(num, 2);
2943
2944    if (!num)
2945       return;
2946
2947    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2948    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2949          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2950          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2951          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2952          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2953    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2954    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2955
2956    unsigned emitted = 0;
2957    for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2958       for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2959          tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2960          emitted++;
2961       }
2962    }
2963
2964    for (; emitted < anum; emitted++) {
2965       tu_cs_emit(cs, 0xffffffff);
2966       tu_cs_emit(cs, 0xffffffff);
2967    }
2968 }
2969
2970 static struct tu_cs_entry
2971 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2972                 const struct tu_pipeline *pipeline,
2973                 struct tu_descriptor_state *descriptors_state,
2974                 gl_shader_stage type)
2975 {
2976    struct tu_cs cs;
2977    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2978
2979    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2980    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2981
2982    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2983 }
2984
2985 static VkResult
2986 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2987                    const struct tu_draw_info *draw,
2988                    struct tu_cs_entry *entry)
2989 {
2990    /* TODO: fill out more than just base instance */
2991    const struct tu_program_descriptor_linkage *link =
2992       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2993    const struct ir3_const_state *const_state = &link->const_state;
2994    struct tu_cs cs;
2995
2996    if (const_state->offsets.driver_param >= link->constlen) {
2997       *entry = (struct tu_cs_entry) {};
2998       return VK_SUCCESS;
2999    }
3000
3001    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
3002    if (result != VK_SUCCESS)
3003       return result;
3004
3005    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3006    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
3007          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3008          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3009          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
3010          CP_LOAD_STATE6_0_NUM_UNIT(1));
3011    tu_cs_emit(&cs, 0);
3012    tu_cs_emit(&cs, 0);
3013
3014    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
3015
3016    tu_cs_emit(&cs, 0);
3017    tu_cs_emit(&cs, 0);
3018    tu_cs_emit(&cs, draw->first_instance);
3019    tu_cs_emit(&cs, 0);
3020
3021    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3022    return VK_SUCCESS;
3023 }
3024
3025 static VkResult
3026 tu6_emit_textures(struct tu_cmd_buffer *cmd,
3027                   const struct tu_pipeline *pipeline,
3028                   struct tu_descriptor_state *descriptors_state,
3029                   gl_shader_stage type,
3030                   struct tu_cs_entry *entry,
3031                   bool *needs_border,
3032                   bool is_sysmem)
3033 {
3034    struct tu_cs *draw_state = &cmd->sub_cs;
3035    const struct tu_program_descriptor_linkage *link =
3036       &pipeline->program.link[type];
3037    VkResult result;
3038
3039    if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
3040       *entry = (struct tu_cs_entry) {};
3041       return VK_SUCCESS;
3042    }
3043
3044    /* allocate and fill texture state */
3045    struct ts_cs_memory tex_const;
3046    result = tu_cs_alloc(draw_state, link->texture_map.num_desc,
3047                         A6XX_TEX_CONST_DWORDS, &tex_const);
3048    if (result != VK_SUCCESS)
3049       return result;
3050
3051    int tex_index = 0;
3052    for (unsigned i = 0; i < link->texture_map.num; i++) {
3053       for (int j = 0; j < link->texture_map.array_size[i]; j++) {
3054          write_tex_const(cmd,
3055                          &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
3056                          descriptors_state, &link->texture_map, i, j,
3057                          is_sysmem);
3058       }
3059    }
3060
3061    /* allocate and fill sampler state */
3062    struct ts_cs_memory tex_samp = { 0 };
3063    if (link->sampler_map.num_desc) {
3064       result = tu_cs_alloc(draw_state, link->sampler_map.num_desc,
3065                            A6XX_TEX_SAMP_DWORDS, &tex_samp);
3066       if (result != VK_SUCCESS)
3067          return result;
3068
3069       int sampler_index = 0;
3070       for (unsigned i = 0; i < link->sampler_map.num; i++) {
3071          for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
3072             const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3073                                                            &link->sampler_map,
3074                                                            i, j);
3075             memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
3076                    sampler->state, sizeof(sampler->state));
3077             *needs_border |= sampler->needs_border;
3078          }
3079       }
3080    }
3081
3082    unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
3083    enum a6xx_state_block sb;
3084
3085    switch (type) {
3086    case MESA_SHADER_VERTEX:
3087       sb = SB6_VS_TEX;
3088       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
3089       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
3090       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
3091       break;
3092    case MESA_SHADER_FRAGMENT:
3093       sb = SB6_FS_TEX;
3094       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
3095       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
3096       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
3097       break;
3098    case MESA_SHADER_COMPUTE:
3099       sb = SB6_CS_TEX;
3100       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
3101       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
3102       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
3103       break;
3104    default:
3105       unreachable("bad state block");
3106    }
3107
3108    struct tu_cs cs;
3109    result = tu_cs_begin_sub_stream(draw_state, 16, &cs);
3110    if (result != VK_SUCCESS)
3111       return result;
3112
3113    if (link->sampler_map.num_desc) {
3114       /* output sampler state: */
3115       tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3116       tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3117                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
3118                  CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3119                  CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3120                  CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
3121       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3122
3123       tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
3124       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3125    }
3126
3127    /* emit texture state: */
3128    tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3129    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3130       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3131       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3132       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3133       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
3134    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3135
3136    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
3137    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3138
3139    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
3140    tu_cs_emit(&cs, link->texture_map.num_desc);
3141
3142    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3143    return VK_SUCCESS;
3144 }
3145
3146 static VkResult
3147 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
3148              const struct tu_pipeline *pipeline,
3149              struct tu_descriptor_state *descriptors_state,
3150              gl_shader_stage type,
3151              struct tu_cs_entry *entry)
3152 {
3153    struct tu_cs *draw_state = &cmd->sub_cs;
3154    const struct tu_program_descriptor_linkage *link =
3155       &pipeline->program.link[type];
3156    VkResult result;
3157
3158    unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
3159
3160    if (num_desc == 0) {
3161       *entry = (struct tu_cs_entry) {};
3162       return VK_SUCCESS;
3163    }
3164
3165    struct ts_cs_memory ibo_const;
3166    result = tu_cs_alloc(draw_state, num_desc,
3167                         A6XX_TEX_CONST_DWORDS, &ibo_const);
3168    if (result != VK_SUCCESS)
3169       return result;
3170
3171    int ssbo_index = 0;
3172    for (unsigned i = 0; i < link->ssbo_map.num; i++) {
3173       for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
3174          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3175
3176          uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
3177          /* We don't expose robustBufferAccess, so leave the size unlimited. */
3178          uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
3179
3180          dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
3181          dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
3182                   A6XX_IBO_1_HEIGHT(sz >> 15);
3183          dst[2] = A6XX_IBO_2_UNK4 |
3184                   A6XX_IBO_2_UNK31 |
3185                   A6XX_IBO_2_TYPE(A6XX_TEX_1D);
3186          dst[3] = 0;
3187          dst[4] = va;
3188          dst[5] = va >> 32;
3189          for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
3190             dst[i] = 0;
3191
3192          ssbo_index++;
3193       }
3194    }
3195
3196    for (unsigned i = 0; i < link->image_map.num; i++) {
3197       for (int j = 0; j < link->image_map.array_size[i]; j++) {
3198          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3199
3200          write_image_ibo(cmd, dst,
3201                          descriptors_state, &link->image_map, i, j);
3202
3203          ssbo_index++;
3204       }
3205    }
3206
3207    assert(ssbo_index == num_desc);
3208
3209    struct tu_cs cs;
3210    result = tu_cs_begin_sub_stream(draw_state, 7, &cs);
3211    if (result != VK_SUCCESS)
3212       return result;
3213
3214    uint32_t opcode, ibo_addr_reg;
3215    enum a6xx_state_block sb;
3216    enum a6xx_state_type st;
3217
3218    switch (type) {
3219    case MESA_SHADER_FRAGMENT:
3220       opcode = CP_LOAD_STATE6;
3221       st = ST6_SHADER;
3222       sb = SB6_IBO;
3223       ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3224       break;
3225    case MESA_SHADER_COMPUTE:
3226       opcode = CP_LOAD_STATE6_FRAG;
3227       st = ST6_IBO;
3228       sb = SB6_CS_SHADER;
3229       ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3230       break;
3231    default:
3232       unreachable("unsupported stage for ibos");
3233    }
3234
3235    /* emit texture state: */
3236    tu_cs_emit_pkt7(&cs, opcode, 3);
3237    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3238               CP_LOAD_STATE6_0_STATE_TYPE(st) |
3239               CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3240               CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3241               CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3242    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3243
3244    tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3245    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3246
3247    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3248    return VK_SUCCESS;
3249 }
3250
3251 struct PACKED bcolor_entry {
3252    uint32_t fp32[4];
3253    uint16_t ui16[4];
3254    int16_t  si16[4];
3255    uint16_t fp16[4];
3256    uint16_t rgb565;
3257    uint16_t rgb5a1;
3258    uint16_t rgba4;
3259    uint8_t __pad0[2];
3260    uint8_t  ui8[4];
3261    int8_t   si8[4];
3262    uint32_t rgb10a2;
3263    uint32_t z24; /* also s8? */
3264    uint16_t srgb[4];      /* appears to duplicate fp16[], but clamped, used for srgb */
3265    uint8_t  __pad1[56];
3266 } border_color[] = {
3267    [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3268    [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3269    [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3270       .fp32[3] = 0x3f800000,
3271       .ui16[3] = 0xffff,
3272       .si16[3] = 0x7fff,
3273       .fp16[3] = 0x3c00,
3274       .rgb5a1 = 0x8000,
3275       .rgba4 = 0xf000,
3276       .ui8[3] = 0xff,
3277       .si8[3] = 0x7f,
3278       .rgb10a2 = 0xc0000000,
3279       .srgb[3] = 0x3c00,
3280    },
3281    [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3282       .fp32[3] = 1,
3283       .fp16[3] = 1,
3284    },
3285    [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3286       .fp32[0 ... 3] = 0x3f800000,
3287       .ui16[0 ... 3] = 0xffff,
3288       .si16[0 ... 3] = 0x7fff,
3289       .fp16[0 ... 3] = 0x3c00,
3290       .rgb565 = 0xffff,
3291       .rgb5a1 = 0xffff,
3292       .rgba4 = 0xffff,
3293       .ui8[0 ... 3] = 0xff,
3294       .si8[0 ... 3] = 0x7f,
3295       .rgb10a2 = 0xffffffff,
3296       .z24 = 0xffffff,
3297       .srgb[0 ... 3] = 0x3c00,
3298    },
3299    [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3300       .fp32[0 ... 3] = 1,
3301       .fp16[0 ... 3] = 1,
3302    },
3303 };
3304
3305 static VkResult
3306 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3307                       struct tu_cs *cs)
3308 {
3309    STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3310
3311    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3312    struct tu_descriptor_state *descriptors_state =
3313       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3314    const struct tu_descriptor_map *vs_sampler =
3315       &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3316    const struct tu_descriptor_map *fs_sampler =
3317       &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3318    struct ts_cs_memory ptr;
3319
3320    VkResult result = tu_cs_alloc(&cmd->sub_cs,
3321                                  vs_sampler->num_desc + fs_sampler->num_desc,
3322                                  128 / 4,
3323                                  &ptr);
3324    if (result != VK_SUCCESS)
3325       return result;
3326
3327    for (unsigned i = 0; i < vs_sampler->num; i++) {
3328       for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3329          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3330                                                         vs_sampler, i, j);
3331          memcpy(ptr.map, &border_color[sampler->border], 128);
3332          ptr.map += 128 / 4;
3333       }
3334    }
3335
3336    for (unsigned i = 0; i < fs_sampler->num; i++) {
3337       for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3338          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3339                                                         fs_sampler, i, j);
3340          memcpy(ptr.map, &border_color[sampler->border], 128);
3341          ptr.map += 128 / 4;
3342       }
3343    }
3344
3345    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3346    tu_cs_emit_qw(cs, ptr.iova);
3347    return VK_SUCCESS;
3348 }
3349
3350 static VkResult
3351 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3352                      struct tu_cs *cs,
3353                      const struct tu_draw_info *draw)
3354 {
3355    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3356    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3357    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3358    uint32_t draw_state_group_count = 0;
3359    VkResult result;
3360
3361    struct tu_descriptor_state *descriptors_state =
3362       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3363
3364    /* TODO lrz */
3365
3366    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3367    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3368    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3369
3370    tu_cs_emit_regs(cs,
3371                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3372                                             pipeline->ia.primitive_restart && draw->indexed));
3373
3374    if (cmd->state.dirty &
3375           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3376        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3377       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3378                             dynamic->line_width);
3379    }
3380
3381    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3382        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3383       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3384                                     dynamic->stencil_compare_mask.back);
3385    }
3386
3387    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3388        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3389       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3390                                   dynamic->stencil_write_mask.back);
3391    }
3392
3393    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3394        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3395       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3396                                  dynamic->stencil_reference.back);
3397    }
3398
3399    if (cmd->state.dirty &
3400        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3401       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3402          const uint32_t binding = pipeline->vi.bindings[i];
3403          const uint32_t stride = pipeline->vi.strides[i];
3404          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3405          const VkDeviceSize offset = buf->bo_offset +
3406                                      cmd->state.vb.offsets[binding] +
3407                                      pipeline->vi.offsets[i];
3408          const VkDeviceSize size =
3409             offset < buf->bo->size ? buf->bo->size - offset : 0;
3410
3411          tu_cs_emit_regs(cs,
3412                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3413                          A6XX_VFD_FETCH_SIZE(i, size),
3414                          A6XX_VFD_FETCH_STRIDE(i, stride));
3415       }
3416    }
3417
3418    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3419       draw_state_groups[draw_state_group_count++] =
3420          (struct tu_draw_state_group) {
3421             .id = TU_DRAW_STATE_PROGRAM,
3422             .enable_mask = ENABLE_DRAW,
3423             .ib = pipeline->program.state_ib,
3424          };
3425       draw_state_groups[draw_state_group_count++] =
3426          (struct tu_draw_state_group) {
3427             .id = TU_DRAW_STATE_PROGRAM_BINNING,
3428             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3429             .ib = pipeline->program.binning_state_ib,
3430          };
3431       draw_state_groups[draw_state_group_count++] =
3432          (struct tu_draw_state_group) {
3433             .id = TU_DRAW_STATE_VI,
3434             .enable_mask = ENABLE_DRAW,
3435             .ib = pipeline->vi.state_ib,
3436          };
3437       draw_state_groups[draw_state_group_count++] =
3438          (struct tu_draw_state_group) {
3439             .id = TU_DRAW_STATE_VI_BINNING,
3440             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3441             .ib = pipeline->vi.binning_state_ib,
3442          };
3443       draw_state_groups[draw_state_group_count++] =
3444          (struct tu_draw_state_group) {
3445             .id = TU_DRAW_STATE_VP,
3446             .enable_mask = ENABLE_ALL,
3447             .ib = pipeline->vp.state_ib,
3448          };
3449       draw_state_groups[draw_state_group_count++] =
3450          (struct tu_draw_state_group) {
3451             .id = TU_DRAW_STATE_RAST,
3452             .enable_mask = ENABLE_ALL,
3453             .ib = pipeline->rast.state_ib,
3454          };
3455       draw_state_groups[draw_state_group_count++] =
3456          (struct tu_draw_state_group) {
3457             .id = TU_DRAW_STATE_DS,
3458             .enable_mask = ENABLE_ALL,
3459             .ib = pipeline->ds.state_ib,
3460          };
3461       draw_state_groups[draw_state_group_count++] =
3462          (struct tu_draw_state_group) {
3463             .id = TU_DRAW_STATE_BLEND,
3464             .enable_mask = ENABLE_ALL,
3465             .ib = pipeline->blend.state_ib,
3466          };
3467    }
3468
3469    if (cmd->state.dirty &
3470          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3471       draw_state_groups[draw_state_group_count++] =
3472          (struct tu_draw_state_group) {
3473             .id = TU_DRAW_STATE_VS_CONST,
3474             .enable_mask = ENABLE_ALL,
3475             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3476          };
3477       draw_state_groups[draw_state_group_count++] =
3478          (struct tu_draw_state_group) {
3479             .id = TU_DRAW_STATE_FS_CONST,
3480             .enable_mask = ENABLE_DRAW,
3481             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3482          };
3483    }
3484
3485    if (cmd->state.dirty &
3486          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3487       bool needs_border = false;
3488       struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
3489
3490       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3491                                  MESA_SHADER_VERTEX, &vs_tex, &needs_border,
3492                                  false);
3493       if (result != VK_SUCCESS)
3494          return result;
3495
3496       /* TODO: we could emit just one texture descriptor draw state when there
3497        * are no input attachments, which is the most common case. We could
3498        * also split out the sampler state, which doesn't change even for input
3499        * attachments.
3500        */
3501       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3502                                  MESA_SHADER_FRAGMENT, &fs_tex_sysmem,
3503                                  &needs_border, true);
3504       if (result != VK_SUCCESS)
3505          return result;
3506
3507       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3508                                  MESA_SHADER_FRAGMENT, &fs_tex_gmem,
3509                                  &needs_border, false);
3510       if (result != VK_SUCCESS)
3511          return result;
3512
3513       result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3514                             MESA_SHADER_FRAGMENT, &fs_ibo);
3515       if (result != VK_SUCCESS)
3516          return result;
3517
3518       draw_state_groups[draw_state_group_count++] =
3519          (struct tu_draw_state_group) {
3520             .id = TU_DRAW_STATE_VS_TEX,
3521             .enable_mask = ENABLE_ALL,
3522             .ib = vs_tex,
3523          };
3524       draw_state_groups[draw_state_group_count++] =
3525          (struct tu_draw_state_group) {
3526             .id = TU_DRAW_STATE_FS_TEX_GMEM,
3527             .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3528             .ib = fs_tex_gmem,
3529          };
3530       draw_state_groups[draw_state_group_count++] =
3531          (struct tu_draw_state_group) {
3532             .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
3533             .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
3534             .ib = fs_tex_sysmem,
3535          };
3536       draw_state_groups[draw_state_group_count++] =
3537          (struct tu_draw_state_group) {
3538             .id = TU_DRAW_STATE_FS_IBO,
3539             .enable_mask = ENABLE_DRAW,
3540             .ib = fs_ibo,
3541          };
3542
3543       if (needs_border) {
3544          result = tu6_emit_border_color(cmd, cs);
3545          if (result != VK_SUCCESS)
3546             return result;
3547       }
3548    }
3549
3550    struct tu_cs_entry vs_params;
3551    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3552    if (result != VK_SUCCESS)
3553       return result;
3554
3555    draw_state_groups[draw_state_group_count++] =
3556       (struct tu_draw_state_group) {
3557          .id = TU_DRAW_STATE_VS_PARAMS,
3558          .enable_mask = ENABLE_ALL,
3559          .ib = vs_params,
3560       };
3561
3562    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3563    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3564       const struct tu_draw_state_group *group = &draw_state_groups[i];
3565       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3566       uint32_t cp_set_draw_state =
3567          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3568          group->enable_mask |
3569          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3570       uint64_t iova;
3571       if (group->ib.size) {
3572          iova = group->ib.bo->iova + group->ib.offset;
3573       } else {
3574          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3575          iova = 0;
3576       }
3577
3578       tu_cs_emit(cs, cp_set_draw_state);
3579       tu_cs_emit_qw(cs, iova);
3580    }
3581
3582    tu_cs_sanity_check(cs);
3583
3584    /* track BOs */
3585    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3586       for (uint32_t i = 0; i < MAX_VBS; i++) {
3587          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3588          if (buf)
3589             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3590       }
3591    }
3592    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3593       unsigned i;
3594       for_each_bit(i, descriptors_state->valid) {
3595          struct tu_descriptor_set *set = descriptors_state->sets[i];
3596          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3597             if (set->descriptors[j]) {
3598                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3599                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3600             }
3601       }
3602    }
3603
3604    /* Fragment shader state overwrites compute shader state, so flag the
3605     * compute pipeline for re-emit.
3606     */
3607    cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3608    return VK_SUCCESS;
3609 }
3610
3611 static void
3612 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3613                      struct tu_cs *cs,
3614                      const struct tu_draw_info *draw)
3615 {
3616
3617    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3618
3619    tu_cs_emit_regs(cs,
3620                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3621                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3622
3623    /* TODO hw binning */
3624    if (draw->indexed) {
3625       const enum a4xx_index_size index_size =
3626          tu6_index_size(cmd->state.index_type);
3627       const uint32_t index_bytes =
3628          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3629       const struct tu_buffer *buf = cmd->state.index_buffer;
3630       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3631                                   index_bytes * draw->first_index;
3632       const uint32_t size = index_bytes * draw->count;
3633
3634       const uint32_t cp_draw_indx =
3635          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3636          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3637          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3638          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3639
3640       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3641       tu_cs_emit(cs, cp_draw_indx);
3642       tu_cs_emit(cs, draw->instance_count);
3643       tu_cs_emit(cs, draw->count);
3644       tu_cs_emit(cs, 0x0); /* XXX */
3645       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3646       tu_cs_emit(cs, size);
3647    } else {
3648       const uint32_t cp_draw_indx =
3649          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3650          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3651          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3652
3653       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3654       tu_cs_emit(cs, cp_draw_indx);
3655       tu_cs_emit(cs, draw->instance_count);
3656       tu_cs_emit(cs, draw->count);
3657    }
3658 }
3659
3660 static void
3661 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3662 {
3663    struct tu_cs *cs = &cmd->draw_cs;
3664    VkResult result;
3665
3666    result = tu6_bind_draw_states(cmd, cs, draw);
3667    if (result != VK_SUCCESS) {
3668       cmd->record_result = result;
3669       return;
3670    }
3671
3672    if (draw->indirect) {
3673       tu_finishme("indirect draw");
3674       return;
3675    }
3676
3677    tu6_emit_draw_direct(cmd, cs, draw);
3678
3679    cmd->wait_for_idle = true;
3680
3681    tu_cs_sanity_check(cs);
3682 }
3683
3684 void
3685 tu_CmdDraw(VkCommandBuffer commandBuffer,
3686            uint32_t vertexCount,
3687            uint32_t instanceCount,
3688            uint32_t firstVertex,
3689            uint32_t firstInstance)
3690 {
3691    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3692    struct tu_draw_info info = {};
3693
3694    info.count = vertexCount;
3695    info.instance_count = instanceCount;
3696    info.first_instance = firstInstance;
3697    info.vertex_offset = firstVertex;
3698
3699    tu_draw(cmd_buffer, &info);
3700 }
3701
3702 void
3703 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3704                   uint32_t indexCount,
3705                   uint32_t instanceCount,
3706                   uint32_t firstIndex,
3707                   int32_t vertexOffset,
3708                   uint32_t firstInstance)
3709 {
3710    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3711    struct tu_draw_info info = {};
3712
3713    info.indexed = true;
3714    info.count = indexCount;
3715    info.instance_count = instanceCount;
3716    info.first_index = firstIndex;
3717    info.vertex_offset = vertexOffset;
3718    info.first_instance = firstInstance;
3719
3720    tu_draw(cmd_buffer, &info);
3721 }
3722
3723 void
3724 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3725                    VkBuffer _buffer,
3726                    VkDeviceSize offset,
3727                    uint32_t drawCount,
3728                    uint32_t stride)
3729 {
3730    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3731    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3732    struct tu_draw_info info = {};
3733
3734    info.count = drawCount;
3735    info.indirect = buffer;
3736    info.indirect_offset = offset;
3737    info.stride = stride;
3738
3739    tu_draw(cmd_buffer, &info);
3740 }
3741
3742 void
3743 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3744                           VkBuffer _buffer,
3745                           VkDeviceSize offset,
3746                           uint32_t drawCount,
3747                           uint32_t stride)
3748 {
3749    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3750    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3751    struct tu_draw_info info = {};
3752
3753    info.indexed = true;
3754    info.count = drawCount;
3755    info.indirect = buffer;
3756    info.indirect_offset = offset;
3757    info.stride = stride;
3758
3759    tu_draw(cmd_buffer, &info);
3760 }
3761
3762 struct tu_dispatch_info
3763 {
3764    /**
3765     * Determine the layout of the grid (in block units) to be used.
3766     */
3767    uint32_t blocks[3];
3768
3769    /**
3770     * A starting offset for the grid. If unaligned is set, the offset
3771     * must still be aligned.
3772     */
3773    uint32_t offsets[3];
3774    /**
3775     * Whether it's an unaligned compute dispatch.
3776     */
3777    bool unaligned;
3778
3779    /**
3780     * Indirect compute parameters resource.
3781     */
3782    struct tu_buffer *indirect;
3783    uint64_t indirect_offset;
3784 };
3785
3786 static void
3787 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3788                               const struct tu_dispatch_info *info)
3789 {
3790    gl_shader_stage type = MESA_SHADER_COMPUTE;
3791    const struct tu_program_descriptor_linkage *link =
3792       &pipeline->program.link[type];
3793    const struct ir3_const_state *const_state = &link->const_state;
3794    uint32_t offset = const_state->offsets.driver_param;
3795
3796    if (link->constlen <= offset)
3797       return;
3798
3799    if (!info->indirect) {
3800       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3801          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3802          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3803          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3804          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3805          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3806          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3807       };
3808
3809       uint32_t num_consts = MIN2(const_state->num_driver_params,
3810                                  (link->constlen - offset) * 4);
3811       /* push constants */
3812       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3813       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3814                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3815                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3816                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3817                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3818       tu_cs_emit(cs, 0);
3819       tu_cs_emit(cs, 0);
3820       uint32_t i;
3821       for (i = 0; i < num_consts; i++)
3822          tu_cs_emit(cs, driver_params[i]);
3823    } else {
3824       tu_finishme("Indirect driver params");
3825    }
3826 }
3827
3828 static void
3829 tu_dispatch(struct tu_cmd_buffer *cmd,
3830             const struct tu_dispatch_info *info)
3831 {
3832    struct tu_cs *cs = &cmd->cs;
3833    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3834    struct tu_descriptor_state *descriptors_state =
3835       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3836    VkResult result;
3837
3838    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3839       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3840
3841    struct tu_cs_entry ib;
3842
3843    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3844    if (ib.size)
3845       tu_cs_emit_ib(cs, &ib);
3846
3847    tu_emit_compute_driver_params(cs, pipeline, info);
3848
3849    bool needs_border;
3850    result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3851                               MESA_SHADER_COMPUTE, &ib, &needs_border, false);
3852    if (result != VK_SUCCESS) {
3853       cmd->record_result = result;
3854       return;
3855    }
3856
3857    if (ib.size)
3858       tu_cs_emit_ib(cs, &ib);
3859
3860    if (needs_border)
3861       tu_finishme("compute border color");
3862
3863    result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3864    if (result != VK_SUCCESS) {
3865       cmd->record_result = result;
3866       return;
3867    }
3868
3869    if (ib.size)
3870       tu_cs_emit_ib(cs, &ib);
3871
3872    /* track BOs */
3873    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3874       unsigned i;
3875       for_each_bit(i, descriptors_state->valid) {
3876          struct tu_descriptor_set *set = descriptors_state->sets[i];
3877          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3878             if (set->descriptors[j]) {
3879                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3880                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3881             }
3882       }
3883    }
3884
3885    /* Compute shader state overwrites fragment shader state, so we flag the
3886     * graphics pipeline for re-emit.
3887     */
3888    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3889
3890    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3891    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3892
3893    const uint32_t *local_size = pipeline->compute.local_size;
3894    const uint32_t *num_groups = info->blocks;
3895    tu_cs_emit_regs(cs,
3896                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3897                                           .localsizex = local_size[0] - 1,
3898                                           .localsizey = local_size[1] - 1,
3899                                           .localsizez = local_size[2] - 1),
3900                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3901                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3902                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3903                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3904                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3905                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3906
3907    tu_cs_emit_regs(cs,
3908                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3909                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3910                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3911
3912    if (info->indirect) {
3913       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3914
3915       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3916                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3917
3918       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3919       tu_cs_emit(cs, 0x00000000);
3920       tu_cs_emit_qw(cs, iova);
3921       tu_cs_emit(cs,
3922                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3923                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3924                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3925    } else {
3926       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3927       tu_cs_emit(cs, 0x00000000);
3928       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3929       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3930       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3931    }
3932
3933    tu_cs_emit_wfi(cs);
3934
3935    tu6_emit_cache_flush(cmd, cs);
3936 }
3937
3938 void
3939 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3940                    uint32_t base_x,
3941                    uint32_t base_y,
3942                    uint32_t base_z,
3943                    uint32_t x,
3944                    uint32_t y,
3945                    uint32_t z)
3946 {
3947    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3948    struct tu_dispatch_info info = {};
3949
3950    info.blocks[0] = x;
3951    info.blocks[1] = y;
3952    info.blocks[2] = z;
3953
3954    info.offsets[0] = base_x;
3955    info.offsets[1] = base_y;
3956    info.offsets[2] = base_z;
3957    tu_dispatch(cmd_buffer, &info);
3958 }
3959
3960 void
3961 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3962                uint32_t x,
3963                uint32_t y,
3964                uint32_t z)
3965 {
3966    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3967 }
3968
3969 void
3970 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3971                        VkBuffer _buffer,
3972                        VkDeviceSize offset)
3973 {
3974    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3975    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3976    struct tu_dispatch_info info = {};
3977
3978    info.indirect = buffer;
3979    info.indirect_offset = offset;
3980
3981    tu_dispatch(cmd_buffer, &info);
3982 }
3983
3984 void
3985 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3986 {
3987    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3988
3989    tu_cs_end(&cmd_buffer->draw_cs);
3990    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3991
3992    if (use_sysmem_rendering(cmd_buffer))
3993       tu_cmd_render_sysmem(cmd_buffer);
3994    else
3995       tu_cmd_render_tiles(cmd_buffer);
3996
3997    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3998       rendered */
3999    tu_cs_discard_entries(&cmd_buffer->draw_cs);
4000    tu_cs_begin(&cmd_buffer->draw_cs);
4001    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
4002    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
4003
4004    cmd_buffer->state.pass = NULL;
4005    cmd_buffer->state.subpass = NULL;
4006    cmd_buffer->state.framebuffer = NULL;
4007 }
4008
4009 void
4010 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
4011                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
4012 {
4013    tu_CmdEndRenderPass(commandBuffer);
4014 }
4015
4016 struct tu_barrier_info
4017 {
4018    uint32_t eventCount;
4019    const VkEvent *pEvents;
4020    VkPipelineStageFlags srcStageMask;
4021 };
4022
4023 static void
4024 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
4025            uint32_t memoryBarrierCount,
4026            const VkMemoryBarrier *pMemoryBarriers,
4027            uint32_t bufferMemoryBarrierCount,
4028            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4029            uint32_t imageMemoryBarrierCount,
4030            const VkImageMemoryBarrier *pImageMemoryBarriers,
4031            const struct tu_barrier_info *info)
4032 {
4033 }
4034
4035 void
4036 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
4037                       VkPipelineStageFlags srcStageMask,
4038                       VkPipelineStageFlags destStageMask,
4039                       VkBool32 byRegion,
4040                       uint32_t memoryBarrierCount,
4041                       const VkMemoryBarrier *pMemoryBarriers,
4042                       uint32_t bufferMemoryBarrierCount,
4043                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4044                       uint32_t imageMemoryBarrierCount,
4045                       const VkImageMemoryBarrier *pImageMemoryBarriers)
4046 {
4047    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4048    struct tu_barrier_info info;
4049
4050    info.eventCount = 0;
4051    info.pEvents = NULL;
4052    info.srcStageMask = srcStageMask;
4053
4054    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4055               bufferMemoryBarrierCount, pBufferMemoryBarriers,
4056               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4057 }
4058
4059 static void
4060 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
4061 {
4062    struct tu_cs *cs = &cmd->cs;
4063
4064    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
4065
4066    /* TODO: any flush required before/after ? */
4067
4068    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
4069    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
4070    tu_cs_emit(cs, value);
4071 }
4072
4073 void
4074 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
4075                VkEvent _event,
4076                VkPipelineStageFlags stageMask)
4077 {
4078    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4079    TU_FROM_HANDLE(tu_event, event, _event);
4080
4081    write_event(cmd, event, 1);
4082 }
4083
4084 void
4085 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
4086                  VkEvent _event,
4087                  VkPipelineStageFlags stageMask)
4088 {
4089    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4090    TU_FROM_HANDLE(tu_event, event, _event);
4091
4092    write_event(cmd, event, 0);
4093 }
4094
4095 void
4096 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
4097                  uint32_t eventCount,
4098                  const VkEvent *pEvents,
4099                  VkPipelineStageFlags srcStageMask,
4100                  VkPipelineStageFlags dstStageMask,
4101                  uint32_t memoryBarrierCount,
4102                  const VkMemoryBarrier *pMemoryBarriers,
4103                  uint32_t bufferMemoryBarrierCount,
4104                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4105                  uint32_t imageMemoryBarrierCount,
4106                  const VkImageMemoryBarrier *pImageMemoryBarriers)
4107 {
4108    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4109    struct tu_cs *cs = &cmd->cs;
4110
4111    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
4112
4113    for (uint32_t i = 0; i < eventCount; i++) {
4114       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
4115
4116       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
4117
4118       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
4119       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
4120                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
4121       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
4122       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
4123       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
4124       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
4125    }
4126 }
4127
4128 void
4129 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
4130 {
4131    /* No-op */
4132 }