2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
118 const uint32_t tile_align_w
= 64; /* note: 32 when no input attachments */
119 const uint32_t tile_align_h
= 16;
120 const uint32_t max_tile_width
= 1024;
122 /* note: don't offset the tiling config by render_area.offset,
123 * because binning pass can't deal with it
124 * this means we might end up with more tiles than necessary,
125 * but load/store/etc are still scissored to the render_area
127 tiling
->tile0
.offset
= (VkOffset2D
) {};
129 const uint32_t ra_width
=
130 tiling
->render_area
.extent
.width
+
131 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
132 const uint32_t ra_height
=
133 tiling
->render_area
.extent
.height
+
134 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
136 /* start from 1 tile */
137 tiling
->tile_count
= (VkExtent2D
) {
141 tiling
->tile0
.extent
= (VkExtent2D
) {
142 .width
= align(ra_width
, tile_align_w
),
143 .height
= align(ra_height
, tile_align_h
),
146 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
147 /* start with 2x2 tiles */
148 tiling
->tile_count
.width
= 2;
149 tiling
->tile_count
.height
= 2;
150 tiling
->tile0
.extent
.width
= align(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
151 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), tile_align_h
);
154 /* do not exceed max tile width */
155 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
156 tiling
->tile_count
.width
++;
157 tiling
->tile0
.extent
.width
=
158 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
161 /* will force to sysmem, don't bother trying to have a valid tile config
162 * TODO: just skip all GMEM stuff when sysmem is forced?
167 /* do not exceed gmem size */
168 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pixels
) {
169 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
170 tiling
->tile_count
.width
++;
171 tiling
->tile0
.extent
.width
=
172 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
174 /* if this assert fails then layout is impossible.. */
175 assert(tiling
->tile0
.extent
.height
> tile_align_h
);
176 tiling
->tile_count
.height
++;
177 tiling
->tile0
.extent
.height
=
178 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), tile_align_h
);
184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
185 const struct tu_device
*dev
)
187 const uint32_t max_pipe_count
= 32; /* A6xx */
189 /* start from 1 tile per pipe */
190 tiling
->pipe0
= (VkExtent2D
) {
194 tiling
->pipe_count
= tiling
->tile_count
;
196 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
197 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
198 tiling
->pipe0
.width
+= 1;
199 tiling
->pipe_count
.width
=
200 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
202 tiling
->pipe0
.height
+= 1;
203 tiling
->pipe_count
.height
=
204 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
210 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
211 const struct tu_device
*dev
)
213 const uint32_t max_pipe_count
= 32; /* A6xx */
214 const uint32_t used_pipe_count
=
215 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
216 const VkExtent2D last_pipe
= {
217 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
218 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
221 assert(used_pipe_count
<= max_pipe_count
);
222 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
224 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
225 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
226 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
227 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
228 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
230 : tiling
->pipe0
.width
;
231 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
233 : tiling
->pipe0
.height
;
234 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
236 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
237 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
238 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
239 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
240 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
244 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
245 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
249 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
250 const struct tu_device
*dev
,
253 struct tu_tile
*tile
)
255 /* find the pipe and the slot for tile (tx, ty) */
256 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
257 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
258 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
259 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
260 /* last pipe has different width */
261 const uint32_t pipe_width
=
262 MIN2(tiling
->pipe0
.width
,
263 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
265 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
266 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
267 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
269 /* convert to 1D indices */
270 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
271 tile
->slot
= pipe_width
* sy
+ sx
;
273 /* get the blit area for the tile */
274 tile
->begin
= (VkOffset2D
) {
275 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
276 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
279 (tx
== tiling
->tile_count
.width
- 1)
280 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
281 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
283 (ty
== tiling
->tile_count
.height
- 1)
284 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
285 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
288 enum a3xx_msaa_samples
289 tu_msaa_samples(uint32_t samples
)
301 assert(!"invalid sample count");
306 static enum a4xx_index_size
307 tu6_index_size(VkIndexType type
)
310 case VK_INDEX_TYPE_UINT16
:
311 return INDEX4_SIZE_16_BIT
;
312 case VK_INDEX_TYPE_UINT32
:
313 return INDEX4_SIZE_32_BIT
;
315 unreachable("invalid VkIndexType");
316 return INDEX4_SIZE_8_BIT
;
321 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
323 enum vgt_event_type event
,
328 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
329 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
331 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
332 seqno
= ++cmd
->scratch_seqno
;
333 tu_cs_emit(cs
, seqno
);
340 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
342 tu6_emit_event_write(cmd
, cs
, 0x31, false);
346 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
348 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
352 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
354 if (cmd
->wait_for_idle
) {
356 cmd
->wait_for_idle
= false;
361 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
362 const struct tu_subpass
*subpass
,
365 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
367 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
368 if (a
== VK_ATTACHMENT_UNUSED
) {
370 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
371 A6XX_RB_DEPTH_BUFFER_PITCH(0),
372 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
373 A6XX_RB_DEPTH_BUFFER_BASE(0),
374 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
377 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
380 A6XX_GRAS_LRZ_BUFFER_BASE(0),
381 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
382 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
384 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
389 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
390 enum a6xx_depth_format fmt
= tu6_pipe2depth(iview
->vk_format
);
393 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
),
394 A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)),
395 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(
396 fdl_layer_stride(&iview
->image
->layout
, iview
->base_mip
)),
397 A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview
)),
398 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd
->state
.pass
->attachments
[a
].gmem_offset
));
401 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
404 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview
)),
405 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview
)));
408 A6XX_GRAS_LRZ_BUFFER_BASE(0),
409 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
410 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
413 A6XX_RB_STENCIL_INFO(0));
419 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
420 const struct tu_subpass
*subpass
,
423 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
424 unsigned char mrt_comp
[MAX_RTS
] = { 0 };
425 unsigned srgb_cntl
= 0;
427 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
428 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
429 if (a
== VK_ATTACHMENT_UNUSED
)
432 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
436 if (vk_format_is_srgb(iview
->vk_format
))
437 srgb_cntl
|= (1 << i
);
439 struct tu_native_format format
=
440 tu6_format_image(iview
->image
, iview
->vk_format
, iview
->base_mip
);
443 A6XX_RB_MRT_BUF_INFO(i
,
444 .color_tile_mode
= format
.tile_mode
,
445 .color_format
= format
.fmt
,
446 .color_swap
= format
.swap
),
447 A6XX_RB_MRT_PITCH(i
, tu_image_stride(iview
->image
, iview
->base_mip
)),
448 A6XX_RB_MRT_ARRAY_PITCH(i
,
449 fdl_layer_stride(&iview
->image
->layout
, iview
->base_mip
)),
450 A6XX_RB_MRT_BASE(i
, tu_image_view_base_ref(iview
)),
451 A6XX_RB_MRT_BASE_GMEM(i
, cmd
->state
.pass
->attachments
[a
].gmem_offset
));
454 A6XX_SP_FS_MRT_REG(i
,
455 .color_format
= format
.fmt
,
456 .color_sint
= vk_format_is_sint(iview
->vk_format
),
457 .color_uint
= vk_format_is_uint(iview
->vk_format
)));
460 A6XX_RB_MRT_FLAG_BUFFER_ADDR(i
, tu_image_view_ubwc_base_ref(iview
)),
461 A6XX_RB_MRT_FLAG_BUFFER_PITCH(i
, tu_image_view_ubwc_pitches(iview
)));
465 A6XX_RB_SRGB_CNTL(.dword
= srgb_cntl
));
468 A6XX_SP_SRGB_CNTL(.dword
= srgb_cntl
));
471 A6XX_RB_RENDER_COMPONENTS(
479 .rt7
= mrt_comp
[7]));
482 A6XX_SP_FS_RENDER_COMPONENTS(
490 .rt7
= mrt_comp
[7]));
492 // XXX: We probably can't hardcode LAYER_CNTL_TYPE.
494 A6XX_GRAS_LAYER_CNTL(.layered
= fb
->layers
> 1,
495 .type
= LAYER_2D_ARRAY
));
499 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
501 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
502 bool msaa_disable
= samples
== MSAA_ONE
;
505 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
506 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
507 .msaa_disable
= msaa_disable
));
510 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
511 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
512 .msaa_disable
= msaa_disable
));
515 A6XX_RB_RAS_MSAA_CNTL(samples
),
516 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
517 .msaa_disable
= msaa_disable
));
520 A6XX_RB_MSAA_CNTL(samples
));
524 tu6_emit_bin_size(struct tu_cs
*cs
,
525 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
528 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
533 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
537 /* no flag for RB_BIN_CONTROL2... */
539 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
544 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
545 const struct tu_subpass
*subpass
,
549 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
551 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
553 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
555 uint32_t mrts_ubwc_enable
= 0;
556 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
557 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
558 if (a
== VK_ATTACHMENT_UNUSED
)
561 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
562 if (iview
->image
->layout
.ubwc_layer_size
!= 0)
563 mrts_ubwc_enable
|= 1 << i
;
566 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
568 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
569 if (a
!= VK_ATTACHMENT_UNUSED
) {
570 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
571 if (iview
->image
->layout
.ubwc_layer_size
!= 0)
572 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
575 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
576 * in order to set it correctly for the different subpasses. However,
577 * that means the packets we're emitting also happen during binning. So
578 * we need to guard the write on !BINNING at CP execution time.
580 tu_cs_reserve(cs
, 3 + 4);
581 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
582 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
583 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
584 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
587 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
588 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
589 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
590 tu_cs_emit(cs
, cntl
);
594 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
596 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
597 uint32_t x1
= render_area
->offset
.x
;
598 uint32_t y1
= render_area
->offset
.y
;
599 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
600 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
603 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
604 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
605 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
606 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
610 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
611 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
615 tu6_emit_window_scissor(struct tu_cs
*cs
,
622 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
623 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
626 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
627 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
631 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
634 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
637 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
640 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
643 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
647 use_hw_binning(struct tu_cmd_buffer
*cmd
)
649 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
651 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
654 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
657 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
661 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
663 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
666 /* can't fit attachments into gmem */
667 if (!cmd
->state
.pass
->gmem_pixels
)
670 if (cmd
->state
.framebuffer
->layers
> 1)
673 return cmd
->state
.tiling_config
.force_sysmem
;
677 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
679 const struct tu_tile
*tile
)
681 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
682 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
684 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
685 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
687 const uint32_t x1
= tile
->begin
.x
;
688 const uint32_t y1
= tile
->begin
.y
;
689 const uint32_t x2
= tile
->end
.x
- 1;
690 const uint32_t y2
= tile
->end
.y
- 1;
691 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
692 tu6_emit_window_offset(cs
, x1
, y1
);
695 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
697 if (use_hw_binning(cmd
)) {
698 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
700 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
703 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
704 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
705 A6XX_CP_REG_TEST_0_BIT(0) |
706 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
708 tu_cs_reserve(cs
, 3 + 11);
709 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
710 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
711 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
713 /* if (no overflow) */ {
714 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
715 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
716 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
717 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
718 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
719 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
721 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
724 /* use a NOP packet to skip over the 'else' side: */
725 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
727 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
731 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
735 A6XX_RB_UNKNOWN_8804(0));
738 A6XX_SP_TP_UNKNOWN_B304(0));
741 A6XX_GRAS_UNKNOWN_80A4(0));
743 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
746 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
752 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
757 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
758 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
759 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
761 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
765 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
767 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
768 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
770 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
771 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
772 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
773 CP_SET_DRAW_STATE__0_GROUP_ID(0));
774 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
775 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
777 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
780 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
781 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
783 /* blit scissor may have been changed by CmdClearAttachments */
784 tu6_emit_blit_scissor(cmd
, cs
, false);
786 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
787 if (pass
->attachments
[a
].gmem_offset
>= 0)
788 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
791 if (subpass
->resolve_attachments
) {
792 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
793 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
794 if (a
!= VK_ATTACHMENT_UNUSED
)
795 tu_store_gmem_attachment(cmd
, cs
, a
,
796 subpass
->color_attachments
[i
].attachment
);
802 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
805 A6XX_PC_RESTART_INDEX(restart_index
));
809 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
811 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
813 tu6_emit_cache_flush(cmd
, cs
);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
818 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
819 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
820 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
822 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
823 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
825 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
826 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
844 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
851 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
852 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
853 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
854 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
855 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
856 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
857 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
858 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
859 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
860 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
861 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
863 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
864 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
866 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
867 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
869 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
870 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
872 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
873 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
874 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
875 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
877 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
878 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
880 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
882 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
884 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
885 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
886 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
887 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
888 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
889 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
890 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
891 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
892 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
893 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
894 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
895 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
896 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8804
, 0);
897 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
898 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
899 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
900 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8805
, 0);
901 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8806
, 0);
902 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
903 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
904 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
906 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
908 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
910 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
912 /* we don't use this yet.. probably best to disable.. */
913 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
914 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
915 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
916 CP_SET_DRAW_STATE__0_GROUP_ID(0));
917 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
918 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
920 /* Set not to use streamout by default, */
921 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
922 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
924 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
928 A6XX_SP_HS_CTRL_REG0(0));
931 A6XX_SP_GS_CTRL_REG0(0));
934 A6XX_GRAS_LRZ_CNTL(0));
937 A6XX_RB_LRZ_CNTL(0));
940 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
942 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
944 tu_cs_sanity_check(cs
);
948 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
952 seqno
= tu6_emit_event_write(cmd
, cs
, RB_DONE_TS
, true);
954 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
955 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
956 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
957 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
958 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
959 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
960 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
962 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
964 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
965 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
966 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
967 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
971 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
973 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
976 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
977 .height
= tiling
->tile0
.extent
.height
),
978 A6XX_VSC_SIZE_ADDRESS(.bo
= &cmd
->vsc_data
,
979 .bo_offset
= 32 * cmd
->vsc_data_pitch
));
982 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
983 .ny
= tiling
->tile_count
.height
));
985 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
986 for (unsigned i
= 0; i
< 32; i
++)
987 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
990 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo
= &cmd
->vsc_data2
),
991 A6XX_VSC_PIPE_DATA2_PITCH(cmd
->vsc_data2_pitch
),
992 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd
->vsc_data2
.size
));
995 A6XX_VSC_PIPE_DATA_ADDRESS(.bo
= &cmd
->vsc_data
),
996 A6XX_VSC_PIPE_DATA_PITCH(cmd
->vsc_data_pitch
),
997 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd
->vsc_data
.size
));
1001 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1003 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1004 const uint32_t used_pipe_count
=
1005 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1007 /* Clear vsc_scratch: */
1008 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1009 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1010 tu_cs_emit(cs
, 0x0);
1012 /* Check for overflow, write vsc_scratch if detected: */
1013 for (int i
= 0; i
< used_pipe_count
; i
++) {
1014 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1015 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1016 CP_COND_WRITE5_0_WRITE_MEMORY
);
1017 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
1018 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1019 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
1020 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1021 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1022 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
1024 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1025 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1026 CP_COND_WRITE5_0_WRITE_MEMORY
);
1027 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
1028 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1029 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
1030 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1031 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1032 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
1035 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1037 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1039 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1040 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
1041 CP_MEM_TO_REG_0_CNT(1 - 1));
1042 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1045 * This is a bit awkward, we really want a way to invert the
1046 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1047 * execute cmds to use hwbinning when a bit is *not* set. This
1048 * dance is to invert OVERFLOW_FLAG_REG
1050 * A CP_NOP packet is used to skip executing the 'else' clause
1054 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1055 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1056 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1057 A6XX_CP_REG_TEST_0_BIT(0) |
1058 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1060 tu_cs_reserve(cs
, 3 + 7);
1061 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1062 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1063 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1067 * On overflow, mirror the value to control->vsc_overflow
1068 * which CPU is checking to detect overflow (see
1069 * check_vsc_overflow())
1071 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1072 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1073 CP_REG_TO_MEM_0_CNT(0));
1074 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1076 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1077 tu_cs_emit(cs
, 0x0);
1079 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1081 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1082 tu_cs_emit(cs
, 0x1);
1087 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1089 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1090 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1092 uint32_t x1
= tiling
->tile0
.offset
.x
;
1093 uint32_t y1
= tiling
->tile0
.offset
.y
;
1094 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1095 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1097 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1099 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1100 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1102 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1103 tu_cs_emit(cs
, 0x1);
1105 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1106 tu_cs_emit(cs
, 0x1);
1111 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1113 update_vsc_pipe(cmd
, cs
);
1116 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1119 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1121 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1122 tu_cs_emit(cs
, UNK_2C
);
1125 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1128 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1130 /* emit IB to binning drawcmds: */
1131 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1133 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1134 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1135 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1136 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1137 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1138 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1140 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1141 tu_cs_emit(cs
, UNK_2D
);
1143 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1144 tu6_cache_flush(cmd
, cs
);
1148 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1150 emit_vsc_overflow_test(cmd
, cs
);
1152 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1153 tu_cs_emit(cs
, 0x0);
1155 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1156 tu_cs_emit(cs
, 0x0);
1158 cmd
->wait_for_idle
= false;
1162 tu_emit_load_clear(struct tu_cmd_buffer
*cmd
,
1163 const VkRenderPassBeginInfo
*info
)
1165 struct tu_cs
*cs
= &cmd
->draw_cs
;
1167 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1169 tu6_emit_blit_scissor(cmd
, cs
, true);
1171 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1172 tu_load_gmem_attachment(cmd
, cs
, i
);
1174 tu6_emit_blit_scissor(cmd
, cs
, false);
1176 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1177 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1179 tu_cond_exec_end(cs
);
1181 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1183 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1184 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1186 tu_cond_exec_end(cs
);
1190 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1191 const struct VkRect2D
*renderArea
)
1193 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1194 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1196 assert(fb
->width
> 0 && fb
->height
> 0);
1197 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1198 tu6_emit_window_offset(cs
, 0, 0);
1200 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1202 tu6_emit_lrz_flush(cmd
, cs
);
1204 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1205 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1207 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1208 tu_cs_emit(cs
, 0x0);
1210 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1211 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1212 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1214 tu6_emit_wfi(cmd
, cs
);
1216 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
1218 /* enable stream-out, with sysmem there is only one pass: */
1220 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1222 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1223 tu_cs_emit(cs
, 0x1);
1225 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1226 tu_cs_emit(cs
, 0x0);
1228 tu_cs_sanity_check(cs
);
1232 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1234 /* Do any resolves of the last subpass. These are handled in the
1235 * tile_store_ib in the gmem path.
1237 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1238 if (subpass
->resolve_attachments
) {
1239 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
1240 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
1241 if (a
!= VK_ATTACHMENT_UNUSED
)
1242 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
1243 subpass
->color_attachments
[i
].attachment
);
1247 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1249 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1250 tu_cs_emit(cs
, 0x0);
1252 tu6_emit_lrz_flush(cmd
, cs
);
1254 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1255 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1257 tu_cs_sanity_check(cs
);
1262 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1264 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1266 tu6_emit_lrz_flush(cmd
, cs
);
1270 tu6_emit_cache_flush(cmd
, cs
);
1272 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1273 tu_cs_emit(cs
, 0x0);
1275 /* TODO: flushing with barriers instead of blindly always flushing */
1276 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1277 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1278 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1279 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1283 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_gmem
, .gmem
= 1));
1285 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1286 if (use_hw_binning(cmd
)) {
1287 /* enable stream-out during binning pass: */
1288 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1290 tu6_emit_bin_size(cs
,
1291 tiling
->tile0
.extent
.width
,
1292 tiling
->tile0
.extent
.height
,
1293 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1295 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1297 tu6_emit_binning_pass(cmd
, cs
);
1299 /* and disable stream-out for draw pass: */
1300 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1302 tu6_emit_bin_size(cs
,
1303 tiling
->tile0
.extent
.width
,
1304 tiling
->tile0
.extent
.height
,
1305 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1308 A6XX_VFD_MODE_CNTL(0));
1310 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1312 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1314 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1315 tu_cs_emit(cs
, 0x1);
1317 /* no binning pass, so enable stream-out for draw pass:: */
1318 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1320 tu6_emit_bin_size(cs
,
1321 tiling
->tile0
.extent
.width
,
1322 tiling
->tile0
.extent
.height
,
1326 tu_cs_sanity_check(cs
);
1330 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1332 const struct tu_tile
*tile
)
1334 tu6_emit_tile_select(cmd
, cs
, tile
);
1336 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1337 cmd
->wait_for_idle
= true;
1339 if (use_hw_binning(cmd
)) {
1340 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1341 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1342 A6XX_CP_REG_TEST_0_BIT(0) |
1343 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1345 tu_cs_reserve(cs
, 3 + 2);
1346 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1347 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1348 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1350 /* if (no overflow) */ {
1351 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1352 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1356 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1358 tu_cs_sanity_check(cs
);
1362 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1364 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1367 A6XX_GRAS_LRZ_CNTL(0));
1369 tu6_emit_lrz_flush(cmd
, cs
);
1371 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1373 tu_cs_sanity_check(cs
);
1377 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1379 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1381 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1383 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1384 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1385 struct tu_tile tile
;
1386 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1387 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1391 tu6_tile_render_end(cmd
, &cmd
->cs
);
1395 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1397 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1399 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1401 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1402 cmd
->wait_for_idle
= true;
1404 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1408 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1410 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1411 struct tu_cs sub_cs
;
1414 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1415 if (result
!= VK_SUCCESS
) {
1416 cmd
->record_result
= result
;
1420 /* emit to tile-store sub_cs */
1421 tu6_emit_tile_store(cmd
, &sub_cs
);
1423 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1427 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1428 const VkRect2D
*render_area
)
1430 const struct tu_device
*dev
= cmd
->device
;
1431 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1433 tiling
->render_area
= *render_area
;
1434 tiling
->force_sysmem
= false;
1436 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
->gmem_pixels
);
1437 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1438 tu_tiling_config_update_pipes(tiling
, dev
);
1441 const struct tu_dynamic_state default_dynamic_state
= {
1457 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1463 .stencil_compare_mask
=
1468 .stencil_write_mask
=
1473 .stencil_reference
=
1480 static void UNUSED
/* FINISHME */
1481 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1482 const struct tu_dynamic_state
*src
)
1484 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1485 uint32_t copy_mask
= src
->mask
;
1486 uint32_t dest_mask
= 0;
1488 tu_use_args(cmd_buffer
); /* FINISHME */
1490 /* Make sure to copy the number of viewports/scissors because they can
1491 * only be specified at pipeline creation time.
1493 dest
->viewport
.count
= src
->viewport
.count
;
1494 dest
->scissor
.count
= src
->scissor
.count
;
1495 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1497 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1498 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1499 src
->viewport
.count
* sizeof(VkViewport
))) {
1500 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1501 src
->viewport
.count
);
1502 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1506 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1507 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1508 src
->scissor
.count
* sizeof(VkRect2D
))) {
1509 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1510 src
->scissor
.count
);
1511 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1515 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1516 if (dest
->line_width
!= src
->line_width
) {
1517 dest
->line_width
= src
->line_width
;
1518 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1522 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1523 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1524 sizeof(src
->depth_bias
))) {
1525 dest
->depth_bias
= src
->depth_bias
;
1526 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1530 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1531 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1532 sizeof(src
->blend_constants
))) {
1533 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1534 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1538 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1539 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1540 sizeof(src
->depth_bounds
))) {
1541 dest
->depth_bounds
= src
->depth_bounds
;
1542 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1546 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1547 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1548 sizeof(src
->stencil_compare_mask
))) {
1549 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1550 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1554 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1555 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1556 sizeof(src
->stencil_write_mask
))) {
1557 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1558 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1562 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1563 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1564 sizeof(src
->stencil_reference
))) {
1565 dest
->stencil_reference
= src
->stencil_reference
;
1566 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1570 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1571 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1572 &src
->discard_rectangle
.rectangles
,
1573 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1574 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1575 src
->discard_rectangle
.rectangles
,
1576 src
->discard_rectangle
.count
);
1577 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1583 tu_create_cmd_buffer(struct tu_device
*device
,
1584 struct tu_cmd_pool
*pool
,
1585 VkCommandBufferLevel level
,
1586 VkCommandBuffer
*pCommandBuffer
)
1588 struct tu_cmd_buffer
*cmd_buffer
;
1589 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1590 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1591 if (cmd_buffer
== NULL
)
1592 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1594 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1595 cmd_buffer
->device
= device
;
1596 cmd_buffer
->pool
= pool
;
1597 cmd_buffer
->level
= level
;
1600 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1601 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1604 /* Init the pool_link so we can safely call list_del when we destroy
1605 * the command buffer
1607 list_inithead(&cmd_buffer
->pool_link
);
1608 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1611 tu_bo_list_init(&cmd_buffer
->bo_list
);
1612 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1613 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1614 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1615 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1617 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1619 list_inithead(&cmd_buffer
->upload
.list
);
1621 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1622 if (result
!= VK_SUCCESS
)
1623 goto fail_scratch_bo
;
1625 /* TODO: resize on overflow */
1626 cmd_buffer
->vsc_data_pitch
= device
->vsc_data_pitch
;
1627 cmd_buffer
->vsc_data2_pitch
= device
->vsc_data2_pitch
;
1628 cmd_buffer
->vsc_data
= device
->vsc_data
;
1629 cmd_buffer
->vsc_data2
= device
->vsc_data2
;
1634 list_del(&cmd_buffer
->pool_link
);
1639 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1641 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1643 list_del(&cmd_buffer
->pool_link
);
1645 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1646 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1648 tu_cs_finish(&cmd_buffer
->cs
);
1649 tu_cs_finish(&cmd_buffer
->draw_cs
);
1650 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1651 tu_cs_finish(&cmd_buffer
->sub_cs
);
1653 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1654 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1658 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1660 cmd_buffer
->wait_for_idle
= true;
1662 cmd_buffer
->record_result
= VK_SUCCESS
;
1664 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1665 tu_cs_reset(&cmd_buffer
->cs
);
1666 tu_cs_reset(&cmd_buffer
->draw_cs
);
1667 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1668 tu_cs_reset(&cmd_buffer
->sub_cs
);
1670 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1671 cmd_buffer
->descriptors
[i
].valid
= 0;
1672 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1675 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1677 return cmd_buffer
->record_result
;
1681 tu_AllocateCommandBuffers(VkDevice _device
,
1682 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1683 VkCommandBuffer
*pCommandBuffers
)
1685 TU_FROM_HANDLE(tu_device
, device
, _device
);
1686 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1688 VkResult result
= VK_SUCCESS
;
1691 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1693 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1694 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1695 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1697 list_del(&cmd_buffer
->pool_link
);
1698 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1700 result
= tu_reset_cmd_buffer(cmd_buffer
);
1701 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1702 cmd_buffer
->level
= pAllocateInfo
->level
;
1704 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1706 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1707 &pCommandBuffers
[i
]);
1709 if (result
!= VK_SUCCESS
)
1713 if (result
!= VK_SUCCESS
) {
1714 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1717 /* From the Vulkan 1.0.66 spec:
1719 * "vkAllocateCommandBuffers can be used to create multiple
1720 * command buffers. If the creation of any of those command
1721 * buffers fails, the implementation must destroy all
1722 * successfully created command buffer objects from this
1723 * command, set all entries of the pCommandBuffers array to
1724 * NULL and return the error."
1726 memset(pCommandBuffers
, 0,
1727 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1734 tu_FreeCommandBuffers(VkDevice device
,
1735 VkCommandPool commandPool
,
1736 uint32_t commandBufferCount
,
1737 const VkCommandBuffer
*pCommandBuffers
)
1739 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1740 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1743 if (cmd_buffer
->pool
) {
1744 list_del(&cmd_buffer
->pool_link
);
1745 list_addtail(&cmd_buffer
->pool_link
,
1746 &cmd_buffer
->pool
->free_cmd_buffers
);
1748 tu_cmd_buffer_destroy(cmd_buffer
);
1754 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1755 VkCommandBufferResetFlags flags
)
1757 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1758 return tu_reset_cmd_buffer(cmd_buffer
);
1762 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1763 const VkCommandBufferBeginInfo
*pBeginInfo
)
1765 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1766 VkResult result
= VK_SUCCESS
;
1768 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1769 /* If the command buffer has already been resetted with
1770 * vkResetCommandBuffer, no need to do it again.
1772 result
= tu_reset_cmd_buffer(cmd_buffer
);
1773 if (result
!= VK_SUCCESS
)
1777 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1778 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1780 tu_cs_begin(&cmd_buffer
->cs
);
1781 tu_cs_begin(&cmd_buffer
->draw_cs
);
1782 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1784 cmd_buffer
->scratch_seqno
= 0;
1786 /* setup initial configuration into command buffer */
1787 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1788 switch (cmd_buffer
->queue_family_index
) {
1789 case TU_QUEUE_GENERAL
:
1790 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1795 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1796 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1797 assert(pBeginInfo
->pInheritanceInfo
);
1798 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1799 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1802 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1808 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1809 uint32_t firstBinding
,
1810 uint32_t bindingCount
,
1811 const VkBuffer
*pBuffers
,
1812 const VkDeviceSize
*pOffsets
)
1814 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1816 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1818 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1819 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1820 tu_buffer_from_handle(pBuffers
[i
]);
1821 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1824 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1825 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1829 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1831 VkDeviceSize offset
,
1832 VkIndexType indexType
)
1834 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1835 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1837 /* initialize/update the restart index */
1838 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1839 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1841 tu6_emit_restart_index(
1842 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1844 tu_cs_sanity_check(draw_cs
);
1848 if (cmd
->state
.index_buffer
!= buf
)
1849 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1851 cmd
->state
.index_buffer
= buf
;
1852 cmd
->state
.index_offset
= offset
;
1853 cmd
->state
.index_type
= indexType
;
1857 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1858 VkPipelineBindPoint pipelineBindPoint
,
1859 VkPipelineLayout _layout
,
1861 uint32_t descriptorSetCount
,
1862 const VkDescriptorSet
*pDescriptorSets
,
1863 uint32_t dynamicOffsetCount
,
1864 const uint32_t *pDynamicOffsets
)
1866 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1867 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1868 unsigned dyn_idx
= 0;
1870 struct tu_descriptor_state
*descriptors_state
=
1871 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1873 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1874 unsigned idx
= i
+ firstSet
;
1875 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1877 descriptors_state
->sets
[idx
] = set
;
1878 descriptors_state
->valid
|= (1u << idx
);
1880 /* Note: the actual input attachment indices come from the shader
1881 * itself, so we can't generate the patched versions of these until
1882 * draw time when both the pipeline and descriptors are bound and
1883 * we're inside the render pass.
1885 unsigned dst_idx
= layout
->set
[idx
].input_attachment_start
;
1886 memcpy(&descriptors_state
->input_attachments
[dst_idx
* A6XX_TEX_CONST_DWORDS
],
1887 set
->dynamic_descriptors
,
1888 set
->layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
1890 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1891 /* Dynamic buffers come after input attachments in the descriptor set
1892 * itself, but due to how the Vulkan descriptor set binding works, we
1893 * have to put input attachments and dynamic buffers in separate
1894 * buffers in the descriptor_state and then combine them at draw
1895 * time. Binding a descriptor set only invalidates the descriptor
1896 * sets after it, but if we try to tightly pack the descriptors after
1897 * the input attachments then we could corrupt dynamic buffers in the
1898 * descriptor set before it, or we'd have to move all the dynamic
1899 * buffers over. We just put them into separate buffers to make
1900 * binding as well as the later patching of input attachments easy.
1902 unsigned src_idx
= j
+ set
->layout
->input_attachment_count
;
1903 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1904 assert(dyn_idx
< dynamicOffsetCount
);
1907 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1909 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1910 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1912 /* Patch the storage/uniform descriptors right away. */
1913 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1914 /* Note: we can assume here that the addition won't roll over and
1915 * change the SIZE field.
1917 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1922 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1923 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1924 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1932 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
)
1933 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1935 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1938 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1939 uint32_t firstBinding
,
1940 uint32_t bindingCount
,
1941 const VkBuffer
*pBuffers
,
1942 const VkDeviceSize
*pOffsets
,
1943 const VkDeviceSize
*pSizes
)
1945 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1946 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1948 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1949 uint32_t idx
= firstBinding
+ i
;
1950 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1952 if (pOffsets
[i
] != 0)
1953 cmd
->state
.streamout_reset
|= 1 << idx
;
1955 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1956 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1957 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1959 cmd
->state
.streamout_enabled
|= 1 << idx
;
1962 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1965 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1966 uint32_t firstCounterBuffer
,
1967 uint32_t counterBufferCount
,
1968 const VkBuffer
*pCounterBuffers
,
1969 const VkDeviceSize
*pCounterBufferOffsets
)
1971 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1972 /* TODO do something with counter buffer? */
1975 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1976 uint32_t firstCounterBuffer
,
1977 uint32_t counterBufferCount
,
1978 const VkBuffer
*pCounterBuffers
,
1979 const VkDeviceSize
*pCounterBufferOffsets
)
1981 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1982 /* TODO do something with counter buffer? */
1984 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1985 cmd
->state
.streamout_enabled
= 0;
1989 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1990 VkPipelineLayout layout
,
1991 VkShaderStageFlags stageFlags
,
1994 const void *pValues
)
1996 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1997 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1998 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
2002 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
2004 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2006 if (cmd_buffer
->scratch_seqno
) {
2007 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2008 MSM_SUBMIT_BO_WRITE
);
2011 if (cmd_buffer
->use_vsc_data
) {
2012 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
2013 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2014 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
2015 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2018 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
2019 MSM_SUBMIT_BO_READ
);
2021 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2022 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2023 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2026 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2027 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2028 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2031 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2032 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2033 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2036 tu_cs_end(&cmd_buffer
->cs
);
2037 tu_cs_end(&cmd_buffer
->draw_cs
);
2038 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2040 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2042 return cmd_buffer
->record_result
;
2046 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2047 VkPipelineBindPoint pipelineBindPoint
,
2048 VkPipeline _pipeline
)
2050 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2051 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2053 switch (pipelineBindPoint
) {
2054 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2055 cmd
->state
.pipeline
= pipeline
;
2056 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2058 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2059 cmd
->state
.compute_pipeline
= pipeline
;
2060 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2063 unreachable("unrecognized pipeline bind point");
2067 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2068 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2069 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2070 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2071 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2076 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2077 uint32_t firstViewport
,
2078 uint32_t viewportCount
,
2079 const VkViewport
*pViewports
)
2081 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2083 assert(firstViewport
== 0 && viewportCount
== 1);
2084 cmd
->state
.dynamic
.viewport
.viewports
[0] = pViewports
[0];
2085 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2089 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2090 uint32_t firstScissor
,
2091 uint32_t scissorCount
,
2092 const VkRect2D
*pScissors
)
2094 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2096 assert(firstScissor
== 0 && scissorCount
== 1);
2097 cmd
->state
.dynamic
.scissor
.scissors
[0] = pScissors
[0];
2098 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_SCISSOR
;
2102 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2104 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2106 cmd
->state
.dynamic
.line_width
= lineWidth
;
2108 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2109 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2113 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2114 float depthBiasConstantFactor
,
2115 float depthBiasClamp
,
2116 float depthBiasSlopeFactor
)
2118 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2119 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2121 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2122 depthBiasSlopeFactor
);
2124 tu_cs_sanity_check(draw_cs
);
2128 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2129 const float blendConstants
[4])
2131 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2132 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2134 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2136 tu_cs_sanity_check(draw_cs
);
2140 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2141 float minDepthBounds
,
2142 float maxDepthBounds
)
2147 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2148 VkStencilFaceFlags faceMask
,
2149 uint32_t compareMask
)
2151 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2153 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2154 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2155 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2156 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2158 /* the front/back compare masks must be updated together */
2159 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2163 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2164 VkStencilFaceFlags faceMask
,
2167 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2169 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2170 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2171 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2172 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2174 /* the front/back write masks must be updated together */
2175 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2179 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2180 VkStencilFaceFlags faceMask
,
2183 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2185 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2186 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2187 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2188 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2190 /* the front/back references must be updated together */
2191 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2195 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2196 uint32_t commandBufferCount
,
2197 const VkCommandBuffer
*pCmdBuffers
)
2199 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2202 assert(commandBufferCount
> 0);
2204 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2205 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2207 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2208 if (result
!= VK_SUCCESS
) {
2209 cmd
->record_result
= result
;
2213 if (secondary
->usage_flags
&
2214 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2215 assert(tu_cs_is_empty(&secondary
->cs
));
2217 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2218 if (result
!= VK_SUCCESS
) {
2219 cmd
->record_result
= result
;
2223 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2224 &secondary
->draw_epilogue_cs
);
2225 if (result
!= VK_SUCCESS
) {
2226 cmd
->record_result
= result
;
2230 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2231 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2233 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2234 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2235 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2238 tu_cs_emit_call(&cmd
->cs
, &secondary
->cs
);
2241 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2245 tu_CreateCommandPool(VkDevice _device
,
2246 const VkCommandPoolCreateInfo
*pCreateInfo
,
2247 const VkAllocationCallbacks
*pAllocator
,
2248 VkCommandPool
*pCmdPool
)
2250 TU_FROM_HANDLE(tu_device
, device
, _device
);
2251 struct tu_cmd_pool
*pool
;
2253 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2254 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2256 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2259 pool
->alloc
= *pAllocator
;
2261 pool
->alloc
= device
->alloc
;
2263 list_inithead(&pool
->cmd_buffers
);
2264 list_inithead(&pool
->free_cmd_buffers
);
2266 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2268 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2274 tu_DestroyCommandPool(VkDevice _device
,
2275 VkCommandPool commandPool
,
2276 const VkAllocationCallbacks
*pAllocator
)
2278 TU_FROM_HANDLE(tu_device
, device
, _device
);
2279 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2284 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2285 &pool
->cmd_buffers
, pool_link
)
2287 tu_cmd_buffer_destroy(cmd_buffer
);
2290 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2291 &pool
->free_cmd_buffers
, pool_link
)
2293 tu_cmd_buffer_destroy(cmd_buffer
);
2296 vk_free2(&device
->alloc
, pAllocator
, pool
);
2300 tu_ResetCommandPool(VkDevice device
,
2301 VkCommandPool commandPool
,
2302 VkCommandPoolResetFlags flags
)
2304 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2307 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2310 result
= tu_reset_cmd_buffer(cmd_buffer
);
2311 if (result
!= VK_SUCCESS
)
2319 tu_TrimCommandPool(VkDevice device
,
2320 VkCommandPool commandPool
,
2321 VkCommandPoolTrimFlags flags
)
2323 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2328 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2329 &pool
->free_cmd_buffers
, pool_link
)
2331 tu_cmd_buffer_destroy(cmd_buffer
);
2336 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2337 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2338 VkSubpassContents contents
)
2340 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2341 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2342 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2344 cmd
->state
.pass
= pass
;
2345 cmd
->state
.subpass
= pass
->subpasses
;
2346 cmd
->state
.framebuffer
= fb
;
2348 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2349 tu_cmd_prepare_tile_store_ib(cmd
);
2351 tu_emit_load_clear(cmd
, pRenderPassBegin
);
2353 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2354 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2355 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2356 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2358 /* note: use_hw_binning only checks tiling config */
2359 if (use_hw_binning(cmd
))
2360 cmd
->use_vsc_data
= true;
2362 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2363 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2364 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2365 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2368 /* Flag input attachment descriptors for re-emission if necessary */
2369 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2373 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2374 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2375 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2377 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2378 pSubpassBeginInfo
->contents
);
2382 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2384 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2385 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2386 struct tu_cs
*cs
= &cmd
->draw_cs
;
2388 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2390 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2392 if (subpass
->resolve_attachments
) {
2393 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2394 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2395 if (a
== VK_ATTACHMENT_UNUSED
)
2398 tu_store_gmem_attachment(cmd
, cs
, a
,
2399 subpass
->color_attachments
[i
].attachment
);
2401 if (pass
->attachments
[a
].gmem_offset
< 0)
2405 * check if the resolved attachment is needed by later subpasses,
2406 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2408 tu_finishme("missing GMEM->GMEM resolve path\n");
2409 tu_emit_load_gmem_attachment(cmd
, cs
, a
);
2413 tu_cond_exec_end(cs
);
2415 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2417 /* Emit flushes so that input attachments will read the correct value.
2418 * TODO: use subpass dependencies to flush or not
2420 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2421 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
2423 if (subpass
->resolve_attachments
) {
2424 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2426 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2427 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2428 if (a
== VK_ATTACHMENT_UNUSED
)
2431 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
2432 subpass
->color_attachments
[i
].attachment
);
2435 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2438 tu_cond_exec_end(cs
);
2440 /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2441 if (cmd
->state
.subpass
->input_count
)
2442 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2444 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2445 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2446 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2447 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2448 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2450 /* Flag input attachment descriptors for re-emission if necessary */
2451 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2455 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2456 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2457 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2459 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2465 * Number of vertices.
2470 * Index of the first vertex.
2472 int32_t vertex_offset
;
2475 * First instance id.
2477 uint32_t first_instance
;
2480 * Number of instances.
2482 uint32_t instance_count
;
2485 * First index (indexed draws only).
2487 uint32_t first_index
;
2490 * Whether it's an indexed draw.
2495 * Indirect draw parameters resource.
2497 struct tu_buffer
*indirect
;
2498 uint64_t indirect_offset
;
2502 * Draw count parameters resource.
2504 struct tu_buffer
*count_buffer
;
2505 uint64_t count_buffer_offset
;
2508 * Stream output parameters resource.
2510 struct tu_buffer
*streamout_buffer
;
2511 uint64_t streamout_buffer_offset
;
2514 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2515 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2516 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2518 enum tu_draw_state_group_id
2520 TU_DRAW_STATE_PROGRAM
,
2521 TU_DRAW_STATE_PROGRAM_BINNING
,
2523 TU_DRAW_STATE_VI_BINNING
,
2527 TU_DRAW_STATE_BLEND
,
2528 TU_DRAW_STATE_VS_CONST
,
2529 TU_DRAW_STATE_FS_CONST
,
2530 TU_DRAW_STATE_DESC_SETS
,
2531 TU_DRAW_STATE_DESC_SETS_GMEM
,
2532 TU_DRAW_STATE_DESC_SETS_LOAD
,
2533 TU_DRAW_STATE_VS_PARAMS
,
2535 TU_DRAW_STATE_COUNT
,
2538 struct tu_draw_state_group
2540 enum tu_draw_state_group_id id
;
2541 uint32_t enable_mask
;
2542 struct tu_cs_entry ib
;
2545 static inline uint32_t
2546 tu6_stage2opcode(gl_shader_stage type
)
2549 case MESA_SHADER_VERTEX
:
2550 case MESA_SHADER_TESS_CTRL
:
2551 case MESA_SHADER_TESS_EVAL
:
2552 case MESA_SHADER_GEOMETRY
:
2553 return CP_LOAD_STATE6_GEOM
;
2554 case MESA_SHADER_FRAGMENT
:
2555 case MESA_SHADER_COMPUTE
:
2556 case MESA_SHADER_KERNEL
:
2557 return CP_LOAD_STATE6_FRAG
;
2559 unreachable("bad shader type");
2563 static inline enum a6xx_state_block
2564 tu6_stage2shadersb(gl_shader_stage type
)
2567 case MESA_SHADER_VERTEX
:
2568 return SB6_VS_SHADER
;
2569 case MESA_SHADER_FRAGMENT
:
2570 return SB6_FS_SHADER
;
2571 case MESA_SHADER_COMPUTE
:
2572 case MESA_SHADER_KERNEL
:
2573 return SB6_CS_SHADER
;
2575 unreachable("bad shader type");
2581 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2582 struct tu_descriptor_state
*descriptors_state
,
2583 gl_shader_stage type
,
2584 uint32_t *push_constants
)
2586 const struct tu_program_descriptor_linkage
*link
=
2587 &pipeline
->program
.link
[type
];
2588 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2590 if (link
->push_consts
.count
> 0) {
2591 unsigned num_units
= link
->push_consts
.count
;
2592 unsigned offset
= link
->push_consts
.lo
;
2593 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2594 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2595 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2596 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2597 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2598 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2601 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2602 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2605 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2606 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2607 uint32_t offset
= state
->range
[i
].start
;
2609 /* and even if the start of the const buffer is before
2610 * first_immediate, the end may not be:
2612 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2617 /* things should be aligned to vec4: */
2618 debug_assert((state
->range
[i
].offset
% 16) == 0);
2619 debug_assert((size
% 16) == 0);
2620 debug_assert((offset
% 16) == 0);
2622 /* Dig out the descriptor from the descriptor state and read the VA from
2625 assert(state
->range
[i
].bindless
);
2626 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2627 descriptors_state
->dynamic_descriptors
:
2628 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2629 unsigned block
= state
->range
[i
].block
;
2630 /* If the block in the shader here is in the dynamic descriptor set, it
2631 * is an index into the dynamic descriptor set which is combined from
2632 * dynamic descriptors and input attachments on-the-fly, and we don't
2633 * have access to it here. Instead we work backwards to get the index
2634 * into dynamic_descriptors.
2636 if (state
->range
[i
].bindless_base
== MAX_SETS
)
2637 block
-= pipeline
->layout
->input_attachment_count
;
2638 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2639 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2642 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2643 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2644 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2645 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2646 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2647 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2648 tu_cs_emit_qw(cs
, va
+ offset
);
2652 static struct tu_cs_entry
2653 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2654 const struct tu_pipeline
*pipeline
,
2655 struct tu_descriptor_state
*descriptors_state
,
2656 gl_shader_stage type
)
2659 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2661 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2663 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2667 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2668 const struct tu_draw_info
*draw
,
2669 struct tu_cs_entry
*entry
)
2671 /* TODO: fill out more than just base instance */
2672 const struct tu_program_descriptor_linkage
*link
=
2673 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2674 const struct ir3_const_state
*const_state
= &link
->const_state
;
2677 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2678 *entry
= (struct tu_cs_entry
) {};
2682 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2683 if (result
!= VK_SUCCESS
)
2686 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2687 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2688 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2689 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2690 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2691 CP_LOAD_STATE6_0_NUM_UNIT(1));
2695 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2699 tu_cs_emit(&cs
, draw
->first_instance
);
2702 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2707 tu6_emit_descriptor_sets(struct tu_cmd_buffer
*cmd
,
2708 const struct tu_pipeline
*pipeline
,
2709 VkPipelineBindPoint bind_point
,
2710 struct tu_cs_entry
*entry
,
2713 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2714 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
2715 struct tu_descriptor_state
*descriptors_state
=
2716 tu_get_descriptors_state(cmd
, bind_point
);
2717 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2718 const uint32_t *input_attachment_idx
=
2719 pipeline
->program
.input_attachment_idx
;
2720 uint32_t num_dynamic_descs
= layout
->dynamic_offset_count
+
2721 layout
->input_attachment_count
;
2722 struct ts_cs_memory dynamic_desc_set
;
2725 if (num_dynamic_descs
> 0) {
2726 /* allocate and fill out dynamic descriptor set */
2727 result
= tu_cs_alloc(draw_state
, num_dynamic_descs
,
2728 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
2729 if (result
!= VK_SUCCESS
)
2732 memcpy(dynamic_desc_set
.map
, descriptors_state
->input_attachments
,
2733 layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
2736 /* Patch input attachments to refer to GMEM instead */
2737 for (unsigned i
= 0; i
< layout
->input_attachment_count
; i
++) {
2739 &dynamic_desc_set
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2741 /* The compiler has already laid out input_attachment_idx in the
2742 * final order of input attachments, so there's no need to go
2743 * through the pipeline layout finding input attachments.
2745 unsigned attachment_idx
= input_attachment_idx
[i
];
2747 /* It's possible for the pipeline layout to include an input
2748 * attachment which doesn't actually exist for the current
2749 * subpass. Of course, this is only valid so long as the pipeline
2750 * doesn't try to actually load that attachment. Just skip
2751 * patching in that scenario to avoid out-of-bounds accesses.
2753 if (attachment_idx
>= cmd
->state
.subpass
->input_count
)
2756 uint32_t a
= cmd
->state
.subpass
->input_attachments
[attachment_idx
].attachment
;
2757 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2759 assert(att
->gmem_offset
>= 0);
2761 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2762 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2763 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2765 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2766 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2768 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
2769 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2770 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2773 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2774 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2778 memcpy(dynamic_desc_set
.map
+ layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
,
2779 descriptors_state
->dynamic_descriptors
,
2780 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
2783 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
;
2784 uint32_t hlsq_update_value
;
2785 switch (bind_point
) {
2786 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2787 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
2788 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
2789 hlsq_update_value
= 0x7c000;
2791 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2792 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2793 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2794 hlsq_update_value
= 0x3e00;
2797 unreachable("bad bind point");
2800 /* Be careful here to *not* refer to the pipeline, so that if only the
2801 * pipeline changes we don't have to emit this again (except if there are
2802 * dynamic descriptors in the pipeline layout). This means always emitting
2803 * all the valid descriptors, which means that we always have to put the
2804 * dynamic descriptor in the driver-only slot at the end
2806 uint32_t num_user_sets
= util_last_bit(descriptors_state
->valid
);
2807 uint32_t num_sets
= num_user_sets
;
2808 if (num_dynamic_descs
> 0) {
2809 num_user_sets
= MAX_SETS
;
2810 num_sets
= num_user_sets
+ 1;
2813 unsigned regs
[2] = { sp_bindless_base_reg
, hlsq_bindless_base_reg
};
2816 result
= tu_cs_begin_sub_stream(draw_state
, ARRAY_SIZE(regs
) * (1 + num_sets
* 2) + 2, &cs
);
2817 if (result
!= VK_SUCCESS
)
2821 for (unsigned i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
2822 tu_cs_emit_pkt4(&cs
, regs
[i
], num_sets
* 2);
2823 for (unsigned j
= 0; j
< num_user_sets
; j
++) {
2824 if (descriptors_state
->valid
& (1 << j
)) {
2825 /* magic | 3 copied from the blob */
2826 tu_cs_emit_qw(&cs
, descriptors_state
->sets
[j
]->va
| 3);
2828 tu_cs_emit_qw(&cs
, 0 | 3);
2831 if (num_dynamic_descs
> 0) {
2832 tu_cs_emit_qw(&cs
, dynamic_desc_set
.iova
| 3);
2836 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value
));
2839 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2844 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2846 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2848 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2849 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2854 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2856 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2857 .bo_offset
= buf
->bo_offset
));
2858 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2860 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2861 offset
*= tf
->stride
[i
];
2863 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2864 cmd
->state
.streamout_reset
&= ~(1 << i
);
2866 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2867 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2868 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2869 CP_MEM_TO_REG_0_CNT(0));
2870 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2871 ctrl_offset(flush_base
[i
].offset
));
2874 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
2876 ctrl_offset(flush_base
[i
])));
2879 if (cmd
->state
.streamout_enabled
) {
2880 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
2881 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2882 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
2883 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
2884 tu_cs_emit(cs
, tf
->ncomp
[0]);
2885 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
2886 tu_cs_emit(cs
, tf
->ncomp
[1]);
2887 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
2888 tu_cs_emit(cs
, tf
->ncomp
[2]);
2889 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
2890 tu_cs_emit(cs
, tf
->ncomp
[3]);
2891 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2892 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
2893 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
2894 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
2895 tu_cs_emit(cs
, tf
->prog
[i
]);
2898 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
2899 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2901 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2907 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2909 const struct tu_draw_info
*draw
)
2911 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2912 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2913 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2914 uint32_t draw_state_group_count
= 0;
2917 struct tu_descriptor_state
*descriptors_state
=
2918 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2923 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
2924 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
2926 if (cmd
->state
.dirty
&
2927 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2928 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2929 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2930 dynamic
->line_width
);
2933 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2934 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2935 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2936 dynamic
->stencil_compare_mask
.back
);
2939 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2940 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2941 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2942 dynamic
->stencil_write_mask
.back
);
2945 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2946 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2947 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2948 dynamic
->stencil_reference
.back
);
2951 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2952 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2953 tu6_emit_viewport(cs
, &cmd
->state
.dynamic
.viewport
.viewports
[0]);
2956 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_SCISSOR
) &&
2957 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2958 tu6_emit_scissor(cs
, &cmd
->state
.dynamic
.scissor
.scissors
[0]);
2961 if (cmd
->state
.dirty
&
2962 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
2963 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
2964 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
2965 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2966 const VkDeviceSize offset
= buf
->bo_offset
+
2967 cmd
->state
.vb
.offsets
[binding
];
2968 const VkDeviceSize size
=
2969 offset
< buf
->size
? buf
->size
- offset
: 0;
2972 A6XX_VFD_FETCH_BASE(i
, .bo
= buf
->bo
, .bo_offset
= offset
),
2973 A6XX_VFD_FETCH_SIZE(i
, size
));
2977 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2978 draw_state_groups
[draw_state_group_count
++] =
2979 (struct tu_draw_state_group
) {
2980 .id
= TU_DRAW_STATE_PROGRAM
,
2981 .enable_mask
= ENABLE_DRAW
,
2982 .ib
= pipeline
->program
.state_ib
,
2984 draw_state_groups
[draw_state_group_count
++] =
2985 (struct tu_draw_state_group
) {
2986 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2987 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2988 .ib
= pipeline
->program
.binning_state_ib
,
2990 draw_state_groups
[draw_state_group_count
++] =
2991 (struct tu_draw_state_group
) {
2992 .id
= TU_DRAW_STATE_VI
,
2993 .enable_mask
= ENABLE_DRAW
,
2994 .ib
= pipeline
->vi
.state_ib
,
2996 draw_state_groups
[draw_state_group_count
++] =
2997 (struct tu_draw_state_group
) {
2998 .id
= TU_DRAW_STATE_VI_BINNING
,
2999 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
3000 .ib
= pipeline
->vi
.binning_state_ib
,
3002 draw_state_groups
[draw_state_group_count
++] =
3003 (struct tu_draw_state_group
) {
3004 .id
= TU_DRAW_STATE_VP
,
3005 .enable_mask
= ENABLE_ALL
,
3006 .ib
= pipeline
->vp
.state_ib
,
3008 draw_state_groups
[draw_state_group_count
++] =
3009 (struct tu_draw_state_group
) {
3010 .id
= TU_DRAW_STATE_RAST
,
3011 .enable_mask
= ENABLE_ALL
,
3012 .ib
= pipeline
->rast
.state_ib
,
3014 draw_state_groups
[draw_state_group_count
++] =
3015 (struct tu_draw_state_group
) {
3016 .id
= TU_DRAW_STATE_DS
,
3017 .enable_mask
= ENABLE_ALL
,
3018 .ib
= pipeline
->ds
.state_ib
,
3020 draw_state_groups
[draw_state_group_count
++] =
3021 (struct tu_draw_state_group
) {
3022 .id
= TU_DRAW_STATE_BLEND
,
3023 .enable_mask
= ENABLE_ALL
,
3024 .ib
= pipeline
->blend
.state_ib
,
3028 if (cmd
->state
.dirty
&
3029 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
3030 draw_state_groups
[draw_state_group_count
++] =
3031 (struct tu_draw_state_group
) {
3032 .id
= TU_DRAW_STATE_VS_CONST
,
3033 .enable_mask
= ENABLE_ALL
,
3034 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
3036 draw_state_groups
[draw_state_group_count
++] =
3037 (struct tu_draw_state_group
) {
3038 .id
= TU_DRAW_STATE_FS_CONST
,
3039 .enable_mask
= ENABLE_DRAW
,
3040 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3044 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3045 tu6_emit_streamout(cmd
, cs
);
3047 /* If there are any any dynamic descriptors, then we may need to re-emit
3048 * them after every pipeline change in case the number of input attachments
3049 * changes. We also always need to re-emit after a pipeline change if there
3050 * are any input attachments, because the input attachment index comes from
3051 * the pipeline. Finally, it can also happen that the subpass changes
3052 * without the pipeline changing, in which case the GMEM descriptors need
3053 * to be patched differently.
3055 * TODO: We could probably be clever and avoid re-emitting state on
3056 * pipeline changes if the number of input attachments is always 0. We
3057 * could also only re-emit dynamic state.
3059 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
||
3060 ((pipeline
->layout
->dynamic_offset_count
+
3061 pipeline
->layout
->input_attachment_count
> 0) &&
3062 cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) ||
3063 (pipeline
->layout
->input_attachment_count
> 0 &&
3064 cmd
->state
.dirty
& TU_CMD_DIRTY_INPUT_ATTACHMENTS
)) {
3065 struct tu_cs_entry desc_sets
, desc_sets_gmem
;
3066 bool need_gmem_desc_set
= pipeline
->layout
->input_attachment_count
> 0;
3068 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3069 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3071 if (result
!= VK_SUCCESS
)
3074 draw_state_groups
[draw_state_group_count
++] =
3075 (struct tu_draw_state_group
) {
3076 .id
= TU_DRAW_STATE_DESC_SETS
,
3077 .enable_mask
= need_gmem_desc_set
? ENABLE_NON_GMEM
: ENABLE_ALL
,
3081 if (need_gmem_desc_set
) {
3082 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3083 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3084 &desc_sets_gmem
, true);
3085 if (result
!= VK_SUCCESS
)
3088 draw_state_groups
[draw_state_group_count
++] =
3089 (struct tu_draw_state_group
) {
3090 .id
= TU_DRAW_STATE_DESC_SETS_GMEM
,
3091 .enable_mask
= CP_SET_DRAW_STATE__0_GMEM
,
3092 .ib
= desc_sets_gmem
,
3096 /* We need to reload the descriptors every time the descriptor sets
3097 * change. However, the commands we send only depend on the pipeline
3098 * because the whole point is to cache descriptors which are used by the
3099 * pipeline. There's a problem here, in that the firmware has an
3100 * "optimization" which skips executing groups that are set to the same
3101 * value as the last draw. This means that if the descriptor sets change
3102 * but not the pipeline, we'd try to re-execute the same buffer which
3103 * the firmware would ignore and we wouldn't pre-load the new
3104 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3105 * the descriptor sets change, which we emulate here by copying the
3106 * pre-prepared buffer.
3108 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3109 if (load_entry
->size
> 0) {
3110 struct tu_cs load_cs
;
3111 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3112 if (result
!= VK_SUCCESS
)
3114 tu_cs_emit_array(&load_cs
,
3115 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3116 load_entry
->size
/ 4);
3117 struct tu_cs_entry load_copy
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3119 draw_state_groups
[draw_state_group_count
++] =
3120 (struct tu_draw_state_group
) {
3121 .id
= TU_DRAW_STATE_DESC_SETS_LOAD
,
3122 /* The blob seems to not enable this for binning, even when
3123 * resources would actually be used in the binning shader.
3124 * Presumably the overhead of prefetching the resources isn't
3127 .enable_mask
= ENABLE_DRAW
,
3133 struct tu_cs_entry vs_params
;
3134 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3135 if (result
!= VK_SUCCESS
)
3138 draw_state_groups
[draw_state_group_count
++] =
3139 (struct tu_draw_state_group
) {
3140 .id
= TU_DRAW_STATE_VS_PARAMS
,
3141 .enable_mask
= ENABLE_ALL
,
3145 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3146 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3147 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3148 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3149 uint32_t cp_set_draw_state
=
3150 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3151 group
->enable_mask
|
3152 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3154 if (group
->ib
.size
) {
3155 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3157 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3161 tu_cs_emit(cs
, cp_set_draw_state
);
3162 tu_cs_emit_qw(cs
, iova
);
3165 tu_cs_sanity_check(cs
);
3168 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3169 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3170 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3172 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3175 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3177 for_each_bit(i
, descriptors_state
->valid
) {
3178 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3179 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3180 if (set
->buffers
[j
]) {
3181 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3182 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3185 if (set
->size
> 0) {
3186 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3187 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3191 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3192 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3193 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3195 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3196 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3201 /* There are too many graphics dirty bits to list here, so just list the
3202 * bits to preserve instead. The only things not emitted here are
3203 * compute-related state.
3205 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
3207 /* Fragment shader state overwrites compute shader state, so flag the
3208 * compute pipeline for re-emit.
3210 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3215 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3217 const struct tu_draw_info
*draw
)
3219 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3220 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3221 VK_SHADER_STAGE_GEOMETRY_BIT
;
3224 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3225 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3227 if (draw
->indexed
) {
3228 const enum a4xx_index_size index_size
=
3229 tu6_index_size(cmd
->state
.index_type
);
3230 const uint32_t index_bytes
=
3231 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3232 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3233 unsigned max_indicies
=
3234 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3236 const uint32_t cp_draw_indx
=
3237 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3238 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3239 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3240 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3241 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3243 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3244 tu_cs_emit(cs
, cp_draw_indx
);
3245 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3246 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3247 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3249 const uint32_t cp_draw_indx
=
3250 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3251 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3252 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3253 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3255 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3256 tu_cs_emit(cs
, cp_draw_indx
);
3257 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3260 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3264 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3266 const struct tu_draw_info
*draw
)
3269 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3270 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3271 VK_SHADER_STAGE_GEOMETRY_BIT
;
3274 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3275 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3277 /* TODO hw binning */
3278 if (draw
->indexed
) {
3279 const enum a4xx_index_size index_size
=
3280 tu6_index_size(cmd
->state
.index_type
);
3281 const uint32_t index_bytes
=
3282 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3283 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3284 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3285 index_bytes
* draw
->first_index
;
3286 const uint32_t size
= index_bytes
* draw
->count
;
3288 const uint32_t cp_draw_indx
=
3289 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3290 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3291 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3292 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3293 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3295 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3296 tu_cs_emit(cs
, cp_draw_indx
);
3297 tu_cs_emit(cs
, draw
->instance_count
);
3298 tu_cs_emit(cs
, draw
->count
);
3299 tu_cs_emit(cs
, 0x0); /* XXX */
3300 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3301 tu_cs_emit(cs
, size
);
3303 const uint32_t cp_draw_indx
=
3304 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3305 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3306 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3307 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3309 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3310 tu_cs_emit(cs
, cp_draw_indx
);
3311 tu_cs_emit(cs
, draw
->instance_count
);
3312 tu_cs_emit(cs
, draw
->count
);
3317 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3319 struct tu_cs
*cs
= &cmd
->draw_cs
;
3322 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3323 if (result
!= VK_SUCCESS
) {
3324 cmd
->record_result
= result
;
3329 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3331 tu6_emit_draw_direct(cmd
, cs
, draw
);
3333 if (cmd
->state
.streamout_enabled
) {
3334 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3335 if (cmd
->state
.streamout_enabled
& (1 << i
))
3336 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
, false);
3340 cmd
->wait_for_idle
= true;
3342 tu_cs_sanity_check(cs
);
3346 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3347 uint32_t vertexCount
,
3348 uint32_t instanceCount
,
3349 uint32_t firstVertex
,
3350 uint32_t firstInstance
)
3352 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3353 struct tu_draw_info info
= {};
3355 info
.count
= vertexCount
;
3356 info
.instance_count
= instanceCount
;
3357 info
.first_instance
= firstInstance
;
3358 info
.vertex_offset
= firstVertex
;
3360 tu_draw(cmd_buffer
, &info
);
3364 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3365 uint32_t indexCount
,
3366 uint32_t instanceCount
,
3367 uint32_t firstIndex
,
3368 int32_t vertexOffset
,
3369 uint32_t firstInstance
)
3371 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3372 struct tu_draw_info info
= {};
3374 info
.indexed
= true;
3375 info
.count
= indexCount
;
3376 info
.instance_count
= instanceCount
;
3377 info
.first_index
= firstIndex
;
3378 info
.vertex_offset
= vertexOffset
;
3379 info
.first_instance
= firstInstance
;
3381 tu_draw(cmd_buffer
, &info
);
3385 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3387 VkDeviceSize offset
,
3391 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3392 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3393 struct tu_draw_info info
= {};
3395 info
.count
= drawCount
;
3396 info
.indirect
= buffer
;
3397 info
.indirect_offset
= offset
;
3398 info
.stride
= stride
;
3400 tu_draw(cmd_buffer
, &info
);
3404 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3406 VkDeviceSize offset
,
3410 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3411 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3412 struct tu_draw_info info
= {};
3414 info
.indexed
= true;
3415 info
.count
= drawCount
;
3416 info
.indirect
= buffer
;
3417 info
.indirect_offset
= offset
;
3418 info
.stride
= stride
;
3420 tu_draw(cmd_buffer
, &info
);
3423 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3424 uint32_t instanceCount
,
3425 uint32_t firstInstance
,
3426 VkBuffer _counterBuffer
,
3427 VkDeviceSize counterBufferOffset
,
3428 uint32_t counterOffset
,
3429 uint32_t vertexStride
)
3431 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3432 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3434 struct tu_draw_info info
= {};
3436 info
.instance_count
= instanceCount
;
3437 info
.first_instance
= firstInstance
;
3438 info
.streamout_buffer
= buffer
;
3439 info
.streamout_buffer_offset
= counterBufferOffset
;
3440 info
.stride
= vertexStride
;
3442 tu_draw(cmd_buffer
, &info
);
3445 struct tu_dispatch_info
3448 * Determine the layout of the grid (in block units) to be used.
3453 * A starting offset for the grid. If unaligned is set, the offset
3454 * must still be aligned.
3456 uint32_t offsets
[3];
3458 * Whether it's an unaligned compute dispatch.
3463 * Indirect compute parameters resource.
3465 struct tu_buffer
*indirect
;
3466 uint64_t indirect_offset
;
3470 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3471 const struct tu_dispatch_info
*info
)
3473 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3474 const struct tu_program_descriptor_linkage
*link
=
3475 &pipeline
->program
.link
[type
];
3476 const struct ir3_const_state
*const_state
= &link
->const_state
;
3477 uint32_t offset
= const_state
->offsets
.driver_param
;
3479 if (link
->constlen
<= offset
)
3482 if (!info
->indirect
) {
3483 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3484 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3485 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3486 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3487 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3488 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3489 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3492 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3493 (link
->constlen
- offset
) * 4);
3494 /* push constants */
3495 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3496 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3497 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3498 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3499 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3500 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3504 for (i
= 0; i
< num_consts
; i
++)
3505 tu_cs_emit(cs
, driver_params
[i
]);
3507 tu_finishme("Indirect driver params");
3512 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3513 const struct tu_dispatch_info
*info
)
3515 struct tu_cs
*cs
= &cmd
->cs
;
3516 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3517 struct tu_descriptor_state
*descriptors_state
=
3518 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3521 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3522 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3524 struct tu_cs_entry ib
;
3526 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3528 tu_cs_emit_ib(cs
, &ib
);
3530 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3532 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) {
3533 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3534 VK_PIPELINE_BIND_POINT_COMPUTE
, &ib
,
3536 if (result
!= VK_SUCCESS
) {
3537 cmd
->record_result
= result
;
3543 for_each_bit(i
, descriptors_state
->valid
) {
3544 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3545 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3546 if (set
->buffers
[j
]) {
3547 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3548 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3552 if (set
->size
> 0) {
3553 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3554 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3560 tu_cs_emit_ib(cs
, &ib
);
3562 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
)
3563 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3566 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3568 /* Compute shader state overwrites fragment shader state, so we flag the
3569 * graphics pipeline for re-emit.
3571 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
3573 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3574 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3576 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3577 const uint32_t *num_groups
= info
->blocks
;
3579 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3580 .localsizex
= local_size
[0] - 1,
3581 .localsizey
= local_size
[1] - 1,
3582 .localsizez
= local_size
[2] - 1),
3583 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3584 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3585 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3586 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3587 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3588 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3591 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3592 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3593 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3595 if (info
->indirect
) {
3596 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3598 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3599 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3601 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3602 tu_cs_emit(cs
, 0x00000000);
3603 tu_cs_emit_qw(cs
, iova
);
3605 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3606 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3607 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3609 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3610 tu_cs_emit(cs
, 0x00000000);
3611 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3612 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3613 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3618 tu6_emit_cache_flush(cmd
, cs
);
3622 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3630 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3631 struct tu_dispatch_info info
= {};
3637 info
.offsets
[0] = base_x
;
3638 info
.offsets
[1] = base_y
;
3639 info
.offsets
[2] = base_z
;
3640 tu_dispatch(cmd_buffer
, &info
);
3644 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3649 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3653 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3655 VkDeviceSize offset
)
3657 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3658 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3659 struct tu_dispatch_info info
= {};
3661 info
.indirect
= buffer
;
3662 info
.indirect_offset
= offset
;
3664 tu_dispatch(cmd_buffer
, &info
);
3668 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3670 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3672 tu_cs_end(&cmd_buffer
->draw_cs
);
3673 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3675 if (use_sysmem_rendering(cmd_buffer
))
3676 tu_cmd_render_sysmem(cmd_buffer
);
3678 tu_cmd_render_tiles(cmd_buffer
);
3680 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3682 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3683 tu_cs_begin(&cmd_buffer
->draw_cs
);
3684 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3685 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3687 cmd_buffer
->state
.pass
= NULL
;
3688 cmd_buffer
->state
.subpass
= NULL
;
3689 cmd_buffer
->state
.framebuffer
= NULL
;
3693 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3694 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3696 tu_CmdEndRenderPass(commandBuffer
);
3699 struct tu_barrier_info
3701 uint32_t eventCount
;
3702 const VkEvent
*pEvents
;
3703 VkPipelineStageFlags srcStageMask
;
3707 tu_barrier(struct tu_cmd_buffer
*cmd
,
3708 uint32_t memoryBarrierCount
,
3709 const VkMemoryBarrier
*pMemoryBarriers
,
3710 uint32_t bufferMemoryBarrierCount
,
3711 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3712 uint32_t imageMemoryBarrierCount
,
3713 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3714 const struct tu_barrier_info
*info
)
3716 /* renderpass case is only for subpass self-dependencies
3717 * which means syncing the render output with texture cache
3718 * note: only the CACHE_INVALIDATE is needed in GMEM mode
3719 * and in sysmem mode we might not need either color/depth flush
3721 if (cmd
->state
.pass
) {
3722 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_COLOR_TS
, true);
3723 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
3724 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, CACHE_INVALIDATE
, false);
3730 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3731 VkPipelineStageFlags srcStageMask
,
3732 VkPipelineStageFlags dstStageMask
,
3733 VkDependencyFlags dependencyFlags
,
3734 uint32_t memoryBarrierCount
,
3735 const VkMemoryBarrier
*pMemoryBarriers
,
3736 uint32_t bufferMemoryBarrierCount
,
3737 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3738 uint32_t imageMemoryBarrierCount
,
3739 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3741 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3742 struct tu_barrier_info info
;
3744 info
.eventCount
= 0;
3745 info
.pEvents
= NULL
;
3746 info
.srcStageMask
= srcStageMask
;
3748 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3749 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3750 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3754 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
, unsigned value
)
3756 struct tu_cs
*cs
= &cmd
->cs
;
3758 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3760 /* TODO: any flush required before/after ? */
3762 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3763 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3764 tu_cs_emit(cs
, value
);
3768 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3770 VkPipelineStageFlags stageMask
)
3772 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3773 TU_FROM_HANDLE(tu_event
, event
, _event
);
3775 write_event(cmd
, event
, 1);
3779 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3781 VkPipelineStageFlags stageMask
)
3783 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3784 TU_FROM_HANDLE(tu_event
, event
, _event
);
3786 write_event(cmd
, event
, 0);
3790 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3791 uint32_t eventCount
,
3792 const VkEvent
*pEvents
,
3793 VkPipelineStageFlags srcStageMask
,
3794 VkPipelineStageFlags dstStageMask
,
3795 uint32_t memoryBarrierCount
,
3796 const VkMemoryBarrier
*pMemoryBarriers
,
3797 uint32_t bufferMemoryBarrierCount
,
3798 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3799 uint32_t imageMemoryBarrierCount
,
3800 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3802 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3803 struct tu_cs
*cs
= &cmd
->cs
;
3805 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3807 for (uint32_t i
= 0; i
< eventCount
; i
++) {
3808 TU_FROM_HANDLE(tu_event
, event
, pEvents
[i
]);
3810 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3812 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3813 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3814 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3815 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3816 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3817 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3818 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3823 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)