2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
113 const struct tu_device
*dev
,
114 const struct tu_render_pass
*pass
)
116 const uint32_t tile_align_w
= pass
->tile_align_w
;
117 const uint32_t max_tile_width
= 1024;
119 /* note: don't offset the tiling config by render_area.offset,
120 * because binning pass can't deal with it
121 * this means we might end up with more tiles than necessary,
122 * but load/store/etc are still scissored to the render_area
124 tiling
->tile0
.offset
= (VkOffset2D
) {};
126 const uint32_t ra_width
=
127 tiling
->render_area
.extent
.width
+
128 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
129 const uint32_t ra_height
=
130 tiling
->render_area
.extent
.height
+
131 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
133 /* start from 1 tile */
134 tiling
->tile_count
= (VkExtent2D
) {
138 tiling
->tile0
.extent
= (VkExtent2D
) {
139 .width
= util_align_npot(ra_width
, tile_align_w
),
140 .height
= align(ra_height
, TILE_ALIGN_H
),
143 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
144 /* start with 2x2 tiles */
145 tiling
->tile_count
.width
= 2;
146 tiling
->tile_count
.height
= 2;
147 tiling
->tile0
.extent
.width
= util_align_npot(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
148 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), TILE_ALIGN_H
);
151 /* do not exceed max tile width */
152 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
153 tiling
->tile_count
.width
++;
154 tiling
->tile0
.extent
.width
=
155 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
158 /* will force to sysmem, don't bother trying to have a valid tile config
159 * TODO: just skip all GMEM stuff when sysmem is forced?
161 if (!pass
->gmem_pixels
)
164 /* do not exceed gmem size */
165 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pass
->gmem_pixels
) {
166 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
167 tiling
->tile_count
.width
++;
168 tiling
->tile0
.extent
.width
=
169 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
171 /* if this assert fails then layout is impossible.. */
172 assert(tiling
->tile0
.extent
.height
> TILE_ALIGN_H
);
173 tiling
->tile_count
.height
++;
174 tiling
->tile0
.extent
.height
=
175 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), TILE_ALIGN_H
);
181 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
182 const struct tu_device
*dev
)
184 const uint32_t max_pipe_count
= 32; /* A6xx */
186 /* start from 1 tile per pipe */
187 tiling
->pipe0
= (VkExtent2D
) {
191 tiling
->pipe_count
= tiling
->tile_count
;
193 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
194 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
195 tiling
->pipe0
.width
+= 1;
196 tiling
->pipe_count
.width
=
197 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
199 tiling
->pipe0
.height
+= 1;
200 tiling
->pipe_count
.height
=
201 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
207 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
208 const struct tu_device
*dev
)
210 const uint32_t max_pipe_count
= 32; /* A6xx */
211 const uint32_t used_pipe_count
=
212 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
213 const VkExtent2D last_pipe
= {
214 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
215 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
218 assert(used_pipe_count
<= max_pipe_count
);
219 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
221 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
222 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
223 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
224 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
225 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
227 : tiling
->pipe0
.width
;
228 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
230 : tiling
->pipe0
.height
;
231 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
233 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
234 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
235 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
236 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
237 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
241 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
242 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
246 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
247 const struct tu_device
*dev
,
250 struct tu_tile
*tile
)
252 /* find the pipe and the slot for tile (tx, ty) */
253 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
254 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
255 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
256 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
257 /* last pipe has different width */
258 const uint32_t pipe_width
=
259 MIN2(tiling
->pipe0
.width
,
260 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
262 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
263 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
264 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
266 /* convert to 1D indices */
267 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
268 tile
->slot
= pipe_width
* sy
+ sx
;
270 /* get the blit area for the tile */
271 tile
->begin
= (VkOffset2D
) {
272 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
273 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
276 (tx
== tiling
->tile_count
.width
- 1)
277 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
278 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
280 (ty
== tiling
->tile_count
.height
- 1)
281 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
282 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
286 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
288 enum vgt_event_type event
)
290 bool need_seqno
= false;
295 case PC_CCU_FLUSH_DEPTH_TS
:
296 case PC_CCU_FLUSH_COLOR_TS
:
297 case PC_CCU_RESOLVE_TS
:
304 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
305 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
307 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
313 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
315 enum tu_cmd_flush_bits flushes
)
317 /* Experiments show that invalidating CCU while it still has data in it
318 * doesn't work, so make sure to always flush before invalidating in case
319 * any data remains that hasn't yet been made available through a barrier.
320 * However it does seem to work for UCHE.
322 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
323 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
324 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
325 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
326 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
327 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
328 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
329 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
330 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
331 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
332 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
333 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
334 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
335 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
336 if (flushes
& TU_CMD_FLAG_WFI
)
340 /* "Normal" cache flushes, that don't require any special handling */
343 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
346 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
347 cmd_buffer
->state
.cache
.flush_bits
= 0;
350 /* Renderpass cache flushes */
353 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
356 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
357 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
360 /* Cache flushes for things that use the color/depth read/write path (i.e.
361 * blits and draws). This deals with changing CCU state as well as the usual
366 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
368 enum tu_cmd_ccu_state ccu_state
)
370 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
372 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
374 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
375 * the CCU may also contain data that we haven't flushed out yet, so we
376 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
377 * emit a WFI as it isn't pipelined.
379 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
380 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
382 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
383 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
384 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
385 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
386 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
389 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
390 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
392 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
393 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
394 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
);
397 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
398 cmd_buffer
->state
.cache
.flush_bits
= 0;
400 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
401 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
403 A6XX_RB_CCU_CNTL(.offset
=
404 ccu_state
== TU_CMD_CCU_GMEM
?
405 phys_dev
->ccu_offset_gmem
:
406 phys_dev
->ccu_offset_bypass
,
407 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
408 cmd_buffer
->state
.ccu_state
= ccu_state
;
413 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
414 const struct tu_subpass
*subpass
,
417 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
419 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
420 if (a
== VK_ATTACHMENT_UNUSED
) {
422 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
423 A6XX_RB_DEPTH_BUFFER_PITCH(0),
424 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
425 A6XX_RB_DEPTH_BUFFER_BASE(0),
426 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
429 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
432 A6XX_GRAS_LRZ_BUFFER_BASE(0),
433 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
434 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
436 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
441 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
442 const struct tu_render_pass_attachment
*attachment
=
443 &cmd
->state
.pass
->attachments
[a
];
444 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
446 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
447 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
448 tu_cs_image_ref(cs
, iview
, 0);
449 tu_cs_emit(cs
, attachment
->gmem_offset
);
452 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
454 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
455 tu_cs_image_flag_ref(cs
, iview
, 0);
458 A6XX_GRAS_LRZ_BUFFER_BASE(0),
459 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
460 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
462 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
463 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
464 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
465 tu_cs_image_ref(cs
, iview
, 0);
466 tu_cs_emit(cs
, attachment
->gmem_offset
);
469 A6XX_RB_STENCIL_INFO(0));
474 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
475 const struct tu_subpass
*subpass
,
478 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
480 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
481 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
482 if (a
== VK_ATTACHMENT_UNUSED
)
485 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
487 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
488 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
489 tu_cs_image_ref(cs
, iview
, 0);
490 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
493 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
495 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
496 tu_cs_image_flag_ref(cs
, iview
, 0);
500 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
502 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
504 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
508 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
510 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
511 bool msaa_disable
= samples
== MSAA_ONE
;
514 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
515 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
516 .msaa_disable
= msaa_disable
));
519 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
520 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
521 .msaa_disable
= msaa_disable
));
524 A6XX_RB_RAS_MSAA_CNTL(samples
),
525 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
526 .msaa_disable
= msaa_disable
));
529 A6XX_RB_MSAA_CNTL(samples
));
533 tu6_emit_bin_size(struct tu_cs
*cs
,
534 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
537 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
542 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
546 /* no flag for RB_BIN_CONTROL2... */
548 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
553 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
554 const struct tu_subpass
*subpass
,
558 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
560 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
562 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
564 uint32_t mrts_ubwc_enable
= 0;
565 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
566 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
567 if (a
== VK_ATTACHMENT_UNUSED
)
570 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
571 if (iview
->ubwc_enabled
)
572 mrts_ubwc_enable
|= 1 << i
;
575 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
577 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
578 if (a
!= VK_ATTACHMENT_UNUSED
) {
579 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
580 if (iview
->ubwc_enabled
)
581 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
584 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
585 * in order to set it correctly for the different subpasses. However,
586 * that means the packets we're emitting also happen during binning. So
587 * we need to guard the write on !BINNING at CP execution time.
589 tu_cs_reserve(cs
, 3 + 4);
590 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
591 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
592 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
593 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
596 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
597 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
598 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
599 tu_cs_emit(cs
, cntl
);
603 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
605 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
606 uint32_t x1
= render_area
->offset
.x
;
607 uint32_t y1
= render_area
->offset
.y
;
608 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
609 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
612 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
613 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
614 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
615 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
619 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
620 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
624 tu6_emit_window_scissor(struct tu_cs
*cs
,
631 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
632 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
635 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
636 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
640 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
643 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
646 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
649 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
652 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
656 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
658 uint32_t enable_mask
;
660 case TU_DRAW_STATE_PROGRAM
:
661 case TU_DRAW_STATE_VI
:
662 case TU_DRAW_STATE_FS_CONST
:
663 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
664 * when resources would actually be used in the binning shader.
665 * Presumably the overhead of prefetching the resources isn't
668 case TU_DRAW_STATE_DESC_SETS_LOAD
:
669 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
670 CP_SET_DRAW_STATE__0_SYSMEM
;
672 case TU_DRAW_STATE_PROGRAM_BINNING
:
673 case TU_DRAW_STATE_VI_BINNING
:
674 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
676 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
677 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
679 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
680 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
683 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
684 CP_SET_DRAW_STATE__0_SYSMEM
|
685 CP_SET_DRAW_STATE__0_BINNING
;
689 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
691 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
692 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
693 tu_cs_emit_qw(cs
, state
.iova
);
696 /* note: get rid of this eventually */
698 tu_cs_emit_sds_ib(struct tu_cs
*cs
, uint32_t id
, struct tu_cs_entry entry
)
700 tu_cs_emit_draw_state(cs
, id
, (struct tu_draw_state
) {
701 .iova
= entry
.size
? entry
.bo
->iova
+ entry
.offset
: 0,
702 .size
= entry
.size
/ 4,
707 use_hw_binning(struct tu_cmd_buffer
*cmd
)
709 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
711 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
714 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
717 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
721 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
723 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
726 /* can't fit attachments into gmem */
727 if (!cmd
->state
.pass
->gmem_pixels
)
730 if (cmd
->state
.framebuffer
->layers
> 1)
733 return cmd
->state
.tiling_config
.force_sysmem
;
737 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
739 const struct tu_tile
*tile
)
741 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
742 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
744 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
745 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
747 const uint32_t x1
= tile
->begin
.x
;
748 const uint32_t y1
= tile
->begin
.y
;
749 const uint32_t x2
= tile
->end
.x
- 1;
750 const uint32_t y2
= tile
->end
.y
- 1;
751 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
752 tu6_emit_window_offset(cs
, x1
, y1
);
755 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
757 if (use_hw_binning(cmd
)) {
758 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
760 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
763 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
764 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
765 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
766 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ tile
->pipe
* cmd
->vsc_draw_strm_pitch
);
767 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_draw_strm_pitch
));
768 tu_cs_emit_qw(cs
, cmd
->vsc_prim_strm
.iova
+ (tile
->pipe
* cmd
->vsc_prim_strm_pitch
));
770 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
773 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
776 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
779 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
785 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
790 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
791 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
792 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
794 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
798 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
800 const struct tu_subpass
*subpass
)
802 if (subpass
->resolve_attachments
) {
803 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
806 * End-of-subpass multisample resolves are treated as color
807 * attachment writes for the purposes of synchronization. That is,
808 * they are considered to execute in the
809 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
810 * their writes are synchronized with
811 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
812 * rendering within a subpass and any resolve operations at the end
813 * of the subpass occurs automatically, without need for explicit
814 * dependencies or pipeline barriers. However, if the resolve
815 * attachment is also used in a different subpass, an explicit
816 * dependency is needed.
818 * We use the CP_BLIT path for sysmem resolves, which is really a
819 * transfer command, so we have to manually flush similar to the gmem
820 * resolve case. However, a flush afterwards isn't needed because of the
821 * last sentence and the fact that we're in sysmem mode.
823 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
824 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
826 /* Wait for the flushes to land before using the 2D engine */
829 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
830 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
831 if (a
== VK_ATTACHMENT_UNUSED
)
834 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
835 subpass
->color_attachments
[i
].attachment
);
841 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
843 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
844 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
846 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
847 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
848 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
849 CP_SET_DRAW_STATE__0_GROUP_ID(0));
850 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
851 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
853 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
856 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
857 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
859 tu6_emit_blit_scissor(cmd
, cs
, true);
861 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
862 if (pass
->attachments
[a
].gmem_offset
>= 0)
863 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
866 if (subpass
->resolve_attachments
) {
867 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
868 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
869 if (a
!= VK_ATTACHMENT_UNUSED
)
870 tu_store_gmem_attachment(cmd
, cs
, a
,
871 subpass
->color_attachments
[i
].attachment
);
877 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
880 A6XX_PC_RESTART_INDEX(restart_index
));
884 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
886 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
888 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
890 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
893 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
894 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
895 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
896 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
897 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
898 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
899 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
900 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
901 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
902 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
904 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
905 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
906 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
907 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
908 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
909 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
910 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
911 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
912 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
913 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
914 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
915 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
916 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
917 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
919 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
920 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
921 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
923 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
925 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
927 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
928 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
929 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
930 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
931 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
932 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
933 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
934 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
935 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
936 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
937 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
939 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
940 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
942 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
,
943 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
944 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
946 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
947 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
949 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
950 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
951 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
954 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
958 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
960 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
961 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
962 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
963 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
965 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
966 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
970 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
973 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
975 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
977 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
979 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
981 /* we don't use this yet.. probably best to disable.. */
982 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
983 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
984 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
985 CP_SET_DRAW_STATE__0_GROUP_ID(0));
986 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
987 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
989 /* Set not to use streamout by default, */
990 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
991 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
993 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
997 A6XX_SP_HS_CTRL_REG0(0));
1000 A6XX_SP_GS_CTRL_REG0(0));
1003 A6XX_GRAS_LRZ_CNTL(0));
1006 A6XX_RB_LRZ_CNTL(0));
1009 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1011 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1013 tu_cs_sanity_check(cs
);
1017 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1019 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1022 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
1023 .height
= tiling
->tile0
.extent
.height
),
1024 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= &cmd
->vsc_draw_strm
,
1025 .bo_offset
= 32 * cmd
->vsc_draw_strm_pitch
));
1028 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
1029 .ny
= tiling
->tile_count
.height
));
1031 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1032 for (unsigned i
= 0; i
< 32; i
++)
1033 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
1036 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= &cmd
->vsc_prim_strm
),
1037 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
1038 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- 64));
1041 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= &cmd
->vsc_draw_strm
),
1042 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
1043 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- 64));
1047 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1049 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1050 const uint32_t used_pipe_count
=
1051 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1053 /* Clear vsc_scratch: */
1054 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1055 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1056 tu_cs_emit(cs
, 0x0);
1058 /* Check for overflow, write vsc_scratch if detected: */
1059 for (int i
= 0; i
< used_pipe_count
; i
++) {
1060 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1061 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1062 CP_COND_WRITE5_0_WRITE_MEMORY
);
1063 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
1064 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1065 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- 64));
1066 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1067 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1068 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_draw_strm_pitch
));
1070 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1071 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1072 CP_COND_WRITE5_0_WRITE_MEMORY
);
1073 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
1074 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1075 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- 64));
1076 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1077 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1078 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_prim_strm_pitch
));
1081 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1085 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1087 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1088 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1090 uint32_t x1
= tiling
->tile0
.offset
.x
;
1091 uint32_t y1
= tiling
->tile0
.offset
.y
;
1092 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1093 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1095 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1097 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1098 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1100 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1101 tu_cs_emit(cs
, 0x1);
1103 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1104 tu_cs_emit(cs
, 0x1);
1109 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1111 update_vsc_pipe(cmd
, cs
);
1114 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1117 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1119 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1120 tu_cs_emit(cs
, UNK_2C
);
1123 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1126 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1128 /* emit IB to binning drawcmds: */
1129 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1131 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1132 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1133 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1134 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1135 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1136 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1138 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1139 tu_cs_emit(cs
, UNK_2D
);
1141 /* This flush is probably required because the VSC, which produces the
1142 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1143 * visibility stream (without caching) to do draw skipping. The
1144 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1145 * submitted are finished before reading the VSC regs (in
1146 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1149 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1153 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1155 emit_vsc_overflow_test(cmd
, cs
);
1157 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1158 tu_cs_emit(cs
, 0x0);
1160 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1161 tu_cs_emit(cs
, 0x0);
1165 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1166 const struct tu_subpass
*subpass
,
1167 struct tu_cs_entry
*ib
,
1170 /* note: we can probably emit input attachments just once for the whole
1171 * renderpass, this would avoid emitting both sysmem/gmem versions
1173 * emit two texture descriptors for each input, as a workaround for
1174 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1175 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1177 * TODO: a smarter workaround
1180 if (!subpass
->input_count
)
1183 struct ts_cs_memory texture
;
1184 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1185 A6XX_TEX_CONST_DWORDS
, &texture
);
1186 assert(result
== VK_SUCCESS
);
1188 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1189 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1190 if (a
== VK_ATTACHMENT_UNUSED
)
1193 struct tu_image_view
*iview
=
1194 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1195 const struct tu_render_pass_attachment
*att
=
1196 &cmd
->state
.pass
->attachments
[a
];
1197 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1199 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1201 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1202 /* note this works because spec says fb and input attachments
1203 * must use identity swizzle
1205 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1206 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1207 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1208 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1209 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1210 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1211 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1212 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1218 /* patched for gmem */
1219 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1220 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1222 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1223 A6XX_TEX_CONST_2_PITCH(cmd
->state
.tiling_config
.tile0
.extent
.width
* att
->cpp
);
1225 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1226 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1227 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1232 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 9, &cs
);
1234 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1235 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1236 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1237 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1238 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1239 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1240 tu_cs_emit_qw(&cs
, texture
.iova
);
1242 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1243 tu_cs_emit_qw(&cs
, texture
.iova
);
1245 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1247 *ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
1251 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1253 struct tu_cs
*cs
= &cmd
->draw_cs
;
1255 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_gmem_ib
, true);
1256 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_sysmem_ib
, false);
1258 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1259 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
, cmd
->state
.ia_gmem_ib
);
1260 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
, cmd
->state
.ia_sysmem_ib
);
1264 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1265 const VkRenderPassBeginInfo
*info
)
1267 struct tu_cs
*cs
= &cmd
->draw_cs
;
1269 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1271 tu6_emit_blit_scissor(cmd
, cs
, true);
1273 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1274 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1276 tu6_emit_blit_scissor(cmd
, cs
, false);
1278 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1279 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1281 tu_cond_exec_end(cs
);
1283 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1285 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1286 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1288 tu_cond_exec_end(cs
);
1292 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1293 const struct VkRect2D
*renderArea
)
1295 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1297 assert(fb
->width
> 0 && fb
->height
> 0);
1298 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1299 tu6_emit_window_offset(cs
, 0, 0);
1301 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1303 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1305 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1306 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1308 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1309 tu_cs_emit(cs
, 0x0);
1311 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1313 /* enable stream-out, with sysmem there is only one pass: */
1315 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1317 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1318 tu_cs_emit(cs
, 0x1);
1320 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1321 tu_cs_emit(cs
, 0x0);
1323 tu_cs_sanity_check(cs
);
1327 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1329 /* Do any resolves of the last subpass. These are handled in the
1330 * tile_store_ib in the gmem path.
1332 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1334 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1336 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1337 tu_cs_emit(cs
, 0x0);
1339 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1341 tu_cs_sanity_check(cs
);
1345 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1347 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1349 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1353 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1354 tu_cs_emit(cs
, 0x0);
1356 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1358 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1359 if (use_hw_binning(cmd
)) {
1360 /* enable stream-out during binning pass: */
1361 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1363 tu6_emit_bin_size(cs
,
1364 tiling
->tile0
.extent
.width
,
1365 tiling
->tile0
.extent
.height
,
1366 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1368 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1370 tu6_emit_binning_pass(cmd
, cs
);
1372 /* and disable stream-out for draw pass: */
1373 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1375 tu6_emit_bin_size(cs
,
1376 tiling
->tile0
.extent
.width
,
1377 tiling
->tile0
.extent
.height
,
1378 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1381 A6XX_VFD_MODE_CNTL(0));
1383 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1385 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1387 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1388 tu_cs_emit(cs
, 0x1);
1390 /* no binning pass, so enable stream-out for draw pass:: */
1391 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1393 tu6_emit_bin_size(cs
,
1394 tiling
->tile0
.extent
.width
,
1395 tiling
->tile0
.extent
.height
,
1399 tu_cs_sanity_check(cs
);
1403 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1405 const struct tu_tile
*tile
)
1407 tu6_emit_tile_select(cmd
, cs
, tile
);
1409 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1411 if (use_hw_binning(cmd
)) {
1412 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1413 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1416 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1418 tu_cs_sanity_check(cs
);
1422 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1424 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1427 A6XX_GRAS_LRZ_CNTL(0));
1429 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1431 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1433 tu_cs_sanity_check(cs
);
1437 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1439 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1441 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1443 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1444 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1445 struct tu_tile tile
;
1446 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1447 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1451 tu6_tile_render_end(cmd
, &cmd
->cs
);
1455 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1457 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1459 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1461 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1463 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1467 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1469 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1470 struct tu_cs sub_cs
;
1473 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1474 if (result
!= VK_SUCCESS
) {
1475 cmd
->record_result
= result
;
1479 /* emit to tile-store sub_cs */
1480 tu6_emit_tile_store(cmd
, &sub_cs
);
1482 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1486 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1487 const VkRect2D
*render_area
)
1489 const struct tu_device
*dev
= cmd
->device
;
1490 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1492 tiling
->render_area
= *render_area
;
1493 tiling
->force_sysmem
= false;
1495 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
);
1496 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1497 tu_tiling_config_update_pipes(tiling
, dev
);
1501 tu_create_cmd_buffer(struct tu_device
*device
,
1502 struct tu_cmd_pool
*pool
,
1503 VkCommandBufferLevel level
,
1504 VkCommandBuffer
*pCommandBuffer
)
1506 struct tu_cmd_buffer
*cmd_buffer
;
1507 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1508 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1509 if (cmd_buffer
== NULL
)
1510 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1512 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1513 cmd_buffer
->device
= device
;
1514 cmd_buffer
->pool
= pool
;
1515 cmd_buffer
->level
= level
;
1518 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1519 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1522 /* Init the pool_link so we can safely call list_del when we destroy
1523 * the command buffer
1525 list_inithead(&cmd_buffer
->pool_link
);
1526 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1529 tu_bo_list_init(&cmd_buffer
->bo_list
);
1530 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1531 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1532 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1533 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1535 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1537 list_inithead(&cmd_buffer
->upload
.list
);
1539 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1540 if (result
!= VK_SUCCESS
)
1541 goto fail_scratch_bo
;
1543 /* TODO: resize on overflow */
1544 cmd_buffer
->vsc_draw_strm_pitch
= device
->vsc_draw_strm_pitch
;
1545 cmd_buffer
->vsc_prim_strm_pitch
= device
->vsc_prim_strm_pitch
;
1546 cmd_buffer
->vsc_draw_strm
= device
->vsc_draw_strm
;
1547 cmd_buffer
->vsc_prim_strm
= device
->vsc_prim_strm
;
1552 list_del(&cmd_buffer
->pool_link
);
1557 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1559 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1561 list_del(&cmd_buffer
->pool_link
);
1563 tu_cs_finish(&cmd_buffer
->cs
);
1564 tu_cs_finish(&cmd_buffer
->draw_cs
);
1565 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1566 tu_cs_finish(&cmd_buffer
->sub_cs
);
1568 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1569 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1573 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1575 cmd_buffer
->record_result
= VK_SUCCESS
;
1577 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1578 tu_cs_reset(&cmd_buffer
->cs
);
1579 tu_cs_reset(&cmd_buffer
->draw_cs
);
1580 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1581 tu_cs_reset(&cmd_buffer
->sub_cs
);
1583 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1584 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1586 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1588 return cmd_buffer
->record_result
;
1592 tu_AllocateCommandBuffers(VkDevice _device
,
1593 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1594 VkCommandBuffer
*pCommandBuffers
)
1596 TU_FROM_HANDLE(tu_device
, device
, _device
);
1597 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1599 VkResult result
= VK_SUCCESS
;
1602 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1604 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1605 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1606 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1608 list_del(&cmd_buffer
->pool_link
);
1609 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1611 result
= tu_reset_cmd_buffer(cmd_buffer
);
1612 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1613 cmd_buffer
->level
= pAllocateInfo
->level
;
1615 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1617 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1618 &pCommandBuffers
[i
]);
1620 if (result
!= VK_SUCCESS
)
1624 if (result
!= VK_SUCCESS
) {
1625 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1628 /* From the Vulkan 1.0.66 spec:
1630 * "vkAllocateCommandBuffers can be used to create multiple
1631 * command buffers. If the creation of any of those command
1632 * buffers fails, the implementation must destroy all
1633 * successfully created command buffer objects from this
1634 * command, set all entries of the pCommandBuffers array to
1635 * NULL and return the error."
1637 memset(pCommandBuffers
, 0,
1638 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1645 tu_FreeCommandBuffers(VkDevice device
,
1646 VkCommandPool commandPool
,
1647 uint32_t commandBufferCount
,
1648 const VkCommandBuffer
*pCommandBuffers
)
1650 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1651 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1654 if (cmd_buffer
->pool
) {
1655 list_del(&cmd_buffer
->pool_link
);
1656 list_addtail(&cmd_buffer
->pool_link
,
1657 &cmd_buffer
->pool
->free_cmd_buffers
);
1659 tu_cmd_buffer_destroy(cmd_buffer
);
1665 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1666 VkCommandBufferResetFlags flags
)
1668 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1669 return tu_reset_cmd_buffer(cmd_buffer
);
1672 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1676 tu_cache_init(struct tu_cache_state
*cache
)
1678 cache
->flush_bits
= 0;
1679 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1683 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1684 const VkCommandBufferBeginInfo
*pBeginInfo
)
1686 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1687 VkResult result
= VK_SUCCESS
;
1689 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1690 /* If the command buffer has already been resetted with
1691 * vkResetCommandBuffer, no need to do it again.
1693 result
= tu_reset_cmd_buffer(cmd_buffer
);
1694 if (result
!= VK_SUCCESS
)
1698 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1699 tu_cache_init(&cmd_buffer
->state
.cache
);
1700 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1701 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1703 tu_cs_begin(&cmd_buffer
->cs
);
1704 tu_cs_begin(&cmd_buffer
->draw_cs
);
1705 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1707 /* setup initial configuration into command buffer */
1708 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1709 switch (cmd_buffer
->queue_family_index
) {
1710 case TU_QUEUE_GENERAL
:
1711 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1716 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1717 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1718 assert(pBeginInfo
->pInheritanceInfo
);
1719 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1720 cmd_buffer
->state
.subpass
=
1721 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1723 /* When executing in the middle of another command buffer, the CCU
1726 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1730 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1735 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1736 * rendering can skip over unused state), so we need to collect all the
1737 * bindings together into a single state emit at draw time.
1740 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1741 uint32_t firstBinding
,
1742 uint32_t bindingCount
,
1743 const VkBuffer
*pBuffers
,
1744 const VkDeviceSize
*pOffsets
)
1746 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1748 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1750 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1751 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1753 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1754 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1756 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1759 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1763 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1765 VkDeviceSize offset
,
1766 VkIndexType indexType
)
1768 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1769 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1771 /* initialize/update the restart index */
1772 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1773 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1775 tu6_emit_restart_index(
1776 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1778 tu_cs_sanity_check(draw_cs
);
1782 if (cmd
->state
.index_buffer
!= buf
)
1783 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1785 cmd
->state
.index_buffer
= buf
;
1786 cmd
->state
.index_offset
= offset
;
1787 cmd
->state
.index_type
= indexType
;
1791 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1792 VkPipelineBindPoint pipelineBindPoint
,
1793 VkPipelineLayout _layout
,
1795 uint32_t descriptorSetCount
,
1796 const VkDescriptorSet
*pDescriptorSets
,
1797 uint32_t dynamicOffsetCount
,
1798 const uint32_t *pDynamicOffsets
)
1800 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1801 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1802 unsigned dyn_idx
= 0;
1804 struct tu_descriptor_state
*descriptors_state
=
1805 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1807 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1808 unsigned idx
= i
+ firstSet
;
1809 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1811 descriptors_state
->sets
[idx
] = set
;
1813 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1814 /* update the contents of the dynamic descriptor set */
1815 unsigned src_idx
= j
;
1816 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1817 assert(dyn_idx
< dynamicOffsetCount
);
1820 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1822 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1823 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1825 /* Patch the storage/uniform descriptors right away. */
1826 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1827 /* Note: we can assume here that the addition won't roll over and
1828 * change the SIZE field.
1830 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1835 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1836 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1837 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1844 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1845 if (set
->buffers
[j
]) {
1846 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1847 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1851 if (set
->size
> 0) {
1852 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1853 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1856 assert(dyn_idx
== dynamicOffsetCount
);
1858 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_update_value
;
1859 uint64_t addr
[MAX_SETS
+ 1] = {};
1862 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1863 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1865 addr
[i
] = set
->va
| 3;
1868 if (layout
->dynamic_offset_count
) {
1869 /* allocate and fill out dynamic descriptor set */
1870 struct ts_cs_memory dynamic_desc_set
;
1871 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1872 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1873 assert(result
== VK_SUCCESS
);
1875 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1876 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1877 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1880 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1881 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1882 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1883 hlsq_update_value
= 0x7c000;
1885 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_SHADER_CONSTS
;
1887 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1889 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1890 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1891 hlsq_update_value
= 0x3e00;
1893 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1896 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 24, &cs
);
1898 tu_cs_emit_pkt4(&cs
, sp_bindless_base_reg
, 10);
1899 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
1900 tu_cs_emit_pkt4(&cs
, hlsq_bindless_base_reg
, 10);
1901 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
1902 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(.dword
= hlsq_update_value
));
1904 struct tu_cs_entry ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
1905 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1906 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1907 tu_cs_emit_sds_ib(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, ib
);
1908 cmd
->state
.desc_sets_ib
= ib
;
1910 /* note: for compute we could emit directly, instead of a CP_INDIRECT
1911 * however, the blob uses draw states for compute
1913 tu_cs_emit_ib(&cmd
->cs
, &ib
);
1917 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1918 uint32_t firstBinding
,
1919 uint32_t bindingCount
,
1920 const VkBuffer
*pBuffers
,
1921 const VkDeviceSize
*pOffsets
,
1922 const VkDeviceSize
*pSizes
)
1924 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1925 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1927 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1928 uint32_t idx
= firstBinding
+ i
;
1929 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1931 if (pOffsets
[i
] != 0)
1932 cmd
->state
.streamout_reset
|= 1 << idx
;
1934 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1935 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1936 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1938 cmd
->state
.streamout_enabled
|= 1 << idx
;
1941 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1944 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1945 uint32_t firstCounterBuffer
,
1946 uint32_t counterBufferCount
,
1947 const VkBuffer
*pCounterBuffers
,
1948 const VkDeviceSize
*pCounterBufferOffsets
)
1950 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1951 /* TODO do something with counter buffer? */
1954 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1955 uint32_t firstCounterBuffer
,
1956 uint32_t counterBufferCount
,
1957 const VkBuffer
*pCounterBuffers
,
1958 const VkDeviceSize
*pCounterBufferOffsets
)
1960 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1961 /* TODO do something with counter buffer? */
1963 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1964 cmd
->state
.streamout_enabled
= 0;
1968 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1969 VkPipelineLayout layout
,
1970 VkShaderStageFlags stageFlags
,
1973 const void *pValues
)
1975 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1976 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1977 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1980 /* Flush everything which has been made available but we haven't actually
1984 tu_flush_all_pending(struct tu_cache_state
*cache
)
1986 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1987 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1991 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1993 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1995 /* We currently flush CCU at the end of the command buffer, like
1996 * what the blob does. There's implicit synchronization around every
1997 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1998 * know yet if this command buffer will be the last in the submit so we
1999 * have to defensively flush everything else.
2001 * TODO: We could definitely do better than this, since these flushes
2002 * aren't required by Vulkan, but we'd need kernel support to do that.
2003 * Ideally, we'd like the kernel to flush everything afterwards, so that we
2004 * wouldn't have to do any flushes here, and when submitting multiple
2005 * command buffers there wouldn't be any unnecessary flushes in between.
2007 if (cmd_buffer
->state
.pass
) {
2008 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
2009 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
2011 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
2012 cmd_buffer
->state
.cache
.flush_bits
|=
2013 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
2014 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
2015 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
2018 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2019 MSM_SUBMIT_BO_WRITE
);
2021 if (cmd_buffer
->use_vsc_data
) {
2022 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_draw_strm
,
2023 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2024 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_prim_strm
,
2025 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2028 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
2029 MSM_SUBMIT_BO_READ
);
2031 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2032 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2033 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2036 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2037 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2038 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2041 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2042 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2043 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2046 tu_cs_end(&cmd_buffer
->cs
);
2047 tu_cs_end(&cmd_buffer
->draw_cs
);
2048 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2050 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2052 return cmd_buffer
->record_result
;
2056 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2058 struct ts_cs_memory memory
;
2061 /* TODO: share this logic with tu_pipeline_static_state */
2062 tu_cs_alloc(&cmd
->sub_cs
, size
, 1, &memory
);
2063 tu_cs_init_external(&cs
, memory
.map
, memory
.map
+ size
);
2065 tu_cs_reserve_space(&cs
, size
);
2067 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2068 cmd
->state
.dynamic_state
[id
].iova
= memory
.iova
;
2069 cmd
->state
.dynamic_state
[id
].size
= size
;
2071 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2072 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2078 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2079 VkPipelineBindPoint pipelineBindPoint
,
2080 VkPipeline _pipeline
)
2082 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2083 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2085 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2086 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2087 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2088 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2089 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2092 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2093 cmd
->state
.compute_pipeline
= pipeline
;
2094 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2098 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2100 cmd
->state
.pipeline
= pipeline
;
2101 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
2103 struct tu_cs
*cs
= &cmd
->draw_cs
;
2104 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2107 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2108 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
2109 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
2110 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
2111 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
2112 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
2113 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
2114 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
2116 for_each_bit(i
, mask
)
2117 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2119 /* If the new pipeline requires more VBs than we had previously set up, we
2120 * need to re-emit them in SDS. If it requires the same set or fewer, we
2121 * can just re-use the old SDS.
2123 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2124 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2126 /* If the pipeline needs a dynamic descriptor, re-emit descriptor sets */
2127 if (pipeline
->layout
->dynamic_offset_count
)
2128 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
2130 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2131 * so the dynamic state ib must be updated when pipeline changes
2133 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2134 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2136 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2137 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2139 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2144 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2145 uint32_t firstViewport
,
2146 uint32_t viewportCount
,
2147 const VkViewport
*pViewports
)
2149 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2150 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2152 assert(firstViewport
== 0 && viewportCount
== 1);
2154 tu6_emit_viewport(&cs
, pViewports
);
2158 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2159 uint32_t firstScissor
,
2160 uint32_t scissorCount
,
2161 const VkRect2D
*pScissors
)
2163 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2164 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2166 assert(firstScissor
== 0 && scissorCount
== 1);
2168 tu6_emit_scissor(&cs
, pScissors
);
2172 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2174 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2175 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2177 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2178 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2180 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2184 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2185 float depthBiasConstantFactor
,
2186 float depthBiasClamp
,
2187 float depthBiasSlopeFactor
)
2189 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2190 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2192 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2196 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2197 const float blendConstants
[4])
2199 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2200 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2202 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2203 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2207 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2208 float minDepthBounds
,
2209 float maxDepthBounds
)
2214 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2216 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2217 *value
|= A6XX_RB_STENCILMASK_MASK(mask
);
2218 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2219 *value
|= A6XX_RB_STENCILMASK_BFMASK(mask
);
2223 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2224 VkStencilFaceFlags faceMask
,
2225 uint32_t compareMask
)
2227 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2228 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2230 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2232 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2236 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2237 VkStencilFaceFlags faceMask
,
2240 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2241 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2243 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2245 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2249 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2250 VkStencilFaceFlags faceMask
,
2253 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2254 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2256 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2258 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2262 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2263 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2265 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2266 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2268 assert(pSampleLocationsInfo
);
2270 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2274 tu_flush_for_access(struct tu_cache_state
*cache
,
2275 enum tu_cmd_access_mask src_mask
,
2276 enum tu_cmd_access_mask dst_mask
)
2278 enum tu_cmd_flush_bits flush_bits
= 0;
2280 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2281 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2284 #define SRC_FLUSH(domain, flush, invalidate) \
2285 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2286 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2287 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2290 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2291 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2292 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2296 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2297 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2298 flush_bits |= TU_CMD_FLAG_##flush; \
2299 cache->pending_flush_bits |= \
2300 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2303 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2304 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2306 #undef SRC_INCOHERENT_FLUSH
2308 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
)) {
2309 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2312 #define DST_FLUSH(domain, flush, invalidate) \
2313 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2314 TU_ACCESS_##domain##_WRITE)) { \
2315 flush_bits |= cache->pending_flush_bits & \
2316 (TU_CMD_FLAG_##invalidate | \
2317 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2320 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2321 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2322 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2326 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2327 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2328 TU_ACCESS_##domain##_WRITE)) { \
2329 flush_bits |= TU_CMD_FLAG_##invalidate | \
2330 (cache->pending_flush_bits & \
2331 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2334 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2335 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2337 #undef DST_INCOHERENT_FLUSH
2339 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2340 flush_bits
|= TU_CMD_FLAG_WFI
;
2343 cache
->flush_bits
|= flush_bits
;
2344 cache
->pending_flush_bits
&= ~flush_bits
;
2347 static enum tu_cmd_access_mask
2348 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2350 enum tu_cmd_access_mask mask
= 0;
2352 /* If the GPU writes a buffer that is then read by an indirect draw
2353 * command, we theoretically need a WFI + WAIT_FOR_ME combination to
2354 * wait for the writes to complete. The WAIT_FOR_ME is performed as part
2355 * of the draw by the firmware, so we just need to execute a WFI.
2358 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2359 VK_ACCESS_MEMORY_READ_BIT
)) {
2360 mask
|= TU_ACCESS_WFI_READ
;
2364 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2365 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP, I think */
2366 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2367 VK_ACCESS_HOST_READ_BIT
| /* sysmem by definition */
2368 VK_ACCESS_MEMORY_READ_BIT
)) {
2369 mask
|= TU_ACCESS_SYSMEM_READ
;
2373 (VK_ACCESS_HOST_WRITE_BIT
|
2374 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
| /* Write performed by CP, I think */
2375 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2376 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2380 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2381 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2382 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2383 /* TODO: Is there a no-cache bit for textures so that we can ignore
2386 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2387 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2388 VK_ACCESS_MEMORY_READ_BIT
)) {
2389 mask
|= TU_ACCESS_UCHE_READ
;
2393 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2394 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2395 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2396 mask
|= TU_ACCESS_UCHE_WRITE
;
2399 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2400 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2401 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2402 * can ignore CCU and pretend that color attachments and transfers use
2407 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2408 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2409 VK_ACCESS_MEMORY_READ_BIT
)) {
2411 mask
|= TU_ACCESS_SYSMEM_READ
;
2413 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2417 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2418 VK_ACCESS_MEMORY_READ_BIT
)) {
2420 mask
|= TU_ACCESS_SYSMEM_READ
;
2422 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2426 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2427 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2429 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2431 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2436 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2437 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2439 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2441 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2445 /* When the dst access is a transfer read/write, it seems we sometimes need
2446 * to insert a WFI after any flushes, to guarantee that the flushes finish
2447 * before the 2D engine starts. However the opposite (i.e. a WFI after
2448 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2449 * the blob doesn't emit such a WFI.
2453 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2454 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2456 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2458 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2460 mask
|= TU_ACCESS_WFI_READ
;
2464 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2465 VK_ACCESS_MEMORY_READ_BIT
)) {
2466 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2474 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2475 uint32_t commandBufferCount
,
2476 const VkCommandBuffer
*pCmdBuffers
)
2478 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2481 assert(commandBufferCount
> 0);
2483 /* Emit any pending flushes. */
2484 if (cmd
->state
.pass
) {
2485 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2486 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2488 tu_flush_all_pending(&cmd
->state
.cache
);
2489 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2492 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2493 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2495 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2496 if (result
!= VK_SUCCESS
) {
2497 cmd
->record_result
= result
;
2501 if (secondary
->usage_flags
&
2502 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2503 assert(tu_cs_is_empty(&secondary
->cs
));
2505 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2506 if (result
!= VK_SUCCESS
) {
2507 cmd
->record_result
= result
;
2511 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2512 &secondary
->draw_epilogue_cs
);
2513 if (result
!= VK_SUCCESS
) {
2514 cmd
->record_result
= result
;
2518 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2519 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2521 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2522 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2523 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2526 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2529 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2531 /* After executing secondary command buffers, there may have been arbitrary
2532 * flushes executed, so when we encounter a pipeline barrier with a
2533 * srcMask, we have to assume that we need to invalidate. Therefore we need
2534 * to re-initialize the cache with all pending invalidate bits set.
2536 if (cmd
->state
.pass
) {
2537 tu_cache_init(&cmd
->state
.renderpass_cache
);
2539 tu_cache_init(&cmd
->state
.cache
);
2544 tu_CreateCommandPool(VkDevice _device
,
2545 const VkCommandPoolCreateInfo
*pCreateInfo
,
2546 const VkAllocationCallbacks
*pAllocator
,
2547 VkCommandPool
*pCmdPool
)
2549 TU_FROM_HANDLE(tu_device
, device
, _device
);
2550 struct tu_cmd_pool
*pool
;
2552 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2553 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2555 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2558 pool
->alloc
= *pAllocator
;
2560 pool
->alloc
= device
->alloc
;
2562 list_inithead(&pool
->cmd_buffers
);
2563 list_inithead(&pool
->free_cmd_buffers
);
2565 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2567 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2573 tu_DestroyCommandPool(VkDevice _device
,
2574 VkCommandPool commandPool
,
2575 const VkAllocationCallbacks
*pAllocator
)
2577 TU_FROM_HANDLE(tu_device
, device
, _device
);
2578 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2583 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2584 &pool
->cmd_buffers
, pool_link
)
2586 tu_cmd_buffer_destroy(cmd_buffer
);
2589 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2590 &pool
->free_cmd_buffers
, pool_link
)
2592 tu_cmd_buffer_destroy(cmd_buffer
);
2595 vk_free2(&device
->alloc
, pAllocator
, pool
);
2599 tu_ResetCommandPool(VkDevice device
,
2600 VkCommandPool commandPool
,
2601 VkCommandPoolResetFlags flags
)
2603 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2606 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2609 result
= tu_reset_cmd_buffer(cmd_buffer
);
2610 if (result
!= VK_SUCCESS
)
2618 tu_TrimCommandPool(VkDevice device
,
2619 VkCommandPool commandPool
,
2620 VkCommandPoolTrimFlags flags
)
2622 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2627 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2628 &pool
->free_cmd_buffers
, pool_link
)
2630 tu_cmd_buffer_destroy(cmd_buffer
);
2635 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2636 const struct tu_subpass_barrier
*barrier
,
2639 /* Note: we don't know until the end of the subpass whether we'll use
2640 * sysmem, so assume sysmem here to be safe.
2642 struct tu_cache_state
*cache
=
2643 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2644 enum tu_cmd_access_mask src_flags
=
2645 vk2tu_access(barrier
->src_access_mask
, false);
2646 enum tu_cmd_access_mask dst_flags
=
2647 vk2tu_access(barrier
->dst_access_mask
, false);
2649 if (barrier
->incoherent_ccu_color
)
2650 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2651 if (barrier
->incoherent_ccu_depth
)
2652 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2654 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2658 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2659 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2660 VkSubpassContents contents
)
2662 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2663 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2664 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2666 cmd
->state
.pass
= pass
;
2667 cmd
->state
.subpass
= pass
->subpasses
;
2668 cmd
->state
.framebuffer
= fb
;
2670 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2671 tu_cmd_prepare_tile_store_ib(cmd
);
2673 /* Note: because this is external, any flushes will happen before draw_cs
2674 * gets called. However deferred flushes could have to happen later as part
2677 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2678 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2679 cmd
->state
.cache
.pending_flush_bits
;
2680 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2682 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2684 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2685 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2686 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2687 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2689 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2691 /* note: use_hw_binning only checks tiling config */
2692 if (use_hw_binning(cmd
))
2693 cmd
->use_vsc_data
= true;
2695 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2696 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2697 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2698 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2701 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2705 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2706 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2707 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2709 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2710 pSubpassBeginInfo
->contents
);
2714 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2716 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2717 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2718 struct tu_cs
*cs
= &cmd
->draw_cs
;
2720 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2722 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2724 if (subpass
->resolve_attachments
) {
2725 tu6_emit_blit_scissor(cmd
, cs
, true);
2727 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2728 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2729 if (a
== VK_ATTACHMENT_UNUSED
)
2732 tu_store_gmem_attachment(cmd
, cs
, a
,
2733 subpass
->color_attachments
[i
].attachment
);
2735 if (pass
->attachments
[a
].gmem_offset
< 0)
2739 * check if the resolved attachment is needed by later subpasses,
2740 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2742 tu_finishme("missing GMEM->GMEM resolve path\n");
2743 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2747 tu_cond_exec_end(cs
);
2749 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2751 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2753 tu_cond_exec_end(cs
);
2755 /* Handle dependencies for the next subpass */
2756 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2758 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2759 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2760 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2761 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2762 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2764 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2768 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2769 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2770 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2772 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2778 * Number of vertices.
2783 * Index of the first vertex.
2785 int32_t vertex_offset
;
2788 * First instance id.
2790 uint32_t first_instance
;
2793 * Number of instances.
2795 uint32_t instance_count
;
2798 * First index (indexed draws only).
2800 uint32_t first_index
;
2803 * Whether it's an indexed draw.
2808 * Indirect draw parameters resource.
2810 struct tu_buffer
*indirect
;
2811 uint64_t indirect_offset
;
2815 * Draw count parameters resource.
2817 struct tu_buffer
*count_buffer
;
2818 uint64_t count_buffer_offset
;
2821 * Stream output parameters resource.
2823 struct tu_buffer
*streamout_buffer
;
2824 uint64_t streamout_buffer_offset
;
2828 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2829 struct tu_descriptor_state
*descriptors_state
,
2830 gl_shader_stage type
,
2831 uint32_t *push_constants
)
2833 const struct tu_program_descriptor_linkage
*link
=
2834 &pipeline
->program
.link
[type
];
2835 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2837 if (link
->push_consts
.count
> 0) {
2838 unsigned num_units
= link
->push_consts
.count
;
2839 unsigned offset
= link
->push_consts
.lo
;
2840 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2841 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2842 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2843 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2844 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2845 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2848 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2849 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2852 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2853 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2854 uint32_t offset
= state
->range
[i
].start
;
2856 /* and even if the start of the const buffer is before
2857 * first_immediate, the end may not be:
2859 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2864 /* things should be aligned to vec4: */
2865 debug_assert((state
->range
[i
].offset
% 16) == 0);
2866 debug_assert((size
% 16) == 0);
2867 debug_assert((offset
% 16) == 0);
2869 /* Dig out the descriptor from the descriptor state and read the VA from
2872 assert(state
->range
[i
].ubo
.bindless
);
2873 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2874 descriptors_state
->dynamic_descriptors
:
2875 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2876 unsigned block
= state
->range
[i
].ubo
.block
;
2877 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2878 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2881 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2882 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2883 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2884 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2885 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2886 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2887 tu_cs_emit_qw(cs
, va
+ offset
);
2891 static struct tu_cs_entry
2892 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2893 const struct tu_pipeline
*pipeline
,
2894 struct tu_descriptor_state
*descriptors_state
,
2895 gl_shader_stage type
)
2898 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2900 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2902 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2906 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2907 const struct tu_draw_info
*draw
,
2908 struct tu_cs_entry
*entry
)
2910 /* TODO: fill out more than just base instance */
2911 const struct tu_program_descriptor_linkage
*link
=
2912 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2913 const struct ir3_const_state
*const_state
= &link
->const_state
;
2916 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2917 *entry
= (struct tu_cs_entry
) {};
2921 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2922 if (result
!= VK_SUCCESS
)
2925 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2926 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2927 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2928 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2929 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2930 CP_LOAD_STATE6_0_NUM_UNIT(1));
2934 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2938 tu_cs_emit(&cs
, draw
->first_instance
);
2941 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2945 static struct tu_cs_entry
2946 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2947 const struct tu_pipeline
*pipeline
)
2950 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2953 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2954 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2955 const VkDeviceSize offset
= buf
->bo_offset
+
2956 cmd
->state
.vb
.offsets
[binding
];
2958 tu_cs_emit_regs(&cs
,
2959 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2960 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2964 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2966 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2970 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2972 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2974 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2975 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2980 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2982 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2983 .bo_offset
= buf
->bo_offset
));
2984 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2986 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2987 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2988 cmd
->state
.streamout_reset
&= ~(1 << i
);
2990 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2991 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2992 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2993 CP_MEM_TO_REG_0_CNT(0));
2994 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2995 ctrl_offset(flush_base
[i
].offset
));
2998 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
3000 ctrl_offset(flush_base
[i
])));
3003 if (cmd
->state
.streamout_enabled
) {
3004 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
3005 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3006 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
3007 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
3008 tu_cs_emit(cs
, tf
->ncomp
[0]);
3009 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
3010 tu_cs_emit(cs
, tf
->ncomp
[1]);
3011 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
3012 tu_cs_emit(cs
, tf
->ncomp
[2]);
3013 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
3014 tu_cs_emit(cs
, tf
->ncomp
[3]);
3015 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3016 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
3017 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
3018 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
3019 tu_cs_emit(cs
, tf
->prog
[i
]);
3022 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
3023 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3025 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3031 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
3033 const struct tu_draw_info
*draw
)
3035 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3038 struct tu_descriptor_state
*descriptors_state
=
3039 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3044 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
3045 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
3047 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3048 cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
] =
3049 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
3050 cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
] =
3051 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
3052 cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
] =
3053 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3056 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3057 tu6_emit_streamout(cmd
, cs
);
3059 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3060 /* We need to reload the descriptors every time the descriptor sets
3061 * change. However, the commands we send only depend on the pipeline
3062 * because the whole point is to cache descriptors which are used by the
3063 * pipeline. There's a problem here, in that the firmware has an
3064 * "optimization" which skips executing groups that are set to the same
3065 * value as the last draw. This means that if the descriptor sets change
3066 * but not the pipeline, we'd try to re-execute the same buffer which
3067 * the firmware would ignore and we wouldn't pre-load the new
3068 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3069 * the descriptor sets change, which we emulate here by copying the
3070 * pre-prepared buffer.
3072 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3073 if (load_entry
->size
> 0) {
3074 struct tu_cs load_cs
;
3075 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3076 if (result
!= VK_SUCCESS
)
3078 tu_cs_emit_array(&load_cs
,
3079 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3080 load_entry
->size
/ 4);
3081 cmd
->state
.desc_sets_load_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3083 cmd
->state
.desc_sets_load_ib
.size
= 0;
3087 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3088 cmd
->state
.vertex_buffers_ib
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3090 struct tu_cs_entry vs_params
;
3091 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3092 if (result
!= VK_SUCCESS
)
3095 /* for the first draw in a renderpass, re-emit all the draw states
3097 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3098 * used, then draw states must be re-emitted. note however this only happens
3099 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3101 * the two input attachment states are excluded because secondary command
3102 * buffer doesn't have a state ib to restore it, and not re-emitting them
3103 * is OK since CmdClearAttachments won't disable/overwrite them
3105 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3106 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3108 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
3109 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
3110 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
3111 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
3112 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
3113 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
3114 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
3115 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3116 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3117 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3118 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets_ib
);
3119 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3120 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3121 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3123 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3124 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3125 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3126 cmd
->state
.dynamic_state
[i
] :
3127 pipeline
->dynamic_state
[i
]));
3131 /* emit draw states that were just updated
3132 * note we eventually don't want to have to emit anything here
3134 uint32_t draw_state_count
=
3135 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 3 : 0) +
3136 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) ? 1 : 0) +
3137 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3140 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3142 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3143 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3144 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3145 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3147 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
)
3148 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3149 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3150 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3151 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3154 tu_cs_sanity_check(cs
);
3157 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3158 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3159 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3161 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3162 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3167 /* There are too many graphics dirty bits to list here, so just list the
3168 * bits to preserve instead. The only things not emitted here are
3169 * compute-related state.
3171 cmd
->state
.dirty
&= (TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3176 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3178 const struct tu_draw_info
*draw
)
3180 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3181 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3182 VK_SHADER_STAGE_GEOMETRY_BIT
;
3185 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3186 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3188 if (draw
->indexed
) {
3189 const enum a4xx_index_size index_size
=
3190 tu6_index_size(cmd
->state
.index_type
);
3191 const uint32_t index_bytes
=
3192 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3193 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3194 unsigned max_indicies
=
3195 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3197 const uint32_t cp_draw_indx
=
3198 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3199 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3200 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3201 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3202 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3204 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3205 tu_cs_emit(cs
, cp_draw_indx
);
3206 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3207 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3208 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3210 const uint32_t cp_draw_indx
=
3211 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3212 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3213 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3214 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3216 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3217 tu_cs_emit(cs
, cp_draw_indx
);
3218 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3221 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3225 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3227 const struct tu_draw_info
*draw
)
3230 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3231 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3232 VK_SHADER_STAGE_GEOMETRY_BIT
;
3235 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3236 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3238 /* TODO hw binning */
3239 if (draw
->indexed
) {
3240 const enum a4xx_index_size index_size
=
3241 tu6_index_size(cmd
->state
.index_type
);
3242 const uint32_t index_bytes
=
3243 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3244 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3245 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3246 index_bytes
* draw
->first_index
;
3247 const uint32_t size
= index_bytes
* draw
->count
;
3249 const uint32_t cp_draw_indx
=
3250 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3251 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3252 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3253 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3254 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3256 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3257 tu_cs_emit(cs
, cp_draw_indx
);
3258 tu_cs_emit(cs
, draw
->instance_count
);
3259 tu_cs_emit(cs
, draw
->count
);
3260 tu_cs_emit(cs
, 0x0); /* XXX */
3261 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3262 tu_cs_emit(cs
, size
);
3264 const uint32_t cp_draw_indx
=
3265 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3266 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3267 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3268 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3270 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3271 tu_cs_emit(cs
, cp_draw_indx
);
3272 tu_cs_emit(cs
, draw
->instance_count
);
3273 tu_cs_emit(cs
, draw
->count
);
3278 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3280 struct tu_cs
*cs
= &cmd
->draw_cs
;
3283 tu_emit_cache_flush_renderpass(cmd
, cs
);
3285 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3286 if (result
!= VK_SUCCESS
) {
3287 cmd
->record_result
= result
;
3292 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3294 tu6_emit_draw_direct(cmd
, cs
, draw
);
3296 if (cmd
->state
.streamout_enabled
) {
3297 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3298 if (cmd
->state
.streamout_enabled
& (1 << i
))
3299 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
3303 tu_cs_sanity_check(cs
);
3307 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3308 uint32_t vertexCount
,
3309 uint32_t instanceCount
,
3310 uint32_t firstVertex
,
3311 uint32_t firstInstance
)
3313 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3314 struct tu_draw_info info
= {};
3316 info
.count
= vertexCount
;
3317 info
.instance_count
= instanceCount
;
3318 info
.first_instance
= firstInstance
;
3319 info
.vertex_offset
= firstVertex
;
3321 tu_draw(cmd_buffer
, &info
);
3325 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3326 uint32_t indexCount
,
3327 uint32_t instanceCount
,
3328 uint32_t firstIndex
,
3329 int32_t vertexOffset
,
3330 uint32_t firstInstance
)
3332 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3333 struct tu_draw_info info
= {};
3335 info
.indexed
= true;
3336 info
.count
= indexCount
;
3337 info
.instance_count
= instanceCount
;
3338 info
.first_index
= firstIndex
;
3339 info
.vertex_offset
= vertexOffset
;
3340 info
.first_instance
= firstInstance
;
3342 tu_draw(cmd_buffer
, &info
);
3346 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3348 VkDeviceSize offset
,
3352 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3353 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3354 struct tu_draw_info info
= {};
3356 info
.count
= drawCount
;
3357 info
.indirect
= buffer
;
3358 info
.indirect_offset
= offset
;
3359 info
.stride
= stride
;
3361 tu_draw(cmd_buffer
, &info
);
3365 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3367 VkDeviceSize offset
,
3371 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3372 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3373 struct tu_draw_info info
= {};
3375 info
.indexed
= true;
3376 info
.count
= drawCount
;
3377 info
.indirect
= buffer
;
3378 info
.indirect_offset
= offset
;
3379 info
.stride
= stride
;
3381 tu_draw(cmd_buffer
, &info
);
3384 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3385 uint32_t instanceCount
,
3386 uint32_t firstInstance
,
3387 VkBuffer _counterBuffer
,
3388 VkDeviceSize counterBufferOffset
,
3389 uint32_t counterOffset
,
3390 uint32_t vertexStride
)
3392 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3393 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3395 struct tu_draw_info info
= {};
3397 info
.instance_count
= instanceCount
;
3398 info
.first_instance
= firstInstance
;
3399 info
.streamout_buffer
= buffer
;
3400 info
.streamout_buffer_offset
= counterBufferOffset
;
3401 info
.stride
= vertexStride
;
3403 tu_draw(cmd_buffer
, &info
);
3406 struct tu_dispatch_info
3409 * Determine the layout of the grid (in block units) to be used.
3414 * A starting offset for the grid. If unaligned is set, the offset
3415 * must still be aligned.
3417 uint32_t offsets
[3];
3419 * Whether it's an unaligned compute dispatch.
3424 * Indirect compute parameters resource.
3426 struct tu_buffer
*indirect
;
3427 uint64_t indirect_offset
;
3431 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3432 const struct tu_dispatch_info
*info
)
3434 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3435 const struct tu_program_descriptor_linkage
*link
=
3436 &pipeline
->program
.link
[type
];
3437 const struct ir3_const_state
*const_state
= &link
->const_state
;
3438 uint32_t offset
= const_state
->offsets
.driver_param
;
3440 if (link
->constlen
<= offset
)
3443 if (!info
->indirect
) {
3444 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3445 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3446 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3447 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3448 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3449 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3450 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3453 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3454 (link
->constlen
- offset
) * 4);
3455 /* push constants */
3456 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3457 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3458 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3459 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3460 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3461 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3465 for (i
= 0; i
< num_consts
; i
++)
3466 tu_cs_emit(cs
, driver_params
[i
]);
3468 tu_finishme("Indirect driver params");
3473 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3474 const struct tu_dispatch_info
*info
)
3476 struct tu_cs
*cs
= &cmd
->cs
;
3477 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3478 struct tu_descriptor_state
*descriptors_state
=
3479 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3481 /* TODO: We could probably flush less if we add a compute_flush_bits
3484 tu_emit_cache_flush(cmd
, cs
);
3486 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3487 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3489 struct tu_cs_entry ib
;
3491 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3493 tu_cs_emit_ib(cs
, &ib
);
3495 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3497 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) &&
3498 pipeline
->load_state
.state_ib
.size
> 0) {
3499 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3503 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3505 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3506 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3508 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3509 const uint32_t *num_groups
= info
->blocks
;
3511 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3512 .localsizex
= local_size
[0] - 1,
3513 .localsizey
= local_size
[1] - 1,
3514 .localsizez
= local_size
[2] - 1),
3515 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3516 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3517 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3518 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3519 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3520 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3523 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3524 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3525 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3527 if (info
->indirect
) {
3528 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3530 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3531 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3533 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3534 tu_cs_emit(cs
, 0x00000000);
3535 tu_cs_emit_qw(cs
, iova
);
3537 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3538 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3539 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3541 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3542 tu_cs_emit(cs
, 0x00000000);
3543 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3544 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3545 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3552 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3560 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3561 struct tu_dispatch_info info
= {};
3567 info
.offsets
[0] = base_x
;
3568 info
.offsets
[1] = base_y
;
3569 info
.offsets
[2] = base_z
;
3570 tu_dispatch(cmd_buffer
, &info
);
3574 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3579 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3583 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3585 VkDeviceSize offset
)
3587 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3588 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3589 struct tu_dispatch_info info
= {};
3591 info
.indirect
= buffer
;
3592 info
.indirect_offset
= offset
;
3594 tu_dispatch(cmd_buffer
, &info
);
3598 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3600 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3602 tu_cs_end(&cmd_buffer
->draw_cs
);
3603 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3605 if (use_sysmem_rendering(cmd_buffer
))
3606 tu_cmd_render_sysmem(cmd_buffer
);
3608 tu_cmd_render_tiles(cmd_buffer
);
3610 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3612 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3613 tu_cs_begin(&cmd_buffer
->draw_cs
);
3614 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3615 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3617 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3618 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3619 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3621 cmd_buffer
->state
.pass
= NULL
;
3622 cmd_buffer
->state
.subpass
= NULL
;
3623 cmd_buffer
->state
.framebuffer
= NULL
;
3627 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3628 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3630 tu_CmdEndRenderPass(commandBuffer
);
3633 struct tu_barrier_info
3635 uint32_t eventCount
;
3636 const VkEvent
*pEvents
;
3637 VkPipelineStageFlags srcStageMask
;
3641 tu_barrier(struct tu_cmd_buffer
*cmd
,
3642 uint32_t memoryBarrierCount
,
3643 const VkMemoryBarrier
*pMemoryBarriers
,
3644 uint32_t bufferMemoryBarrierCount
,
3645 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3646 uint32_t imageMemoryBarrierCount
,
3647 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3648 const struct tu_barrier_info
*info
)
3650 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3651 VkAccessFlags srcAccessMask
= 0;
3652 VkAccessFlags dstAccessMask
= 0;
3654 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3655 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3656 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3659 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3660 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3661 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3664 enum tu_cmd_access_mask src_flags
= 0;
3665 enum tu_cmd_access_mask dst_flags
= 0;
3667 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3668 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3669 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3670 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3671 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3672 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3673 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3674 /* The underlying memory for this image may have been used earlier
3675 * within the same queue submission for a different image, which
3676 * means that there may be old, stale cache entries which are in the
3677 * "wrong" location, which could cause problems later after writing
3678 * to the image. We don't want these entries being flushed later and
3679 * overwriting the actual image, so we need to flush the CCU.
3681 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3683 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3684 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3687 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3688 * so we have to use the sysmem flushes.
3690 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3692 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3693 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3695 struct tu_cache_state
*cache
=
3696 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3697 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3699 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3700 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3702 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3704 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3705 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3706 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3707 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3708 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3709 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3710 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3715 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3716 VkPipelineStageFlags srcStageMask
,
3717 VkPipelineStageFlags dstStageMask
,
3718 VkDependencyFlags dependencyFlags
,
3719 uint32_t memoryBarrierCount
,
3720 const VkMemoryBarrier
*pMemoryBarriers
,
3721 uint32_t bufferMemoryBarrierCount
,
3722 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3723 uint32_t imageMemoryBarrierCount
,
3724 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3726 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3727 struct tu_barrier_info info
;
3729 info
.eventCount
= 0;
3730 info
.pEvents
= NULL
;
3731 info
.srcStageMask
= srcStageMask
;
3733 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3734 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3735 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3739 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3740 VkPipelineStageFlags stageMask
, unsigned value
)
3742 struct tu_cs
*cs
= &cmd
->cs
;
3744 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3745 assert(!cmd
->state
.pass
);
3747 tu_emit_cache_flush(cmd
, cs
);
3749 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3751 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3752 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3754 VkPipelineStageFlags top_of_pipe_flags
=
3755 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3756 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3758 if (!(stageMask
& ~top_of_pipe_flags
)) {
3759 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3760 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3761 tu_cs_emit(cs
, value
);
3763 /* Use a RB_DONE_TS event to wait for everything to complete. */
3764 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3765 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3766 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3767 tu_cs_emit(cs
, value
);
3772 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3774 VkPipelineStageFlags stageMask
)
3776 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3777 TU_FROM_HANDLE(tu_event
, event
, _event
);
3779 write_event(cmd
, event
, stageMask
, 1);
3783 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3785 VkPipelineStageFlags stageMask
)
3787 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3788 TU_FROM_HANDLE(tu_event
, event
, _event
);
3790 write_event(cmd
, event
, stageMask
, 0);
3794 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3795 uint32_t eventCount
,
3796 const VkEvent
*pEvents
,
3797 VkPipelineStageFlags srcStageMask
,
3798 VkPipelineStageFlags dstStageMask
,
3799 uint32_t memoryBarrierCount
,
3800 const VkMemoryBarrier
*pMemoryBarriers
,
3801 uint32_t bufferMemoryBarrierCount
,
3802 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3803 uint32_t imageMemoryBarrierCount
,
3804 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3806 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3807 struct tu_barrier_info info
;
3809 info
.eventCount
= eventCount
;
3810 info
.pEvents
= pEvents
;
3811 info
.srcStageMask
= 0;
3813 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3814 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3815 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3819 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)