2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
118 const uint32_t tile_align_w
= 64; /* note: 32 when no input attachments */
119 const uint32_t tile_align_h
= 16;
120 const uint32_t max_tile_width
= 1024;
122 /* note: don't offset the tiling config by render_area.offset,
123 * because binning pass can't deal with it
124 * this means we might end up with more tiles than necessary,
125 * but load/store/etc are still scissored to the render_area
127 tiling
->tile0
.offset
= (VkOffset2D
) {};
129 const uint32_t ra_width
=
130 tiling
->render_area
.extent
.width
+
131 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
132 const uint32_t ra_height
=
133 tiling
->render_area
.extent
.height
+
134 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
136 /* start from 1 tile */
137 tiling
->tile_count
= (VkExtent2D
) {
141 tiling
->tile0
.extent
= (VkExtent2D
) {
142 .width
= align(ra_width
, tile_align_w
),
143 .height
= align(ra_height
, tile_align_h
),
146 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
147 /* start with 2x2 tiles */
148 tiling
->tile_count
.width
= 2;
149 tiling
->tile_count
.height
= 2;
150 tiling
->tile0
.extent
.width
= align(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
151 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), tile_align_h
);
154 /* do not exceed max tile width */
155 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
156 tiling
->tile_count
.width
++;
157 tiling
->tile0
.extent
.width
=
158 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
161 /* will force to sysmem, don't bother trying to have a valid tile config
162 * TODO: just skip all GMEM stuff when sysmem is forced?
167 /* do not exceed gmem size */
168 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pixels
) {
169 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
170 tiling
->tile_count
.width
++;
171 tiling
->tile0
.extent
.width
=
172 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
174 /* if this assert fails then layout is impossible.. */
175 assert(tiling
->tile0
.extent
.height
> tile_align_h
);
176 tiling
->tile_count
.height
++;
177 tiling
->tile0
.extent
.height
=
178 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), tile_align_h
);
184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
185 const struct tu_device
*dev
)
187 const uint32_t max_pipe_count
= 32; /* A6xx */
189 /* start from 1 tile per pipe */
190 tiling
->pipe0
= (VkExtent2D
) {
194 tiling
->pipe_count
= tiling
->tile_count
;
196 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
197 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
198 tiling
->pipe0
.width
+= 1;
199 tiling
->pipe_count
.width
=
200 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
202 tiling
->pipe0
.height
+= 1;
203 tiling
->pipe_count
.height
=
204 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
210 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
211 const struct tu_device
*dev
)
213 const uint32_t max_pipe_count
= 32; /* A6xx */
214 const uint32_t used_pipe_count
=
215 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
216 const VkExtent2D last_pipe
= {
217 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
218 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
221 assert(used_pipe_count
<= max_pipe_count
);
222 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
224 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
225 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
226 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
227 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
228 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
230 : tiling
->pipe0
.width
;
231 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
233 : tiling
->pipe0
.height
;
234 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
236 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
237 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
238 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
239 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
240 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
244 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
245 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
249 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
250 const struct tu_device
*dev
,
253 struct tu_tile
*tile
)
255 /* find the pipe and the slot for tile (tx, ty) */
256 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
257 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
258 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
259 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
260 /* last pipe has different width */
261 const uint32_t pipe_width
=
262 MIN2(tiling
->pipe0
.width
,
263 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
265 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
266 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
267 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
269 /* convert to 1D indices */
270 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
271 tile
->slot
= pipe_width
* sy
+ sx
;
273 /* get the blit area for the tile */
274 tile
->begin
= (VkOffset2D
) {
275 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
276 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
279 (tx
== tiling
->tile_count
.width
- 1)
280 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
281 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
283 (ty
== tiling
->tile_count
.height
- 1)
284 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
285 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
288 enum a3xx_msaa_samples
289 tu_msaa_samples(uint32_t samples
)
301 assert(!"invalid sample count");
306 static enum a4xx_index_size
307 tu6_index_size(VkIndexType type
)
310 case VK_INDEX_TYPE_UINT16
:
311 return INDEX4_SIZE_16_BIT
;
312 case VK_INDEX_TYPE_UINT32
:
313 return INDEX4_SIZE_32_BIT
;
315 unreachable("invalid VkIndexType");
316 return INDEX4_SIZE_8_BIT
;
321 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
323 enum vgt_event_type event
,
328 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
329 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
331 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
332 seqno
= ++cmd
->scratch_seqno
;
333 tu_cs_emit(cs
, seqno
);
340 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
342 tu6_emit_event_write(cmd
, cs
, 0x31, false);
346 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
348 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
352 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
354 if (cmd
->wait_for_idle
) {
356 cmd
->wait_for_idle
= false;
361 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
362 const struct tu_subpass
*subpass
,
365 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
367 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
368 if (a
== VK_ATTACHMENT_UNUSED
) {
370 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
371 A6XX_RB_DEPTH_BUFFER_PITCH(0),
372 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
373 A6XX_RB_DEPTH_BUFFER_BASE(0),
374 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
377 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
380 A6XX_GRAS_LRZ_BUFFER_BASE(0),
381 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
382 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
384 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
389 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
390 enum a6xx_depth_format fmt
= tu6_pipe2depth(iview
->vk_format
);
393 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
),
394 A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)),
395 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(
396 fdl_layer_stride(&iview
->image
->layout
, iview
->base_mip
)),
397 A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview
)),
398 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd
->state
.pass
->attachments
[a
].gmem_offset
));
401 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
404 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview
)),
405 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview
)));
408 A6XX_GRAS_LRZ_BUFFER_BASE(0),
409 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
410 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
413 A6XX_RB_STENCIL_INFO(0));
419 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
420 const struct tu_subpass
*subpass
,
423 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
424 unsigned char mrt_comp
[MAX_RTS
] = { 0 };
425 unsigned srgb_cntl
= 0;
427 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
428 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
429 if (a
== VK_ATTACHMENT_UNUSED
)
432 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
436 if (vk_format_is_srgb(iview
->vk_format
))
437 srgb_cntl
|= (1 << i
);
439 struct tu_native_format format
=
440 tu6_format_image(iview
->image
, iview
->vk_format
, iview
->base_mip
);
443 A6XX_RB_MRT_BUF_INFO(i
,
444 .color_tile_mode
= format
.tile_mode
,
445 .color_format
= format
.fmt
,
446 .color_swap
= format
.swap
),
447 A6XX_RB_MRT_PITCH(i
, tu_image_stride(iview
->image
, iview
->base_mip
)),
448 A6XX_RB_MRT_ARRAY_PITCH(i
,
449 fdl_layer_stride(&iview
->image
->layout
, iview
->base_mip
)),
450 A6XX_RB_MRT_BASE(i
, tu_image_view_base_ref(iview
)),
451 A6XX_RB_MRT_BASE_GMEM(i
, cmd
->state
.pass
->attachments
[a
].gmem_offset
));
454 A6XX_SP_FS_MRT_REG(i
,
455 .color_format
= format
.fmt
,
456 .color_sint
= vk_format_is_sint(iview
->vk_format
),
457 .color_uint
= vk_format_is_uint(iview
->vk_format
)));
460 A6XX_RB_MRT_FLAG_BUFFER_ADDR(i
, tu_image_view_ubwc_base_ref(iview
)),
461 A6XX_RB_MRT_FLAG_BUFFER_PITCH(i
, tu_image_view_ubwc_pitches(iview
)));
465 A6XX_RB_SRGB_CNTL(.dword
= srgb_cntl
));
468 A6XX_SP_SRGB_CNTL(.dword
= srgb_cntl
));
471 A6XX_RB_RENDER_COMPONENTS(
479 .rt7
= mrt_comp
[7]));
482 A6XX_SP_FS_RENDER_COMPONENTS(
490 .rt7
= mrt_comp
[7]));
492 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
496 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
498 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
499 bool msaa_disable
= samples
== MSAA_ONE
;
502 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
503 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
504 .msaa_disable
= msaa_disable
));
507 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
508 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
509 .msaa_disable
= msaa_disable
));
512 A6XX_RB_RAS_MSAA_CNTL(samples
),
513 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
514 .msaa_disable
= msaa_disable
));
517 A6XX_RB_MSAA_CNTL(samples
));
521 tu6_emit_bin_size(struct tu_cs
*cs
,
522 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
525 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
530 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
534 /* no flag for RB_BIN_CONTROL2... */
536 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
541 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
542 const struct tu_subpass
*subpass
,
546 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
548 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
550 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
552 uint32_t mrts_ubwc_enable
= 0;
553 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
554 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
555 if (a
== VK_ATTACHMENT_UNUSED
)
558 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
559 if (iview
->image
->layout
.ubwc_layer_size
!= 0)
560 mrts_ubwc_enable
|= 1 << i
;
563 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
565 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
566 if (a
!= VK_ATTACHMENT_UNUSED
) {
567 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
568 if (iview
->image
->layout
.ubwc_layer_size
!= 0)
569 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
572 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
573 * in order to set it correctly for the different subpasses. However,
574 * that means the packets we're emitting also happen during binning. So
575 * we need to guard the write on !BINNING at CP execution time.
577 tu_cs_reserve(cs
, 3 + 4);
578 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
579 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
580 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
581 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
584 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
585 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
586 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
587 tu_cs_emit(cs
, cntl
);
591 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
593 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
594 uint32_t x1
= render_area
->offset
.x
;
595 uint32_t y1
= render_area
->offset
.y
;
596 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
597 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
600 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
601 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
602 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
603 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
607 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
608 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
612 tu6_emit_window_scissor(struct tu_cs
*cs
,
619 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
620 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
623 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
624 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
628 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
631 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
634 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
637 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
640 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
644 use_hw_binning(struct tu_cmd_buffer
*cmd
)
646 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
648 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
651 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
654 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
658 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
660 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
663 /* can't fit attachments into gmem */
664 if (!cmd
->state
.pass
->gmem_pixels
)
667 if (cmd
->state
.framebuffer
->layers
> 1)
670 return cmd
->state
.tiling_config
.force_sysmem
;
674 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
676 const struct tu_tile
*tile
)
678 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
679 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
681 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
682 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
684 const uint32_t x1
= tile
->begin
.x
;
685 const uint32_t y1
= tile
->begin
.y
;
686 const uint32_t x2
= tile
->end
.x
- 1;
687 const uint32_t y2
= tile
->end
.y
- 1;
688 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
689 tu6_emit_window_offset(cs
, x1
, y1
);
692 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
694 if (use_hw_binning(cmd
)) {
695 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
697 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
700 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
701 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
702 A6XX_CP_REG_TEST_0_BIT(0) |
703 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
705 tu_cs_reserve(cs
, 3 + 11);
706 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
707 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
708 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
710 /* if (no overflow) */ {
711 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
712 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
713 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
714 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
715 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
716 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
718 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
721 /* use a NOP packet to skip over the 'else' side: */
722 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
724 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
728 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
732 A6XX_RB_UNKNOWN_8804(0));
735 A6XX_SP_TP_UNKNOWN_B304(0));
738 A6XX_GRAS_UNKNOWN_80A4(0));
740 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
743 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
749 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
754 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
755 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
756 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
758 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
762 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
764 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
765 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
767 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
768 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
769 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
770 CP_SET_DRAW_STATE__0_GROUP_ID(0));
771 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
772 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
774 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
777 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
778 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
780 tu6_emit_blit_scissor(cmd
, cs
, true);
782 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
783 if (pass
->attachments
[a
].gmem_offset
>= 0)
784 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
787 if (subpass
->resolve_attachments
) {
788 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
789 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
790 if (a
!= VK_ATTACHMENT_UNUSED
)
791 tu_store_gmem_attachment(cmd
, cs
, a
,
792 subpass
->color_attachments
[i
].attachment
);
798 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
801 A6XX_PC_RESTART_INDEX(restart_index
));
805 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
807 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
809 tu6_emit_cache_flush(cmd
, cs
);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
814 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
815 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
816 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
817 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
818 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
819 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
820 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
822 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
825 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
826 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
827 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
848 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
850 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
851 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
852 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
853 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
854 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
855 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
856 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
857 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
859 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
860 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
862 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
863 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
865 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
866 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
868 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
869 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
870 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
871 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
873 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
874 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
876 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
878 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
880 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
881 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
882 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
883 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
884 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
885 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
886 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
887 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
888 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
889 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
890 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
891 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
892 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8804
, 0);
893 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
894 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
895 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
896 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8805
, 0);
897 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8806
, 0);
898 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
899 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
900 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
902 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
904 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
906 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
908 /* we don't use this yet.. probably best to disable.. */
909 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
910 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
911 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
912 CP_SET_DRAW_STATE__0_GROUP_ID(0));
913 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
914 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
916 /* Set not to use streamout by default, */
917 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
918 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
920 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
924 A6XX_SP_HS_CTRL_REG0(0));
927 A6XX_SP_GS_CTRL_REG0(0));
930 A6XX_GRAS_LRZ_CNTL(0));
933 A6XX_RB_LRZ_CNTL(0));
936 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
938 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
940 tu_cs_sanity_check(cs
);
944 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
948 seqno
= tu6_emit_event_write(cmd
, cs
, RB_DONE_TS
, true);
950 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
951 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
952 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
953 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
954 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
955 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
956 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
958 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
960 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
961 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
962 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
963 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
967 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
969 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
972 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
973 .height
= tiling
->tile0
.extent
.height
),
974 A6XX_VSC_SIZE_ADDRESS(.bo
= &cmd
->vsc_data
,
975 .bo_offset
= 32 * cmd
->vsc_data_pitch
));
978 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
979 .ny
= tiling
->tile_count
.height
));
981 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
982 for (unsigned i
= 0; i
< 32; i
++)
983 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
986 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo
= &cmd
->vsc_data2
),
987 A6XX_VSC_PIPE_DATA2_PITCH(cmd
->vsc_data2_pitch
),
988 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd
->vsc_data2
.size
));
991 A6XX_VSC_PIPE_DATA_ADDRESS(.bo
= &cmd
->vsc_data
),
992 A6XX_VSC_PIPE_DATA_PITCH(cmd
->vsc_data_pitch
),
993 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd
->vsc_data
.size
));
997 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
999 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1000 const uint32_t used_pipe_count
=
1001 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1003 /* Clear vsc_scratch: */
1004 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1005 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1006 tu_cs_emit(cs
, 0x0);
1008 /* Check for overflow, write vsc_scratch if detected: */
1009 for (int i
= 0; i
< used_pipe_count
; i
++) {
1010 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1011 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1012 CP_COND_WRITE5_0_WRITE_MEMORY
);
1013 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
1014 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1015 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
1016 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1017 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1018 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
1020 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1021 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1022 CP_COND_WRITE5_0_WRITE_MEMORY
);
1023 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
1024 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1025 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
1026 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1027 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1028 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
1031 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1033 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1035 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1036 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
1037 CP_MEM_TO_REG_0_CNT(1 - 1));
1038 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1041 * This is a bit awkward, we really want a way to invert the
1042 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1043 * execute cmds to use hwbinning when a bit is *not* set. This
1044 * dance is to invert OVERFLOW_FLAG_REG
1046 * A CP_NOP packet is used to skip executing the 'else' clause
1050 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1051 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1052 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1053 A6XX_CP_REG_TEST_0_BIT(0) |
1054 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1056 tu_cs_reserve(cs
, 3 + 7);
1057 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1058 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1059 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1063 * On overflow, mirror the value to control->vsc_overflow
1064 * which CPU is checking to detect overflow (see
1065 * check_vsc_overflow())
1067 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1068 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1069 CP_REG_TO_MEM_0_CNT(0));
1070 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1072 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1073 tu_cs_emit(cs
, 0x0);
1075 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1077 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1078 tu_cs_emit(cs
, 0x1);
1083 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1085 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1086 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1088 uint32_t x1
= tiling
->tile0
.offset
.x
;
1089 uint32_t y1
= tiling
->tile0
.offset
.y
;
1090 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1091 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1093 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1095 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1096 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1098 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1099 tu_cs_emit(cs
, 0x1);
1101 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1102 tu_cs_emit(cs
, 0x1);
1107 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1109 update_vsc_pipe(cmd
, cs
);
1112 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1115 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1117 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1118 tu_cs_emit(cs
, UNK_2C
);
1121 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1124 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1126 /* emit IB to binning drawcmds: */
1127 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1129 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1130 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1131 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1132 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1133 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1134 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1136 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1137 tu_cs_emit(cs
, UNK_2D
);
1139 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1140 tu6_cache_flush(cmd
, cs
);
1144 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1146 emit_vsc_overflow_test(cmd
, cs
);
1148 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1149 tu_cs_emit(cs
, 0x0);
1151 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1152 tu_cs_emit(cs
, 0x0);
1154 cmd
->wait_for_idle
= false;
1158 tu_emit_load_clear(struct tu_cmd_buffer
*cmd
,
1159 const VkRenderPassBeginInfo
*info
)
1161 struct tu_cs
*cs
= &cmd
->draw_cs
;
1163 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1165 tu6_emit_blit_scissor(cmd
, cs
, true);
1167 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1168 tu_load_gmem_attachment(cmd
, cs
, i
);
1170 tu6_emit_blit_scissor(cmd
, cs
, false);
1172 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1173 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1175 tu_cond_exec_end(cs
);
1177 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1179 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1180 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1182 tu_cond_exec_end(cs
);
1186 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1187 const struct VkRect2D
*renderArea
)
1189 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1190 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1192 assert(fb
->width
> 0 && fb
->height
> 0);
1193 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1194 tu6_emit_window_offset(cs
, 0, 0);
1196 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1198 tu6_emit_lrz_flush(cmd
, cs
);
1200 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1201 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1203 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1204 tu_cs_emit(cs
, 0x0);
1206 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1207 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1208 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1210 tu6_emit_wfi(cmd
, cs
);
1212 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
1214 /* enable stream-out, with sysmem there is only one pass: */
1216 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1218 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1219 tu_cs_emit(cs
, 0x1);
1221 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1222 tu_cs_emit(cs
, 0x0);
1224 tu_cs_sanity_check(cs
);
1228 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1230 /* Do any resolves of the last subpass. These are handled in the
1231 * tile_store_ib in the gmem path.
1233 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1234 if (subpass
->resolve_attachments
) {
1235 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
1236 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
1237 if (a
!= VK_ATTACHMENT_UNUSED
)
1238 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
1239 subpass
->color_attachments
[i
].attachment
);
1243 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1245 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1246 tu_cs_emit(cs
, 0x0);
1248 tu6_emit_lrz_flush(cmd
, cs
);
1250 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1251 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1253 tu_cs_sanity_check(cs
);
1258 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1260 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1262 tu6_emit_lrz_flush(cmd
, cs
);
1266 tu6_emit_cache_flush(cmd
, cs
);
1268 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1269 tu_cs_emit(cs
, 0x0);
1271 /* TODO: flushing with barriers instead of blindly always flushing */
1272 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1273 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1274 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1275 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1279 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_gmem
, .gmem
= 1));
1281 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1282 if (use_hw_binning(cmd
)) {
1283 /* enable stream-out during binning pass: */
1284 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1286 tu6_emit_bin_size(cs
,
1287 tiling
->tile0
.extent
.width
,
1288 tiling
->tile0
.extent
.height
,
1289 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1291 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1293 tu6_emit_binning_pass(cmd
, cs
);
1295 /* and disable stream-out for draw pass: */
1296 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1298 tu6_emit_bin_size(cs
,
1299 tiling
->tile0
.extent
.width
,
1300 tiling
->tile0
.extent
.height
,
1301 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1304 A6XX_VFD_MODE_CNTL(0));
1306 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1308 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1310 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1311 tu_cs_emit(cs
, 0x1);
1313 /* no binning pass, so enable stream-out for draw pass:: */
1314 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1316 tu6_emit_bin_size(cs
,
1317 tiling
->tile0
.extent
.width
,
1318 tiling
->tile0
.extent
.height
,
1322 tu_cs_sanity_check(cs
);
1326 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1328 const struct tu_tile
*tile
)
1330 tu6_emit_tile_select(cmd
, cs
, tile
);
1332 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1333 cmd
->wait_for_idle
= true;
1335 if (use_hw_binning(cmd
)) {
1336 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1337 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1338 A6XX_CP_REG_TEST_0_BIT(0) |
1339 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1341 tu_cs_reserve(cs
, 3 + 2);
1342 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1343 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1344 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1346 /* if (no overflow) */ {
1347 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1348 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1352 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1354 tu_cs_sanity_check(cs
);
1358 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1360 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1363 A6XX_GRAS_LRZ_CNTL(0));
1365 tu6_emit_lrz_flush(cmd
, cs
);
1367 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1369 tu_cs_sanity_check(cs
);
1373 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1375 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1377 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1379 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1380 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1381 struct tu_tile tile
;
1382 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1383 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1387 tu6_tile_render_end(cmd
, &cmd
->cs
);
1391 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1393 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1395 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1397 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1398 cmd
->wait_for_idle
= true;
1400 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1404 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1406 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1407 struct tu_cs sub_cs
;
1410 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1411 if (result
!= VK_SUCCESS
) {
1412 cmd
->record_result
= result
;
1416 /* emit to tile-store sub_cs */
1417 tu6_emit_tile_store(cmd
, &sub_cs
);
1419 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1423 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1424 const VkRect2D
*render_area
)
1426 const struct tu_device
*dev
= cmd
->device
;
1427 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1429 tiling
->render_area
= *render_area
;
1430 tiling
->force_sysmem
= false;
1432 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
->gmem_pixels
);
1433 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1434 tu_tiling_config_update_pipes(tiling
, dev
);
1437 const struct tu_dynamic_state default_dynamic_state
= {
1453 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1459 .stencil_compare_mask
=
1464 .stencil_write_mask
=
1469 .stencil_reference
=
1476 static void UNUSED
/* FINISHME */
1477 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1478 const struct tu_dynamic_state
*src
)
1480 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1481 uint32_t copy_mask
= src
->mask
;
1482 uint32_t dest_mask
= 0;
1484 tu_use_args(cmd_buffer
); /* FINISHME */
1486 /* Make sure to copy the number of viewports/scissors because they can
1487 * only be specified at pipeline creation time.
1489 dest
->viewport
.count
= src
->viewport
.count
;
1490 dest
->scissor
.count
= src
->scissor
.count
;
1491 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1493 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1494 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1495 src
->viewport
.count
* sizeof(VkViewport
))) {
1496 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1497 src
->viewport
.count
);
1498 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1502 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1503 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1504 src
->scissor
.count
* sizeof(VkRect2D
))) {
1505 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1506 src
->scissor
.count
);
1507 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1511 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1512 if (dest
->line_width
!= src
->line_width
) {
1513 dest
->line_width
= src
->line_width
;
1514 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1518 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1519 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1520 sizeof(src
->depth_bias
))) {
1521 dest
->depth_bias
= src
->depth_bias
;
1522 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1526 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1527 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1528 sizeof(src
->blend_constants
))) {
1529 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1530 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1534 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1535 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1536 sizeof(src
->depth_bounds
))) {
1537 dest
->depth_bounds
= src
->depth_bounds
;
1538 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1542 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1543 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1544 sizeof(src
->stencil_compare_mask
))) {
1545 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1546 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1550 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1551 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1552 sizeof(src
->stencil_write_mask
))) {
1553 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1554 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1558 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1559 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1560 sizeof(src
->stencil_reference
))) {
1561 dest
->stencil_reference
= src
->stencil_reference
;
1562 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1566 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1567 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1568 &src
->discard_rectangle
.rectangles
,
1569 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1570 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1571 src
->discard_rectangle
.rectangles
,
1572 src
->discard_rectangle
.count
);
1573 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1579 tu_create_cmd_buffer(struct tu_device
*device
,
1580 struct tu_cmd_pool
*pool
,
1581 VkCommandBufferLevel level
,
1582 VkCommandBuffer
*pCommandBuffer
)
1584 struct tu_cmd_buffer
*cmd_buffer
;
1585 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1586 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1587 if (cmd_buffer
== NULL
)
1588 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1590 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1591 cmd_buffer
->device
= device
;
1592 cmd_buffer
->pool
= pool
;
1593 cmd_buffer
->level
= level
;
1596 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1597 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1600 /* Init the pool_link so we can safely call list_del when we destroy
1601 * the command buffer
1603 list_inithead(&cmd_buffer
->pool_link
);
1604 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1607 tu_bo_list_init(&cmd_buffer
->bo_list
);
1608 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1609 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1610 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1611 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1613 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1615 list_inithead(&cmd_buffer
->upload
.list
);
1617 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1618 if (result
!= VK_SUCCESS
)
1619 goto fail_scratch_bo
;
1621 /* TODO: resize on overflow */
1622 cmd_buffer
->vsc_data_pitch
= device
->vsc_data_pitch
;
1623 cmd_buffer
->vsc_data2_pitch
= device
->vsc_data2_pitch
;
1624 cmd_buffer
->vsc_data
= device
->vsc_data
;
1625 cmd_buffer
->vsc_data2
= device
->vsc_data2
;
1630 list_del(&cmd_buffer
->pool_link
);
1635 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1637 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1639 list_del(&cmd_buffer
->pool_link
);
1641 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1642 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1644 tu_cs_finish(&cmd_buffer
->cs
);
1645 tu_cs_finish(&cmd_buffer
->draw_cs
);
1646 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1647 tu_cs_finish(&cmd_buffer
->sub_cs
);
1649 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1650 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1654 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1656 cmd_buffer
->wait_for_idle
= true;
1658 cmd_buffer
->record_result
= VK_SUCCESS
;
1660 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1661 tu_cs_reset(&cmd_buffer
->cs
);
1662 tu_cs_reset(&cmd_buffer
->draw_cs
);
1663 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1664 tu_cs_reset(&cmd_buffer
->sub_cs
);
1666 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1667 cmd_buffer
->descriptors
[i
].valid
= 0;
1668 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1671 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1673 return cmd_buffer
->record_result
;
1677 tu_AllocateCommandBuffers(VkDevice _device
,
1678 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1679 VkCommandBuffer
*pCommandBuffers
)
1681 TU_FROM_HANDLE(tu_device
, device
, _device
);
1682 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1684 VkResult result
= VK_SUCCESS
;
1687 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1689 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1690 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1691 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1693 list_del(&cmd_buffer
->pool_link
);
1694 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1696 result
= tu_reset_cmd_buffer(cmd_buffer
);
1697 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1698 cmd_buffer
->level
= pAllocateInfo
->level
;
1700 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1702 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1703 &pCommandBuffers
[i
]);
1705 if (result
!= VK_SUCCESS
)
1709 if (result
!= VK_SUCCESS
) {
1710 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1713 /* From the Vulkan 1.0.66 spec:
1715 * "vkAllocateCommandBuffers can be used to create multiple
1716 * command buffers. If the creation of any of those command
1717 * buffers fails, the implementation must destroy all
1718 * successfully created command buffer objects from this
1719 * command, set all entries of the pCommandBuffers array to
1720 * NULL and return the error."
1722 memset(pCommandBuffers
, 0,
1723 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1730 tu_FreeCommandBuffers(VkDevice device
,
1731 VkCommandPool commandPool
,
1732 uint32_t commandBufferCount
,
1733 const VkCommandBuffer
*pCommandBuffers
)
1735 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1736 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1739 if (cmd_buffer
->pool
) {
1740 list_del(&cmd_buffer
->pool_link
);
1741 list_addtail(&cmd_buffer
->pool_link
,
1742 &cmd_buffer
->pool
->free_cmd_buffers
);
1744 tu_cmd_buffer_destroy(cmd_buffer
);
1750 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1751 VkCommandBufferResetFlags flags
)
1753 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1754 return tu_reset_cmd_buffer(cmd_buffer
);
1758 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1759 const VkCommandBufferBeginInfo
*pBeginInfo
)
1761 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1762 VkResult result
= VK_SUCCESS
;
1764 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1765 /* If the command buffer has already been resetted with
1766 * vkResetCommandBuffer, no need to do it again.
1768 result
= tu_reset_cmd_buffer(cmd_buffer
);
1769 if (result
!= VK_SUCCESS
)
1773 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1774 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1776 tu_cs_begin(&cmd_buffer
->cs
);
1777 tu_cs_begin(&cmd_buffer
->draw_cs
);
1778 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1780 cmd_buffer
->scratch_seqno
= 0;
1782 /* setup initial configuration into command buffer */
1783 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1784 switch (cmd_buffer
->queue_family_index
) {
1785 case TU_QUEUE_GENERAL
:
1786 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1791 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1792 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1793 assert(pBeginInfo
->pInheritanceInfo
);
1794 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1795 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1798 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1804 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1805 uint32_t firstBinding
,
1806 uint32_t bindingCount
,
1807 const VkBuffer
*pBuffers
,
1808 const VkDeviceSize
*pOffsets
)
1810 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1812 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1814 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1815 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1816 tu_buffer_from_handle(pBuffers
[i
]);
1817 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1820 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1821 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1825 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1827 VkDeviceSize offset
,
1828 VkIndexType indexType
)
1830 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1831 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1833 /* initialize/update the restart index */
1834 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1835 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1837 tu6_emit_restart_index(
1838 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1840 tu_cs_sanity_check(draw_cs
);
1844 if (cmd
->state
.index_buffer
!= buf
)
1845 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1847 cmd
->state
.index_buffer
= buf
;
1848 cmd
->state
.index_offset
= offset
;
1849 cmd
->state
.index_type
= indexType
;
1853 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1854 VkPipelineBindPoint pipelineBindPoint
,
1855 VkPipelineLayout _layout
,
1857 uint32_t descriptorSetCount
,
1858 const VkDescriptorSet
*pDescriptorSets
,
1859 uint32_t dynamicOffsetCount
,
1860 const uint32_t *pDynamicOffsets
)
1862 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1863 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1864 unsigned dyn_idx
= 0;
1866 struct tu_descriptor_state
*descriptors_state
=
1867 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1869 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1870 unsigned idx
= i
+ firstSet
;
1871 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1873 descriptors_state
->sets
[idx
] = set
;
1874 descriptors_state
->valid
|= (1u << idx
);
1876 /* Note: the actual input attachment indices come from the shader
1877 * itself, so we can't generate the patched versions of these until
1878 * draw time when both the pipeline and descriptors are bound and
1879 * we're inside the render pass.
1881 unsigned dst_idx
= layout
->set
[idx
].input_attachment_start
;
1882 memcpy(&descriptors_state
->input_attachments
[dst_idx
* A6XX_TEX_CONST_DWORDS
],
1883 set
->dynamic_descriptors
,
1884 set
->layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
1886 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1887 /* Dynamic buffers come after input attachments in the descriptor set
1888 * itself, but due to how the Vulkan descriptor set binding works, we
1889 * have to put input attachments and dynamic buffers in separate
1890 * buffers in the descriptor_state and then combine them at draw
1891 * time. Binding a descriptor set only invalidates the descriptor
1892 * sets after it, but if we try to tightly pack the descriptors after
1893 * the input attachments then we could corrupt dynamic buffers in the
1894 * descriptor set before it, or we'd have to move all the dynamic
1895 * buffers over. We just put them into separate buffers to make
1896 * binding as well as the later patching of input attachments easy.
1898 unsigned src_idx
= j
+ set
->layout
->input_attachment_count
;
1899 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1900 assert(dyn_idx
< dynamicOffsetCount
);
1903 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1905 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1906 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1908 /* Patch the storage/uniform descriptors right away. */
1909 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1910 /* Note: we can assume here that the addition won't roll over and
1911 * change the SIZE field.
1913 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1918 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1919 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1920 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1928 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
)
1929 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1931 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1934 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1935 uint32_t firstBinding
,
1936 uint32_t bindingCount
,
1937 const VkBuffer
*pBuffers
,
1938 const VkDeviceSize
*pOffsets
,
1939 const VkDeviceSize
*pSizes
)
1941 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1942 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1944 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1945 uint32_t idx
= firstBinding
+ i
;
1946 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1948 if (pOffsets
[i
] != 0)
1949 cmd
->state
.streamout_reset
|= 1 << idx
;
1951 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1952 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1953 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1955 cmd
->state
.streamout_enabled
|= 1 << idx
;
1958 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1961 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1962 uint32_t firstCounterBuffer
,
1963 uint32_t counterBufferCount
,
1964 const VkBuffer
*pCounterBuffers
,
1965 const VkDeviceSize
*pCounterBufferOffsets
)
1967 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1968 /* TODO do something with counter buffer? */
1971 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1972 uint32_t firstCounterBuffer
,
1973 uint32_t counterBufferCount
,
1974 const VkBuffer
*pCounterBuffers
,
1975 const VkDeviceSize
*pCounterBufferOffsets
)
1977 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1978 /* TODO do something with counter buffer? */
1980 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1981 cmd
->state
.streamout_enabled
= 0;
1985 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1986 VkPipelineLayout layout
,
1987 VkShaderStageFlags stageFlags
,
1990 const void *pValues
)
1992 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1993 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1994 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
1998 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
2000 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2002 if (cmd_buffer
->scratch_seqno
) {
2003 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2004 MSM_SUBMIT_BO_WRITE
);
2007 if (cmd_buffer
->use_vsc_data
) {
2008 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
2009 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2010 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
2011 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2014 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
2015 MSM_SUBMIT_BO_READ
);
2017 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2018 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2019 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2022 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2023 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2024 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2027 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2028 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2029 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2032 tu_cs_end(&cmd_buffer
->cs
);
2033 tu_cs_end(&cmd_buffer
->draw_cs
);
2034 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2036 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2038 return cmd_buffer
->record_result
;
2042 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2043 VkPipelineBindPoint pipelineBindPoint
,
2044 VkPipeline _pipeline
)
2046 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2047 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2049 switch (pipelineBindPoint
) {
2050 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2051 cmd
->state
.pipeline
= pipeline
;
2052 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2054 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2055 cmd
->state
.compute_pipeline
= pipeline
;
2056 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2059 unreachable("unrecognized pipeline bind point");
2063 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2064 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2065 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2066 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2067 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2072 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2073 uint32_t firstViewport
,
2074 uint32_t viewportCount
,
2075 const VkViewport
*pViewports
)
2077 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2079 assert(firstViewport
== 0 && viewportCount
== 1);
2080 cmd
->state
.dynamic
.viewport
.viewports
[0] = pViewports
[0];
2081 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2085 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2086 uint32_t firstScissor
,
2087 uint32_t scissorCount
,
2088 const VkRect2D
*pScissors
)
2090 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2092 assert(firstScissor
== 0 && scissorCount
== 1);
2093 cmd
->state
.dynamic
.scissor
.scissors
[0] = pScissors
[0];
2094 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_SCISSOR
;
2098 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2100 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2102 cmd
->state
.dynamic
.line_width
= lineWidth
;
2104 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2105 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2109 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2110 float depthBiasConstantFactor
,
2111 float depthBiasClamp
,
2112 float depthBiasSlopeFactor
)
2114 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2115 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2117 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2118 depthBiasSlopeFactor
);
2120 tu_cs_sanity_check(draw_cs
);
2124 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2125 const float blendConstants
[4])
2127 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2128 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2130 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2132 tu_cs_sanity_check(draw_cs
);
2136 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2137 float minDepthBounds
,
2138 float maxDepthBounds
)
2143 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2144 VkStencilFaceFlags faceMask
,
2145 uint32_t compareMask
)
2147 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2149 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2150 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2151 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2152 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2154 /* the front/back compare masks must be updated together */
2155 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2159 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2160 VkStencilFaceFlags faceMask
,
2163 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2165 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2166 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2167 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2168 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2170 /* the front/back write masks must be updated together */
2171 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2175 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2176 VkStencilFaceFlags faceMask
,
2179 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2181 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2182 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2183 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2184 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2186 /* the front/back references must be updated together */
2187 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2191 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2192 uint32_t commandBufferCount
,
2193 const VkCommandBuffer
*pCmdBuffers
)
2195 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2198 assert(commandBufferCount
> 0);
2200 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2201 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2203 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2204 if (result
!= VK_SUCCESS
) {
2205 cmd
->record_result
= result
;
2209 if (secondary
->usage_flags
&
2210 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2211 assert(tu_cs_is_empty(&secondary
->cs
));
2213 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2214 if (result
!= VK_SUCCESS
) {
2215 cmd
->record_result
= result
;
2219 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2220 &secondary
->draw_epilogue_cs
);
2221 if (result
!= VK_SUCCESS
) {
2222 cmd
->record_result
= result
;
2226 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2227 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2229 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2230 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2231 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2234 tu_cs_emit_call(&cmd
->cs
, &secondary
->cs
);
2237 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2241 tu_CreateCommandPool(VkDevice _device
,
2242 const VkCommandPoolCreateInfo
*pCreateInfo
,
2243 const VkAllocationCallbacks
*pAllocator
,
2244 VkCommandPool
*pCmdPool
)
2246 TU_FROM_HANDLE(tu_device
, device
, _device
);
2247 struct tu_cmd_pool
*pool
;
2249 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2250 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2252 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2255 pool
->alloc
= *pAllocator
;
2257 pool
->alloc
= device
->alloc
;
2259 list_inithead(&pool
->cmd_buffers
);
2260 list_inithead(&pool
->free_cmd_buffers
);
2262 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2264 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2270 tu_DestroyCommandPool(VkDevice _device
,
2271 VkCommandPool commandPool
,
2272 const VkAllocationCallbacks
*pAllocator
)
2274 TU_FROM_HANDLE(tu_device
, device
, _device
);
2275 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2280 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2281 &pool
->cmd_buffers
, pool_link
)
2283 tu_cmd_buffer_destroy(cmd_buffer
);
2286 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2287 &pool
->free_cmd_buffers
, pool_link
)
2289 tu_cmd_buffer_destroy(cmd_buffer
);
2292 vk_free2(&device
->alloc
, pAllocator
, pool
);
2296 tu_ResetCommandPool(VkDevice device
,
2297 VkCommandPool commandPool
,
2298 VkCommandPoolResetFlags flags
)
2300 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2303 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2306 result
= tu_reset_cmd_buffer(cmd_buffer
);
2307 if (result
!= VK_SUCCESS
)
2315 tu_TrimCommandPool(VkDevice device
,
2316 VkCommandPool commandPool
,
2317 VkCommandPoolTrimFlags flags
)
2319 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2324 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2325 &pool
->free_cmd_buffers
, pool_link
)
2327 tu_cmd_buffer_destroy(cmd_buffer
);
2332 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2333 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2334 VkSubpassContents contents
)
2336 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2337 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2338 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2340 cmd
->state
.pass
= pass
;
2341 cmd
->state
.subpass
= pass
->subpasses
;
2342 cmd
->state
.framebuffer
= fb
;
2344 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2345 tu_cmd_prepare_tile_store_ib(cmd
);
2347 tu_emit_load_clear(cmd
, pRenderPassBegin
);
2349 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2350 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2351 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2352 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2354 /* note: use_hw_binning only checks tiling config */
2355 if (use_hw_binning(cmd
))
2356 cmd
->use_vsc_data
= true;
2358 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2359 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2360 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2361 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2364 /* Flag input attachment descriptors for re-emission if necessary */
2365 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2369 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2370 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2371 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2373 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2374 pSubpassBeginInfo
->contents
);
2378 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2380 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2381 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2382 struct tu_cs
*cs
= &cmd
->draw_cs
;
2384 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2386 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2388 if (subpass
->resolve_attachments
) {
2389 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2390 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2391 if (a
== VK_ATTACHMENT_UNUSED
)
2394 tu_store_gmem_attachment(cmd
, cs
, a
,
2395 subpass
->color_attachments
[i
].attachment
);
2397 if (pass
->attachments
[a
].gmem_offset
< 0)
2401 * check if the resolved attachment is needed by later subpasses,
2402 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2404 tu_finishme("missing GMEM->GMEM resolve path\n");
2405 tu_emit_load_gmem_attachment(cmd
, cs
, a
);
2409 tu_cond_exec_end(cs
);
2411 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2413 /* Emit flushes so that input attachments will read the correct value.
2414 * TODO: use subpass dependencies to flush or not
2416 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2417 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
2419 if (subpass
->resolve_attachments
) {
2420 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2422 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2423 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2424 if (a
== VK_ATTACHMENT_UNUSED
)
2427 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
2428 subpass
->color_attachments
[i
].attachment
);
2431 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2434 tu_cond_exec_end(cs
);
2436 /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2437 if (cmd
->state
.subpass
->input_count
)
2438 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2440 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2441 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2442 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2443 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2444 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2446 /* Flag input attachment descriptors for re-emission if necessary */
2447 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2451 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2452 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2453 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2455 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2461 * Number of vertices.
2466 * Index of the first vertex.
2468 int32_t vertex_offset
;
2471 * First instance id.
2473 uint32_t first_instance
;
2476 * Number of instances.
2478 uint32_t instance_count
;
2481 * First index (indexed draws only).
2483 uint32_t first_index
;
2486 * Whether it's an indexed draw.
2491 * Indirect draw parameters resource.
2493 struct tu_buffer
*indirect
;
2494 uint64_t indirect_offset
;
2498 * Draw count parameters resource.
2500 struct tu_buffer
*count_buffer
;
2501 uint64_t count_buffer_offset
;
2504 * Stream output parameters resource.
2506 struct tu_buffer
*streamout_buffer
;
2507 uint64_t streamout_buffer_offset
;
2510 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2511 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2512 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2514 enum tu_draw_state_group_id
2516 TU_DRAW_STATE_PROGRAM
,
2517 TU_DRAW_STATE_PROGRAM_BINNING
,
2519 TU_DRAW_STATE_VI_BINNING
,
2523 TU_DRAW_STATE_BLEND
,
2524 TU_DRAW_STATE_VS_CONST
,
2525 TU_DRAW_STATE_GS_CONST
,
2526 TU_DRAW_STATE_FS_CONST
,
2527 TU_DRAW_STATE_DESC_SETS
,
2528 TU_DRAW_STATE_DESC_SETS_GMEM
,
2529 TU_DRAW_STATE_DESC_SETS_LOAD
,
2530 TU_DRAW_STATE_VS_PARAMS
,
2532 TU_DRAW_STATE_COUNT
,
2535 struct tu_draw_state_group
2537 enum tu_draw_state_group_id id
;
2538 uint32_t enable_mask
;
2539 struct tu_cs_entry ib
;
2542 static inline uint32_t
2543 tu6_stage2opcode(gl_shader_stage type
)
2546 case MESA_SHADER_VERTEX
:
2547 case MESA_SHADER_TESS_CTRL
:
2548 case MESA_SHADER_TESS_EVAL
:
2549 case MESA_SHADER_GEOMETRY
:
2550 return CP_LOAD_STATE6_GEOM
;
2551 case MESA_SHADER_FRAGMENT
:
2552 case MESA_SHADER_COMPUTE
:
2553 case MESA_SHADER_KERNEL
:
2554 return CP_LOAD_STATE6_FRAG
;
2556 unreachable("bad shader type");
2560 static inline enum a6xx_state_block
2561 tu6_stage2shadersb(gl_shader_stage type
)
2564 case MESA_SHADER_VERTEX
:
2565 return SB6_VS_SHADER
;
2566 case MESA_SHADER_GEOMETRY
:
2567 return SB6_GS_SHADER
;
2568 case MESA_SHADER_FRAGMENT
:
2569 return SB6_FS_SHADER
;
2570 case MESA_SHADER_COMPUTE
:
2571 case MESA_SHADER_KERNEL
:
2572 return SB6_CS_SHADER
;
2574 unreachable("bad shader type");
2580 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2581 struct tu_descriptor_state
*descriptors_state
,
2582 gl_shader_stage type
,
2583 uint32_t *push_constants
)
2585 const struct tu_program_descriptor_linkage
*link
=
2586 &pipeline
->program
.link
[type
];
2587 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2589 if (link
->push_consts
.count
> 0) {
2590 unsigned num_units
= link
->push_consts
.count
;
2591 unsigned offset
= link
->push_consts
.lo
;
2592 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2593 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2594 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2595 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2596 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2597 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2600 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2601 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2604 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2605 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2606 uint32_t offset
= state
->range
[i
].start
;
2608 /* and even if the start of the const buffer is before
2609 * first_immediate, the end may not be:
2611 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2616 /* things should be aligned to vec4: */
2617 debug_assert((state
->range
[i
].offset
% 16) == 0);
2618 debug_assert((size
% 16) == 0);
2619 debug_assert((offset
% 16) == 0);
2621 /* Dig out the descriptor from the descriptor state and read the VA from
2624 assert(state
->range
[i
].bindless
);
2625 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2626 descriptors_state
->dynamic_descriptors
:
2627 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2628 unsigned block
= state
->range
[i
].block
;
2629 /* If the block in the shader here is in the dynamic descriptor set, it
2630 * is an index into the dynamic descriptor set which is combined from
2631 * dynamic descriptors and input attachments on-the-fly, and we don't
2632 * have access to it here. Instead we work backwards to get the index
2633 * into dynamic_descriptors.
2635 if (state
->range
[i
].bindless_base
== MAX_SETS
)
2636 block
-= pipeline
->layout
->input_attachment_count
;
2637 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2638 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2641 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2642 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2643 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2644 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2645 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2646 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2647 tu_cs_emit_qw(cs
, va
+ offset
);
2651 static struct tu_cs_entry
2652 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2653 const struct tu_pipeline
*pipeline
,
2654 struct tu_descriptor_state
*descriptors_state
,
2655 gl_shader_stage type
)
2658 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2660 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2662 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2666 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2667 const struct tu_draw_info
*draw
,
2668 struct tu_cs_entry
*entry
)
2670 /* TODO: fill out more than just base instance */
2671 const struct tu_program_descriptor_linkage
*link
=
2672 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2673 const struct ir3_const_state
*const_state
= &link
->const_state
;
2676 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2677 *entry
= (struct tu_cs_entry
) {};
2681 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2682 if (result
!= VK_SUCCESS
)
2685 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2686 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2687 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2688 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2689 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2690 CP_LOAD_STATE6_0_NUM_UNIT(1));
2694 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2698 tu_cs_emit(&cs
, draw
->first_instance
);
2701 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2706 tu6_emit_descriptor_sets(struct tu_cmd_buffer
*cmd
,
2707 const struct tu_pipeline
*pipeline
,
2708 VkPipelineBindPoint bind_point
,
2709 struct tu_cs_entry
*entry
,
2712 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2713 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
2714 struct tu_descriptor_state
*descriptors_state
=
2715 tu_get_descriptors_state(cmd
, bind_point
);
2716 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2717 const uint32_t *input_attachment_idx
=
2718 pipeline
->program
.input_attachment_idx
;
2719 uint32_t num_dynamic_descs
= layout
->dynamic_offset_count
+
2720 layout
->input_attachment_count
;
2721 struct ts_cs_memory dynamic_desc_set
;
2724 if (num_dynamic_descs
> 0) {
2725 /* allocate and fill out dynamic descriptor set */
2726 result
= tu_cs_alloc(draw_state
, num_dynamic_descs
,
2727 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
2728 if (result
!= VK_SUCCESS
)
2731 memcpy(dynamic_desc_set
.map
, descriptors_state
->input_attachments
,
2732 layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
2735 /* Patch input attachments to refer to GMEM instead */
2736 for (unsigned i
= 0; i
< layout
->input_attachment_count
; i
++) {
2738 &dynamic_desc_set
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2740 /* The compiler has already laid out input_attachment_idx in the
2741 * final order of input attachments, so there's no need to go
2742 * through the pipeline layout finding input attachments.
2744 unsigned attachment_idx
= input_attachment_idx
[i
];
2746 /* It's possible for the pipeline layout to include an input
2747 * attachment which doesn't actually exist for the current
2748 * subpass. Of course, this is only valid so long as the pipeline
2749 * doesn't try to actually load that attachment. Just skip
2750 * patching in that scenario to avoid out-of-bounds accesses.
2752 if (attachment_idx
>= cmd
->state
.subpass
->input_count
)
2755 uint32_t a
= cmd
->state
.subpass
->input_attachments
[attachment_idx
].attachment
;
2756 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2758 assert(att
->gmem_offset
>= 0);
2760 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2761 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2762 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2764 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2765 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2767 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
2768 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2769 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2772 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2773 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2777 memcpy(dynamic_desc_set
.map
+ layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
,
2778 descriptors_state
->dynamic_descriptors
,
2779 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
2782 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
;
2783 uint32_t hlsq_update_value
;
2784 switch (bind_point
) {
2785 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2786 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
2787 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
2788 hlsq_update_value
= 0x7c000;
2790 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2791 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2792 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2793 hlsq_update_value
= 0x3e00;
2796 unreachable("bad bind point");
2799 /* Be careful here to *not* refer to the pipeline, so that if only the
2800 * pipeline changes we don't have to emit this again (except if there are
2801 * dynamic descriptors in the pipeline layout). This means always emitting
2802 * all the valid descriptors, which means that we always have to put the
2803 * dynamic descriptor in the driver-only slot at the end
2805 uint32_t num_user_sets
= util_last_bit(descriptors_state
->valid
);
2806 uint32_t num_sets
= num_user_sets
;
2807 if (num_dynamic_descs
> 0) {
2808 num_user_sets
= MAX_SETS
;
2809 num_sets
= num_user_sets
+ 1;
2812 unsigned regs
[2] = { sp_bindless_base_reg
, hlsq_bindless_base_reg
};
2815 result
= tu_cs_begin_sub_stream(draw_state
, ARRAY_SIZE(regs
) * (1 + num_sets
* 2) + 2, &cs
);
2816 if (result
!= VK_SUCCESS
)
2820 for (unsigned i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
2821 tu_cs_emit_pkt4(&cs
, regs
[i
], num_sets
* 2);
2822 for (unsigned j
= 0; j
< num_user_sets
; j
++) {
2823 if (descriptors_state
->valid
& (1 << j
)) {
2824 /* magic | 3 copied from the blob */
2825 tu_cs_emit_qw(&cs
, descriptors_state
->sets
[j
]->va
| 3);
2827 tu_cs_emit_qw(&cs
, 0 | 3);
2830 if (num_dynamic_descs
> 0) {
2831 tu_cs_emit_qw(&cs
, dynamic_desc_set
.iova
| 3);
2835 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value
));
2838 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2843 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2845 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2847 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2848 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2853 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2855 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2856 .bo_offset
= buf
->bo_offset
));
2857 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2859 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2860 offset
*= tf
->stride
[i
];
2862 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2863 cmd
->state
.streamout_reset
&= ~(1 << i
);
2865 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2866 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2867 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2868 CP_MEM_TO_REG_0_CNT(0));
2869 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2870 ctrl_offset(flush_base
[i
].offset
));
2873 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
2875 ctrl_offset(flush_base
[i
])));
2878 if (cmd
->state
.streamout_enabled
) {
2879 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
2880 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2881 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
2882 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
2883 tu_cs_emit(cs
, tf
->ncomp
[0]);
2884 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
2885 tu_cs_emit(cs
, tf
->ncomp
[1]);
2886 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
2887 tu_cs_emit(cs
, tf
->ncomp
[2]);
2888 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
2889 tu_cs_emit(cs
, tf
->ncomp
[3]);
2890 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2891 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
2892 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
2893 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
2894 tu_cs_emit(cs
, tf
->prog
[i
]);
2897 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
2898 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2900 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2906 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2908 const struct tu_draw_info
*draw
)
2910 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2911 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2912 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2913 uint32_t draw_state_group_count
= 0;
2916 struct tu_descriptor_state
*descriptors_state
=
2917 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2922 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
2923 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
2925 if (cmd
->state
.dirty
&
2926 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2927 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2928 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2929 dynamic
->line_width
);
2932 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2933 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2934 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2935 dynamic
->stencil_compare_mask
.back
);
2938 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2939 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2940 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2941 dynamic
->stencil_write_mask
.back
);
2944 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2945 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2946 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2947 dynamic
->stencil_reference
.back
);
2950 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2951 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2952 tu6_emit_viewport(cs
, &cmd
->state
.dynamic
.viewport
.viewports
[0]);
2955 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_SCISSOR
) &&
2956 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2957 tu6_emit_scissor(cs
, &cmd
->state
.dynamic
.scissor
.scissors
[0]);
2960 if (cmd
->state
.dirty
&
2961 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
2962 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
2963 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
2964 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2965 const VkDeviceSize offset
= buf
->bo_offset
+
2966 cmd
->state
.vb
.offsets
[binding
];
2967 const VkDeviceSize size
=
2968 offset
< buf
->size
? buf
->size
- offset
: 0;
2971 A6XX_VFD_FETCH_BASE(i
, .bo
= buf
->bo
, .bo_offset
= offset
),
2972 A6XX_VFD_FETCH_SIZE(i
, size
));
2976 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2977 draw_state_groups
[draw_state_group_count
++] =
2978 (struct tu_draw_state_group
) {
2979 .id
= TU_DRAW_STATE_PROGRAM
,
2980 .enable_mask
= ENABLE_DRAW
,
2981 .ib
= pipeline
->program
.state_ib
,
2983 draw_state_groups
[draw_state_group_count
++] =
2984 (struct tu_draw_state_group
) {
2985 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2986 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2987 .ib
= pipeline
->program
.binning_state_ib
,
2989 draw_state_groups
[draw_state_group_count
++] =
2990 (struct tu_draw_state_group
) {
2991 .id
= TU_DRAW_STATE_VI
,
2992 .enable_mask
= ENABLE_DRAW
,
2993 .ib
= pipeline
->vi
.state_ib
,
2995 draw_state_groups
[draw_state_group_count
++] =
2996 (struct tu_draw_state_group
) {
2997 .id
= TU_DRAW_STATE_VI_BINNING
,
2998 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2999 .ib
= pipeline
->vi
.binning_state_ib
,
3001 draw_state_groups
[draw_state_group_count
++] =
3002 (struct tu_draw_state_group
) {
3003 .id
= TU_DRAW_STATE_VP
,
3004 .enable_mask
= ENABLE_ALL
,
3005 .ib
= pipeline
->vp
.state_ib
,
3007 draw_state_groups
[draw_state_group_count
++] =
3008 (struct tu_draw_state_group
) {
3009 .id
= TU_DRAW_STATE_RAST
,
3010 .enable_mask
= ENABLE_ALL
,
3011 .ib
= pipeline
->rast
.state_ib
,
3013 draw_state_groups
[draw_state_group_count
++] =
3014 (struct tu_draw_state_group
) {
3015 .id
= TU_DRAW_STATE_DS
,
3016 .enable_mask
= ENABLE_ALL
,
3017 .ib
= pipeline
->ds
.state_ib
,
3019 draw_state_groups
[draw_state_group_count
++] =
3020 (struct tu_draw_state_group
) {
3021 .id
= TU_DRAW_STATE_BLEND
,
3022 .enable_mask
= ENABLE_ALL
,
3023 .ib
= pipeline
->blend
.state_ib
,
3027 if (cmd
->state
.dirty
&
3028 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
3029 draw_state_groups
[draw_state_group_count
++] =
3030 (struct tu_draw_state_group
) {
3031 .id
= TU_DRAW_STATE_VS_CONST
,
3032 .enable_mask
= ENABLE_ALL
,
3033 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
3035 draw_state_groups
[draw_state_group_count
++] =
3036 (struct tu_draw_state_group
) {
3037 .id
= TU_DRAW_STATE_GS_CONST
,
3038 .enable_mask
= ENABLE_ALL
,
3039 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
)
3041 draw_state_groups
[draw_state_group_count
++] =
3042 (struct tu_draw_state_group
) {
3043 .id
= TU_DRAW_STATE_FS_CONST
,
3044 .enable_mask
= ENABLE_DRAW
,
3045 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3049 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3050 tu6_emit_streamout(cmd
, cs
);
3052 /* If there are any any dynamic descriptors, then we may need to re-emit
3053 * them after every pipeline change in case the number of input attachments
3054 * changes. We also always need to re-emit after a pipeline change if there
3055 * are any input attachments, because the input attachment index comes from
3056 * the pipeline. Finally, it can also happen that the subpass changes
3057 * without the pipeline changing, in which case the GMEM descriptors need
3058 * to be patched differently.
3060 * TODO: We could probably be clever and avoid re-emitting state on
3061 * pipeline changes if the number of input attachments is always 0. We
3062 * could also only re-emit dynamic state.
3064 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
||
3065 ((pipeline
->layout
->dynamic_offset_count
+
3066 pipeline
->layout
->input_attachment_count
> 0) &&
3067 cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) ||
3068 (pipeline
->layout
->input_attachment_count
> 0 &&
3069 cmd
->state
.dirty
& TU_CMD_DIRTY_INPUT_ATTACHMENTS
)) {
3070 struct tu_cs_entry desc_sets
, desc_sets_gmem
;
3071 bool need_gmem_desc_set
= pipeline
->layout
->input_attachment_count
> 0;
3073 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3074 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3076 if (result
!= VK_SUCCESS
)
3079 draw_state_groups
[draw_state_group_count
++] =
3080 (struct tu_draw_state_group
) {
3081 .id
= TU_DRAW_STATE_DESC_SETS
,
3082 .enable_mask
= need_gmem_desc_set
? ENABLE_NON_GMEM
: ENABLE_ALL
,
3086 if (need_gmem_desc_set
) {
3087 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3088 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3089 &desc_sets_gmem
, true);
3090 if (result
!= VK_SUCCESS
)
3093 draw_state_groups
[draw_state_group_count
++] =
3094 (struct tu_draw_state_group
) {
3095 .id
= TU_DRAW_STATE_DESC_SETS_GMEM
,
3096 .enable_mask
= CP_SET_DRAW_STATE__0_GMEM
,
3097 .ib
= desc_sets_gmem
,
3101 /* We need to reload the descriptors every time the descriptor sets
3102 * change. However, the commands we send only depend on the pipeline
3103 * because the whole point is to cache descriptors which are used by the
3104 * pipeline. There's a problem here, in that the firmware has an
3105 * "optimization" which skips executing groups that are set to the same
3106 * value as the last draw. This means that if the descriptor sets change
3107 * but not the pipeline, we'd try to re-execute the same buffer which
3108 * the firmware would ignore and we wouldn't pre-load the new
3109 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3110 * the descriptor sets change, which we emulate here by copying the
3111 * pre-prepared buffer.
3113 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3114 if (load_entry
->size
> 0) {
3115 struct tu_cs load_cs
;
3116 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3117 if (result
!= VK_SUCCESS
)
3119 tu_cs_emit_array(&load_cs
,
3120 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3121 load_entry
->size
/ 4);
3122 struct tu_cs_entry load_copy
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3124 draw_state_groups
[draw_state_group_count
++] =
3125 (struct tu_draw_state_group
) {
3126 .id
= TU_DRAW_STATE_DESC_SETS_LOAD
,
3127 /* The blob seems to not enable this for binning, even when
3128 * resources would actually be used in the binning shader.
3129 * Presumably the overhead of prefetching the resources isn't
3132 .enable_mask
= ENABLE_DRAW
,
3138 struct tu_cs_entry vs_params
;
3139 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3140 if (result
!= VK_SUCCESS
)
3143 draw_state_groups
[draw_state_group_count
++] =
3144 (struct tu_draw_state_group
) {
3145 .id
= TU_DRAW_STATE_VS_PARAMS
,
3146 .enable_mask
= ENABLE_ALL
,
3150 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3151 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3152 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3153 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3154 uint32_t cp_set_draw_state
=
3155 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3156 group
->enable_mask
|
3157 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3159 if (group
->ib
.size
) {
3160 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3162 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3166 tu_cs_emit(cs
, cp_set_draw_state
);
3167 tu_cs_emit_qw(cs
, iova
);
3170 tu_cs_sanity_check(cs
);
3173 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3174 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3175 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3177 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3180 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3182 for_each_bit(i
, descriptors_state
->valid
) {
3183 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3184 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3185 if (set
->buffers
[j
]) {
3186 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3187 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3190 if (set
->size
> 0) {
3191 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3192 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3196 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3197 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3198 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3200 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3201 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3206 /* There are too many graphics dirty bits to list here, so just list the
3207 * bits to preserve instead. The only things not emitted here are
3208 * compute-related state.
3210 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
3212 /* Fragment shader state overwrites compute shader state, so flag the
3213 * compute pipeline for re-emit.
3215 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3220 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3222 const struct tu_draw_info
*draw
)
3224 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3225 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3226 VK_SHADER_STAGE_GEOMETRY_BIT
;
3229 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3230 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3232 if (draw
->indexed
) {
3233 const enum a4xx_index_size index_size
=
3234 tu6_index_size(cmd
->state
.index_type
);
3235 const uint32_t index_bytes
=
3236 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3237 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3238 unsigned max_indicies
=
3239 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3241 const uint32_t cp_draw_indx
=
3242 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3243 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3244 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3245 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3246 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3248 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3249 tu_cs_emit(cs
, cp_draw_indx
);
3250 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3251 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3252 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3254 const uint32_t cp_draw_indx
=
3255 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3256 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3257 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3258 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3260 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3261 tu_cs_emit(cs
, cp_draw_indx
);
3262 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3265 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3269 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3271 const struct tu_draw_info
*draw
)
3274 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3275 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3276 VK_SHADER_STAGE_GEOMETRY_BIT
;
3279 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3280 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3282 /* TODO hw binning */
3283 if (draw
->indexed
) {
3284 const enum a4xx_index_size index_size
=
3285 tu6_index_size(cmd
->state
.index_type
);
3286 const uint32_t index_bytes
=
3287 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3288 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3289 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3290 index_bytes
* draw
->first_index
;
3291 const uint32_t size
= index_bytes
* draw
->count
;
3293 const uint32_t cp_draw_indx
=
3294 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3295 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3296 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3297 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3298 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3300 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3301 tu_cs_emit(cs
, cp_draw_indx
);
3302 tu_cs_emit(cs
, draw
->instance_count
);
3303 tu_cs_emit(cs
, draw
->count
);
3304 tu_cs_emit(cs
, 0x0); /* XXX */
3305 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3306 tu_cs_emit(cs
, size
);
3308 const uint32_t cp_draw_indx
=
3309 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3310 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3311 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3312 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3314 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3315 tu_cs_emit(cs
, cp_draw_indx
);
3316 tu_cs_emit(cs
, draw
->instance_count
);
3317 tu_cs_emit(cs
, draw
->count
);
3322 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3324 struct tu_cs
*cs
= &cmd
->draw_cs
;
3327 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3328 if (result
!= VK_SUCCESS
) {
3329 cmd
->record_result
= result
;
3334 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3336 tu6_emit_draw_direct(cmd
, cs
, draw
);
3338 if (cmd
->state
.streamout_enabled
) {
3339 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3340 if (cmd
->state
.streamout_enabled
& (1 << i
))
3341 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
, false);
3345 cmd
->wait_for_idle
= true;
3347 tu_cs_sanity_check(cs
);
3351 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3352 uint32_t vertexCount
,
3353 uint32_t instanceCount
,
3354 uint32_t firstVertex
,
3355 uint32_t firstInstance
)
3357 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3358 struct tu_draw_info info
= {};
3360 info
.count
= vertexCount
;
3361 info
.instance_count
= instanceCount
;
3362 info
.first_instance
= firstInstance
;
3363 info
.vertex_offset
= firstVertex
;
3365 tu_draw(cmd_buffer
, &info
);
3369 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3370 uint32_t indexCount
,
3371 uint32_t instanceCount
,
3372 uint32_t firstIndex
,
3373 int32_t vertexOffset
,
3374 uint32_t firstInstance
)
3376 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3377 struct tu_draw_info info
= {};
3379 info
.indexed
= true;
3380 info
.count
= indexCount
;
3381 info
.instance_count
= instanceCount
;
3382 info
.first_index
= firstIndex
;
3383 info
.vertex_offset
= vertexOffset
;
3384 info
.first_instance
= firstInstance
;
3386 tu_draw(cmd_buffer
, &info
);
3390 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3392 VkDeviceSize offset
,
3396 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3397 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3398 struct tu_draw_info info
= {};
3400 info
.count
= drawCount
;
3401 info
.indirect
= buffer
;
3402 info
.indirect_offset
= offset
;
3403 info
.stride
= stride
;
3405 tu_draw(cmd_buffer
, &info
);
3409 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3411 VkDeviceSize offset
,
3415 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3416 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3417 struct tu_draw_info info
= {};
3419 info
.indexed
= true;
3420 info
.count
= drawCount
;
3421 info
.indirect
= buffer
;
3422 info
.indirect_offset
= offset
;
3423 info
.stride
= stride
;
3425 tu_draw(cmd_buffer
, &info
);
3428 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3429 uint32_t instanceCount
,
3430 uint32_t firstInstance
,
3431 VkBuffer _counterBuffer
,
3432 VkDeviceSize counterBufferOffset
,
3433 uint32_t counterOffset
,
3434 uint32_t vertexStride
)
3436 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3437 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3439 struct tu_draw_info info
= {};
3441 info
.instance_count
= instanceCount
;
3442 info
.first_instance
= firstInstance
;
3443 info
.streamout_buffer
= buffer
;
3444 info
.streamout_buffer_offset
= counterBufferOffset
;
3445 info
.stride
= vertexStride
;
3447 tu_draw(cmd_buffer
, &info
);
3450 struct tu_dispatch_info
3453 * Determine the layout of the grid (in block units) to be used.
3458 * A starting offset for the grid. If unaligned is set, the offset
3459 * must still be aligned.
3461 uint32_t offsets
[3];
3463 * Whether it's an unaligned compute dispatch.
3468 * Indirect compute parameters resource.
3470 struct tu_buffer
*indirect
;
3471 uint64_t indirect_offset
;
3475 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3476 const struct tu_dispatch_info
*info
)
3478 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3479 const struct tu_program_descriptor_linkage
*link
=
3480 &pipeline
->program
.link
[type
];
3481 const struct ir3_const_state
*const_state
= &link
->const_state
;
3482 uint32_t offset
= const_state
->offsets
.driver_param
;
3484 if (link
->constlen
<= offset
)
3487 if (!info
->indirect
) {
3488 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3489 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3490 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3491 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3492 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3493 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3494 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3497 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3498 (link
->constlen
- offset
) * 4);
3499 /* push constants */
3500 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3501 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3502 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3503 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3504 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3505 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3509 for (i
= 0; i
< num_consts
; i
++)
3510 tu_cs_emit(cs
, driver_params
[i
]);
3512 tu_finishme("Indirect driver params");
3517 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3518 const struct tu_dispatch_info
*info
)
3520 struct tu_cs
*cs
= &cmd
->cs
;
3521 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3522 struct tu_descriptor_state
*descriptors_state
=
3523 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3526 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3527 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3529 struct tu_cs_entry ib
;
3531 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3533 tu_cs_emit_ib(cs
, &ib
);
3535 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3537 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) {
3538 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3539 VK_PIPELINE_BIND_POINT_COMPUTE
, &ib
,
3541 if (result
!= VK_SUCCESS
) {
3542 cmd
->record_result
= result
;
3548 for_each_bit(i
, descriptors_state
->valid
) {
3549 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3550 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3551 if (set
->buffers
[j
]) {
3552 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3553 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3557 if (set
->size
> 0) {
3558 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3559 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3565 tu_cs_emit_ib(cs
, &ib
);
3567 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
)
3568 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3571 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3573 /* Compute shader state overwrites fragment shader state, so we flag the
3574 * graphics pipeline for re-emit.
3576 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
3578 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3579 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3581 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3582 const uint32_t *num_groups
= info
->blocks
;
3584 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3585 .localsizex
= local_size
[0] - 1,
3586 .localsizey
= local_size
[1] - 1,
3587 .localsizez
= local_size
[2] - 1),
3588 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3589 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3590 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3591 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3592 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3593 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3596 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3597 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3598 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3600 if (info
->indirect
) {
3601 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3603 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3604 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3606 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3607 tu_cs_emit(cs
, 0x00000000);
3608 tu_cs_emit_qw(cs
, iova
);
3610 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3611 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3612 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3614 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3615 tu_cs_emit(cs
, 0x00000000);
3616 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3617 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3618 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3623 tu6_emit_cache_flush(cmd
, cs
);
3627 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3635 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3636 struct tu_dispatch_info info
= {};
3642 info
.offsets
[0] = base_x
;
3643 info
.offsets
[1] = base_y
;
3644 info
.offsets
[2] = base_z
;
3645 tu_dispatch(cmd_buffer
, &info
);
3649 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3654 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3658 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3660 VkDeviceSize offset
)
3662 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3663 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3664 struct tu_dispatch_info info
= {};
3666 info
.indirect
= buffer
;
3667 info
.indirect_offset
= offset
;
3669 tu_dispatch(cmd_buffer
, &info
);
3673 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3675 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3677 tu_cs_end(&cmd_buffer
->draw_cs
);
3678 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3680 if (use_sysmem_rendering(cmd_buffer
))
3681 tu_cmd_render_sysmem(cmd_buffer
);
3683 tu_cmd_render_tiles(cmd_buffer
);
3685 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3687 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3688 tu_cs_begin(&cmd_buffer
->draw_cs
);
3689 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3690 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3692 cmd_buffer
->state
.pass
= NULL
;
3693 cmd_buffer
->state
.subpass
= NULL
;
3694 cmd_buffer
->state
.framebuffer
= NULL
;
3698 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3699 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3701 tu_CmdEndRenderPass(commandBuffer
);
3704 struct tu_barrier_info
3706 uint32_t eventCount
;
3707 const VkEvent
*pEvents
;
3708 VkPipelineStageFlags srcStageMask
;
3712 tu_barrier(struct tu_cmd_buffer
*cmd
,
3713 uint32_t memoryBarrierCount
,
3714 const VkMemoryBarrier
*pMemoryBarriers
,
3715 uint32_t bufferMemoryBarrierCount
,
3716 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3717 uint32_t imageMemoryBarrierCount
,
3718 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3719 const struct tu_barrier_info
*info
)
3721 /* renderpass case is only for subpass self-dependencies
3722 * which means syncing the render output with texture cache
3723 * note: only the CACHE_INVALIDATE is needed in GMEM mode
3724 * and in sysmem mode we might not need either color/depth flush
3726 if (cmd
->state
.pass
) {
3727 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_COLOR_TS
, true);
3728 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
3729 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, CACHE_INVALIDATE
, false);
3735 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3736 VkPipelineStageFlags srcStageMask
,
3737 VkPipelineStageFlags dstStageMask
,
3738 VkDependencyFlags dependencyFlags
,
3739 uint32_t memoryBarrierCount
,
3740 const VkMemoryBarrier
*pMemoryBarriers
,
3741 uint32_t bufferMemoryBarrierCount
,
3742 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3743 uint32_t imageMemoryBarrierCount
,
3744 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3746 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3747 struct tu_barrier_info info
;
3749 info
.eventCount
= 0;
3750 info
.pEvents
= NULL
;
3751 info
.srcStageMask
= srcStageMask
;
3753 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3754 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3755 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3759 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
, unsigned value
)
3761 struct tu_cs
*cs
= &cmd
->cs
;
3763 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3765 /* TODO: any flush required before/after ? */
3767 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3768 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3769 tu_cs_emit(cs
, value
);
3773 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3775 VkPipelineStageFlags stageMask
)
3777 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3778 TU_FROM_HANDLE(tu_event
, event
, _event
);
3780 write_event(cmd
, event
, 1);
3784 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3786 VkPipelineStageFlags stageMask
)
3788 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3789 TU_FROM_HANDLE(tu_event
, event
, _event
);
3791 write_event(cmd
, event
, 0);
3795 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3796 uint32_t eventCount
,
3797 const VkEvent
*pEvents
,
3798 VkPipelineStageFlags srcStageMask
,
3799 VkPipelineStageFlags dstStageMask
,
3800 uint32_t memoryBarrierCount
,
3801 const VkMemoryBarrier
*pMemoryBarriers
,
3802 uint32_t bufferMemoryBarrierCount
,
3803 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3804 uint32_t imageMemoryBarrierCount
,
3805 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3807 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3808 struct tu_cs
*cs
= &cmd
->cs
;
3810 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3812 for (uint32_t i
= 0; i
< eventCount
; i
++) {
3813 TU_FROM_HANDLE(tu_event
, event
, pEvents
[i
]);
3815 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3817 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3818 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3819 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3820 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3821 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3822 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3823 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3828 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)