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9e69b918fe94c73ee1c7abc932353048e9578665
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 for (uint32_t i = 0; i < list->count; ++i) {
66 if (list->bo_infos[i].handle == bo_info->handle) {
67 assert(list->bo_infos[i].presumed == bo_info->presumed);
68 list->bo_infos[i].flags |= bo_info->flags;
69 return i;
70 }
71 }
72
73 /* grow list->bo_infos if needed */
74 if (list->count == list->capacity) {
75 uint32_t new_capacity = MAX2(2 * list->count, 16);
76 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
77 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
78 if (!new_bo_infos)
79 return TU_BO_LIST_FAILED;
80 list->bo_infos = new_bo_infos;
81 list->capacity = new_capacity;
82 }
83
84 list->bo_infos[list->count] = *bo_info;
85 return list->count++;
86 }
87
88 uint32_t
89 tu_bo_list_add(struct tu_bo_list *list,
90 const struct tu_bo *bo,
91 uint32_t flags)
92 {
93 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
94 .flags = flags,
95 .handle = bo->gem_handle,
96 .presumed = bo->iova,
97 });
98 }
99
100 VkResult
101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
102 {
103 for (uint32_t i = 0; i < other->count; i++) {
104 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
105 return VK_ERROR_OUT_OF_HOST_MEMORY;
106 }
107
108 return VK_SUCCESS;
109 }
110
111 static VkResult
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
113 const struct tu_device *dev)
114 {
115 const uint32_t gmem_size = dev->physical_device->gmem_size;
116 uint32_t offset = 0;
117
118 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
119 /* 16KB-aligned */
120 offset = align(offset, 0x4000);
121
122 tiling->gmem_offsets[i] = offset;
123 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
124 tiling->buffer_cpp[i];
125 }
126
127 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
128 }
129
130 static void
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
132 const struct tu_device *dev)
133 {
134 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
135 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
136 const uint32_t max_tile_width = 1024; /* A6xx */
137
138 tiling->tile0.offset = (VkOffset2D) {
139 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
140 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
141 };
142
143 const uint32_t ra_width =
144 tiling->render_area.extent.width +
145 (tiling->render_area.offset.x - tiling->tile0.offset.x);
146 const uint32_t ra_height =
147 tiling->render_area.extent.height +
148 (tiling->render_area.offset.y - tiling->tile0.offset.y);
149
150 /* start from 1 tile */
151 tiling->tile_count = (VkExtent2D) {
152 .width = 1,
153 .height = 1,
154 };
155 tiling->tile0.extent = (VkExtent2D) {
156 .width = align(ra_width, tile_align_w),
157 .height = align(ra_height, tile_align_h),
158 };
159
160 /* do not exceed max tile width */
161 while (tiling->tile0.extent.width > max_tile_width) {
162 tiling->tile_count.width++;
163 tiling->tile0.extent.width =
164 align(ra_width / tiling->tile_count.width, tile_align_w);
165 }
166
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
169 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
170 tiling->tile_count.width++;
171 tiling->tile0.extent.width =
172 align(ra_width / tiling->tile_count.width, tile_align_w);
173 } else {
174 tiling->tile_count.height++;
175 tiling->tile0.extent.height =
176 align(ra_height / tiling->tile_count.height, tile_align_h);
177 }
178 }
179 }
180
181 static void
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
183 const struct tu_device *dev)
184 {
185 const uint32_t max_pipe_count = 32; /* A6xx */
186
187 /* start from 1 tile per pipe */
188 tiling->pipe0 = (VkExtent2D) {
189 .width = 1,
190 .height = 1,
191 };
192 tiling->pipe_count = tiling->tile_count;
193
194 /* do not exceed max pipe count vertically */
195 while (tiling->pipe_count.height > max_pipe_count) {
196 tiling->pipe0.height += 2;
197 tiling->pipe_count.height =
198 (tiling->tile_count.height + tiling->pipe0.height - 1) /
199 tiling->pipe0.height;
200 }
201
202 /* do not exceed max pipe count */
203 while (tiling->pipe_count.width * tiling->pipe_count.height >
204 max_pipe_count) {
205 tiling->pipe0.width += 1;
206 tiling->pipe_count.width =
207 (tiling->tile_count.width + tiling->pipe0.width - 1) /
208 tiling->pipe0.width;
209 }
210 }
211
212 static void
213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
214 const struct tu_device *dev)
215 {
216 const uint32_t max_pipe_count = 32; /* A6xx */
217 const uint32_t used_pipe_count =
218 tiling->pipe_count.width * tiling->pipe_count.height;
219 const VkExtent2D last_pipe = {
220 .width = tiling->tile_count.width % tiling->pipe0.width,
221 .height = tiling->tile_count.height % tiling->pipe0.height,
222 };
223
224 assert(used_pipe_count <= max_pipe_count);
225 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
226
227 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
228 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
229 const uint32_t pipe_x = tiling->pipe0.width * x;
230 const uint32_t pipe_y = tiling->pipe0.height * y;
231 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
232 ? last_pipe.width
233 : tiling->pipe0.width;
234 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
235 ? last_pipe.height
236 : tiling->pipe0.height;
237 const uint32_t n = tiling->pipe_count.width * y + x;
238
239 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
243 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
244 }
245 }
246
247 memset(tiling->pipe_config + used_pipe_count, 0,
248 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
249 }
250
251 static void
252 tu_tiling_config_update(struct tu_tiling_config *tiling,
253 const struct tu_device *dev,
254 const uint32_t *buffer_cpp,
255 uint32_t buffer_count,
256 const VkRect2D *render_area)
257 {
258 /* see if there is any real change */
259 const bool ra_changed =
260 render_area &&
261 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
262 const bool buf_changed = tiling->buffer_count != buffer_count ||
263 memcmp(tiling->buffer_cpp, buffer_cpp,
264 sizeof(*buffer_cpp) * buffer_count);
265 if (!ra_changed && !buf_changed)
266 return;
267
268 if (ra_changed)
269 tiling->render_area = *render_area;
270
271 if (buf_changed) {
272 memcpy(tiling->buffer_cpp, buffer_cpp,
273 sizeof(*buffer_cpp) * buffer_count);
274 tiling->buffer_count = buffer_count;
275 }
276
277 tu_tiling_config_update_tile_layout(tiling, dev);
278 tu_tiling_config_update_pipe_layout(tiling, dev);
279 tu_tiling_config_update_pipes(tiling, dev);
280 }
281
282 static void
283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
284 const struct tu_device *dev,
285 uint32_t tx,
286 uint32_t ty,
287 struct tu_tile *tile)
288 {
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px = tx / tiling->pipe0.width;
291 const uint32_t py = ty / tiling->pipe0.height;
292 const uint32_t sx = tx - tiling->pipe0.width * px;
293 const uint32_t sy = ty - tiling->pipe0.height * py;
294
295 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
296 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
297 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
298
299 /* convert to 1D indices */
300 tile->pipe = tiling->pipe_count.width * py + px;
301 tile->slot = tiling->pipe0.width * sy + sx;
302
303 /* get the blit area for the tile */
304 tile->begin = (VkOffset2D) {
305 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
306 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
307 };
308 tile->end.x =
309 (tx == tiling->tile_count.width - 1)
310 ? tiling->render_area.offset.x + tiling->render_area.extent.width
311 : tile->begin.x + tiling->tile0.extent.width;
312 tile->end.y =
313 (ty == tiling->tile_count.height - 1)
314 ? tiling->render_area.offset.y + tiling->render_area.extent.height
315 : tile->begin.y + tiling->tile0.extent.height;
316 }
317
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples)
320 {
321 switch (samples) {
322 case 1:
323 return MSAA_ONE;
324 case 2:
325 return MSAA_TWO;
326 case 4:
327 return MSAA_FOUR;
328 case 8:
329 return MSAA_EIGHT;
330 default:
331 assert(!"invalid sample count");
332 return MSAA_ONE;
333 }
334 }
335
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type)
338 {
339 switch (type) {
340 case VK_INDEX_TYPE_UINT16:
341 return INDEX4_SIZE_16_BIT;
342 case VK_INDEX_TYPE_UINT32:
343 return INDEX4_SIZE_32_BIT;
344 default:
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT;
347 }
348 }
349
350 static void
351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
354 }
355
356 void
357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
358 struct tu_cs *cs,
359 enum vgt_event_type event,
360 bool need_seqno)
361 {
362 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
363 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
364 if (need_seqno) {
365 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
366 tu_cs_emit(cs, ++cmd->scratch_seqno);
367 }
368 }
369
370 static void
371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
372 {
373 tu6_emit_event_write(cmd, cs, 0x31, false);
374 }
375
376 static void
377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
378 {
379 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
380 }
381
382 static void
383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
384 {
385 if (cmd->wait_for_idle) {
386 tu_cs_emit_wfi(cs);
387 cmd->wait_for_idle = false;
388 }
389 }
390
391 static void
392 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
393 {
394 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
395 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
396 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
397 if (iview->image->ubwc_size) {
398 tu_cs_emit_qw(cs, va);
399 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
401 } else {
402 tu_cs_emit_qw(cs, 0);
403 tu_cs_emit(cs, 0);
404 }
405 }
406
407 static void
408 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
409 {
410 const struct tu_framebuffer *fb = cmd->state.framebuffer;
411 const struct tu_subpass *subpass = cmd->state.subpass;
412 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
413
414 const uint32_t a = subpass->depth_stencil_attachment.attachment;
415 if (a == VK_ATTACHMENT_UNUSED) {
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
417 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
418 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
419 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
422 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
423
424 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
425 tu_cs_emit(cs,
426 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
429 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
430 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
431 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
432 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
433 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
436 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
437
438 return;
439 }
440
441 const struct tu_image_view *iview = fb->attachments[a].attachment;
442 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
443
444 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
445 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
446 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
447 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layer_size));
448 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
449 tu_cs_emit(cs, tiling->gmem_offsets[subpass->color_count]);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
452 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
453
454 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
455 tu6_emit_flag_buffer(cs, iview);
456
457 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
458 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
459 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
460 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
461 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
462 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
465 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
466
467 /* enable zs? */
468 }
469
470 static void
471 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
472 {
473 const struct tu_framebuffer *fb = cmd->state.framebuffer;
474 const struct tu_subpass *subpass = cmd->state.subpass;
475 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
476 unsigned char mrt_comp[MAX_RTS] = { 0 };
477 unsigned srgb_cntl = 0;
478
479 for (uint32_t i = 0; i < subpass->color_count; ++i) {
480 uint32_t a = subpass->color_attachments[i].attachment;
481 if (a == VK_ATTACHMENT_UNUSED)
482 continue;
483
484 const struct tu_image_view *iview = fb->attachments[a].attachment;
485 const enum a6xx_tile_mode tile_mode =
486 tu6_get_image_tile_mode(iview->image, iview->base_mip);
487
488 mrt_comp[i] = 0xf;
489
490 if (vk_format_is_srgb(iview->vk_format))
491 srgb_cntl |= (1 << i);
492
493 const struct tu_native_format *format =
494 tu6_get_native_format(iview->vk_format);
495 assert(format && format->rb >= 0);
496
497 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
498 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
499 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
500 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
501 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
502 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layer_size));
503 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
504 tu_cs_emit(
505 cs, tiling->gmem_offsets[i]); /* RB_MRT[i].BASE_GMEM */
506
507 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
508 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
509 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
510 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
511
512 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
513 tu6_emit_flag_buffer(cs, iview);
514 }
515
516 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
517 tu_cs_emit(cs, srgb_cntl);
518
519 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
520 tu_cs_emit(cs, srgb_cntl);
521
522 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
523 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
524 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
525 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
526 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
527 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
528 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
529 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
530 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
533 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
534 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
535 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
536 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
537 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
538 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
539 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
540 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
541 }
542
543 static void
544 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
545 {
546 const struct tu_subpass *subpass = cmd->state.subpass;
547 const enum a3xx_msaa_samples samples =
548 tu_msaa_samples(subpass->max_sample_count);
549
550 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
551 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
552 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
553 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
556 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
557 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
558 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
559
560 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
561 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
562 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
563 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
564
565 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
566 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
567 }
568
569 static void
570 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
571 {
572 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
573 const uint32_t bin_w = tiling->tile0.extent.width;
574 const uint32_t bin_h = tiling->tile0.extent.height;
575
576 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
577 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
578 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
579
580 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
581 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
582 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
583
584 /* no flag for RB_BIN_CONTROL2... */
585 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
586 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
587 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
588 }
589
590 static void
591 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
592 struct tu_cs *cs,
593 bool binning)
594 {
595 uint32_t cntl = 0;
596 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
597 if (binning)
598 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
599
600 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
601 tu_cs_emit(cs, 0x2);
602 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
603 tu_cs_emit(cs, cntl);
604 }
605
606 static void
607 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
608 {
609 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
610 const uint32_t x1 = render_area->offset.x;
611 const uint32_t y1 = render_area->offset.y;
612 const uint32_t x2 = x1 + render_area->extent.width - 1;
613 const uint32_t y2 = y1 + render_area->extent.height - 1;
614
615 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
616 tu_cs_emit(cs,
617 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
618 tu_cs_emit(cs,
619 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
620 }
621
622 static void
623 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
624 struct tu_cs *cs,
625 const struct tu_image_view *iview,
626 uint32_t gmem_offset,
627 uint32_t blit_info)
628 {
629 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
630 tu_cs_emit(cs, blit_info);
631
632 const struct tu_native_format *format =
633 tu6_get_native_format(iview->vk_format);
634 assert(format && format->rb >= 0);
635
636 enum a6xx_tile_mode tile_mode =
637 tu6_get_image_tile_mode(iview->image, iview->base_mip);
638 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
639 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
640 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
641 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
642 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
643 COND(iview->image->ubwc_size, A6XX_RB_BLIT_DST_INFO_FLAGS));
644 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
645 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
646 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layer_size));
647
648 if (iview->image->ubwc_size) {
649 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
650 tu6_emit_flag_buffer(cs, iview);
651 }
652
653 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
654 tu_cs_emit(cs, gmem_offset);
655 }
656
657 static void
658 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
659 struct tu_cs *cs,
660 const struct tu_image_view *iview,
661 uint32_t gmem_offset,
662 const VkClearValue *clear_value)
663 {
664 const struct tu_native_format *format =
665 tu6_get_native_format(iview->vk_format);
666 assert(format && format->rb >= 0);
667 /* must be WZYX; other values are ignored */
668 const enum a3xx_color_swap swap = WZYX;
669
670 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
671 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
672 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
673 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
674 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
675
676 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
677 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
678
679 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
680 tu_cs_emit(cs, gmem_offset);
681
682 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
683 tu_cs_emit(cs, 0);
684
685 /* pack clear_value into WZYX order */
686 uint32_t clear_vals[4] = { 0 };
687 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
688
689 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
690 tu_cs_emit(cs, clear_vals[0]);
691 tu_cs_emit(cs, clear_vals[1]);
692 tu_cs_emit(cs, clear_vals[2]);
693 tu_cs_emit(cs, clear_vals[3]);
694 }
695
696 static void
697 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
698 {
699 tu6_emit_marker(cmd, cs);
700 tu6_emit_event_write(cmd, cs, BLIT, false);
701 tu6_emit_marker(cmd, cs);
702 }
703
704 static void
705 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
706 struct tu_cs *cs,
707 uint32_t x1,
708 uint32_t y1,
709 uint32_t x2,
710 uint32_t y2)
711 {
712 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
713 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
714 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
715 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
716 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
717
718 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
719 tu_cs_emit(
720 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
721 tu_cs_emit(
722 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
723 }
724
725 static void
726 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
727 struct tu_cs *cs,
728 uint32_t x1,
729 uint32_t y1)
730 {
731 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
732 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
733
734 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
735 tu_cs_emit(cs,
736 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
737
738 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
739 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
740
741 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
742 tu_cs_emit(
743 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
744 }
745
746 static void
747 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
748 struct tu_cs *cs,
749 const struct tu_tile *tile)
750 {
751 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
752 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
753
754 tu6_emit_marker(cmd, cs);
755 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
756 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
757 tu6_emit_marker(cmd, cs);
758
759 const uint32_t x1 = tile->begin.x;
760 const uint32_t y1 = tile->begin.y;
761 const uint32_t x2 = tile->end.x - 1;
762 const uint32_t y2 = tile->end.y - 1;
763 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
764 tu6_emit_window_offset(cmd, cs, x1, y1);
765
766 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
767 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
768
769 if (false) {
770 /* hw binning? */
771 } else {
772 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
773 tu_cs_emit(cs, 0x1);
774
775 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
776 tu_cs_emit(cs, 0x0);
777 }
778 }
779
780 static void
781 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
782 struct tu_cs *cs,
783 uint32_t a,
784 uint32_t gmem_index)
785 {
786 const struct tu_framebuffer *fb = cmd->state.framebuffer;
787 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
788 const struct tu_attachment_state *attachments = cmd->state.attachments;
789
790 const struct tu_image_view *iview = fb->attachments[a].attachment;
791 const struct tu_attachment_state *att = attachments + a;
792 if (att->pending_clear_aspects) {
793 tu6_emit_blit_clear(cmd, cs, iview,
794 tiling->gmem_offsets[gmem_index],
795 &att->clear_value);
796 } else {
797 tu6_emit_blit_info(cmd, cs, iview,
798 tiling->gmem_offsets[gmem_index],
799 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
800 }
801
802 tu6_emit_blit(cmd, cs);
803 }
804
805 static void
806 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
807 {
808 const struct tu_subpass *subpass = cmd->state.subpass;
809
810 tu6_emit_blit_scissor(cmd, cs);
811
812 for (uint32_t i = 0; i < subpass->color_count; ++i) {
813 const uint32_t a = subpass->color_attachments[i].attachment;
814 if (a != VK_ATTACHMENT_UNUSED)
815 tu6_emit_tile_load_attachment(cmd, cs, a, i);
816 }
817
818 const uint32_t a = subpass->depth_stencil_attachment.attachment;
819 if (a != VK_ATTACHMENT_UNUSED)
820 tu6_emit_tile_load_attachment(cmd, cs, a, subpass->color_count);
821 }
822
823 static void
824 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
825 {
826 const struct tu_framebuffer *fb = cmd->state.framebuffer;
827 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
828
829 if (false) {
830 /* hw binning? */
831 }
832
833 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
834 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
835 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
836 CP_SET_DRAW_STATE__0_GROUP_ID(0));
837 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
838 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
839
840 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
841 tu_cs_emit(cs, 0x0);
842
843 tu6_emit_marker(cmd, cs);
844 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
845 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
846 tu6_emit_marker(cmd, cs);
847
848 tu6_emit_blit_scissor(cmd, cs);
849
850 for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
851 uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
852 if (a == VK_ATTACHMENT_UNUSED)
853 continue;
854
855 const struct tu_image_view *iview = fb->attachments[a].attachment;
856 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[i], 0);
857 tu6_emit_blit(cmd, cs);
858 }
859
860 const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
861 if (a != VK_ATTACHMENT_UNUSED) {
862 const struct tu_image_view *iview = fb->attachments[a].attachment;
863 tu6_emit_blit_info(cmd, cs, iview,
864 tiling->gmem_offsets[cmd->state.subpass->color_count],
865 0);
866 tu6_emit_blit(cmd, cs);
867 }
868 }
869
870 static void
871 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
872 {
873 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
874 tu_cs_emit(cs, restart_index);
875 }
876
877 static void
878 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
879 {
880 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
881 if (result != VK_SUCCESS) {
882 cmd->record_result = result;
883 return;
884 }
885
886 tu6_emit_cache_flush(cmd, cs);
887
888 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
889
890 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
891 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
892 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
893 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
894 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
895 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
896 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
897 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
898 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
899
900 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
901 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
902 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
903 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
904 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
905 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
906 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
907 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
908 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
909 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
910 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
911 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
912 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
913 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
914
915 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
916
917 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
919 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
920
921 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
922 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
923 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
924 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
926 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
928 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
933
934 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
935 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
936
937 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
938 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
939
940 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
941 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
942
943 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
944 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
945 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
946
947 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
948 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
949
950 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
951
952 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
953
954 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
955 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
956 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
957 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
958 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
959 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
960 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
961 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
962 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
963 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
964 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
965 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
966 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
972 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
974 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
975
976 tu6_emit_marker(cmd, cs);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
979
980 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
981
982 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
983
984 /* we don't use this yet.. probably best to disable.. */
985 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
986 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
987 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
988 CP_SET_DRAW_STATE__0_GROUP_ID(0));
989 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
990 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
991
992 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
993 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
994 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
995 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
996
997 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
998 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
999 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1002 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1003
1004 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1005 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1008 tu_cs_emit(cs, 0x00000000);
1009 tu_cs_emit(cs, 0x00000000);
1010 tu_cs_emit(cs, 0x00000000);
1011
1012 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1013 tu_cs_emit(cs, 0x00000000);
1014 tu_cs_emit(cs, 0x00000000);
1015 tu_cs_emit(cs, 0x00000000);
1016 tu_cs_emit(cs, 0x00000000);
1017 tu_cs_emit(cs, 0x00000000);
1018 tu_cs_emit(cs, 0x00000000);
1019
1020 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1021 tu_cs_emit(cs, 0x00000000);
1022 tu_cs_emit(cs, 0x00000000);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025 tu_cs_emit(cs, 0x00000000);
1026 tu_cs_emit(cs, 0x00000000);
1027
1028 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1029 tu_cs_emit(cs, 0x00000000);
1030 tu_cs_emit(cs, 0x00000000);
1031 tu_cs_emit(cs, 0x00000000);
1032
1033 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1034 tu_cs_emit(cs, 0x00000000);
1035
1036 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1037 tu_cs_emit(cs, 0x00000000);
1038
1039 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1040 tu_cs_emit(cs, 0x00000000);
1041
1042 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1043 tu_cs_emit(cs, 0x00000000);
1044
1045 tu_cs_sanity_check(cs);
1046 }
1047
1048 static void
1049 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1050 {
1051 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1052 if (result != VK_SUCCESS) {
1053 cmd->record_result = result;
1054 return;
1055 }
1056
1057 tu6_emit_lrz_flush(cmd, cs);
1058
1059 /* lrz clear? */
1060
1061 tu6_emit_cache_flush(cmd, cs);
1062
1063 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1064 tu_cs_emit(cs, 0x0);
1065
1066 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1067 tu6_emit_wfi(cmd, cs);
1068 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1069 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1070
1071 tu6_emit_zs(cmd, cs);
1072 tu6_emit_mrt(cmd, cs);
1073 tu6_emit_msaa(cmd, cs);
1074
1075 if (false) {
1076 /* hw binning? */
1077 } else {
1078 tu6_emit_bin_size(cmd, cs, 0x6000000);
1079 /* no draws */
1080 }
1081
1082 tu6_emit_render_cntl(cmd, cs, false);
1083
1084 tu_cs_sanity_check(cs);
1085 }
1086
1087 static void
1088 tu6_render_tile(struct tu_cmd_buffer *cmd,
1089 struct tu_cs *cs,
1090 const struct tu_tile *tile)
1091 {
1092 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1093 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1094 if (result != VK_SUCCESS) {
1095 cmd->record_result = result;
1096 return;
1097 }
1098
1099 tu6_emit_tile_select(cmd, cs, tile);
1100 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1101
1102 tu_cs_emit_call(cs, &cmd->draw_cs);
1103 cmd->wait_for_idle = true;
1104
1105 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1106
1107 tu_cs_sanity_check(cs);
1108 }
1109
1110 static void
1111 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1112 {
1113 const struct tu_subpass *subpass = cmd->state.subpass;
1114 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1115
1116 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1117 if (result != VK_SUCCESS) {
1118 cmd->record_result = result;
1119 return;
1120 }
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1123 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1124
1125 tu6_emit_lrz_flush(cmd, cs);
1126
1127 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1128
1129 if (subpass->has_resolve) {
1130 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1131 struct tu_subpass_attachment src_att = subpass->color_attachments[i];
1132 struct tu_subpass_attachment dst_att = subpass->resolve_attachments[i];
1133
1134 if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
1135 continue;
1136
1137 struct tu_image *src_img = fb->attachments[src_att.attachment].attachment->image;
1138 struct tu_image *dst_img = fb->attachments[dst_att.attachment].attachment->image;
1139
1140 assert(src_img->extent.width == dst_img->extent.width);
1141 assert(src_img->extent.height == dst_img->extent.height);
1142
1143 tu_bo_list_add(&cmd->bo_list, src_img->bo, MSM_SUBMIT_BO_READ);
1144 tu_bo_list_add(&cmd->bo_list, dst_img->bo, MSM_SUBMIT_BO_WRITE);
1145
1146 tu_blit(cmd, &(struct tu_blit) {
1147 .dst = tu_blit_surf_whole(dst_img, 0, 0),
1148 .src = tu_blit_surf_whole(src_img, 0, 0),
1149 .layers = 1,
1150 });
1151 }
1152 }
1153
1154 tu_cs_sanity_check(cs);
1155 }
1156
1157 static void
1158 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1159 {
1160 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1161
1162 tu6_render_begin(cmd, &cmd->cs);
1163
1164 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1165 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1166 struct tu_tile tile;
1167 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1168 tu6_render_tile(cmd, &cmd->cs, &tile);
1169 }
1170 }
1171
1172 tu6_render_end(cmd, &cmd->cs);
1173 }
1174
1175 static void
1176 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1177 {
1178 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1179 const struct tu_subpass *subpass = cmd->state.subpass;
1180 struct tu_attachment_state *attachments = cmd->state.attachments;
1181 struct tu_cs sub_cs;
1182
1183 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1184 tile_load_space, &sub_cs);
1185 if (result != VK_SUCCESS) {
1186 cmd->record_result = result;
1187 return;
1188 }
1189
1190 /* emit to tile-load sub_cs */
1191 tu6_emit_tile_load(cmd, &sub_cs);
1192
1193 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1194
1195 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1196 const uint32_t a = subpass->color_attachments[i].attachment;
1197 if (a != VK_ATTACHMENT_UNUSED)
1198 attachments[a].pending_clear_aspects = 0;
1199 }
1200 }
1201
1202 static void
1203 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1204 {
1205 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1206 struct tu_cs sub_cs;
1207
1208 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1209 tile_store_space, &sub_cs);
1210 if (result != VK_SUCCESS) {
1211 cmd->record_result = result;
1212 return;
1213 }
1214
1215 /* emit to tile-store sub_cs */
1216 tu6_emit_tile_store(cmd, &sub_cs);
1217
1218 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1219 }
1220
1221 static void
1222 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1223 const VkRect2D *render_area)
1224 {
1225 const struct tu_device *dev = cmd->device;
1226 const struct tu_render_pass *pass = cmd->state.pass;
1227 const struct tu_subpass *subpass = cmd->state.subpass;
1228 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1229
1230 uint32_t buffer_cpp[MAX_RTS + 2];
1231 uint32_t buffer_count = 0;
1232
1233 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1234 const uint32_t a = subpass->color_attachments[i].attachment;
1235 if (a == VK_ATTACHMENT_UNUSED) {
1236 buffer_cpp[buffer_count++] = 0;
1237 continue;
1238 }
1239
1240 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1241 buffer_cpp[buffer_count++] =
1242 vk_format_get_blocksize(att->format) * att->samples;
1243 }
1244
1245 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1246 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1247 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1248
1249 /* TODO */
1250 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1251
1252 buffer_cpp[buffer_count++] =
1253 vk_format_get_blocksize(att->format) * att->samples;
1254 }
1255
1256 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1257 render_area);
1258 }
1259
1260 const struct tu_dynamic_state default_dynamic_state = {
1261 .viewport =
1262 {
1263 .count = 0,
1264 },
1265 .scissor =
1266 {
1267 .count = 0,
1268 },
1269 .line_width = 1.0f,
1270 .depth_bias =
1271 {
1272 .bias = 0.0f,
1273 .clamp = 0.0f,
1274 .slope = 0.0f,
1275 },
1276 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1277 .depth_bounds =
1278 {
1279 .min = 0.0f,
1280 .max = 1.0f,
1281 },
1282 .stencil_compare_mask =
1283 {
1284 .front = ~0u,
1285 .back = ~0u,
1286 },
1287 .stencil_write_mask =
1288 {
1289 .front = ~0u,
1290 .back = ~0u,
1291 },
1292 .stencil_reference =
1293 {
1294 .front = 0u,
1295 .back = 0u,
1296 },
1297 };
1298
1299 static void UNUSED /* FINISHME */
1300 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1301 const struct tu_dynamic_state *src)
1302 {
1303 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1304 uint32_t copy_mask = src->mask;
1305 uint32_t dest_mask = 0;
1306
1307 tu_use_args(cmd_buffer); /* FINISHME */
1308
1309 /* Make sure to copy the number of viewports/scissors because they can
1310 * only be specified at pipeline creation time.
1311 */
1312 dest->viewport.count = src->viewport.count;
1313 dest->scissor.count = src->scissor.count;
1314 dest->discard_rectangle.count = src->discard_rectangle.count;
1315
1316 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1317 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1318 src->viewport.count * sizeof(VkViewport))) {
1319 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1320 src->viewport.count);
1321 dest_mask |= TU_DYNAMIC_VIEWPORT;
1322 }
1323 }
1324
1325 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1326 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1327 src->scissor.count * sizeof(VkRect2D))) {
1328 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1329 src->scissor.count);
1330 dest_mask |= TU_DYNAMIC_SCISSOR;
1331 }
1332 }
1333
1334 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1335 if (dest->line_width != src->line_width) {
1336 dest->line_width = src->line_width;
1337 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1338 }
1339 }
1340
1341 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1342 if (memcmp(&dest->depth_bias, &src->depth_bias,
1343 sizeof(src->depth_bias))) {
1344 dest->depth_bias = src->depth_bias;
1345 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1346 }
1347 }
1348
1349 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1350 if (memcmp(&dest->blend_constants, &src->blend_constants,
1351 sizeof(src->blend_constants))) {
1352 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1353 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1354 }
1355 }
1356
1357 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1358 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1359 sizeof(src->depth_bounds))) {
1360 dest->depth_bounds = src->depth_bounds;
1361 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1362 }
1363 }
1364
1365 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1366 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1367 sizeof(src->stencil_compare_mask))) {
1368 dest->stencil_compare_mask = src->stencil_compare_mask;
1369 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1370 }
1371 }
1372
1373 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1374 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1375 sizeof(src->stencil_write_mask))) {
1376 dest->stencil_write_mask = src->stencil_write_mask;
1377 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1378 }
1379 }
1380
1381 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1382 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1383 sizeof(src->stencil_reference))) {
1384 dest->stencil_reference = src->stencil_reference;
1385 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1386 }
1387 }
1388
1389 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1390 if (memcmp(&dest->discard_rectangle.rectangles,
1391 &src->discard_rectangle.rectangles,
1392 src->discard_rectangle.count * sizeof(VkRect2D))) {
1393 typed_memcpy(dest->discard_rectangle.rectangles,
1394 src->discard_rectangle.rectangles,
1395 src->discard_rectangle.count);
1396 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1397 }
1398 }
1399 }
1400
1401 static VkResult
1402 tu_create_cmd_buffer(struct tu_device *device,
1403 struct tu_cmd_pool *pool,
1404 VkCommandBufferLevel level,
1405 VkCommandBuffer *pCommandBuffer)
1406 {
1407 struct tu_cmd_buffer *cmd_buffer;
1408 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1409 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1410 if (cmd_buffer == NULL)
1411 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1412
1413 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1414 cmd_buffer->device = device;
1415 cmd_buffer->pool = pool;
1416 cmd_buffer->level = level;
1417
1418 if (pool) {
1419 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1420 cmd_buffer->queue_family_index = pool->queue_family_index;
1421
1422 } else {
1423 /* Init the pool_link so we can safely call list_del when we destroy
1424 * the command buffer
1425 */
1426 list_inithead(&cmd_buffer->pool_link);
1427 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1428 }
1429
1430 tu_bo_list_init(&cmd_buffer->bo_list);
1431 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1432 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1433 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1434 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1435
1436 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1437
1438 list_inithead(&cmd_buffer->upload.list);
1439
1440 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1441 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1442
1443 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1444 if (result != VK_SUCCESS)
1445 return result;
1446
1447 return VK_SUCCESS;
1448 }
1449
1450 static void
1451 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1452 {
1453 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1454
1455 list_del(&cmd_buffer->pool_link);
1456
1457 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1458 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1459
1460 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1461 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1462 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1463 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1464
1465 tu_bo_list_destroy(&cmd_buffer->bo_list);
1466 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1467 }
1468
1469 static VkResult
1470 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1471 {
1472 cmd_buffer->wait_for_idle = true;
1473
1474 cmd_buffer->record_result = VK_SUCCESS;
1475
1476 tu_bo_list_reset(&cmd_buffer->bo_list);
1477 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1478 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1479 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1480 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1481
1482 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1483 cmd_buffer->descriptors[i].dirty = 0;
1484 cmd_buffer->descriptors[i].valid = 0;
1485 cmd_buffer->descriptors[i].push_dirty = false;
1486 }
1487
1488 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1489
1490 return cmd_buffer->record_result;
1491 }
1492
1493 static VkResult
1494 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1495 const VkRenderPassBeginInfo *info)
1496 {
1497 struct tu_cmd_state *state = &cmd_buffer->state;
1498 const struct tu_framebuffer *fb = state->framebuffer;
1499 const struct tu_render_pass *pass = state->pass;
1500
1501 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1502 const struct tu_image_view *iview = fb->attachments[i].attachment;
1503 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1504 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1505 }
1506
1507 if (pass->attachment_count == 0) {
1508 state->attachments = NULL;
1509 return VK_SUCCESS;
1510 }
1511
1512 state->attachments =
1513 vk_alloc(&cmd_buffer->pool->alloc,
1514 pass->attachment_count * sizeof(state->attachments[0]), 8,
1515 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1516 if (state->attachments == NULL) {
1517 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1518 return cmd_buffer->record_result;
1519 }
1520
1521 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1522 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1523 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1524 VkImageAspectFlags clear_aspects = 0;
1525
1526 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1527 /* color attachment */
1528 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1529 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1530 }
1531 } else {
1532 /* depthstencil attachment */
1533 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1534 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1535 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1536 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1537 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1538 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1539 }
1540 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1541 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1542 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1543 }
1544 }
1545
1546 state->attachments[i].pending_clear_aspects = clear_aspects;
1547 state->attachments[i].cleared_views = 0;
1548 if (clear_aspects && info) {
1549 assert(info->clearValueCount > i);
1550 state->attachments[i].clear_value = info->pClearValues[i];
1551 }
1552
1553 state->attachments[i].current_layout = att->initial_layout;
1554 }
1555
1556 return VK_SUCCESS;
1557 }
1558
1559 VkResult
1560 tu_AllocateCommandBuffers(VkDevice _device,
1561 const VkCommandBufferAllocateInfo *pAllocateInfo,
1562 VkCommandBuffer *pCommandBuffers)
1563 {
1564 TU_FROM_HANDLE(tu_device, device, _device);
1565 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1566
1567 VkResult result = VK_SUCCESS;
1568 uint32_t i;
1569
1570 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1571
1572 if (!list_is_empty(&pool->free_cmd_buffers)) {
1573 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1574 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1575
1576 list_del(&cmd_buffer->pool_link);
1577 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1578
1579 result = tu_reset_cmd_buffer(cmd_buffer);
1580 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1581 cmd_buffer->level = pAllocateInfo->level;
1582
1583 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1584 } else {
1585 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1586 &pCommandBuffers[i]);
1587 }
1588 if (result != VK_SUCCESS)
1589 break;
1590 }
1591
1592 if (result != VK_SUCCESS) {
1593 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1594 pCommandBuffers);
1595
1596 /* From the Vulkan 1.0.66 spec:
1597 *
1598 * "vkAllocateCommandBuffers can be used to create multiple
1599 * command buffers. If the creation of any of those command
1600 * buffers fails, the implementation must destroy all
1601 * successfully created command buffer objects from this
1602 * command, set all entries of the pCommandBuffers array to
1603 * NULL and return the error."
1604 */
1605 memset(pCommandBuffers, 0,
1606 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1607 }
1608
1609 return result;
1610 }
1611
1612 void
1613 tu_FreeCommandBuffers(VkDevice device,
1614 VkCommandPool commandPool,
1615 uint32_t commandBufferCount,
1616 const VkCommandBuffer *pCommandBuffers)
1617 {
1618 for (uint32_t i = 0; i < commandBufferCount; i++) {
1619 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1620
1621 if (cmd_buffer) {
1622 if (cmd_buffer->pool) {
1623 list_del(&cmd_buffer->pool_link);
1624 list_addtail(&cmd_buffer->pool_link,
1625 &cmd_buffer->pool->free_cmd_buffers);
1626 } else
1627 tu_cmd_buffer_destroy(cmd_buffer);
1628 }
1629 }
1630 }
1631
1632 VkResult
1633 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1634 VkCommandBufferResetFlags flags)
1635 {
1636 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1637 return tu_reset_cmd_buffer(cmd_buffer);
1638 }
1639
1640 VkResult
1641 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1642 const VkCommandBufferBeginInfo *pBeginInfo)
1643 {
1644 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1645 VkResult result = VK_SUCCESS;
1646
1647 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1648 /* If the command buffer has already been resetted with
1649 * vkResetCommandBuffer, no need to do it again.
1650 */
1651 result = tu_reset_cmd_buffer(cmd_buffer);
1652 if (result != VK_SUCCESS)
1653 return result;
1654 }
1655
1656 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1657 cmd_buffer->usage_flags = pBeginInfo->flags;
1658
1659 tu_cs_begin(&cmd_buffer->cs);
1660
1661 cmd_buffer->marker_seqno = 0;
1662 cmd_buffer->scratch_seqno = 0;
1663
1664 /* setup initial configuration into command buffer */
1665 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1666 switch (cmd_buffer->queue_family_index) {
1667 case TU_QUEUE_GENERAL:
1668 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1669 break;
1670 default:
1671 break;
1672 }
1673 }
1674
1675 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1676
1677 return VK_SUCCESS;
1678 }
1679
1680 void
1681 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1682 uint32_t firstBinding,
1683 uint32_t bindingCount,
1684 const VkBuffer *pBuffers,
1685 const VkDeviceSize *pOffsets)
1686 {
1687 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1688
1689 assert(firstBinding + bindingCount <= MAX_VBS);
1690
1691 for (uint32_t i = 0; i < bindingCount; i++) {
1692 cmd->state.vb.buffers[firstBinding + i] =
1693 tu_buffer_from_handle(pBuffers[i]);
1694 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1695 }
1696
1697 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1698 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1699 }
1700
1701 void
1702 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1703 VkBuffer buffer,
1704 VkDeviceSize offset,
1705 VkIndexType indexType)
1706 {
1707 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1708 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1709
1710 /* initialize/update the restart index */
1711 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1712 struct tu_cs *draw_cs = &cmd->draw_cs;
1713 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1714 if (result != VK_SUCCESS) {
1715 cmd->record_result = result;
1716 return;
1717 }
1718
1719 tu6_emit_restart_index(
1720 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1721
1722 tu_cs_sanity_check(draw_cs);
1723 }
1724
1725 /* track the BO */
1726 if (cmd->state.index_buffer != buf)
1727 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1728
1729 cmd->state.index_buffer = buf;
1730 cmd->state.index_offset = offset;
1731 cmd->state.index_type = indexType;
1732 }
1733
1734 void
1735 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1736 VkPipelineBindPoint pipelineBindPoint,
1737 VkPipelineLayout _layout,
1738 uint32_t firstSet,
1739 uint32_t descriptorSetCount,
1740 const VkDescriptorSet *pDescriptorSets,
1741 uint32_t dynamicOffsetCount,
1742 const uint32_t *pDynamicOffsets)
1743 {
1744 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1745 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1746 unsigned dyn_idx = 0;
1747
1748 struct tu_descriptor_state *descriptors_state =
1749 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1750
1751 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1752 unsigned idx = i + firstSet;
1753 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1754
1755 descriptors_state->sets[idx] = set;
1756 descriptors_state->valid |= (1u << idx);
1757
1758 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1759 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1760 assert(dyn_idx < dynamicOffsetCount);
1761
1762 descriptors_state->dynamic_buffers[idx] =
1763 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1764 }
1765 }
1766
1767 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1768 }
1769
1770 void
1771 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1772 VkPipelineLayout layout,
1773 VkShaderStageFlags stageFlags,
1774 uint32_t offset,
1775 uint32_t size,
1776 const void *pValues)
1777 {
1778 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1779 memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1780 }
1781
1782 VkResult
1783 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1784 {
1785 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1786
1787 if (cmd_buffer->scratch_seqno) {
1788 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1789 MSM_SUBMIT_BO_WRITE);
1790 }
1791
1792 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1793 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1794 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1795 }
1796
1797 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1798 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1799 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1800 }
1801
1802 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1803 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1804 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1805 }
1806
1807 tu_cs_end(&cmd_buffer->cs);
1808
1809 assert(!cmd_buffer->state.attachments);
1810
1811 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1812
1813 return cmd_buffer->record_result;
1814 }
1815
1816 void
1817 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1818 VkPipelineBindPoint pipelineBindPoint,
1819 VkPipeline _pipeline)
1820 {
1821 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1822 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1823
1824 switch (pipelineBindPoint) {
1825 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1826 cmd->state.pipeline = pipeline;
1827 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1828 break;
1829 case VK_PIPELINE_BIND_POINT_COMPUTE:
1830 tu_finishme("binding compute pipeline");
1831 break;
1832 default:
1833 unreachable("unrecognized pipeline bind point");
1834 break;
1835 }
1836 }
1837
1838 void
1839 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1840 uint32_t firstViewport,
1841 uint32_t viewportCount,
1842 const VkViewport *pViewports)
1843 {
1844 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1845 struct tu_cs *draw_cs = &cmd->draw_cs;
1846
1847 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1848 if (result != VK_SUCCESS) {
1849 cmd->record_result = result;
1850 return;
1851 }
1852
1853 assert(firstViewport == 0 && viewportCount == 1);
1854 tu6_emit_viewport(draw_cs, pViewports);
1855
1856 tu_cs_sanity_check(draw_cs);
1857 }
1858
1859 void
1860 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1861 uint32_t firstScissor,
1862 uint32_t scissorCount,
1863 const VkRect2D *pScissors)
1864 {
1865 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1866 struct tu_cs *draw_cs = &cmd->draw_cs;
1867
1868 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1869 if (result != VK_SUCCESS) {
1870 cmd->record_result = result;
1871 return;
1872 }
1873
1874 assert(firstScissor == 0 && scissorCount == 1);
1875 tu6_emit_scissor(draw_cs, pScissors);
1876
1877 tu_cs_sanity_check(draw_cs);
1878 }
1879
1880 void
1881 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1882 {
1883 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1884
1885 cmd->state.dynamic.line_width = lineWidth;
1886
1887 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1888 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1889 }
1890
1891 void
1892 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1893 float depthBiasConstantFactor,
1894 float depthBiasClamp,
1895 float depthBiasSlopeFactor)
1896 {
1897 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1898 struct tu_cs *draw_cs = &cmd->draw_cs;
1899
1900 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1901 if (result != VK_SUCCESS) {
1902 cmd->record_result = result;
1903 return;
1904 }
1905
1906 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1907 depthBiasSlopeFactor);
1908
1909 tu_cs_sanity_check(draw_cs);
1910 }
1911
1912 void
1913 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1914 const float blendConstants[4])
1915 {
1916 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1917 struct tu_cs *draw_cs = &cmd->draw_cs;
1918
1919 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1920 if (result != VK_SUCCESS) {
1921 cmd->record_result = result;
1922 return;
1923 }
1924
1925 tu6_emit_blend_constants(draw_cs, blendConstants);
1926
1927 tu_cs_sanity_check(draw_cs);
1928 }
1929
1930 void
1931 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1932 float minDepthBounds,
1933 float maxDepthBounds)
1934 {
1935 }
1936
1937 void
1938 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1939 VkStencilFaceFlags faceMask,
1940 uint32_t compareMask)
1941 {
1942 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1943
1944 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1945 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1946 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1947 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1948
1949 /* the front/back compare masks must be updated together */
1950 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1951 }
1952
1953 void
1954 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1955 VkStencilFaceFlags faceMask,
1956 uint32_t writeMask)
1957 {
1958 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1959
1960 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1961 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1962 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1963 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1964
1965 /* the front/back write masks must be updated together */
1966 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1967 }
1968
1969 void
1970 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1971 VkStencilFaceFlags faceMask,
1972 uint32_t reference)
1973 {
1974 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1975
1976 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1977 cmd->state.dynamic.stencil_reference.front = reference;
1978 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1979 cmd->state.dynamic.stencil_reference.back = reference;
1980
1981 /* the front/back references must be updated together */
1982 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1983 }
1984
1985 void
1986 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1987 uint32_t commandBufferCount,
1988 const VkCommandBuffer *pCmdBuffers)
1989 {
1990 }
1991
1992 VkResult
1993 tu_CreateCommandPool(VkDevice _device,
1994 const VkCommandPoolCreateInfo *pCreateInfo,
1995 const VkAllocationCallbacks *pAllocator,
1996 VkCommandPool *pCmdPool)
1997 {
1998 TU_FROM_HANDLE(tu_device, device, _device);
1999 struct tu_cmd_pool *pool;
2000
2001 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2002 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2003 if (pool == NULL)
2004 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2005
2006 if (pAllocator)
2007 pool->alloc = *pAllocator;
2008 else
2009 pool->alloc = device->alloc;
2010
2011 list_inithead(&pool->cmd_buffers);
2012 list_inithead(&pool->free_cmd_buffers);
2013
2014 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2015
2016 *pCmdPool = tu_cmd_pool_to_handle(pool);
2017
2018 return VK_SUCCESS;
2019 }
2020
2021 void
2022 tu_DestroyCommandPool(VkDevice _device,
2023 VkCommandPool commandPool,
2024 const VkAllocationCallbacks *pAllocator)
2025 {
2026 TU_FROM_HANDLE(tu_device, device, _device);
2027 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2028
2029 if (!pool)
2030 return;
2031
2032 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2033 &pool->cmd_buffers, pool_link)
2034 {
2035 tu_cmd_buffer_destroy(cmd_buffer);
2036 }
2037
2038 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2039 &pool->free_cmd_buffers, pool_link)
2040 {
2041 tu_cmd_buffer_destroy(cmd_buffer);
2042 }
2043
2044 vk_free2(&device->alloc, pAllocator, pool);
2045 }
2046
2047 VkResult
2048 tu_ResetCommandPool(VkDevice device,
2049 VkCommandPool commandPool,
2050 VkCommandPoolResetFlags flags)
2051 {
2052 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2053 VkResult result;
2054
2055 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2056 pool_link)
2057 {
2058 result = tu_reset_cmd_buffer(cmd_buffer);
2059 if (result != VK_SUCCESS)
2060 return result;
2061 }
2062
2063 return VK_SUCCESS;
2064 }
2065
2066 void
2067 tu_TrimCommandPool(VkDevice device,
2068 VkCommandPool commandPool,
2069 VkCommandPoolTrimFlags flags)
2070 {
2071 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2072
2073 if (!pool)
2074 return;
2075
2076 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2077 &pool->free_cmd_buffers, pool_link)
2078 {
2079 tu_cmd_buffer_destroy(cmd_buffer);
2080 }
2081 }
2082
2083 void
2084 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2085 const VkRenderPassBeginInfo *pRenderPassBegin,
2086 VkSubpassContents contents)
2087 {
2088 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2089 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2090 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2091 VkResult result;
2092
2093 cmd_buffer->state.pass = pass;
2094 cmd_buffer->state.subpass = pass->subpasses;
2095 cmd_buffer->state.framebuffer = framebuffer;
2096
2097 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2098 if (result != VK_SUCCESS)
2099 return;
2100
2101 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2102 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2103 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2104
2105 /* draw_cs should contain entries only for this render pass */
2106 assert(!cmd_buffer->draw_cs.entry_count);
2107 tu_cs_begin(&cmd_buffer->draw_cs);
2108 }
2109
2110 void
2111 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2112 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2113 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2114 {
2115 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2116 pSubpassBeginInfo->contents);
2117 }
2118
2119 void
2120 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2121 {
2122 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2123
2124 tu_cmd_render_tiles(cmd);
2125
2126 cmd->state.subpass++;
2127
2128 tu_cmd_update_tiling_config(cmd, NULL);
2129 tu_cmd_prepare_tile_load_ib(cmd);
2130 tu_cmd_prepare_tile_store_ib(cmd);
2131 }
2132
2133 void
2134 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2135 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2136 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2137 {
2138 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2139 }
2140
2141 struct tu_draw_info
2142 {
2143 /**
2144 * Number of vertices.
2145 */
2146 uint32_t count;
2147
2148 /**
2149 * Index of the first vertex.
2150 */
2151 int32_t vertex_offset;
2152
2153 /**
2154 * First instance id.
2155 */
2156 uint32_t first_instance;
2157
2158 /**
2159 * Number of instances.
2160 */
2161 uint32_t instance_count;
2162
2163 /**
2164 * First index (indexed draws only).
2165 */
2166 uint32_t first_index;
2167
2168 /**
2169 * Whether it's an indexed draw.
2170 */
2171 bool indexed;
2172
2173 /**
2174 * Indirect draw parameters resource.
2175 */
2176 struct tu_buffer *indirect;
2177 uint64_t indirect_offset;
2178 uint32_t stride;
2179
2180 /**
2181 * Draw count parameters resource.
2182 */
2183 struct tu_buffer *count_buffer;
2184 uint64_t count_buffer_offset;
2185 };
2186
2187 enum tu_draw_state_group_id
2188 {
2189 TU_DRAW_STATE_PROGRAM,
2190 TU_DRAW_STATE_PROGRAM_BINNING,
2191 TU_DRAW_STATE_VI,
2192 TU_DRAW_STATE_VI_BINNING,
2193 TU_DRAW_STATE_VP,
2194 TU_DRAW_STATE_RAST,
2195 TU_DRAW_STATE_DS,
2196 TU_DRAW_STATE_BLEND,
2197 TU_DRAW_STATE_VS_CONST,
2198 TU_DRAW_STATE_FS_CONST,
2199 TU_DRAW_STATE_VS_TEX,
2200 TU_DRAW_STATE_FS_TEX,
2201
2202 TU_DRAW_STATE_COUNT,
2203 };
2204
2205 struct tu_draw_state_group
2206 {
2207 enum tu_draw_state_group_id id;
2208 uint32_t enable_mask;
2209 struct tu_cs_entry ib;
2210 };
2211
2212 static struct tu_sampler*
2213 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2214 const struct tu_descriptor_map *map, unsigned i)
2215 {
2216 assert(descriptors_state->valid & (1 << map->set[i]));
2217
2218 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2219 assert(map->binding[i] < set->layout->binding_count);
2220
2221 const struct tu_descriptor_set_binding_layout *layout =
2222 &set->layout->binding[map->binding[i]];
2223
2224 switch (layout->type) {
2225 case VK_DESCRIPTOR_TYPE_SAMPLER:
2226 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2227 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2228 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2229 default:
2230 unreachable("unimplemented descriptor type");
2231 break;
2232 }
2233 }
2234
2235 static uint32_t*
2236 texture_ptr(struct tu_descriptor_state *descriptors_state,
2237 const struct tu_descriptor_map *map, unsigned i)
2238 {
2239 assert(descriptors_state->valid & (1 << map->set[i]));
2240
2241 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2242 assert(map->binding[i] < set->layout->binding_count);
2243
2244 const struct tu_descriptor_set_binding_layout *layout =
2245 &set->layout->binding[map->binding[i]];
2246
2247 switch (layout->type) {
2248 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2249 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2250 return &set->mapped_ptr[layout->offset / 4];
2251 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2252 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2253 return &set->mapped_ptr[layout->offset / 4];
2254 default:
2255 unreachable("unimplemented descriptor type");
2256 break;
2257 }
2258 }
2259
2260 static uint64_t
2261 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2262 const struct tu_descriptor_map *map,
2263 unsigned i)
2264 {
2265 assert(descriptors_state->valid & (1 << map->set[i]));
2266
2267 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2268 assert(map->binding[i] < set->layout->binding_count);
2269
2270 const struct tu_descriptor_set_binding_layout *layout =
2271 &set->layout->binding[map->binding[i]];
2272
2273 switch (layout->type) {
2274 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2275 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2276 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2277 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2278 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2279 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2280 set->mapped_ptr[layout->offset / 4];
2281 default:
2282 unreachable("unimplemented descriptor type");
2283 break;
2284 }
2285 }
2286
2287 static inline uint32_t
2288 tu6_stage2opcode(gl_shader_stage type)
2289 {
2290 switch (type) {
2291 case MESA_SHADER_VERTEX:
2292 case MESA_SHADER_TESS_CTRL:
2293 case MESA_SHADER_TESS_EVAL:
2294 case MESA_SHADER_GEOMETRY:
2295 return CP_LOAD_STATE6_GEOM;
2296 case MESA_SHADER_FRAGMENT:
2297 case MESA_SHADER_COMPUTE:
2298 case MESA_SHADER_KERNEL:
2299 return CP_LOAD_STATE6_FRAG;
2300 default:
2301 unreachable("bad shader type");
2302 }
2303 }
2304
2305 static inline enum a6xx_state_block
2306 tu6_stage2shadersb(gl_shader_stage type)
2307 {
2308 switch (type) {
2309 case MESA_SHADER_VERTEX:
2310 return SB6_VS_SHADER;
2311 case MESA_SHADER_FRAGMENT:
2312 return SB6_FS_SHADER;
2313 case MESA_SHADER_COMPUTE:
2314 case MESA_SHADER_KERNEL:
2315 return SB6_CS_SHADER;
2316 default:
2317 unreachable("bad shader type");
2318 return ~0;
2319 }
2320 }
2321
2322 static void
2323 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2324 struct tu_descriptor_state *descriptors_state,
2325 gl_shader_stage type,
2326 uint32_t *push_constants)
2327 {
2328 const struct tu_program_descriptor_linkage *link =
2329 &pipeline->program.link[type];
2330 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2331
2332 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2333 if (state->range[i].start < state->range[i].end) {
2334 uint32_t size = state->range[i].end - state->range[i].start;
2335 uint32_t offset = state->range[i].start;
2336
2337 /* and even if the start of the const buffer is before
2338 * first_immediate, the end may not be:
2339 */
2340 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2341
2342 if (size == 0)
2343 continue;
2344
2345 /* things should be aligned to vec4: */
2346 debug_assert((state->range[i].offset % 16) == 0);
2347 debug_assert((size % 16) == 0);
2348 debug_assert((offset % 16) == 0);
2349
2350 if (i == 0) {
2351 /* push constants */
2352 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2353 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2354 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2355 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2356 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2357 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2358 tu_cs_emit(cs, 0);
2359 tu_cs_emit(cs, 0);
2360 for (unsigned i = 0; i < size / 4; i++)
2361 tu_cs_emit(cs, push_constants[i + offset / 4]);
2362 continue;
2363 }
2364
2365 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2366
2367 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2368 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2369 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2370 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2371 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2372 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2373 tu_cs_emit_qw(cs, va + offset);
2374 }
2375 }
2376 }
2377
2378 static void
2379 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2380 struct tu_descriptor_state *descriptors_state,
2381 gl_shader_stage type)
2382 {
2383 const struct tu_program_descriptor_linkage *link =
2384 &pipeline->program.link[type];
2385
2386 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2387 uint32_t anum = align(num, 2);
2388 uint32_t i;
2389
2390 if (!num)
2391 return;
2392
2393 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2394 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2395 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2396 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2397 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2398 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2399 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2400 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2401
2402 for (i = 0; i < num; i++)
2403 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2404
2405 for (; i < anum; i++) {
2406 tu_cs_emit(cs, 0xffffffff);
2407 tu_cs_emit(cs, 0xffffffff);
2408 }
2409 }
2410
2411 static struct tu_cs_entry
2412 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2413 const struct tu_pipeline *pipeline,
2414 struct tu_descriptor_state *descriptors_state,
2415 gl_shader_stage type)
2416 {
2417 struct tu_cs cs;
2418 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2419
2420 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2421 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2422
2423 return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2424 }
2425
2426 static struct tu_cs_entry
2427 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2428 const struct tu_pipeline *pipeline,
2429 struct tu_descriptor_state *descriptors_state,
2430 gl_shader_stage type, bool *needs_border)
2431 {
2432 const struct tu_program_descriptor_linkage *link =
2433 &pipeline->program.link[type];
2434
2435 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2436 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2437 if (!size)
2438 return (struct tu_cs_entry) {};
2439
2440 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2441 enum a6xx_state_block sb;
2442
2443 switch (type) {
2444 case MESA_SHADER_VERTEX:
2445 sb = SB6_VS_TEX;
2446 opcode = CP_LOAD_STATE6_GEOM;
2447 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2448 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2449 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2450 break;
2451 case MESA_SHADER_FRAGMENT:
2452 sb = SB6_FS_TEX;
2453 opcode = CP_LOAD_STATE6_FRAG;
2454 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2455 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2456 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2457 break;
2458 case MESA_SHADER_COMPUTE:
2459 sb = SB6_CS_TEX;
2460 opcode = CP_LOAD_STATE6_FRAG;
2461 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2462 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2463 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2464 break;
2465 default:
2466 unreachable("bad state block");
2467 }
2468
2469 struct tu_cs cs;
2470 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2471
2472 for (unsigned i = 0; i < link->texture_map.num; i++) {
2473 uint32_t *ptr = texture_ptr(descriptors_state, &link->texture_map, i);
2474
2475 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2476 tu_cs_emit(&cs, ptr[j]);
2477 }
2478
2479 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2480 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2481
2482 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2483 tu_cs_emit(&cs, sampler->state[j]);
2484
2485 *needs_border |= sampler->needs_border;
2486 }
2487
2488 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2489
2490 uint64_t tex_addr = entry.bo->iova + entry.offset;
2491 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2492
2493 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2494
2495 /* output sampler state: */
2496 tu_cs_emit_pkt7(&cs, opcode, 3);
2497 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2498 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2499 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2500 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2501 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2502 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2503
2504 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2505 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2506
2507 /* emit texture state: */
2508 tu_cs_emit_pkt7(&cs, opcode, 3);
2509 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2510 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2511 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2512 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2513 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2514 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2515
2516 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2517 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2518
2519 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2520 tu_cs_emit(&cs, link->texture_map.num);
2521
2522 return tu_cs_end_sub_stream(draw_state, &cs);
2523 }
2524
2525 static void
2526 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2527 struct tu_cs *cs)
2528 {
2529 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2530
2531 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2532 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2533 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2534 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2535 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2536
2537 struct tu_cs border_cs;
2538 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2539
2540 /* TODO: actually fill with border color */
2541 for (unsigned i = 0; i < size; i++)
2542 tu_cs_emit(&border_cs, 0);
2543
2544 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2545
2546 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2547 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2548 }
2549
2550 static void
2551 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2552 struct tu_cs *cs,
2553 const struct tu_draw_info *draw)
2554 {
2555 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2556 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2557 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2558 uint32_t draw_state_group_count = 0;
2559
2560 struct tu_descriptor_state *descriptors_state =
2561 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2562
2563 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2564 if (result != VK_SUCCESS) {
2565 cmd->record_result = result;
2566 return;
2567 }
2568
2569 /* TODO lrz */
2570
2571 uint32_t pc_primitive_cntl = 0;
2572 if (pipeline->ia.primitive_restart && draw->indexed)
2573 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2574
2575 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2576 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2577 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2578
2579 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2580 tu_cs_emit(cs, pc_primitive_cntl);
2581
2582 if (cmd->state.dirty &
2583 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2584 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2585 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2586 dynamic->line_width);
2587 }
2588
2589 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2590 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2591 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2592 dynamic->stencil_compare_mask.back);
2593 }
2594
2595 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2596 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2597 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2598 dynamic->stencil_write_mask.back);
2599 }
2600
2601 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2602 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2603 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2604 dynamic->stencil_reference.back);
2605 }
2606
2607 if (cmd->state.dirty &
2608 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2609 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2610 const uint32_t binding = pipeline->vi.bindings[i];
2611 const uint32_t stride = pipeline->vi.strides[i];
2612 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2613 const VkDeviceSize offset = buf->bo_offset +
2614 cmd->state.vb.offsets[binding] +
2615 pipeline->vi.offsets[i];
2616 const VkDeviceSize size =
2617 offset < buf->bo->size ? buf->bo->size - offset : 0;
2618
2619 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2620 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2621 tu_cs_emit(cs, size);
2622 tu_cs_emit(cs, stride);
2623 }
2624 }
2625
2626 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2627 draw_state_groups[draw_state_group_count++] =
2628 (struct tu_draw_state_group) {
2629 .id = TU_DRAW_STATE_PROGRAM,
2630 .enable_mask = 0x6,
2631 .ib = pipeline->program.state_ib,
2632 };
2633 draw_state_groups[draw_state_group_count++] =
2634 (struct tu_draw_state_group) {
2635 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2636 .enable_mask = 0x1,
2637 .ib = pipeline->program.binning_state_ib,
2638 };
2639 draw_state_groups[draw_state_group_count++] =
2640 (struct tu_draw_state_group) {
2641 .id = TU_DRAW_STATE_VI,
2642 .enable_mask = 0x6,
2643 .ib = pipeline->vi.state_ib,
2644 };
2645 draw_state_groups[draw_state_group_count++] =
2646 (struct tu_draw_state_group) {
2647 .id = TU_DRAW_STATE_VI_BINNING,
2648 .enable_mask = 0x1,
2649 .ib = pipeline->vi.binning_state_ib,
2650 };
2651 draw_state_groups[draw_state_group_count++] =
2652 (struct tu_draw_state_group) {
2653 .id = TU_DRAW_STATE_VP,
2654 .enable_mask = 0x7,
2655 .ib = pipeline->vp.state_ib,
2656 };
2657 draw_state_groups[draw_state_group_count++] =
2658 (struct tu_draw_state_group) {
2659 .id = TU_DRAW_STATE_RAST,
2660 .enable_mask = 0x7,
2661 .ib = pipeline->rast.state_ib,
2662 };
2663 draw_state_groups[draw_state_group_count++] =
2664 (struct tu_draw_state_group) {
2665 .id = TU_DRAW_STATE_DS,
2666 .enable_mask = 0x7,
2667 .ib = pipeline->ds.state_ib,
2668 };
2669 draw_state_groups[draw_state_group_count++] =
2670 (struct tu_draw_state_group) {
2671 .id = TU_DRAW_STATE_BLEND,
2672 .enable_mask = 0x7,
2673 .ib = pipeline->blend.state_ib,
2674 };
2675 }
2676
2677 if (cmd->state.dirty &
2678 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2679 bool needs_border = false;
2680
2681 draw_state_groups[draw_state_group_count++] =
2682 (struct tu_draw_state_group) {
2683 .id = TU_DRAW_STATE_VS_CONST,
2684 .enable_mask = 0x7,
2685 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2686 };
2687 draw_state_groups[draw_state_group_count++] =
2688 (struct tu_draw_state_group) {
2689 .id = TU_DRAW_STATE_FS_CONST,
2690 .enable_mask = 0x6,
2691 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2692 };
2693 draw_state_groups[draw_state_group_count++] =
2694 (struct tu_draw_state_group) {
2695 .id = TU_DRAW_STATE_VS_TEX,
2696 .enable_mask = 0x7,
2697 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2698 descriptors_state, MESA_SHADER_VERTEX,
2699 &needs_border)
2700 };
2701 draw_state_groups[draw_state_group_count++] =
2702 (struct tu_draw_state_group) {
2703 .id = TU_DRAW_STATE_FS_TEX,
2704 .enable_mask = 0x6,
2705 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2706 descriptors_state, MESA_SHADER_FRAGMENT,
2707 &needs_border)
2708 };
2709
2710 if (needs_border)
2711 tu6_emit_border_color(cmd, cs);
2712 }
2713
2714 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2715 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2716 const struct tu_draw_state_group *group = &draw_state_groups[i];
2717
2718 uint32_t cp_set_draw_state =
2719 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2720 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2721 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2722 uint64_t iova;
2723 if (group->ib.size) {
2724 iova = group->ib.bo->iova + group->ib.offset;
2725 } else {
2726 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2727 iova = 0;
2728 }
2729
2730 tu_cs_emit(cs, cp_set_draw_state);
2731 tu_cs_emit_qw(cs, iova);
2732 }
2733
2734 tu_cs_sanity_check(cs);
2735
2736 /* track BOs */
2737 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2738 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2739 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2740 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2741 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2742 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2743 }
2744 }
2745 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2746 for (uint32_t i = 0; i < MAX_VBS; i++) {
2747 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2748 if (buf)
2749 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2750 }
2751 }
2752 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2753 unsigned i;
2754 for_each_bit(i, descriptors_state->valid) {
2755 struct tu_descriptor_set *set = descriptors_state->sets[i];
2756 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2757 if (set->descriptors[j]) {
2758 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2759 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2760 }
2761 }
2762 }
2763 cmd->state.dirty = 0;
2764 }
2765
2766 static void
2767 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2768 struct tu_cs *cs,
2769 const struct tu_draw_info *draw)
2770 {
2771
2772 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2773
2774 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2775 tu_cs_emit(cs, draw->vertex_offset);
2776 tu_cs_emit(cs, draw->first_instance);
2777
2778 /* TODO hw binning */
2779 if (draw->indexed) {
2780 const enum a4xx_index_size index_size =
2781 tu6_index_size(cmd->state.index_type);
2782 const uint32_t index_bytes =
2783 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2784 const struct tu_buffer *buf = cmd->state.index_buffer;
2785 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2786 index_bytes * draw->first_index;
2787 const uint32_t size = index_bytes * draw->count;
2788
2789 const uint32_t cp_draw_indx =
2790 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2791 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2792 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2793 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2794
2795 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2796 tu_cs_emit(cs, cp_draw_indx);
2797 tu_cs_emit(cs, draw->instance_count);
2798 tu_cs_emit(cs, draw->count);
2799 tu_cs_emit(cs, 0x0); /* XXX */
2800 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2801 tu_cs_emit(cs, size);
2802 } else {
2803 const uint32_t cp_draw_indx =
2804 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2805 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2806 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2807
2808 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2809 tu_cs_emit(cs, cp_draw_indx);
2810 tu_cs_emit(cs, draw->instance_count);
2811 tu_cs_emit(cs, draw->count);
2812 }
2813 }
2814
2815 static void
2816 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2817 {
2818 struct tu_cs *cs = &cmd->draw_cs;
2819
2820 tu6_bind_draw_states(cmd, cs, draw);
2821
2822 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2823 if (result != VK_SUCCESS) {
2824 cmd->record_result = result;
2825 return;
2826 }
2827
2828 if (draw->indirect) {
2829 tu_finishme("indirect draw");
2830 return;
2831 }
2832
2833 /* TODO tu6_emit_marker should pick different regs depending on cs */
2834 tu6_emit_marker(cmd, cs);
2835 tu6_emit_draw_direct(cmd, cs, draw);
2836 tu6_emit_marker(cmd, cs);
2837
2838 cmd->wait_for_idle = true;
2839
2840 tu_cs_sanity_check(cs);
2841 }
2842
2843 void
2844 tu_CmdDraw(VkCommandBuffer commandBuffer,
2845 uint32_t vertexCount,
2846 uint32_t instanceCount,
2847 uint32_t firstVertex,
2848 uint32_t firstInstance)
2849 {
2850 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2851 struct tu_draw_info info = {};
2852
2853 info.count = vertexCount;
2854 info.instance_count = instanceCount;
2855 info.first_instance = firstInstance;
2856 info.vertex_offset = firstVertex;
2857
2858 tu_draw(cmd_buffer, &info);
2859 }
2860
2861 void
2862 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2863 uint32_t indexCount,
2864 uint32_t instanceCount,
2865 uint32_t firstIndex,
2866 int32_t vertexOffset,
2867 uint32_t firstInstance)
2868 {
2869 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2870 struct tu_draw_info info = {};
2871
2872 info.indexed = true;
2873 info.count = indexCount;
2874 info.instance_count = instanceCount;
2875 info.first_index = firstIndex;
2876 info.vertex_offset = vertexOffset;
2877 info.first_instance = firstInstance;
2878
2879 tu_draw(cmd_buffer, &info);
2880 }
2881
2882 void
2883 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2884 VkBuffer _buffer,
2885 VkDeviceSize offset,
2886 uint32_t drawCount,
2887 uint32_t stride)
2888 {
2889 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2890 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2891 struct tu_draw_info info = {};
2892
2893 info.count = drawCount;
2894 info.indirect = buffer;
2895 info.indirect_offset = offset;
2896 info.stride = stride;
2897
2898 tu_draw(cmd_buffer, &info);
2899 }
2900
2901 void
2902 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2903 VkBuffer _buffer,
2904 VkDeviceSize offset,
2905 uint32_t drawCount,
2906 uint32_t stride)
2907 {
2908 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2909 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2910 struct tu_draw_info info = {};
2911
2912 info.indexed = true;
2913 info.count = drawCount;
2914 info.indirect = buffer;
2915 info.indirect_offset = offset;
2916 info.stride = stride;
2917
2918 tu_draw(cmd_buffer, &info);
2919 }
2920
2921 struct tu_dispatch_info
2922 {
2923 /**
2924 * Determine the layout of the grid (in block units) to be used.
2925 */
2926 uint32_t blocks[3];
2927
2928 /**
2929 * A starting offset for the grid. If unaligned is set, the offset
2930 * must still be aligned.
2931 */
2932 uint32_t offsets[3];
2933 /**
2934 * Whether it's an unaligned compute dispatch.
2935 */
2936 bool unaligned;
2937
2938 /**
2939 * Indirect compute parameters resource.
2940 */
2941 struct tu_buffer *indirect;
2942 uint64_t indirect_offset;
2943 };
2944
2945 static void
2946 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2947 const struct tu_dispatch_info *info)
2948 {
2949 }
2950
2951 void
2952 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2953 uint32_t base_x,
2954 uint32_t base_y,
2955 uint32_t base_z,
2956 uint32_t x,
2957 uint32_t y,
2958 uint32_t z)
2959 {
2960 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2961 struct tu_dispatch_info info = {};
2962
2963 info.blocks[0] = x;
2964 info.blocks[1] = y;
2965 info.blocks[2] = z;
2966
2967 info.offsets[0] = base_x;
2968 info.offsets[1] = base_y;
2969 info.offsets[2] = base_z;
2970 tu_dispatch(cmd_buffer, &info);
2971 }
2972
2973 void
2974 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2975 uint32_t x,
2976 uint32_t y,
2977 uint32_t z)
2978 {
2979 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2980 }
2981
2982 void
2983 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2984 VkBuffer _buffer,
2985 VkDeviceSize offset)
2986 {
2987 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2988 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2989 struct tu_dispatch_info info = {};
2990
2991 info.indirect = buffer;
2992 info.indirect_offset = offset;
2993
2994 tu_dispatch(cmd_buffer, &info);
2995 }
2996
2997 void
2998 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2999 {
3000 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3001
3002 tu_cs_end(&cmd_buffer->draw_cs);
3003
3004 tu_cmd_render_tiles(cmd_buffer);
3005
3006 /* discard draw_cs entries now that the tiles are rendered */
3007 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3008
3009 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3010 cmd_buffer->state.attachments = NULL;
3011
3012 cmd_buffer->state.pass = NULL;
3013 cmd_buffer->state.subpass = NULL;
3014 cmd_buffer->state.framebuffer = NULL;
3015 }
3016
3017 void
3018 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3019 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3020 {
3021 tu_CmdEndRenderPass(commandBuffer);
3022 }
3023
3024 struct tu_barrier_info
3025 {
3026 uint32_t eventCount;
3027 const VkEvent *pEvents;
3028 VkPipelineStageFlags srcStageMask;
3029 };
3030
3031 static void
3032 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3033 uint32_t memoryBarrierCount,
3034 const VkMemoryBarrier *pMemoryBarriers,
3035 uint32_t bufferMemoryBarrierCount,
3036 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3037 uint32_t imageMemoryBarrierCount,
3038 const VkImageMemoryBarrier *pImageMemoryBarriers,
3039 const struct tu_barrier_info *info)
3040 {
3041 }
3042
3043 void
3044 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3045 VkPipelineStageFlags srcStageMask,
3046 VkPipelineStageFlags destStageMask,
3047 VkBool32 byRegion,
3048 uint32_t memoryBarrierCount,
3049 const VkMemoryBarrier *pMemoryBarriers,
3050 uint32_t bufferMemoryBarrierCount,
3051 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3052 uint32_t imageMemoryBarrierCount,
3053 const VkImageMemoryBarrier *pImageMemoryBarriers)
3054 {
3055 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3056 struct tu_barrier_info info;
3057
3058 info.eventCount = 0;
3059 info.pEvents = NULL;
3060 info.srcStageMask = srcStageMask;
3061
3062 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3063 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3064 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3065 }
3066
3067 static void
3068 write_event(struct tu_cmd_buffer *cmd_buffer,
3069 struct tu_event *event,
3070 VkPipelineStageFlags stageMask,
3071 unsigned value)
3072 {
3073 }
3074
3075 void
3076 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3077 VkEvent _event,
3078 VkPipelineStageFlags stageMask)
3079 {
3080 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3081 TU_FROM_HANDLE(tu_event, event, _event);
3082
3083 write_event(cmd_buffer, event, stageMask, 1);
3084 }
3085
3086 void
3087 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3088 VkEvent _event,
3089 VkPipelineStageFlags stageMask)
3090 {
3091 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3092 TU_FROM_HANDLE(tu_event, event, _event);
3093
3094 write_event(cmd_buffer, event, stageMask, 0);
3095 }
3096
3097 void
3098 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3099 uint32_t eventCount,
3100 const VkEvent *pEvents,
3101 VkPipelineStageFlags srcStageMask,
3102 VkPipelineStageFlags dstStageMask,
3103 uint32_t memoryBarrierCount,
3104 const VkMemoryBarrier *pMemoryBarriers,
3105 uint32_t bufferMemoryBarrierCount,
3106 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3107 uint32_t imageMemoryBarrierCount,
3108 const VkImageMemoryBarrier *pImageMemoryBarriers)
3109 {
3110 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3111 struct tu_barrier_info info;
3112
3113 info.eventCount = eventCount;
3114 info.pEvents = pEvents;
3115 info.srcStageMask = 0;
3116
3117 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3118 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3119 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3120 }
3121
3122 void
3123 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3124 {
3125 /* No-op */
3126 }