2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WFI
)
166 /* "Normal" cache flushes, that don't require any special handling */
169 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
172 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
173 cmd_buffer
->state
.cache
.flush_bits
= 0;
176 /* Renderpass cache flushes */
179 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
182 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
183 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
186 /* Cache flushes for things that use the color/depth read/write path (i.e.
187 * blits and draws). This deals with changing CCU state as well as the usual
192 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
194 enum tu_cmd_ccu_state ccu_state
)
196 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
198 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
200 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
201 * the CCU may also contain data that we haven't flushed out yet, so we
202 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
203 * emit a WFI as it isn't pipelined.
205 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
206 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
208 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
209 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
210 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
211 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
212 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
215 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
216 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
218 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
);
223 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
224 cmd_buffer
->state
.cache
.flush_bits
= 0;
226 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
227 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
229 A6XX_RB_CCU_CNTL(.offset
=
230 ccu_state
== TU_CMD_CCU_GMEM
?
231 phys_dev
->ccu_offset_gmem
:
232 phys_dev
->ccu_offset_bypass
,
233 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
234 cmd_buffer
->state
.ccu_state
= ccu_state
;
239 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
240 const struct tu_subpass
*subpass
,
243 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
245 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
246 if (a
== VK_ATTACHMENT_UNUSED
) {
248 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
249 A6XX_RB_DEPTH_BUFFER_PITCH(0),
250 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
251 A6XX_RB_DEPTH_BUFFER_BASE(0),
252 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
255 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
258 A6XX_GRAS_LRZ_BUFFER_BASE(0),
259 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
260 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
262 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
267 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
268 const struct tu_render_pass_attachment
*attachment
=
269 &cmd
->state
.pass
->attachments
[a
];
270 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
272 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
273 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
274 tu_cs_image_ref(cs
, iview
, 0);
275 tu_cs_emit(cs
, attachment
->gmem_offset
);
278 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
280 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
281 tu_cs_image_flag_ref(cs
, iview
, 0);
284 A6XX_GRAS_LRZ_BUFFER_BASE(0),
285 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
286 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
288 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
289 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
290 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
291 tu_cs_image_ref(cs
, iview
, 0);
292 tu_cs_emit(cs
, attachment
->gmem_offset
);
295 A6XX_RB_STENCIL_INFO(0));
300 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
301 const struct tu_subpass
*subpass
,
304 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
306 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
307 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
308 if (a
== VK_ATTACHMENT_UNUSED
)
311 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
313 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
314 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
315 tu_cs_image_ref(cs
, iview
, 0);
316 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
319 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
321 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
322 tu_cs_image_flag_ref(cs
, iview
, 0);
326 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
328 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
330 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
334 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
336 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
337 bool msaa_disable
= samples
== MSAA_ONE
;
340 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
341 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
342 .msaa_disable
= msaa_disable
));
345 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
346 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
347 .msaa_disable
= msaa_disable
));
350 A6XX_RB_RAS_MSAA_CNTL(samples
),
351 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
352 .msaa_disable
= msaa_disable
));
355 A6XX_RB_MSAA_CNTL(samples
));
359 tu6_emit_bin_size(struct tu_cs
*cs
,
360 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
363 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
368 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
372 /* no flag for RB_BIN_CONTROL2... */
374 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
379 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
380 const struct tu_subpass
*subpass
,
384 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
386 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
388 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
390 uint32_t mrts_ubwc_enable
= 0;
391 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
392 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
393 if (a
== VK_ATTACHMENT_UNUSED
)
396 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
397 if (iview
->ubwc_enabled
)
398 mrts_ubwc_enable
|= 1 << i
;
401 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
403 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
404 if (a
!= VK_ATTACHMENT_UNUSED
) {
405 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
406 if (iview
->ubwc_enabled
)
407 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
410 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
411 * in order to set it correctly for the different subpasses. However,
412 * that means the packets we're emitting also happen during binning. So
413 * we need to guard the write on !BINNING at CP execution time.
415 tu_cs_reserve(cs
, 3 + 4);
416 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
417 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
418 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
419 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
422 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
423 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
424 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
425 tu_cs_emit(cs
, cntl
);
429 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
431 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
432 uint32_t x1
= render_area
->offset
.x
;
433 uint32_t y1
= render_area
->offset
.y
;
434 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
435 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
438 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
439 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
440 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
441 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
445 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
446 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
450 tu6_emit_window_scissor(struct tu_cs
*cs
,
457 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
458 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
461 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
462 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
466 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
469 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
472 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
475 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
478 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
482 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
484 uint32_t enable_mask
;
486 case TU_DRAW_STATE_PROGRAM
:
487 case TU_DRAW_STATE_VI
:
488 case TU_DRAW_STATE_FS_CONST
:
489 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
490 * when resources would actually be used in the binning shader.
491 * Presumably the overhead of prefetching the resources isn't
494 case TU_DRAW_STATE_DESC_SETS_LOAD
:
495 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
496 CP_SET_DRAW_STATE__0_SYSMEM
;
498 case TU_DRAW_STATE_PROGRAM_BINNING
:
499 case TU_DRAW_STATE_VI_BINNING
:
500 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
502 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
503 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
505 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
506 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
509 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
510 CP_SET_DRAW_STATE__0_SYSMEM
|
511 CP_SET_DRAW_STATE__0_BINNING
;
515 /* We need to reload the descriptors every time the descriptor sets
516 * change. However, the commands we send only depend on the pipeline
517 * because the whole point is to cache descriptors which are used by the
518 * pipeline. There's a problem here, in that the firmware has an
519 * "optimization" which skips executing groups that are set to the same
520 * value as the last draw. This means that if the descriptor sets change
521 * but not the pipeline, we'd try to re-execute the same buffer which
522 * the firmware would ignore and we wouldn't pre-load the new
523 * descriptors. Set the DIRTY bit to avoid this optimization
525 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
526 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
528 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
530 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
531 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
532 tu_cs_emit_qw(cs
, state
.iova
);
536 use_hw_binning(struct tu_cmd_buffer
*cmd
)
538 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
540 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
541 * with non-hw binning GMEM rendering. this is required because some of the
542 * XFB commands need to only be executed once
544 if (cmd
->state
.xfb_used
)
547 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
550 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
553 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
557 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
559 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
562 /* can't fit attachments into gmem */
563 if (!cmd
->state
.pass
->gmem_pixels
)
566 if (cmd
->state
.framebuffer
->layers
> 1)
576 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
578 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
580 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
582 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
583 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
585 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
586 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
588 const uint32_t x1
= fb
->tile0
.width
* tx
;
589 const uint32_t y1
= fb
->tile0
.height
* ty
;
590 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
591 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
592 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
593 tu6_emit_window_offset(cs
, x1
, y1
);
595 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
597 if (use_hw_binning(cmd
)) {
598 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
600 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
603 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
604 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
605 CP_SET_BIN_DATA5_0_VSC_N(slot
));
606 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
607 tu_cs_emit(cs
, pipe
* 4);
608 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
610 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
613 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
616 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
619 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
625 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
630 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
631 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
632 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
634 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
638 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
640 const struct tu_subpass
*subpass
)
642 if (subpass
->resolve_attachments
) {
643 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
646 * End-of-subpass multisample resolves are treated as color
647 * attachment writes for the purposes of synchronization. That is,
648 * they are considered to execute in the
649 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
650 * their writes are synchronized with
651 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
652 * rendering within a subpass and any resolve operations at the end
653 * of the subpass occurs automatically, without need for explicit
654 * dependencies or pipeline barriers. However, if the resolve
655 * attachment is also used in a different subpass, an explicit
656 * dependency is needed.
658 * We use the CP_BLIT path for sysmem resolves, which is really a
659 * transfer command, so we have to manually flush similar to the gmem
660 * resolve case. However, a flush afterwards isn't needed because of the
661 * last sentence and the fact that we're in sysmem mode.
663 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
664 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
666 /* Wait for the flushes to land before using the 2D engine */
669 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
670 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
671 if (a
== VK_ATTACHMENT_UNUSED
)
674 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
675 subpass
->color_attachments
[i
].attachment
);
681 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
683 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
684 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
686 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
687 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
688 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
689 CP_SET_DRAW_STATE__0_GROUP_ID(0));
690 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
691 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
693 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
696 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
697 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
699 tu6_emit_blit_scissor(cmd
, cs
, true);
701 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
702 if (pass
->attachments
[a
].gmem_offset
>= 0)
703 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
706 if (subpass
->resolve_attachments
) {
707 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
708 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
709 if (a
!= VK_ATTACHMENT_UNUSED
)
710 tu_store_gmem_attachment(cmd
, cs
, a
,
711 subpass
->color_attachments
[i
].attachment
);
717 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
719 struct tu_device
*dev
= cmd
->device
;
720 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
722 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
724 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
733 .gfx_shared_const
= true,
734 .cs_shared_const
= true,
735 .gfx_bindless
= 0x1f,
736 .cs_bindless
= 0x1f));
739 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
740 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
741 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
742 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
743 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
744 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
745 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
746 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
747 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
748 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
750 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
751 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
752 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
753 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
754 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
755 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
756 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
757 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
758 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
759 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
760 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
761 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
762 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
764 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
765 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
766 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
767 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
769 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
787 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
788 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
790 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
792 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
795 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
802 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
814 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
816 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
818 /* we don't use this yet.. probably best to disable.. */
819 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
820 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
821 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
822 CP_SET_DRAW_STATE__0_GROUP_ID(0));
823 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
824 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
827 A6XX_SP_HS_CTRL_REG0(0));
830 A6XX_SP_GS_CTRL_REG0(0));
833 A6XX_GRAS_LRZ_CNTL(0));
836 A6XX_RB_LRZ_CNTL(0));
839 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
840 .bo_offset
= gb_offset(border_color
)));
842 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
843 .bo_offset
= gb_offset(border_color
)));
846 * use vsc pitches from the largest values used so far with this device
847 * if there hasn't been overflow, there will already be a scratch bo
848 * allocated for these sizes
850 * if overflow is detected, the stream size is increased by 2x
852 mtx_lock(&dev
->vsc_pitch_mtx
);
854 struct tu6_global
*global
= dev
->global_bo
.map
;
856 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
857 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
859 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
860 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
862 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
863 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
865 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
866 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
868 mtx_unlock(&dev
->vsc_pitch_mtx
);
870 struct tu_bo
*vsc_bo
;
871 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
872 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
874 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
877 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
879 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
881 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
882 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
884 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
886 tu_cs_sanity_check(cs
);
890 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
892 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
895 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
896 .height
= fb
->tile0
.height
));
899 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
900 .ny
= fb
->tile_count
.height
));
902 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
903 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
906 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
907 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
910 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
911 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
915 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
917 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
918 const uint32_t used_pipe_count
=
919 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
921 for (int i
= 0; i
< used_pipe_count
; i
++) {
922 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
923 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
924 CP_COND_WRITE5_0_WRITE_MEMORY
);
925 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
926 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
927 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
928 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
929 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
930 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
932 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
933 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
934 CP_COND_WRITE5_0_WRITE_MEMORY
);
935 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
936 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
937 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
938 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
939 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
940 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
943 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
947 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
949 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
950 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
952 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
954 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
955 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
957 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
960 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
966 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
968 update_vsc_pipe(cmd
, cs
);
971 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
974 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
976 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
977 tu_cs_emit(cs
, UNK_2C
);
980 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
983 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
985 /* emit IB to binning drawcmds: */
986 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
988 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
989 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
990 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
991 CP_SET_DRAW_STATE__0_GROUP_ID(0));
992 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
993 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
995 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
996 tu_cs_emit(cs
, UNK_2D
);
998 /* This flush is probably required because the VSC, which produces the
999 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1000 * visibility stream (without caching) to do draw skipping. The
1001 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1002 * submitted are finished before reading the VSC regs (in
1003 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1006 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1010 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1012 emit_vsc_overflow_test(cmd
, cs
);
1014 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1015 tu_cs_emit(cs
, 0x0);
1017 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1018 tu_cs_emit(cs
, 0x0);
1021 static struct tu_draw_state
1022 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1023 const struct tu_subpass
*subpass
,
1026 /* note: we can probably emit input attachments just once for the whole
1027 * renderpass, this would avoid emitting both sysmem/gmem versions
1029 * emit two texture descriptors for each input, as a workaround for
1030 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1031 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1033 * TODO: a smarter workaround
1036 if (!subpass
->input_count
)
1037 return (struct tu_draw_state
) {};
1039 struct tu_cs_memory texture
;
1040 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1041 A6XX_TEX_CONST_DWORDS
, &texture
);
1042 assert(result
== VK_SUCCESS
);
1044 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1045 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1046 if (a
== VK_ATTACHMENT_UNUSED
)
1049 struct tu_image_view
*iview
=
1050 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1051 const struct tu_render_pass_attachment
*att
=
1052 &cmd
->state
.pass
->attachments
[a
];
1053 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1055 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1057 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1058 /* note this works because spec says fb and input attachments
1059 * must use identity swizzle
1061 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1062 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1063 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1064 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1065 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1066 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1067 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1068 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1074 /* patched for gmem */
1075 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1076 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1078 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1079 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* att
->cpp
);
1081 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1082 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1083 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1088 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1090 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1091 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1092 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1093 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1094 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1095 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1096 tu_cs_emit_qw(&cs
, texture
.iova
);
1098 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1099 tu_cs_emit_qw(&cs
, texture
.iova
);
1101 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1103 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1109 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1111 struct tu_cs
*cs
= &cmd
->draw_cs
;
1113 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1114 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1115 tu_emit_input_attachments(cmd
, subpass
, true));
1116 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1117 tu_emit_input_attachments(cmd
, subpass
, false));
1121 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1122 const VkRenderPassBeginInfo
*info
)
1124 struct tu_cs
*cs
= &cmd
->draw_cs
;
1126 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1128 tu6_emit_blit_scissor(cmd
, cs
, true);
1130 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1131 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1133 tu6_emit_blit_scissor(cmd
, cs
, false);
1135 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1136 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1138 tu_cond_exec_end(cs
);
1140 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1142 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1143 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1145 tu_cond_exec_end(cs
);
1149 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1151 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1153 assert(fb
->width
> 0 && fb
->height
> 0);
1154 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1155 tu6_emit_window_offset(cs
, 0, 0);
1157 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1159 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1161 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1162 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1164 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1165 tu_cs_emit(cs
, 0x0);
1167 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1169 /* enable stream-out, with sysmem there is only one pass: */
1170 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1172 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1173 tu_cs_emit(cs
, 0x1);
1175 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1176 tu_cs_emit(cs
, 0x0);
1178 tu_cs_sanity_check(cs
);
1182 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1184 /* Do any resolves of the last subpass. These are handled in the
1185 * tile_store_ib in the gmem path.
1187 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1189 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1191 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1192 tu_cs_emit(cs
, 0x0);
1194 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1196 tu_cs_sanity_check(cs
);
1200 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1202 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1204 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1208 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1209 tu_cs_emit(cs
, 0x0);
1211 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1213 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1214 if (use_hw_binning(cmd
)) {
1215 /* enable stream-out during binning pass: */
1216 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1218 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1219 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1221 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1223 tu6_emit_binning_pass(cmd
, cs
);
1225 /* and disable stream-out for draw pass: */
1226 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1228 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1229 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1232 A6XX_VFD_MODE_CNTL(0));
1234 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1236 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1238 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1239 tu_cs_emit(cs
, 0x1);
1241 /* no binning pass, so enable stream-out for draw pass:: */
1242 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1244 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1247 tu_cs_sanity_check(cs
);
1251 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1253 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1255 if (use_hw_binning(cmd
)) {
1256 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1257 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1260 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1262 tu_cs_sanity_check(cs
);
1266 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1268 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1271 A6XX_GRAS_LRZ_CNTL(0));
1273 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1275 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1277 tu_cs_sanity_check(cs
);
1281 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1283 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1285 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1288 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1289 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1290 uint32_t tx1
= px
* fb
->pipe0
.width
;
1291 uint32_t ty1
= py
* fb
->pipe0
.height
;
1292 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1293 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1295 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1296 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1297 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1298 tu6_render_tile(cmd
, &cmd
->cs
);
1304 tu6_tile_render_end(cmd
, &cmd
->cs
);
1308 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1310 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1312 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1314 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1318 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1320 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1321 struct tu_cs sub_cs
;
1324 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1325 if (result
!= VK_SUCCESS
) {
1326 cmd
->record_result
= result
;
1330 /* emit to tile-store sub_cs */
1331 tu6_emit_tile_store(cmd
, &sub_cs
);
1333 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1337 tu_create_cmd_buffer(struct tu_device
*device
,
1338 struct tu_cmd_pool
*pool
,
1339 VkCommandBufferLevel level
,
1340 VkCommandBuffer
*pCommandBuffer
)
1342 struct tu_cmd_buffer
*cmd_buffer
;
1344 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1345 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1346 if (cmd_buffer
== NULL
)
1347 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1349 cmd_buffer
->device
= device
;
1350 cmd_buffer
->pool
= pool
;
1351 cmd_buffer
->level
= level
;
1354 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1355 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1358 /* Init the pool_link so we can safely call list_del when we destroy
1359 * the command buffer
1361 list_inithead(&cmd_buffer
->pool_link
);
1362 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1365 tu_bo_list_init(&cmd_buffer
->bo_list
);
1366 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1367 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1368 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1369 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1371 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1373 list_inithead(&cmd_buffer
->upload
.list
);
1379 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1381 list_del(&cmd_buffer
->pool_link
);
1383 tu_cs_finish(&cmd_buffer
->cs
);
1384 tu_cs_finish(&cmd_buffer
->draw_cs
);
1385 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1386 tu_cs_finish(&cmd_buffer
->sub_cs
);
1388 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1389 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1393 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1395 cmd_buffer
->record_result
= VK_SUCCESS
;
1397 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1398 tu_cs_reset(&cmd_buffer
->cs
);
1399 tu_cs_reset(&cmd_buffer
->draw_cs
);
1400 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1401 tu_cs_reset(&cmd_buffer
->sub_cs
);
1403 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1404 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1406 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1408 return cmd_buffer
->record_result
;
1412 tu_AllocateCommandBuffers(VkDevice _device
,
1413 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1414 VkCommandBuffer
*pCommandBuffers
)
1416 TU_FROM_HANDLE(tu_device
, device
, _device
);
1417 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1419 VkResult result
= VK_SUCCESS
;
1422 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1424 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1425 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1426 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1428 list_del(&cmd_buffer
->pool_link
);
1429 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1431 result
= tu_reset_cmd_buffer(cmd_buffer
);
1432 cmd_buffer
->level
= pAllocateInfo
->level
;
1434 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1436 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1437 &pCommandBuffers
[i
]);
1439 if (result
!= VK_SUCCESS
)
1443 if (result
!= VK_SUCCESS
) {
1444 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1447 /* From the Vulkan 1.0.66 spec:
1449 * "vkAllocateCommandBuffers can be used to create multiple
1450 * command buffers. If the creation of any of those command
1451 * buffers fails, the implementation must destroy all
1452 * successfully created command buffer objects from this
1453 * command, set all entries of the pCommandBuffers array to
1454 * NULL and return the error."
1456 memset(pCommandBuffers
, 0,
1457 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1464 tu_FreeCommandBuffers(VkDevice device
,
1465 VkCommandPool commandPool
,
1466 uint32_t commandBufferCount
,
1467 const VkCommandBuffer
*pCommandBuffers
)
1469 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1470 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1473 if (cmd_buffer
->pool
) {
1474 list_del(&cmd_buffer
->pool_link
);
1475 list_addtail(&cmd_buffer
->pool_link
,
1476 &cmd_buffer
->pool
->free_cmd_buffers
);
1478 tu_cmd_buffer_destroy(cmd_buffer
);
1484 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1485 VkCommandBufferResetFlags flags
)
1487 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1488 return tu_reset_cmd_buffer(cmd_buffer
);
1491 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1495 tu_cache_init(struct tu_cache_state
*cache
)
1497 cache
->flush_bits
= 0;
1498 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1502 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1503 const VkCommandBufferBeginInfo
*pBeginInfo
)
1505 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1506 VkResult result
= VK_SUCCESS
;
1508 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1509 /* If the command buffer has already been resetted with
1510 * vkResetCommandBuffer, no need to do it again.
1512 result
= tu_reset_cmd_buffer(cmd_buffer
);
1513 if (result
!= VK_SUCCESS
)
1517 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1518 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1520 tu_cache_init(&cmd_buffer
->state
.cache
);
1521 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1522 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1524 tu_cs_begin(&cmd_buffer
->cs
);
1525 tu_cs_begin(&cmd_buffer
->draw_cs
);
1526 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1528 /* setup initial configuration into command buffer */
1529 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1530 switch (cmd_buffer
->queue_family_index
) {
1531 case TU_QUEUE_GENERAL
:
1532 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1537 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1538 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1539 assert(pBeginInfo
->pInheritanceInfo
);
1540 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1541 cmd_buffer
->state
.subpass
=
1542 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1544 /* When executing in the middle of another command buffer, the CCU
1547 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1551 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1556 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1557 * rendering can skip over unused state), so we need to collect all the
1558 * bindings together into a single state emit at draw time.
1561 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1562 uint32_t firstBinding
,
1563 uint32_t bindingCount
,
1564 const VkBuffer
*pBuffers
,
1565 const VkDeviceSize
*pOffsets
)
1567 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1569 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1571 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1572 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1574 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1575 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1577 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1580 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1584 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1586 VkDeviceSize offset
,
1587 VkIndexType indexType
)
1589 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1590 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1594 uint32_t index_size
, index_shift
, restart_index
;
1596 switch (indexType
) {
1597 case VK_INDEX_TYPE_UINT16
:
1598 index_size
= INDEX4_SIZE_16_BIT
;
1600 restart_index
= 0xffff;
1602 case VK_INDEX_TYPE_UINT32
:
1603 index_size
= INDEX4_SIZE_32_BIT
;
1605 restart_index
= 0xffffffff;
1607 case VK_INDEX_TYPE_UINT8_EXT
:
1608 index_size
= INDEX4_SIZE_8_BIT
;
1610 restart_index
= 0xff;
1613 unreachable("invalid VkIndexType");
1616 /* initialize/update the restart index */
1617 if (cmd
->state
.index_size
!= index_size
)
1618 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1620 assert(buf
->size
>= offset
);
1622 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1623 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1624 cmd
->state
.index_size
= index_size
;
1626 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1630 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1631 VkPipelineBindPoint pipelineBindPoint
,
1632 VkPipelineLayout _layout
,
1634 uint32_t descriptorSetCount
,
1635 const VkDescriptorSet
*pDescriptorSets
,
1636 uint32_t dynamicOffsetCount
,
1637 const uint32_t *pDynamicOffsets
)
1639 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1640 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1641 unsigned dyn_idx
= 0;
1643 struct tu_descriptor_state
*descriptors_state
=
1644 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1646 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1647 unsigned idx
= i
+ firstSet
;
1648 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1650 descriptors_state
->sets
[idx
] = set
;
1652 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1653 /* update the contents of the dynamic descriptor set */
1654 unsigned src_idx
= j
;
1655 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1656 assert(dyn_idx
< dynamicOffsetCount
);
1659 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1661 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1662 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1664 /* Patch the storage/uniform descriptors right away. */
1665 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1666 /* Note: we can assume here that the addition won't roll over and
1667 * change the SIZE field.
1669 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1674 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1675 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1676 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1683 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1684 if (set
->buffers
[j
]) {
1685 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1686 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1690 if (set
->size
> 0) {
1691 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1692 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1695 assert(dyn_idx
== dynamicOffsetCount
);
1697 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1698 uint64_t addr
[MAX_SETS
+ 1] = {};
1699 struct tu_cs
*cs
, state_cs
;
1701 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1702 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1704 addr
[i
] = set
->va
| 3;
1707 if (layout
->dynamic_offset_count
) {
1708 /* allocate and fill out dynamic descriptor set */
1709 struct tu_cs_memory dynamic_desc_set
;
1710 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1711 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1712 assert(result
== VK_SUCCESS
);
1714 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1715 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1716 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1719 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1720 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1721 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1722 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1724 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1725 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1728 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1730 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1731 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1732 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1734 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1738 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1739 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1740 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1741 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1742 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1744 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1745 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1746 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1747 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1751 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1752 uint32_t firstBinding
,
1753 uint32_t bindingCount
,
1754 const VkBuffer
*pBuffers
,
1755 const VkDeviceSize
*pOffsets
,
1756 const VkDeviceSize
*pSizes
)
1758 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1759 struct tu_cs
*cs
= &cmd
->draw_cs
;
1761 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1762 * presumably there isn't any benefit using a draw state when the
1763 * condition is (SYSMEM | BINNING)
1765 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1766 CP_COND_REG_EXEC_0_SYSMEM
|
1767 CP_COND_REG_EXEC_0_BINNING
);
1769 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1770 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1771 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1772 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1773 uint32_t idx
= i
+ firstBinding
;
1775 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1778 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1779 uint32_t offset
= iova
& 0x1f;
1780 iova
&= ~(uint64_t) 0x1f;
1782 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1783 tu_cs_emit_qw(cs
, iova
);
1784 tu_cs_emit(cs
, size
+ offset
);
1786 cmd
->state
.streamout_offset
[idx
] = offset
;
1788 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1791 tu_cond_exec_end(cs
);
1795 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1796 uint32_t firstCounterBuffer
,
1797 uint32_t counterBufferCount
,
1798 const VkBuffer
*pCounterBuffers
,
1799 const VkDeviceSize
*pCounterBufferOffsets
)
1801 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1802 struct tu_cs
*cs
= &cmd
->draw_cs
;
1804 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1805 CP_COND_REG_EXEC_0_SYSMEM
|
1806 CP_COND_REG_EXEC_0_BINNING
);
1808 /* TODO: only update offset for active buffers */
1809 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1810 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1812 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1813 uint32_t idx
= firstCounterBuffer
+ i
;
1814 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1816 if (!pCounterBuffers
[i
])
1819 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1821 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1823 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1824 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1825 CP_MEM_TO_REG_0_UNK31
|
1826 CP_MEM_TO_REG_0_CNT(1));
1827 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1830 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1831 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1832 CP_REG_RMW_0_SRC1_ADD
);
1833 tu_cs_emit_qw(cs
, 0xffffffff);
1834 tu_cs_emit_qw(cs
, offset
);
1838 tu_cond_exec_end(cs
);
1841 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1842 uint32_t firstCounterBuffer
,
1843 uint32_t counterBufferCount
,
1844 const VkBuffer
*pCounterBuffers
,
1845 const VkDeviceSize
*pCounterBufferOffsets
)
1847 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1848 struct tu_cs
*cs
= &cmd
->draw_cs
;
1850 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1851 CP_COND_REG_EXEC_0_SYSMEM
|
1852 CP_COND_REG_EXEC_0_BINNING
);
1854 /* TODO: only flush buffers that need to be flushed */
1855 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1856 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1857 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1858 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1859 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1862 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1863 uint32_t idx
= firstCounterBuffer
+ i
;
1864 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1866 if (!pCounterBuffers
[i
])
1869 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1871 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1873 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1874 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1875 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1876 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1878 CP_MEM_TO_REG_0_UNK31
|
1879 CP_MEM_TO_REG_0_CNT(1));
1880 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1883 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1884 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1885 CP_REG_RMW_0_SRC1_ADD
);
1886 tu_cs_emit_qw(cs
, 0xffffffff);
1887 tu_cs_emit_qw(cs
, -offset
);
1890 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1891 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1892 CP_REG_TO_MEM_0_CNT(1));
1893 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1896 tu_cond_exec_end(cs
);
1898 cmd
->state
.xfb_used
= true;
1902 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1903 VkPipelineLayout layout
,
1904 VkShaderStageFlags stageFlags
,
1907 const void *pValues
)
1909 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1910 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1911 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1914 /* Flush everything which has been made available but we haven't actually
1918 tu_flush_all_pending(struct tu_cache_state
*cache
)
1920 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1921 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1925 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1927 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1929 /* We currently flush CCU at the end of the command buffer, like
1930 * what the blob does. There's implicit synchronization around every
1931 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1932 * know yet if this command buffer will be the last in the submit so we
1933 * have to defensively flush everything else.
1935 * TODO: We could definitely do better than this, since these flushes
1936 * aren't required by Vulkan, but we'd need kernel support to do that.
1937 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1938 * wouldn't have to do any flushes here, and when submitting multiple
1939 * command buffers there wouldn't be any unnecessary flushes in between.
1941 if (cmd_buffer
->state
.pass
) {
1942 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1943 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
1945 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
1946 cmd_buffer
->state
.cache
.flush_bits
|=
1947 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
1948 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
1949 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
1952 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
1953 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1955 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1956 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1957 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1960 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1961 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1962 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1965 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1966 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1967 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1970 tu_cs_end(&cmd_buffer
->cs
);
1971 tu_cs_end(&cmd_buffer
->draw_cs
);
1972 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
1974 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1976 return cmd_buffer
->record_result
;
1980 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
1984 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
1985 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
1987 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1988 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
1994 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
1995 VkPipelineBindPoint pipelineBindPoint
,
1996 VkPipeline _pipeline
)
1998 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1999 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2001 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2002 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2003 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2006 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2007 cmd
->state
.compute_pipeline
= pipeline
;
2008 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2012 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2014 cmd
->state
.pipeline
= pipeline
;
2015 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2017 struct tu_cs
*cs
= &cmd
->draw_cs
;
2018 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2021 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2022 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2023 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2024 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2025 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2026 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2027 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2028 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2029 for_each_bit(i
, mask
)
2030 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2032 /* If the new pipeline requires more VBs than we had previously set up, we
2033 * need to re-emit them in SDS. If it requires the same set or fewer, we
2034 * can just re-use the old SDS.
2036 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2037 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2039 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2040 * so the dynamic state ib must be updated when pipeline changes
2042 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2043 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2045 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2046 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2048 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2053 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2054 uint32_t firstViewport
,
2055 uint32_t viewportCount
,
2056 const VkViewport
*pViewports
)
2058 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2059 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2061 assert(firstViewport
== 0 && viewportCount
== 1);
2063 tu6_emit_viewport(&cs
, pViewports
);
2067 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2068 uint32_t firstScissor
,
2069 uint32_t scissorCount
,
2070 const VkRect2D
*pScissors
)
2072 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2073 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2075 assert(firstScissor
== 0 && scissorCount
== 1);
2077 tu6_emit_scissor(&cs
, pScissors
);
2081 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2083 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2084 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2086 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2087 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2089 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2093 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2094 float depthBiasConstantFactor
,
2095 float depthBiasClamp
,
2096 float depthBiasSlopeFactor
)
2098 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2099 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2101 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2105 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2106 const float blendConstants
[4])
2108 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2109 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2111 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2112 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2116 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2117 float minDepthBounds
,
2118 float maxDepthBounds
)
2120 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2121 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2123 tu_cs_emit_regs(&cs
,
2124 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2125 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2129 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2131 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2132 *value
= (*value
& 0xff00) | (mask
& 0xff);
2133 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2134 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2138 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2139 VkStencilFaceFlags faceMask
,
2140 uint32_t compareMask
)
2142 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2143 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2145 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2147 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2151 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2152 VkStencilFaceFlags faceMask
,
2155 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2156 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2158 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2160 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2164 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2165 VkStencilFaceFlags faceMask
,
2168 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2169 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2171 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2173 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2177 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2178 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2180 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2181 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2183 assert(pSampleLocationsInfo
);
2185 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2189 tu_flush_for_access(struct tu_cache_state
*cache
,
2190 enum tu_cmd_access_mask src_mask
,
2191 enum tu_cmd_access_mask dst_mask
)
2193 enum tu_cmd_flush_bits flush_bits
= 0;
2195 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2196 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2199 #define SRC_FLUSH(domain, flush, invalidate) \
2200 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2201 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2202 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2205 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2206 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2207 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2211 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2212 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2213 flush_bits |= TU_CMD_FLAG_##flush; \
2214 cache->pending_flush_bits |= \
2215 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2218 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2219 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2221 #undef SRC_INCOHERENT_FLUSH
2223 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
)) {
2224 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2227 #define DST_FLUSH(domain, flush, invalidate) \
2228 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2229 TU_ACCESS_##domain##_WRITE)) { \
2230 flush_bits |= cache->pending_flush_bits & \
2231 (TU_CMD_FLAG_##invalidate | \
2232 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2235 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2236 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2237 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2241 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2242 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2243 TU_ACCESS_##domain##_WRITE)) { \
2244 flush_bits |= TU_CMD_FLAG_##invalidate | \
2245 (cache->pending_flush_bits & \
2246 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2249 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2250 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2252 #undef DST_INCOHERENT_FLUSH
2254 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2255 flush_bits
|= TU_CMD_FLAG_WFI
;
2258 cache
->flush_bits
|= flush_bits
;
2259 cache
->pending_flush_bits
&= ~flush_bits
;
2262 static enum tu_cmd_access_mask
2263 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2265 enum tu_cmd_access_mask mask
= 0;
2267 /* If the GPU writes a buffer that is then read by an indirect draw
2268 * command, we theoretically need a WFI + WAIT_FOR_ME combination to
2269 * wait for the writes to complete. The WAIT_FOR_ME is performed as part
2270 * of the draw by the firmware, so we just need to execute a WFI.
2273 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2274 VK_ACCESS_MEMORY_READ_BIT
)) {
2275 mask
|= TU_ACCESS_WFI_READ
;
2279 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2280 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP, I think */
2281 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2282 VK_ACCESS_HOST_READ_BIT
| /* sysmem by definition */
2283 VK_ACCESS_MEMORY_READ_BIT
)) {
2284 mask
|= TU_ACCESS_SYSMEM_READ
;
2288 (VK_ACCESS_HOST_WRITE_BIT
|
2289 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
| /* Write performed by CP, I think */
2290 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2291 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2295 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2296 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2297 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2298 /* TODO: Is there a no-cache bit for textures so that we can ignore
2301 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2302 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2303 VK_ACCESS_MEMORY_READ_BIT
)) {
2304 mask
|= TU_ACCESS_UCHE_READ
;
2308 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2309 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2310 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2311 mask
|= TU_ACCESS_UCHE_WRITE
;
2314 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2315 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2316 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2317 * can ignore CCU and pretend that color attachments and transfers use
2322 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2323 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2324 VK_ACCESS_MEMORY_READ_BIT
)) {
2326 mask
|= TU_ACCESS_SYSMEM_READ
;
2328 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2332 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2333 VK_ACCESS_MEMORY_READ_BIT
)) {
2335 mask
|= TU_ACCESS_SYSMEM_READ
;
2337 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2341 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2342 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2344 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2346 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2351 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2352 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2354 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2356 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2360 /* When the dst access is a transfer read/write, it seems we sometimes need
2361 * to insert a WFI after any flushes, to guarantee that the flushes finish
2362 * before the 2D engine starts. However the opposite (i.e. a WFI after
2363 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2364 * the blob doesn't emit such a WFI.
2368 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2369 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2371 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2373 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2375 mask
|= TU_ACCESS_WFI_READ
;
2379 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2380 VK_ACCESS_MEMORY_READ_BIT
)) {
2381 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2389 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2390 uint32_t commandBufferCount
,
2391 const VkCommandBuffer
*pCmdBuffers
)
2393 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2396 assert(commandBufferCount
> 0);
2398 /* Emit any pending flushes. */
2399 if (cmd
->state
.pass
) {
2400 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2401 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2403 tu_flush_all_pending(&cmd
->state
.cache
);
2404 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2407 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2408 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2410 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2411 if (result
!= VK_SUCCESS
) {
2412 cmd
->record_result
= result
;
2416 if (secondary
->usage_flags
&
2417 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2418 assert(tu_cs_is_empty(&secondary
->cs
));
2420 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2421 if (result
!= VK_SUCCESS
) {
2422 cmd
->record_result
= result
;
2426 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2427 &secondary
->draw_epilogue_cs
);
2428 if (result
!= VK_SUCCESS
) {
2429 cmd
->record_result
= result
;
2433 if (secondary
->has_tess
)
2434 cmd
->has_tess
= true;
2436 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2437 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2439 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2440 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2441 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2444 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2447 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2449 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2451 /* After executing secondary command buffers, there may have been arbitrary
2452 * flushes executed, so when we encounter a pipeline barrier with a
2453 * srcMask, we have to assume that we need to invalidate. Therefore we need
2454 * to re-initialize the cache with all pending invalidate bits set.
2456 if (cmd
->state
.pass
) {
2457 tu_cache_init(&cmd
->state
.renderpass_cache
);
2459 tu_cache_init(&cmd
->state
.cache
);
2464 tu_CreateCommandPool(VkDevice _device
,
2465 const VkCommandPoolCreateInfo
*pCreateInfo
,
2466 const VkAllocationCallbacks
*pAllocator
,
2467 VkCommandPool
*pCmdPool
)
2469 TU_FROM_HANDLE(tu_device
, device
, _device
);
2470 struct tu_cmd_pool
*pool
;
2472 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2473 VK_OBJECT_TYPE_COMMAND_POOL
);
2475 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2478 pool
->alloc
= *pAllocator
;
2480 pool
->alloc
= device
->vk
.alloc
;
2482 list_inithead(&pool
->cmd_buffers
);
2483 list_inithead(&pool
->free_cmd_buffers
);
2485 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2487 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2493 tu_DestroyCommandPool(VkDevice _device
,
2494 VkCommandPool commandPool
,
2495 const VkAllocationCallbacks
*pAllocator
)
2497 TU_FROM_HANDLE(tu_device
, device
, _device
);
2498 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2503 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2504 &pool
->cmd_buffers
, pool_link
)
2506 tu_cmd_buffer_destroy(cmd_buffer
);
2509 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2510 &pool
->free_cmd_buffers
, pool_link
)
2512 tu_cmd_buffer_destroy(cmd_buffer
);
2515 vk_object_free(&device
->vk
, pAllocator
, pool
);
2519 tu_ResetCommandPool(VkDevice device
,
2520 VkCommandPool commandPool
,
2521 VkCommandPoolResetFlags flags
)
2523 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2526 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2529 result
= tu_reset_cmd_buffer(cmd_buffer
);
2530 if (result
!= VK_SUCCESS
)
2538 tu_TrimCommandPool(VkDevice device
,
2539 VkCommandPool commandPool
,
2540 VkCommandPoolTrimFlags flags
)
2542 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2547 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2548 &pool
->free_cmd_buffers
, pool_link
)
2550 tu_cmd_buffer_destroy(cmd_buffer
);
2555 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2556 const struct tu_subpass_barrier
*barrier
,
2559 /* Note: we don't know until the end of the subpass whether we'll use
2560 * sysmem, so assume sysmem here to be safe.
2562 struct tu_cache_state
*cache
=
2563 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2564 enum tu_cmd_access_mask src_flags
=
2565 vk2tu_access(barrier
->src_access_mask
, false);
2566 enum tu_cmd_access_mask dst_flags
=
2567 vk2tu_access(barrier
->dst_access_mask
, false);
2569 if (barrier
->incoherent_ccu_color
)
2570 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2571 if (barrier
->incoherent_ccu_depth
)
2572 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2574 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2578 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2579 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2580 VkSubpassContents contents
)
2582 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2583 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2584 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2586 cmd
->state
.pass
= pass
;
2587 cmd
->state
.subpass
= pass
->subpasses
;
2588 cmd
->state
.framebuffer
= fb
;
2589 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2591 tu_cmd_prepare_tile_store_ib(cmd
);
2593 /* Note: because this is external, any flushes will happen before draw_cs
2594 * gets called. However deferred flushes could have to happen later as part
2597 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2598 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2599 cmd
->state
.cache
.pending_flush_bits
;
2600 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2602 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2604 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2605 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2606 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2607 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2609 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2611 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2612 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2613 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2614 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2617 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2621 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2622 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2623 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2625 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2626 pSubpassBeginInfo
->contents
);
2630 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2632 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2633 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2634 struct tu_cs
*cs
= &cmd
->draw_cs
;
2636 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2638 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2640 if (subpass
->resolve_attachments
) {
2641 tu6_emit_blit_scissor(cmd
, cs
, true);
2643 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2644 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2645 if (a
== VK_ATTACHMENT_UNUSED
)
2648 tu_store_gmem_attachment(cmd
, cs
, a
,
2649 subpass
->color_attachments
[i
].attachment
);
2651 if (pass
->attachments
[a
].gmem_offset
< 0)
2655 * check if the resolved attachment is needed by later subpasses,
2656 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2658 tu_finishme("missing GMEM->GMEM resolve path\n");
2659 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2663 tu_cond_exec_end(cs
);
2665 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2667 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2669 tu_cond_exec_end(cs
);
2671 /* Handle dependencies for the next subpass */
2672 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2674 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2675 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2676 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2677 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2678 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2680 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2684 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2685 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2686 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2688 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2692 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2693 struct tu_descriptor_state
*descriptors_state
,
2694 gl_shader_stage type
,
2695 uint32_t *push_constants
)
2697 const struct tu_program_descriptor_linkage
*link
=
2698 &pipeline
->program
.link
[type
];
2699 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2701 if (link
->push_consts
.count
> 0) {
2702 unsigned num_units
= link
->push_consts
.count
;
2703 unsigned offset
= link
->push_consts
.lo
;
2704 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2705 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2706 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2707 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2708 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2709 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2712 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2713 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2716 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2717 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2718 uint32_t offset
= state
->range
[i
].start
;
2720 /* and even if the start of the const buffer is before
2721 * first_immediate, the end may not be:
2723 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2728 /* things should be aligned to vec4: */
2729 debug_assert((state
->range
[i
].offset
% 16) == 0);
2730 debug_assert((size
% 16) == 0);
2731 debug_assert((offset
% 16) == 0);
2733 /* Dig out the descriptor from the descriptor state and read the VA from
2736 assert(state
->range
[i
].ubo
.bindless
);
2737 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2738 descriptors_state
->dynamic_descriptors
:
2739 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2740 unsigned block
= state
->range
[i
].ubo
.block
;
2741 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2742 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2745 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2746 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2747 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2748 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2749 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2750 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2751 tu_cs_emit_qw(cs
, va
+ offset
);
2755 static struct tu_draw_state
2756 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2757 const struct tu_pipeline
*pipeline
,
2758 struct tu_descriptor_state
*descriptors_state
,
2759 gl_shader_stage type
)
2762 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2764 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2766 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2769 static struct tu_draw_state
2770 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2771 const struct tu_pipeline
*pipeline
)
2774 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2777 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2778 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2779 const VkDeviceSize offset
= buf
->bo_offset
+
2780 cmd
->state
.vb
.offsets
[binding
];
2782 tu_cs_emit_regs(&cs
,
2783 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2784 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2788 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2790 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2794 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2795 uint32_t draw_count
)
2797 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2798 * Still not sure what to do here, so just allocate a reasonably large
2799 * BO and hope for the best for now. */
2803 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2804 * which includes both the per-vertex outputs and per-patch outputs
2805 * build_primitive_map in ir3 calculates this stride
2807 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2808 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2809 return num_patches
* pipeline
->tess
.param_stride
;
2813 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2814 uint32_t draw_count
)
2816 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2817 * Still not sure what to do here, so just allocate a reasonably large
2818 * BO and hope for the best for now. */
2822 /* Each distinct patch gets its own tess factor output. */
2823 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2824 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2825 uint32_t factor_stride
;
2826 switch (pipeline
->tess
.patch_type
) {
2827 case IR3_TESS_ISOLINES
:
2830 case IR3_TESS_TRIANGLES
:
2833 case IR3_TESS_QUADS
:
2837 unreachable("bad tessmode");
2839 return factor_stride
* num_patches
;
2843 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2844 uint32_t draw_count
,
2845 const struct tu_pipeline
*pipeline
,
2846 struct tu_draw_state
*state
)
2849 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 20, &cs
);
2850 if (result
!= VK_SUCCESS
)
2853 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2854 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2855 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2856 if (tess_bo_size
> 0) {
2857 struct tu_bo
*tess_bo
;
2858 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2859 if (result
!= VK_SUCCESS
)
2862 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2863 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2864 uint64_t tess_factor_iova
= tess_bo
->iova
;
2865 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2867 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2868 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2869 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2870 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2871 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2872 CP_LOAD_STATE6_0_NUM_UNIT(1));
2873 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2874 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2875 tu_cs_emit_qw(&cs
, tess_param_iova
);
2876 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2878 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2879 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2880 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2881 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2882 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2883 CP_LOAD_STATE6_0_NUM_UNIT(1));
2884 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2885 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2886 tu_cs_emit_qw(&cs
, tess_param_iova
);
2887 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2889 tu_cs_emit_pkt4(&cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
2890 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2892 /* TODO: Without this WFI here, the hardware seems unable to read these
2893 * addresses we just emitted. Freedreno emits these consts as part of
2894 * IB1 instead of in a draw state which might make this WFI unnecessary,
2895 * but it requires a bit more indirection (SS6_INDIRECT for consts). */
2896 tu_cs_emit_wfi(&cs
);
2898 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2903 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2906 /* note: draw_count is 0 for indirect */
2907 uint32_t draw_count
)
2909 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2912 struct tu_descriptor_state
*descriptors_state
=
2913 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2915 tu_emit_cache_flush_renderpass(cmd
, cs
);
2919 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
2920 .primitive_restart
=
2921 pipeline
->ia
.primitive_restart
&& indexed
,
2922 .tess_upper_left_domain_origin
=
2923 pipeline
->tess
.upper_left_domain_origin
));
2925 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
2926 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
2927 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
2928 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
2929 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
2930 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
2931 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
2932 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
2933 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
2934 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
2935 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
2938 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
2939 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
2942 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
2943 struct tu_draw_state tess_consts
= {};
2945 cmd
->has_tess
= true;
2946 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
);
2947 if (result
!= VK_SUCCESS
)
2951 /* for the first draw in a renderpass, re-emit all the draw states
2953 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
2954 * used, then draw states must be re-emitted. note however this only happens
2955 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
2957 * the two input attachment states are excluded because secondary command
2958 * buffer doesn't have a state ib to restore it, and not re-emitting them
2959 * is OK since CmdClearAttachments won't disable/overwrite them
2961 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
2962 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
2964 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2965 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2966 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
2967 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2968 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2969 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2970 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2971 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2972 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
2973 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
2974 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
2975 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
2976 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
2977 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
2978 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
2979 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
2980 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
2982 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
2983 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
2984 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
2985 cmd
->state
.dynamic_state
[i
] :
2986 pipeline
->dynamic_state
[i
]));
2990 /* emit draw states that were just updated
2991 * note we eventually don't want to have to emit anything here
2993 uint32_t draw_state_count
=
2995 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
2996 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
2997 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3000 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3002 /* We may need to re-emit tess consts if the current draw call is
3003 * sufficiently larger than the last draw call. */
3005 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3006 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3007 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3008 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3009 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3010 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3011 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3013 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3014 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3015 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3016 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3017 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3020 tu_cs_sanity_check(cs
);
3022 /* There are too many graphics dirty bits to list here, so just list the
3023 * bits to preserve instead. The only things not emitted here are
3024 * compute-related state.
3026 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3031 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3033 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3034 uint32_t initiator
=
3035 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3036 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3037 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3038 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3040 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3041 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3043 switch (pipeline
->tess
.patch_type
) {
3044 case IR3_TESS_TRIANGLES
:
3045 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3046 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3048 case IR3_TESS_ISOLINES
:
3049 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3050 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3053 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3055 case IR3_TESS_QUADS
:
3056 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3057 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3065 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3067 const struct tu_program_descriptor_linkage
*link
=
3068 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3069 const struct ir3_const_state
*const_state
= &link
->const_state
;
3071 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3074 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3075 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3076 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3077 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3079 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3080 assert(const_state
->offsets
.driver_param
!= 0);
3082 return const_state
->offsets
.driver_param
;
3085 static struct tu_draw_state
3086 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3087 uint32_t vertex_offset
,
3088 uint32_t first_instance
)
3090 uint32_t offset
= vs_params_offset(cmd
);
3093 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3094 if (result
!= VK_SUCCESS
) {
3095 cmd
->record_result
= result
;
3096 return (struct tu_draw_state
) {};
3099 /* TODO: don't make a new draw state when it doesn't change */
3101 tu_cs_emit_regs(&cs
,
3102 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3103 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3106 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3107 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3108 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3109 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3110 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3111 CP_LOAD_STATE6_0_NUM_UNIT(1));
3116 tu_cs_emit(&cs
, vertex_offset
);
3117 tu_cs_emit(&cs
, first_instance
);
3121 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3122 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3126 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3127 uint32_t vertexCount
,
3128 uint32_t instanceCount
,
3129 uint32_t firstVertex
,
3130 uint32_t firstInstance
)
3132 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3133 struct tu_cs
*cs
= &cmd
->draw_cs
;
3135 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3137 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3139 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3140 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3141 tu_cs_emit(cs
, instanceCount
);
3142 tu_cs_emit(cs
, vertexCount
);
3146 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3147 uint32_t indexCount
,
3148 uint32_t instanceCount
,
3149 uint32_t firstIndex
,
3150 int32_t vertexOffset
,
3151 uint32_t firstInstance
)
3153 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3154 struct tu_cs
*cs
= &cmd
->draw_cs
;
3156 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3158 tu6_draw_common(cmd
, cs
, true, indexCount
);
3160 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3161 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3162 tu_cs_emit(cs
, instanceCount
);
3163 tu_cs_emit(cs
, indexCount
);
3164 tu_cs_emit(cs
, firstIndex
);
3165 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3166 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3170 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3172 VkDeviceSize offset
,
3176 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3177 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3178 struct tu_cs
*cs
= &cmd
->draw_cs
;
3180 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3182 tu6_draw_common(cmd
, cs
, false, 0);
3184 /* workaround for a firmware bug with CP_DRAW_INDIRECT_MULTI, where it
3185 * doesn't wait for WFIs to be completed and leads to GPU fault/hang
3186 * TODO: this could be worked around in a more performant way,
3187 * or there may exist newer firmware that has been fixed
3189 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3190 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
3192 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3193 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3194 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3195 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3196 tu_cs_emit(cs
, drawCount
);
3197 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3198 tu_cs_emit(cs
, stride
);
3200 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3204 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3206 VkDeviceSize offset
,
3210 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3211 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3212 struct tu_cs
*cs
= &cmd
->draw_cs
;
3214 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3216 tu6_draw_common(cmd
, cs
, true, 0);
3218 /* workaround for a firmware bug with CP_DRAW_INDIRECT_MULTI, where it
3219 * doesn't wait for WFIs to be completed and leads to GPU fault/hang
3220 * TODO: this could be worked around in a more performant way,
3221 * or there may exist newer firmware that has been fixed
3223 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3224 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
3226 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3227 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3228 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3229 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3230 tu_cs_emit(cs
, drawCount
);
3231 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3232 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3233 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3234 tu_cs_emit(cs
, stride
);
3236 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3239 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3240 uint32_t instanceCount
,
3241 uint32_t firstInstance
,
3242 VkBuffer _counterBuffer
,
3243 VkDeviceSize counterBufferOffset
,
3244 uint32_t counterOffset
,
3245 uint32_t vertexStride
)
3247 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3248 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3249 struct tu_cs
*cs
= &cmd
->draw_cs
;
3251 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3253 tu6_draw_common(cmd
, cs
, false, 0);
3255 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3256 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3257 tu_cs_emit(cs
, instanceCount
);
3258 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3259 tu_cs_emit(cs
, counterOffset
);
3260 tu_cs_emit(cs
, vertexStride
);
3262 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3265 struct tu_dispatch_info
3268 * Determine the layout of the grid (in block units) to be used.
3273 * A starting offset for the grid. If unaligned is set, the offset
3274 * must still be aligned.
3276 uint32_t offsets
[3];
3278 * Whether it's an unaligned compute dispatch.
3283 * Indirect compute parameters resource.
3285 struct tu_buffer
*indirect
;
3286 uint64_t indirect_offset
;
3290 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3291 const struct tu_dispatch_info
*info
)
3293 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3294 const struct tu_program_descriptor_linkage
*link
=
3295 &pipeline
->program
.link
[type
];
3296 const struct ir3_const_state
*const_state
= &link
->const_state
;
3297 uint32_t offset
= const_state
->offsets
.driver_param
;
3299 if (link
->constlen
<= offset
)
3302 if (!info
->indirect
) {
3303 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3304 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3305 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3306 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3307 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3308 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3309 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3312 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3313 (link
->constlen
- offset
) * 4);
3314 /* push constants */
3315 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3316 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3317 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3318 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3319 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3320 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3324 for (i
= 0; i
< num_consts
; i
++)
3325 tu_cs_emit(cs
, driver_params
[i
]);
3327 tu_finishme("Indirect driver params");
3332 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3333 const struct tu_dispatch_info
*info
)
3335 struct tu_cs
*cs
= &cmd
->cs
;
3336 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3337 struct tu_descriptor_state
*descriptors_state
=
3338 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3340 /* TODO: We could probably flush less if we add a compute_flush_bits
3343 tu_emit_cache_flush(cmd
, cs
);
3345 /* note: no reason to have this in a separate IB */
3346 tu_cs_emit_state_ib(cs
,
3347 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3349 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3351 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3352 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3354 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3356 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3357 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3359 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3360 const uint32_t *num_groups
= info
->blocks
;
3362 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3363 .localsizex
= local_size
[0] - 1,
3364 .localsizey
= local_size
[1] - 1,
3365 .localsizez
= local_size
[2] - 1),
3366 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3367 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3368 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3369 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3370 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3371 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3374 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3375 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3376 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3378 if (info
->indirect
) {
3379 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3381 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3382 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3384 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3385 tu_cs_emit(cs
, 0x00000000);
3386 tu_cs_emit_qw(cs
, iova
);
3388 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3389 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3390 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3392 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3393 tu_cs_emit(cs
, 0x00000000);
3394 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3395 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3396 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3403 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3411 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3412 struct tu_dispatch_info info
= {};
3418 info
.offsets
[0] = base_x
;
3419 info
.offsets
[1] = base_y
;
3420 info
.offsets
[2] = base_z
;
3421 tu_dispatch(cmd_buffer
, &info
);
3425 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3430 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3434 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3436 VkDeviceSize offset
)
3438 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3439 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3440 struct tu_dispatch_info info
= {};
3442 info
.indirect
= buffer
;
3443 info
.indirect_offset
= offset
;
3445 tu_dispatch(cmd_buffer
, &info
);
3449 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3451 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3453 tu_cs_end(&cmd_buffer
->draw_cs
);
3454 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3456 if (use_sysmem_rendering(cmd_buffer
))
3457 tu_cmd_render_sysmem(cmd_buffer
);
3459 tu_cmd_render_tiles(cmd_buffer
);
3461 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3463 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3464 tu_cs_begin(&cmd_buffer
->draw_cs
);
3465 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3466 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3468 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3469 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3470 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3472 cmd_buffer
->state
.pass
= NULL
;
3473 cmd_buffer
->state
.subpass
= NULL
;
3474 cmd_buffer
->state
.framebuffer
= NULL
;
3478 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3479 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3481 tu_CmdEndRenderPass(commandBuffer
);
3484 struct tu_barrier_info
3486 uint32_t eventCount
;
3487 const VkEvent
*pEvents
;
3488 VkPipelineStageFlags srcStageMask
;
3492 tu_barrier(struct tu_cmd_buffer
*cmd
,
3493 uint32_t memoryBarrierCount
,
3494 const VkMemoryBarrier
*pMemoryBarriers
,
3495 uint32_t bufferMemoryBarrierCount
,
3496 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3497 uint32_t imageMemoryBarrierCount
,
3498 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3499 const struct tu_barrier_info
*info
)
3501 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3502 VkAccessFlags srcAccessMask
= 0;
3503 VkAccessFlags dstAccessMask
= 0;
3505 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3506 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3507 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3510 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3511 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3512 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3515 enum tu_cmd_access_mask src_flags
= 0;
3516 enum tu_cmd_access_mask dst_flags
= 0;
3518 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3519 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3520 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3521 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3522 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3523 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3524 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3525 /* The underlying memory for this image may have been used earlier
3526 * within the same queue submission for a different image, which
3527 * means that there may be old, stale cache entries which are in the
3528 * "wrong" location, which could cause problems later after writing
3529 * to the image. We don't want these entries being flushed later and
3530 * overwriting the actual image, so we need to flush the CCU.
3532 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3534 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3535 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3538 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3539 * so we have to use the sysmem flushes.
3541 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3543 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3544 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3546 struct tu_cache_state
*cache
=
3547 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3548 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3550 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3551 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3553 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3555 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3556 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3557 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3558 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3559 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3560 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3561 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3566 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3567 VkPipelineStageFlags srcStageMask
,
3568 VkPipelineStageFlags dstStageMask
,
3569 VkDependencyFlags dependencyFlags
,
3570 uint32_t memoryBarrierCount
,
3571 const VkMemoryBarrier
*pMemoryBarriers
,
3572 uint32_t bufferMemoryBarrierCount
,
3573 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3574 uint32_t imageMemoryBarrierCount
,
3575 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3577 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3578 struct tu_barrier_info info
;
3580 info
.eventCount
= 0;
3581 info
.pEvents
= NULL
;
3582 info
.srcStageMask
= srcStageMask
;
3584 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3585 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3586 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3590 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3591 VkPipelineStageFlags stageMask
, unsigned value
)
3593 struct tu_cs
*cs
= &cmd
->cs
;
3595 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3596 assert(!cmd
->state
.pass
);
3598 tu_emit_cache_flush(cmd
, cs
);
3600 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3602 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3603 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3605 VkPipelineStageFlags top_of_pipe_flags
=
3606 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3607 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3609 if (!(stageMask
& ~top_of_pipe_flags
)) {
3610 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3611 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3612 tu_cs_emit(cs
, value
);
3614 /* Use a RB_DONE_TS event to wait for everything to complete. */
3615 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3616 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3617 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3618 tu_cs_emit(cs
, value
);
3623 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3625 VkPipelineStageFlags stageMask
)
3627 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3628 TU_FROM_HANDLE(tu_event
, event
, _event
);
3630 write_event(cmd
, event
, stageMask
, 1);
3634 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3636 VkPipelineStageFlags stageMask
)
3638 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3639 TU_FROM_HANDLE(tu_event
, event
, _event
);
3641 write_event(cmd
, event
, stageMask
, 0);
3645 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3646 uint32_t eventCount
,
3647 const VkEvent
*pEvents
,
3648 VkPipelineStageFlags srcStageMask
,
3649 VkPipelineStageFlags dstStageMask
,
3650 uint32_t memoryBarrierCount
,
3651 const VkMemoryBarrier
*pMemoryBarriers
,
3652 uint32_t bufferMemoryBarrierCount
,
3653 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3654 uint32_t imageMemoryBarrierCount
,
3655 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3657 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3658 struct tu_barrier_info info
;
3660 info
.eventCount
= eventCount
;
3661 info
.pEvents
= pEvents
;
3662 info
.srcStageMask
= 0;
3664 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3665 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3666 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3670 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)