2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
118 const uint32_t tile_align_w
= 64; /* note: 32 when no input attachments */
119 const uint32_t tile_align_h
= 16;
120 const uint32_t max_tile_width
= 1024;
122 /* note: don't offset the tiling config by render_area.offset,
123 * because binning pass can't deal with it
124 * this means we might end up with more tiles than necessary,
125 * but load/store/etc are still scissored to the render_area
127 tiling
->tile0
.offset
= (VkOffset2D
) {};
129 const uint32_t ra_width
=
130 tiling
->render_area
.extent
.width
+
131 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
132 const uint32_t ra_height
=
133 tiling
->render_area
.extent
.height
+
134 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
136 /* start from 1 tile */
137 tiling
->tile_count
= (VkExtent2D
) {
141 tiling
->tile0
.extent
= (VkExtent2D
) {
142 .width
= align(ra_width
, tile_align_w
),
143 .height
= align(ra_height
, tile_align_h
),
146 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
147 /* start with 2x2 tiles */
148 tiling
->tile_count
.width
= 2;
149 tiling
->tile_count
.height
= 2;
150 tiling
->tile0
.extent
.width
= align(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
151 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), tile_align_h
);
154 /* do not exceed max tile width */
155 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
156 tiling
->tile_count
.width
++;
157 tiling
->tile0
.extent
.width
=
158 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
161 /* will force to sysmem, don't bother trying to have a valid tile config
162 * TODO: just skip all GMEM stuff when sysmem is forced?
167 /* do not exceed gmem size */
168 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pixels
) {
169 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
170 tiling
->tile_count
.width
++;
171 tiling
->tile0
.extent
.width
=
172 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
174 /* if this assert fails then layout is impossible.. */
175 assert(tiling
->tile0
.extent
.height
> tile_align_h
);
176 tiling
->tile_count
.height
++;
177 tiling
->tile0
.extent
.height
=
178 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), tile_align_h
);
184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
185 const struct tu_device
*dev
)
187 const uint32_t max_pipe_count
= 32; /* A6xx */
189 /* start from 1 tile per pipe */
190 tiling
->pipe0
= (VkExtent2D
) {
194 tiling
->pipe_count
= tiling
->tile_count
;
196 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
197 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
198 tiling
->pipe0
.width
+= 1;
199 tiling
->pipe_count
.width
=
200 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
202 tiling
->pipe0
.height
+= 1;
203 tiling
->pipe_count
.height
=
204 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
210 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
211 const struct tu_device
*dev
)
213 const uint32_t max_pipe_count
= 32; /* A6xx */
214 const uint32_t used_pipe_count
=
215 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
216 const VkExtent2D last_pipe
= {
217 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
218 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
221 assert(used_pipe_count
<= max_pipe_count
);
222 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
224 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
225 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
226 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
227 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
228 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
230 : tiling
->pipe0
.width
;
231 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
233 : tiling
->pipe0
.height
;
234 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
236 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
237 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
238 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
239 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
240 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
244 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
245 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
249 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
250 const struct tu_device
*dev
,
253 struct tu_tile
*tile
)
255 /* find the pipe and the slot for tile (tx, ty) */
256 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
257 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
258 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
259 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
260 /* last pipe has different width */
261 const uint32_t pipe_width
=
262 MIN2(tiling
->pipe0
.width
,
263 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
265 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
266 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
267 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
269 /* convert to 1D indices */
270 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
271 tile
->slot
= pipe_width
* sy
+ sx
;
273 /* get the blit area for the tile */
274 tile
->begin
= (VkOffset2D
) {
275 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
276 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
279 (tx
== tiling
->tile_count
.width
- 1)
280 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
281 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
283 (ty
== tiling
->tile_count
.height
- 1)
284 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
285 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
288 enum a3xx_msaa_samples
289 tu_msaa_samples(uint32_t samples
)
301 assert(!"invalid sample count");
306 static enum a4xx_index_size
307 tu6_index_size(VkIndexType type
)
310 case VK_INDEX_TYPE_UINT16
:
311 return INDEX4_SIZE_16_BIT
;
312 case VK_INDEX_TYPE_UINT32
:
313 return INDEX4_SIZE_32_BIT
;
315 unreachable("invalid VkIndexType");
316 return INDEX4_SIZE_8_BIT
;
321 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
323 enum vgt_event_type event
,
328 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
329 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
331 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
332 seqno
= ++cmd
->scratch_seqno
;
333 tu_cs_emit(cs
, seqno
);
340 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
342 tu6_emit_event_write(cmd
, cs
, 0x31, false);
346 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
348 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
352 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
354 if (cmd
->wait_for_idle
) {
356 cmd
->wait_for_idle
= false;
361 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
362 const struct tu_subpass
*subpass
,
365 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
367 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
368 if (a
== VK_ATTACHMENT_UNUSED
) {
370 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
371 A6XX_RB_DEPTH_BUFFER_PITCH(0),
372 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
373 A6XX_RB_DEPTH_BUFFER_BASE(0),
374 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
377 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
380 A6XX_GRAS_LRZ_BUFFER_BASE(0),
381 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
382 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
384 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
389 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
390 const struct tu_render_pass_attachment
*attachment
=
391 &cmd
->state
.pass
->attachments
[a
];
392 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
394 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
395 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
396 tu_cs_image_ref(cs
, iview
, 0);
397 tu_cs_emit(cs
, attachment
->gmem_offset
);
400 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
402 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
403 tu_cs_image_flag_ref(cs
, iview
, 0);
406 A6XX_GRAS_LRZ_BUFFER_BASE(0),
407 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
408 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
410 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
411 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
412 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
413 tu_cs_image_ref(cs
, iview
, 0);
414 tu_cs_emit(cs
, attachment
->gmem_offset
);
417 A6XX_RB_STENCIL_INFO(0));
422 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
423 const struct tu_subpass
*subpass
,
426 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
428 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
429 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
430 if (a
== VK_ATTACHMENT_UNUSED
)
433 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
435 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
436 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
437 tu_cs_image_ref(cs
, iview
, 0);
438 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
441 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
443 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
444 tu_cs_image_flag_ref(cs
, iview
, 0);
448 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
450 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
453 A6XX_RB_RENDER_COMPONENTS(.dword
= subpass
->render_components
));
455 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= subpass
->render_components
));
457 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
461 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
463 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
464 bool msaa_disable
= samples
== MSAA_ONE
;
467 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
468 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
469 .msaa_disable
= msaa_disable
));
472 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
473 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
474 .msaa_disable
= msaa_disable
));
477 A6XX_RB_RAS_MSAA_CNTL(samples
),
478 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
479 .msaa_disable
= msaa_disable
));
482 A6XX_RB_MSAA_CNTL(samples
));
486 tu6_emit_bin_size(struct tu_cs
*cs
,
487 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
490 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
495 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
499 /* no flag for RB_BIN_CONTROL2... */
501 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
506 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
507 const struct tu_subpass
*subpass
,
511 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
513 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
515 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
517 uint32_t mrts_ubwc_enable
= 0;
518 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
519 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
520 if (a
== VK_ATTACHMENT_UNUSED
)
523 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
524 if (iview
->ubwc_enabled
)
525 mrts_ubwc_enable
|= 1 << i
;
528 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
530 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
531 if (a
!= VK_ATTACHMENT_UNUSED
) {
532 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
533 if (iview
->ubwc_enabled
)
534 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
537 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
538 * in order to set it correctly for the different subpasses. However,
539 * that means the packets we're emitting also happen during binning. So
540 * we need to guard the write on !BINNING at CP execution time.
542 tu_cs_reserve(cs
, 3 + 4);
543 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
544 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
545 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
546 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
549 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
550 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
551 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
552 tu_cs_emit(cs
, cntl
);
556 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
558 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
559 uint32_t x1
= render_area
->offset
.x
;
560 uint32_t y1
= render_area
->offset
.y
;
561 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
562 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
565 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
566 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
567 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
568 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
572 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
573 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
577 tu6_emit_window_scissor(struct tu_cs
*cs
,
584 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
585 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
588 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
589 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
593 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
596 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
599 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
602 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
605 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
609 use_hw_binning(struct tu_cmd_buffer
*cmd
)
611 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
613 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
616 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
619 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
623 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
625 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
628 /* can't fit attachments into gmem */
629 if (!cmd
->state
.pass
->gmem_pixels
)
632 if (cmd
->state
.framebuffer
->layers
> 1)
635 return cmd
->state
.tiling_config
.force_sysmem
;
639 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
641 const struct tu_tile
*tile
)
643 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
644 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
646 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
647 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
649 const uint32_t x1
= tile
->begin
.x
;
650 const uint32_t y1
= tile
->begin
.y
;
651 const uint32_t x2
= tile
->end
.x
- 1;
652 const uint32_t y2
= tile
->end
.y
- 1;
653 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
654 tu6_emit_window_offset(cs
, x1
, y1
);
657 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
659 if (use_hw_binning(cmd
)) {
660 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
662 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
665 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
666 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
667 A6XX_CP_REG_TEST_0_BIT(0) |
668 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
670 tu_cs_reserve(cs
, 3 + 11);
671 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
672 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
673 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
675 /* if (no overflow) */ {
676 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
677 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
678 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
679 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
680 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
681 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
683 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
686 /* use a NOP packet to skip over the 'else' side: */
687 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
689 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
693 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
696 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
699 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
705 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
710 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
711 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
712 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
714 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
718 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
720 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
721 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
723 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
724 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
725 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
726 CP_SET_DRAW_STATE__0_GROUP_ID(0));
727 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
728 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
730 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
733 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
734 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
736 tu6_emit_blit_scissor(cmd
, cs
, true);
738 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
739 if (pass
->attachments
[a
].gmem_offset
>= 0)
740 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
743 if (subpass
->resolve_attachments
) {
744 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
745 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
746 if (a
!= VK_ATTACHMENT_UNUSED
)
747 tu_store_gmem_attachment(cmd
, cs
, a
,
748 subpass
->color_attachments
[i
].attachment
);
754 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
757 A6XX_PC_RESTART_INDEX(restart_index
));
761 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
763 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
765 tu6_emit_cache_flush(cmd
, cs
);
767 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
770 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
771 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
790 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
791 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
792 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
795 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
797 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
799 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
813 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
816 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
818 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
819 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
822 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
825 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
826 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
827 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
844 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
846 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
848 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
851 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
853 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
855 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
857 /* we don't use this yet.. probably best to disable.. */
858 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
859 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
860 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
861 CP_SET_DRAW_STATE__0_GROUP_ID(0));
862 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
863 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
865 /* Set not to use streamout by default, */
866 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
867 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
869 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
873 A6XX_SP_HS_CTRL_REG0(0));
876 A6XX_SP_GS_CTRL_REG0(0));
879 A6XX_GRAS_LRZ_CNTL(0));
882 A6XX_RB_LRZ_CNTL(0));
885 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
887 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
889 tu_cs_sanity_check(cs
);
893 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
897 seqno
= tu6_emit_event_write(cmd
, cs
, RB_DONE_TS
, true);
899 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
900 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
901 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
902 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
903 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
904 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
905 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
907 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
909 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
910 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
911 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
912 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
916 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
918 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
921 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
922 .height
= tiling
->tile0
.extent
.height
),
923 A6XX_VSC_SIZE_ADDRESS(.bo
= &cmd
->vsc_data
,
924 .bo_offset
= 32 * cmd
->vsc_data_pitch
));
927 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
928 .ny
= tiling
->tile_count
.height
));
930 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
931 for (unsigned i
= 0; i
< 32; i
++)
932 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
935 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo
= &cmd
->vsc_data2
),
936 A6XX_VSC_PIPE_DATA2_PITCH(cmd
->vsc_data2_pitch
),
937 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd
->vsc_data2
.size
));
940 A6XX_VSC_PIPE_DATA_ADDRESS(.bo
= &cmd
->vsc_data
),
941 A6XX_VSC_PIPE_DATA_PITCH(cmd
->vsc_data_pitch
),
942 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd
->vsc_data
.size
));
946 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
948 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
949 const uint32_t used_pipe_count
=
950 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
952 /* Clear vsc_scratch: */
953 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
954 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
957 /* Check for overflow, write vsc_scratch if detected: */
958 for (int i
= 0; i
< used_pipe_count
; i
++) {
959 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
960 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
961 CP_COND_WRITE5_0_WRITE_MEMORY
);
962 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
963 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
964 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
965 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
966 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
967 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
969 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
970 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
971 CP_COND_WRITE5_0_WRITE_MEMORY
);
972 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
973 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
974 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
975 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
976 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
977 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
980 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
982 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
984 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
985 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
986 CP_MEM_TO_REG_0_CNT(1 - 1));
987 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
990 * This is a bit awkward, we really want a way to invert the
991 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
992 * execute cmds to use hwbinning when a bit is *not* set. This
993 * dance is to invert OVERFLOW_FLAG_REG
995 * A CP_NOP packet is used to skip executing the 'else' clause
999 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1000 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1001 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1002 A6XX_CP_REG_TEST_0_BIT(0) |
1003 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1005 tu_cs_reserve(cs
, 3 + 7);
1006 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1007 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1008 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1012 * On overflow, mirror the value to control->vsc_overflow
1013 * which CPU is checking to detect overflow (see
1014 * check_vsc_overflow())
1016 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1017 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1018 CP_REG_TO_MEM_0_CNT(0));
1019 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1021 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1022 tu_cs_emit(cs
, 0x0);
1024 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1026 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1027 tu_cs_emit(cs
, 0x1);
1032 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1034 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1035 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1037 uint32_t x1
= tiling
->tile0
.offset
.x
;
1038 uint32_t y1
= tiling
->tile0
.offset
.y
;
1039 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1040 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1042 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1044 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1045 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1047 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1048 tu_cs_emit(cs
, 0x1);
1050 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1051 tu_cs_emit(cs
, 0x1);
1056 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1058 update_vsc_pipe(cmd
, cs
);
1061 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1064 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1066 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1067 tu_cs_emit(cs
, UNK_2C
);
1070 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1073 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1075 /* emit IB to binning drawcmds: */
1076 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1078 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1079 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1080 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1081 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1082 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1083 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1085 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1086 tu_cs_emit(cs
, UNK_2D
);
1088 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1089 tu6_cache_flush(cmd
, cs
);
1093 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1095 emit_vsc_overflow_test(cmd
, cs
);
1097 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1098 tu_cs_emit(cs
, 0x0);
1100 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1101 tu_cs_emit(cs
, 0x0);
1103 cmd
->wait_for_idle
= false;
1107 tu_emit_load_clear(struct tu_cmd_buffer
*cmd
,
1108 const VkRenderPassBeginInfo
*info
)
1110 struct tu_cs
*cs
= &cmd
->draw_cs
;
1112 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1114 tu6_emit_blit_scissor(cmd
, cs
, true);
1116 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1117 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1119 tu6_emit_blit_scissor(cmd
, cs
, false);
1121 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1122 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1124 tu_cond_exec_end(cs
);
1126 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1128 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1129 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1131 tu_cond_exec_end(cs
);
1135 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1136 const struct VkRect2D
*renderArea
)
1138 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1139 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1141 assert(fb
->width
> 0 && fb
->height
> 0);
1142 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1143 tu6_emit_window_offset(cs
, 0, 0);
1145 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1147 tu6_emit_lrz_flush(cmd
, cs
);
1149 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1150 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1152 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1153 tu_cs_emit(cs
, 0x0);
1155 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1156 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1157 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1159 tu6_emit_wfi(cmd
, cs
);
1161 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
1163 /* enable stream-out, with sysmem there is only one pass: */
1165 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1167 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1168 tu_cs_emit(cs
, 0x1);
1170 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1171 tu_cs_emit(cs
, 0x0);
1173 tu_cs_sanity_check(cs
);
1177 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1179 /* Do any resolves of the last subpass. These are handled in the
1180 * tile_store_ib in the gmem path.
1182 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1183 if (subpass
->resolve_attachments
) {
1184 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
1185 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
1186 if (a
!= VK_ATTACHMENT_UNUSED
)
1187 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
1188 subpass
->color_attachments
[i
].attachment
);
1192 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1194 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1195 tu_cs_emit(cs
, 0x0);
1197 tu6_emit_lrz_flush(cmd
, cs
);
1199 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1200 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1202 tu_cs_sanity_check(cs
);
1207 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1209 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1211 tu6_emit_lrz_flush(cmd
, cs
);
1215 tu6_emit_cache_flush(cmd
, cs
);
1217 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1218 tu_cs_emit(cs
, 0x0);
1220 /* TODO: flushing with barriers instead of blindly always flushing */
1221 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
1222 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
1223 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
, false);
1224 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
, false);
1228 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_gmem
, .gmem
= 1));
1230 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1231 if (use_hw_binning(cmd
)) {
1232 /* enable stream-out during binning pass: */
1233 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1235 tu6_emit_bin_size(cs
,
1236 tiling
->tile0
.extent
.width
,
1237 tiling
->tile0
.extent
.height
,
1238 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1240 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1242 tu6_emit_binning_pass(cmd
, cs
);
1244 /* and disable stream-out for draw pass: */
1245 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1247 tu6_emit_bin_size(cs
,
1248 tiling
->tile0
.extent
.width
,
1249 tiling
->tile0
.extent
.height
,
1250 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1253 A6XX_VFD_MODE_CNTL(0));
1255 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1257 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1259 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1260 tu_cs_emit(cs
, 0x1);
1262 /* no binning pass, so enable stream-out for draw pass:: */
1263 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1265 tu6_emit_bin_size(cs
,
1266 tiling
->tile0
.extent
.width
,
1267 tiling
->tile0
.extent
.height
,
1271 tu_cs_sanity_check(cs
);
1275 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1277 const struct tu_tile
*tile
)
1279 tu6_emit_tile_select(cmd
, cs
, tile
);
1281 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1282 cmd
->wait_for_idle
= true;
1284 if (use_hw_binning(cmd
)) {
1285 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1286 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1287 A6XX_CP_REG_TEST_0_BIT(0) |
1288 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1290 tu_cs_reserve(cs
, 3 + 2);
1291 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1292 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1293 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1295 /* if (no overflow) */ {
1296 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1297 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1301 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1303 tu_cs_sanity_check(cs
);
1307 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1309 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1312 A6XX_GRAS_LRZ_CNTL(0));
1314 tu6_emit_lrz_flush(cmd
, cs
);
1316 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1318 tu_cs_sanity_check(cs
);
1322 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1324 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1326 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1328 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1329 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1330 struct tu_tile tile
;
1331 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1332 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1336 tu6_tile_render_end(cmd
, &cmd
->cs
);
1340 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1342 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1344 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1346 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1347 cmd
->wait_for_idle
= true;
1349 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1353 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1355 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1356 struct tu_cs sub_cs
;
1359 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1360 if (result
!= VK_SUCCESS
) {
1361 cmd
->record_result
= result
;
1365 /* emit to tile-store sub_cs */
1366 tu6_emit_tile_store(cmd
, &sub_cs
);
1368 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1372 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1373 const VkRect2D
*render_area
)
1375 const struct tu_device
*dev
= cmd
->device
;
1376 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1378 tiling
->render_area
= *render_area
;
1379 tiling
->force_sysmem
= false;
1381 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
->gmem_pixels
);
1382 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1383 tu_tiling_config_update_pipes(tiling
, dev
);
1386 const struct tu_dynamic_state default_dynamic_state
= {
1402 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1408 .stencil_compare_mask
=
1413 .stencil_write_mask
=
1418 .stencil_reference
=
1425 static void UNUSED
/* FINISHME */
1426 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1427 const struct tu_dynamic_state
*src
)
1429 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1430 uint32_t copy_mask
= src
->mask
;
1431 uint32_t dest_mask
= 0;
1433 tu_use_args(cmd_buffer
); /* FINISHME */
1435 /* Make sure to copy the number of viewports/scissors because they can
1436 * only be specified at pipeline creation time.
1438 dest
->viewport
.count
= src
->viewport
.count
;
1439 dest
->scissor
.count
= src
->scissor
.count
;
1440 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1442 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1443 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1444 src
->viewport
.count
* sizeof(VkViewport
))) {
1445 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1446 src
->viewport
.count
);
1447 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1451 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1452 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1453 src
->scissor
.count
* sizeof(VkRect2D
))) {
1454 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1455 src
->scissor
.count
);
1456 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1460 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1461 if (dest
->line_width
!= src
->line_width
) {
1462 dest
->line_width
= src
->line_width
;
1463 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1467 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1468 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1469 sizeof(src
->depth_bias
))) {
1470 dest
->depth_bias
= src
->depth_bias
;
1471 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1475 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1476 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1477 sizeof(src
->blend_constants
))) {
1478 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1479 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1483 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1484 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1485 sizeof(src
->depth_bounds
))) {
1486 dest
->depth_bounds
= src
->depth_bounds
;
1487 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1491 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1492 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1493 sizeof(src
->stencil_compare_mask
))) {
1494 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1495 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1499 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1500 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1501 sizeof(src
->stencil_write_mask
))) {
1502 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1503 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1507 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1508 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1509 sizeof(src
->stencil_reference
))) {
1510 dest
->stencil_reference
= src
->stencil_reference
;
1511 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1515 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1516 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1517 &src
->discard_rectangle
.rectangles
,
1518 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1519 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1520 src
->discard_rectangle
.rectangles
,
1521 src
->discard_rectangle
.count
);
1522 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1528 tu_create_cmd_buffer(struct tu_device
*device
,
1529 struct tu_cmd_pool
*pool
,
1530 VkCommandBufferLevel level
,
1531 VkCommandBuffer
*pCommandBuffer
)
1533 struct tu_cmd_buffer
*cmd_buffer
;
1534 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1535 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1536 if (cmd_buffer
== NULL
)
1537 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1539 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1540 cmd_buffer
->device
= device
;
1541 cmd_buffer
->pool
= pool
;
1542 cmd_buffer
->level
= level
;
1545 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1546 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1549 /* Init the pool_link so we can safely call list_del when we destroy
1550 * the command buffer
1552 list_inithead(&cmd_buffer
->pool_link
);
1553 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1556 tu_bo_list_init(&cmd_buffer
->bo_list
);
1557 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1558 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1559 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1560 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1562 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1564 list_inithead(&cmd_buffer
->upload
.list
);
1566 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1567 if (result
!= VK_SUCCESS
)
1568 goto fail_scratch_bo
;
1570 /* TODO: resize on overflow */
1571 cmd_buffer
->vsc_data_pitch
= device
->vsc_data_pitch
;
1572 cmd_buffer
->vsc_data2_pitch
= device
->vsc_data2_pitch
;
1573 cmd_buffer
->vsc_data
= device
->vsc_data
;
1574 cmd_buffer
->vsc_data2
= device
->vsc_data2
;
1579 list_del(&cmd_buffer
->pool_link
);
1584 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1586 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1588 list_del(&cmd_buffer
->pool_link
);
1590 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1591 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1593 tu_cs_finish(&cmd_buffer
->cs
);
1594 tu_cs_finish(&cmd_buffer
->draw_cs
);
1595 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1596 tu_cs_finish(&cmd_buffer
->sub_cs
);
1598 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1599 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1603 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1605 cmd_buffer
->wait_for_idle
= true;
1607 cmd_buffer
->record_result
= VK_SUCCESS
;
1609 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1610 tu_cs_reset(&cmd_buffer
->cs
);
1611 tu_cs_reset(&cmd_buffer
->draw_cs
);
1612 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1613 tu_cs_reset(&cmd_buffer
->sub_cs
);
1615 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1616 cmd_buffer
->descriptors
[i
].valid
= 0;
1617 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1620 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1622 return cmd_buffer
->record_result
;
1626 tu_AllocateCommandBuffers(VkDevice _device
,
1627 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1628 VkCommandBuffer
*pCommandBuffers
)
1630 TU_FROM_HANDLE(tu_device
, device
, _device
);
1631 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1633 VkResult result
= VK_SUCCESS
;
1636 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1638 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1639 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1640 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1642 list_del(&cmd_buffer
->pool_link
);
1643 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1645 result
= tu_reset_cmd_buffer(cmd_buffer
);
1646 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1647 cmd_buffer
->level
= pAllocateInfo
->level
;
1649 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1651 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1652 &pCommandBuffers
[i
]);
1654 if (result
!= VK_SUCCESS
)
1658 if (result
!= VK_SUCCESS
) {
1659 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1662 /* From the Vulkan 1.0.66 spec:
1664 * "vkAllocateCommandBuffers can be used to create multiple
1665 * command buffers. If the creation of any of those command
1666 * buffers fails, the implementation must destroy all
1667 * successfully created command buffer objects from this
1668 * command, set all entries of the pCommandBuffers array to
1669 * NULL and return the error."
1671 memset(pCommandBuffers
, 0,
1672 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1679 tu_FreeCommandBuffers(VkDevice device
,
1680 VkCommandPool commandPool
,
1681 uint32_t commandBufferCount
,
1682 const VkCommandBuffer
*pCommandBuffers
)
1684 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1685 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1688 if (cmd_buffer
->pool
) {
1689 list_del(&cmd_buffer
->pool_link
);
1690 list_addtail(&cmd_buffer
->pool_link
,
1691 &cmd_buffer
->pool
->free_cmd_buffers
);
1693 tu_cmd_buffer_destroy(cmd_buffer
);
1699 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1700 VkCommandBufferResetFlags flags
)
1702 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1703 return tu_reset_cmd_buffer(cmd_buffer
);
1707 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1708 const VkCommandBufferBeginInfo
*pBeginInfo
)
1710 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1711 VkResult result
= VK_SUCCESS
;
1713 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1714 /* If the command buffer has already been resetted with
1715 * vkResetCommandBuffer, no need to do it again.
1717 result
= tu_reset_cmd_buffer(cmd_buffer
);
1718 if (result
!= VK_SUCCESS
)
1722 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1723 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1725 tu_cs_begin(&cmd_buffer
->cs
);
1726 tu_cs_begin(&cmd_buffer
->draw_cs
);
1727 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1729 cmd_buffer
->scratch_seqno
= 0;
1731 /* setup initial configuration into command buffer */
1732 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1733 switch (cmd_buffer
->queue_family_index
) {
1734 case TU_QUEUE_GENERAL
:
1735 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1740 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1741 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1742 assert(pBeginInfo
->pInheritanceInfo
);
1743 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1744 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1747 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1753 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1754 uint32_t firstBinding
,
1755 uint32_t bindingCount
,
1756 const VkBuffer
*pBuffers
,
1757 const VkDeviceSize
*pOffsets
)
1759 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1761 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1763 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1764 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1765 tu_buffer_from_handle(pBuffers
[i
]);
1766 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1769 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1770 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1774 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1776 VkDeviceSize offset
,
1777 VkIndexType indexType
)
1779 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1780 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1782 /* initialize/update the restart index */
1783 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1784 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1786 tu6_emit_restart_index(
1787 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1789 tu_cs_sanity_check(draw_cs
);
1793 if (cmd
->state
.index_buffer
!= buf
)
1794 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1796 cmd
->state
.index_buffer
= buf
;
1797 cmd
->state
.index_offset
= offset
;
1798 cmd
->state
.index_type
= indexType
;
1802 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1803 VkPipelineBindPoint pipelineBindPoint
,
1804 VkPipelineLayout _layout
,
1806 uint32_t descriptorSetCount
,
1807 const VkDescriptorSet
*pDescriptorSets
,
1808 uint32_t dynamicOffsetCount
,
1809 const uint32_t *pDynamicOffsets
)
1811 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1812 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1813 unsigned dyn_idx
= 0;
1815 struct tu_descriptor_state
*descriptors_state
=
1816 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1818 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1819 unsigned idx
= i
+ firstSet
;
1820 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1822 descriptors_state
->sets
[idx
] = set
;
1823 descriptors_state
->valid
|= (1u << idx
);
1825 /* Note: the actual input attachment indices come from the shader
1826 * itself, so we can't generate the patched versions of these until
1827 * draw time when both the pipeline and descriptors are bound and
1828 * we're inside the render pass.
1830 unsigned dst_idx
= layout
->set
[idx
].input_attachment_start
;
1831 memcpy(&descriptors_state
->input_attachments
[dst_idx
* A6XX_TEX_CONST_DWORDS
],
1832 set
->dynamic_descriptors
,
1833 set
->layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
1835 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1836 /* Dynamic buffers come after input attachments in the descriptor set
1837 * itself, but due to how the Vulkan descriptor set binding works, we
1838 * have to put input attachments and dynamic buffers in separate
1839 * buffers in the descriptor_state and then combine them at draw
1840 * time. Binding a descriptor set only invalidates the descriptor
1841 * sets after it, but if we try to tightly pack the descriptors after
1842 * the input attachments then we could corrupt dynamic buffers in the
1843 * descriptor set before it, or we'd have to move all the dynamic
1844 * buffers over. We just put them into separate buffers to make
1845 * binding as well as the later patching of input attachments easy.
1847 unsigned src_idx
= j
+ set
->layout
->input_attachment_count
;
1848 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1849 assert(dyn_idx
< dynamicOffsetCount
);
1852 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1854 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1855 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1857 /* Patch the storage/uniform descriptors right away. */
1858 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1859 /* Note: we can assume here that the addition won't roll over and
1860 * change the SIZE field.
1862 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1867 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1868 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1869 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1877 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
)
1878 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1880 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1883 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1884 uint32_t firstBinding
,
1885 uint32_t bindingCount
,
1886 const VkBuffer
*pBuffers
,
1887 const VkDeviceSize
*pOffsets
,
1888 const VkDeviceSize
*pSizes
)
1890 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1891 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1893 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1894 uint32_t idx
= firstBinding
+ i
;
1895 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1897 if (pOffsets
[i
] != 0)
1898 cmd
->state
.streamout_reset
|= 1 << idx
;
1900 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1901 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1902 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1904 cmd
->state
.streamout_enabled
|= 1 << idx
;
1907 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1910 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1911 uint32_t firstCounterBuffer
,
1912 uint32_t counterBufferCount
,
1913 const VkBuffer
*pCounterBuffers
,
1914 const VkDeviceSize
*pCounterBufferOffsets
)
1916 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1917 /* TODO do something with counter buffer? */
1920 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1921 uint32_t firstCounterBuffer
,
1922 uint32_t counterBufferCount
,
1923 const VkBuffer
*pCounterBuffers
,
1924 const VkDeviceSize
*pCounterBufferOffsets
)
1926 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1927 /* TODO do something with counter buffer? */
1929 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1930 cmd
->state
.streamout_enabled
= 0;
1934 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1935 VkPipelineLayout layout
,
1936 VkShaderStageFlags stageFlags
,
1939 const void *pValues
)
1941 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1942 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1943 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
1947 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1949 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1951 if (cmd_buffer
->scratch_seqno
) {
1952 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
1953 MSM_SUBMIT_BO_WRITE
);
1956 if (cmd_buffer
->use_vsc_data
) {
1957 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
1958 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1959 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
1960 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1963 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
1964 MSM_SUBMIT_BO_READ
);
1966 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1967 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1968 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1971 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1972 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1973 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1976 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1977 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1978 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1981 tu_cs_end(&cmd_buffer
->cs
);
1982 tu_cs_end(&cmd_buffer
->draw_cs
);
1983 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
1985 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1987 return cmd_buffer
->record_result
;
1991 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
1992 VkPipelineBindPoint pipelineBindPoint
,
1993 VkPipeline _pipeline
)
1995 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1996 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1998 switch (pipelineBindPoint
) {
1999 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2000 cmd
->state
.pipeline
= pipeline
;
2001 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2003 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2004 cmd
->state
.compute_pipeline
= pipeline
;
2005 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2008 unreachable("unrecognized pipeline bind point");
2012 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2013 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2014 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2015 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2016 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2021 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2022 uint32_t firstViewport
,
2023 uint32_t viewportCount
,
2024 const VkViewport
*pViewports
)
2026 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2028 assert(firstViewport
== 0 && viewportCount
== 1);
2029 cmd
->state
.dynamic
.viewport
.viewports
[0] = pViewports
[0];
2030 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2034 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2035 uint32_t firstScissor
,
2036 uint32_t scissorCount
,
2037 const VkRect2D
*pScissors
)
2039 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2041 assert(firstScissor
== 0 && scissorCount
== 1);
2042 cmd
->state
.dynamic
.scissor
.scissors
[0] = pScissors
[0];
2043 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_SCISSOR
;
2047 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2049 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2051 cmd
->state
.dynamic
.line_width
= lineWidth
;
2053 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2054 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2058 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2059 float depthBiasConstantFactor
,
2060 float depthBiasClamp
,
2061 float depthBiasSlopeFactor
)
2063 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2064 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2066 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2067 depthBiasSlopeFactor
);
2069 tu_cs_sanity_check(draw_cs
);
2073 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2074 const float blendConstants
[4])
2076 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2077 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2079 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2081 tu_cs_sanity_check(draw_cs
);
2085 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2086 float minDepthBounds
,
2087 float maxDepthBounds
)
2092 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2093 VkStencilFaceFlags faceMask
,
2094 uint32_t compareMask
)
2096 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2098 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2099 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2100 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2101 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2103 /* the front/back compare masks must be updated together */
2104 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2108 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2109 VkStencilFaceFlags faceMask
,
2112 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2114 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2115 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2116 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2117 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2119 /* the front/back write masks must be updated together */
2120 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2124 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2125 VkStencilFaceFlags faceMask
,
2128 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2130 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2131 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2132 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2133 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2135 /* the front/back references must be updated together */
2136 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2140 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2141 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2143 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2145 tu6_emit_sample_locations(&cmd
->draw_cs
, pSampleLocationsInfo
);
2149 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2150 uint32_t commandBufferCount
,
2151 const VkCommandBuffer
*pCmdBuffers
)
2153 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2156 assert(commandBufferCount
> 0);
2158 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2159 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2161 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2162 if (result
!= VK_SUCCESS
) {
2163 cmd
->record_result
= result
;
2167 if (secondary
->usage_flags
&
2168 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2169 assert(tu_cs_is_empty(&secondary
->cs
));
2171 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2172 if (result
!= VK_SUCCESS
) {
2173 cmd
->record_result
= result
;
2177 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2178 &secondary
->draw_epilogue_cs
);
2179 if (result
!= VK_SUCCESS
) {
2180 cmd
->record_result
= result
;
2184 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2185 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2187 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2188 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2189 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2192 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2195 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2199 tu_CreateCommandPool(VkDevice _device
,
2200 const VkCommandPoolCreateInfo
*pCreateInfo
,
2201 const VkAllocationCallbacks
*pAllocator
,
2202 VkCommandPool
*pCmdPool
)
2204 TU_FROM_HANDLE(tu_device
, device
, _device
);
2205 struct tu_cmd_pool
*pool
;
2207 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2208 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2210 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2213 pool
->alloc
= *pAllocator
;
2215 pool
->alloc
= device
->alloc
;
2217 list_inithead(&pool
->cmd_buffers
);
2218 list_inithead(&pool
->free_cmd_buffers
);
2220 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2222 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2228 tu_DestroyCommandPool(VkDevice _device
,
2229 VkCommandPool commandPool
,
2230 const VkAllocationCallbacks
*pAllocator
)
2232 TU_FROM_HANDLE(tu_device
, device
, _device
);
2233 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2238 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2239 &pool
->cmd_buffers
, pool_link
)
2241 tu_cmd_buffer_destroy(cmd_buffer
);
2244 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2245 &pool
->free_cmd_buffers
, pool_link
)
2247 tu_cmd_buffer_destroy(cmd_buffer
);
2250 vk_free2(&device
->alloc
, pAllocator
, pool
);
2254 tu_ResetCommandPool(VkDevice device
,
2255 VkCommandPool commandPool
,
2256 VkCommandPoolResetFlags flags
)
2258 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2261 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2264 result
= tu_reset_cmd_buffer(cmd_buffer
);
2265 if (result
!= VK_SUCCESS
)
2273 tu_TrimCommandPool(VkDevice device
,
2274 VkCommandPool commandPool
,
2275 VkCommandPoolTrimFlags flags
)
2277 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2282 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2283 &pool
->free_cmd_buffers
, pool_link
)
2285 tu_cmd_buffer_destroy(cmd_buffer
);
2290 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2291 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2292 VkSubpassContents contents
)
2294 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2295 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2296 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2298 cmd
->state
.pass
= pass
;
2299 cmd
->state
.subpass
= pass
->subpasses
;
2300 cmd
->state
.framebuffer
= fb
;
2302 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2303 tu_cmd_prepare_tile_store_ib(cmd
);
2305 tu_emit_load_clear(cmd
, pRenderPassBegin
);
2307 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2308 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2309 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2310 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2312 /* note: use_hw_binning only checks tiling config */
2313 if (use_hw_binning(cmd
))
2314 cmd
->use_vsc_data
= true;
2316 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2317 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2318 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2319 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2322 /* Flag input attachment descriptors for re-emission if necessary */
2323 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2327 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2328 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2329 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2331 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2332 pSubpassBeginInfo
->contents
);
2336 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2338 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2339 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2340 struct tu_cs
*cs
= &cmd
->draw_cs
;
2342 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2344 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2346 if (subpass
->resolve_attachments
) {
2347 tu6_emit_blit_scissor(cmd
, cs
, true);
2349 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2350 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2351 if (a
== VK_ATTACHMENT_UNUSED
)
2354 tu_store_gmem_attachment(cmd
, cs
, a
,
2355 subpass
->color_attachments
[i
].attachment
);
2357 if (pass
->attachments
[a
].gmem_offset
< 0)
2361 * check if the resolved attachment is needed by later subpasses,
2362 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2364 tu_finishme("missing GMEM->GMEM resolve path\n");
2365 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2369 tu_cond_exec_end(cs
);
2371 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2373 /* Emit flushes so that input attachments will read the correct value.
2374 * TODO: use subpass dependencies to flush or not
2376 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2377 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
2379 if (subpass
->resolve_attachments
) {
2380 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2382 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2383 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2384 if (a
== VK_ATTACHMENT_UNUSED
)
2387 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
2388 subpass
->color_attachments
[i
].attachment
);
2391 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
, true);
2394 tu_cond_exec_end(cs
);
2396 /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2397 if (cmd
->state
.subpass
->input_count
)
2398 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2400 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2401 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2402 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2403 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2404 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2406 /* Flag input attachment descriptors for re-emission if necessary */
2407 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2411 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2412 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2413 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2415 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2421 * Number of vertices.
2426 * Index of the first vertex.
2428 int32_t vertex_offset
;
2431 * First instance id.
2433 uint32_t first_instance
;
2436 * Number of instances.
2438 uint32_t instance_count
;
2441 * First index (indexed draws only).
2443 uint32_t first_index
;
2446 * Whether it's an indexed draw.
2451 * Indirect draw parameters resource.
2453 struct tu_buffer
*indirect
;
2454 uint64_t indirect_offset
;
2458 * Draw count parameters resource.
2460 struct tu_buffer
*count_buffer
;
2461 uint64_t count_buffer_offset
;
2464 * Stream output parameters resource.
2466 struct tu_buffer
*streamout_buffer
;
2467 uint64_t streamout_buffer_offset
;
2470 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2471 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2472 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2474 enum tu_draw_state_group_id
2476 TU_DRAW_STATE_PROGRAM
,
2477 TU_DRAW_STATE_PROGRAM_BINNING
,
2479 TU_DRAW_STATE_VI_BINNING
,
2483 TU_DRAW_STATE_BLEND
,
2484 TU_DRAW_STATE_VS_CONST
,
2485 TU_DRAW_STATE_GS_CONST
,
2486 TU_DRAW_STATE_FS_CONST
,
2487 TU_DRAW_STATE_DESC_SETS
,
2488 TU_DRAW_STATE_DESC_SETS_GMEM
,
2489 TU_DRAW_STATE_DESC_SETS_LOAD
,
2490 TU_DRAW_STATE_VS_PARAMS
,
2492 TU_DRAW_STATE_COUNT
,
2495 struct tu_draw_state_group
2497 enum tu_draw_state_group_id id
;
2498 uint32_t enable_mask
;
2499 struct tu_cs_entry ib
;
2502 static inline uint32_t
2503 tu6_stage2opcode(gl_shader_stage type
)
2506 case MESA_SHADER_VERTEX
:
2507 case MESA_SHADER_TESS_CTRL
:
2508 case MESA_SHADER_TESS_EVAL
:
2509 case MESA_SHADER_GEOMETRY
:
2510 return CP_LOAD_STATE6_GEOM
;
2511 case MESA_SHADER_FRAGMENT
:
2512 case MESA_SHADER_COMPUTE
:
2513 case MESA_SHADER_KERNEL
:
2514 return CP_LOAD_STATE6_FRAG
;
2516 unreachable("bad shader type");
2520 static inline enum a6xx_state_block
2521 tu6_stage2shadersb(gl_shader_stage type
)
2524 case MESA_SHADER_VERTEX
:
2525 return SB6_VS_SHADER
;
2526 case MESA_SHADER_GEOMETRY
:
2527 return SB6_GS_SHADER
;
2528 case MESA_SHADER_FRAGMENT
:
2529 return SB6_FS_SHADER
;
2530 case MESA_SHADER_COMPUTE
:
2531 case MESA_SHADER_KERNEL
:
2532 return SB6_CS_SHADER
;
2534 unreachable("bad shader type");
2540 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2541 struct tu_descriptor_state
*descriptors_state
,
2542 gl_shader_stage type
,
2543 uint32_t *push_constants
)
2545 const struct tu_program_descriptor_linkage
*link
=
2546 &pipeline
->program
.link
[type
];
2547 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2549 if (link
->push_consts
.count
> 0) {
2550 unsigned num_units
= link
->push_consts
.count
;
2551 unsigned offset
= link
->push_consts
.lo
;
2552 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2553 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2554 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2555 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2556 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2557 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2560 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2561 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2564 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2565 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2566 uint32_t offset
= state
->range
[i
].start
;
2568 /* and even if the start of the const buffer is before
2569 * first_immediate, the end may not be:
2571 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2576 /* things should be aligned to vec4: */
2577 debug_assert((state
->range
[i
].offset
% 16) == 0);
2578 debug_assert((size
% 16) == 0);
2579 debug_assert((offset
% 16) == 0);
2581 /* Dig out the descriptor from the descriptor state and read the VA from
2584 assert(state
->range
[i
].bindless
);
2585 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2586 descriptors_state
->dynamic_descriptors
:
2587 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2588 unsigned block
= state
->range
[i
].block
;
2589 /* If the block in the shader here is in the dynamic descriptor set, it
2590 * is an index into the dynamic descriptor set which is combined from
2591 * dynamic descriptors and input attachments on-the-fly, and we don't
2592 * have access to it here. Instead we work backwards to get the index
2593 * into dynamic_descriptors.
2595 if (state
->range
[i
].bindless_base
== MAX_SETS
)
2596 block
-= pipeline
->layout
->input_attachment_count
;
2597 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2598 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2601 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2602 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2603 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2604 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2605 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2606 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2607 tu_cs_emit_qw(cs
, va
+ offset
);
2611 static struct tu_cs_entry
2612 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2613 const struct tu_pipeline
*pipeline
,
2614 struct tu_descriptor_state
*descriptors_state
,
2615 gl_shader_stage type
)
2618 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2620 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2622 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2626 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2627 const struct tu_draw_info
*draw
,
2628 struct tu_cs_entry
*entry
)
2630 /* TODO: fill out more than just base instance */
2631 const struct tu_program_descriptor_linkage
*link
=
2632 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2633 const struct ir3_const_state
*const_state
= &link
->const_state
;
2636 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2637 *entry
= (struct tu_cs_entry
) {};
2641 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2642 if (result
!= VK_SUCCESS
)
2645 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2646 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2647 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2648 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2649 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2650 CP_LOAD_STATE6_0_NUM_UNIT(1));
2654 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2658 tu_cs_emit(&cs
, draw
->first_instance
);
2661 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2666 tu6_emit_descriptor_sets(struct tu_cmd_buffer
*cmd
,
2667 const struct tu_pipeline
*pipeline
,
2668 VkPipelineBindPoint bind_point
,
2669 struct tu_cs_entry
*entry
,
2672 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2673 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
2674 struct tu_descriptor_state
*descriptors_state
=
2675 tu_get_descriptors_state(cmd
, bind_point
);
2676 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2677 const uint32_t *input_attachment_idx
=
2678 pipeline
->program
.input_attachment_idx
;
2679 uint32_t num_dynamic_descs
= layout
->dynamic_offset_count
+
2680 layout
->input_attachment_count
;
2681 struct ts_cs_memory dynamic_desc_set
;
2684 if (num_dynamic_descs
> 0) {
2685 /* allocate and fill out dynamic descriptor set */
2686 result
= tu_cs_alloc(draw_state
, num_dynamic_descs
,
2687 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
2688 if (result
!= VK_SUCCESS
)
2691 memcpy(dynamic_desc_set
.map
, descriptors_state
->input_attachments
,
2692 layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
2695 /* Patch input attachments to refer to GMEM instead */
2696 for (unsigned i
= 0; i
< layout
->input_attachment_count
; i
++) {
2698 &dynamic_desc_set
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2700 /* The compiler has already laid out input_attachment_idx in the
2701 * final order of input attachments, so there's no need to go
2702 * through the pipeline layout finding input attachments.
2704 unsigned attachment_idx
= input_attachment_idx
[i
];
2706 /* It's possible for the pipeline layout to include an input
2707 * attachment which doesn't actually exist for the current
2708 * subpass. Of course, this is only valid so long as the pipeline
2709 * doesn't try to actually load that attachment. Just skip
2710 * patching in that scenario to avoid out-of-bounds accesses.
2712 if (attachment_idx
>= cmd
->state
.subpass
->input_count
)
2715 uint32_t a
= cmd
->state
.subpass
->input_attachments
[attachment_idx
].attachment
;
2716 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2718 assert(att
->gmem_offset
>= 0);
2720 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2721 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2722 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2724 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2725 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2727 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
2728 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2729 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2732 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2733 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2737 memcpy(dynamic_desc_set
.map
+ layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
,
2738 descriptors_state
->dynamic_descriptors
,
2739 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
2742 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
;
2743 uint32_t hlsq_update_value
;
2744 switch (bind_point
) {
2745 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2746 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
2747 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
2748 hlsq_update_value
= 0x7c000;
2750 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2751 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2752 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2753 hlsq_update_value
= 0x3e00;
2756 unreachable("bad bind point");
2759 /* Be careful here to *not* refer to the pipeline, so that if only the
2760 * pipeline changes we don't have to emit this again (except if there are
2761 * dynamic descriptors in the pipeline layout). This means always emitting
2762 * all the valid descriptors, which means that we always have to put the
2763 * dynamic descriptor in the driver-only slot at the end
2765 uint32_t num_user_sets
= util_last_bit(descriptors_state
->valid
);
2766 uint32_t num_sets
= num_user_sets
;
2767 if (num_dynamic_descs
> 0) {
2768 num_user_sets
= MAX_SETS
;
2769 num_sets
= num_user_sets
+ 1;
2772 unsigned regs
[2] = { sp_bindless_base_reg
, hlsq_bindless_base_reg
};
2775 result
= tu_cs_begin_sub_stream(draw_state
, ARRAY_SIZE(regs
) * (1 + num_sets
* 2) + 2, &cs
);
2776 if (result
!= VK_SUCCESS
)
2780 for (unsigned i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
2781 tu_cs_emit_pkt4(&cs
, regs
[i
], num_sets
* 2);
2782 for (unsigned j
= 0; j
< num_user_sets
; j
++) {
2783 if (descriptors_state
->valid
& (1 << j
)) {
2784 /* magic | 3 copied from the blob */
2785 tu_cs_emit_qw(&cs
, descriptors_state
->sets
[j
]->va
| 3);
2787 tu_cs_emit_qw(&cs
, 0 | 3);
2790 if (num_dynamic_descs
> 0) {
2791 tu_cs_emit_qw(&cs
, dynamic_desc_set
.iova
| 3);
2795 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value
));
2798 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2803 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2805 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2807 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2808 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2813 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2815 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2816 .bo_offset
= buf
->bo_offset
));
2817 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2819 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2820 offset
*= tf
->stride
[i
];
2822 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2823 cmd
->state
.streamout_reset
&= ~(1 << i
);
2825 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2826 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2827 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2828 CP_MEM_TO_REG_0_CNT(0));
2829 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2830 ctrl_offset(flush_base
[i
].offset
));
2833 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
2835 ctrl_offset(flush_base
[i
])));
2838 if (cmd
->state
.streamout_enabled
) {
2839 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
2840 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2841 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
2842 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
2843 tu_cs_emit(cs
, tf
->ncomp
[0]);
2844 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
2845 tu_cs_emit(cs
, tf
->ncomp
[1]);
2846 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
2847 tu_cs_emit(cs
, tf
->ncomp
[2]);
2848 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
2849 tu_cs_emit(cs
, tf
->ncomp
[3]);
2850 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2851 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
2852 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
2853 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
2854 tu_cs_emit(cs
, tf
->prog
[i
]);
2857 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
2858 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2860 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2866 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2868 const struct tu_draw_info
*draw
)
2870 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2871 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2872 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2873 uint32_t draw_state_group_count
= 0;
2876 struct tu_descriptor_state
*descriptors_state
=
2877 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2882 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
2883 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
2885 if (cmd
->state
.dirty
&
2886 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2887 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2888 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2889 dynamic
->line_width
);
2892 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2893 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2894 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2895 dynamic
->stencil_compare_mask
.back
);
2898 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2899 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2900 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2901 dynamic
->stencil_write_mask
.back
);
2904 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2905 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2906 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2907 dynamic
->stencil_reference
.back
);
2910 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2911 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2912 tu6_emit_viewport(cs
, &cmd
->state
.dynamic
.viewport
.viewports
[0]);
2915 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_SCISSOR
) &&
2916 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2917 tu6_emit_scissor(cs
, &cmd
->state
.dynamic
.scissor
.scissors
[0]);
2920 if (cmd
->state
.dirty
&
2921 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
2922 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
2923 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
2924 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2925 const VkDeviceSize offset
= buf
->bo_offset
+
2926 cmd
->state
.vb
.offsets
[binding
];
2927 const VkDeviceSize size
=
2928 offset
< buf
->size
? buf
->size
- offset
: 0;
2931 A6XX_VFD_FETCH_BASE(i
, .bo
= buf
->bo
, .bo_offset
= offset
),
2932 A6XX_VFD_FETCH_SIZE(i
, size
));
2936 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2937 draw_state_groups
[draw_state_group_count
++] =
2938 (struct tu_draw_state_group
) {
2939 .id
= TU_DRAW_STATE_PROGRAM
,
2940 .enable_mask
= ENABLE_DRAW
,
2941 .ib
= pipeline
->program
.state_ib
,
2943 draw_state_groups
[draw_state_group_count
++] =
2944 (struct tu_draw_state_group
) {
2945 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2946 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2947 .ib
= pipeline
->program
.binning_state_ib
,
2949 draw_state_groups
[draw_state_group_count
++] =
2950 (struct tu_draw_state_group
) {
2951 .id
= TU_DRAW_STATE_VI
,
2952 .enable_mask
= ENABLE_DRAW
,
2953 .ib
= pipeline
->vi
.state_ib
,
2955 draw_state_groups
[draw_state_group_count
++] =
2956 (struct tu_draw_state_group
) {
2957 .id
= TU_DRAW_STATE_VI_BINNING
,
2958 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2959 .ib
= pipeline
->vi
.binning_state_ib
,
2961 draw_state_groups
[draw_state_group_count
++] =
2962 (struct tu_draw_state_group
) {
2963 .id
= TU_DRAW_STATE_VP
,
2964 .enable_mask
= ENABLE_ALL
,
2965 .ib
= pipeline
->vp
.state_ib
,
2967 draw_state_groups
[draw_state_group_count
++] =
2968 (struct tu_draw_state_group
) {
2969 .id
= TU_DRAW_STATE_RAST
,
2970 .enable_mask
= ENABLE_ALL
,
2971 .ib
= pipeline
->rast
.state_ib
,
2973 draw_state_groups
[draw_state_group_count
++] =
2974 (struct tu_draw_state_group
) {
2975 .id
= TU_DRAW_STATE_DS
,
2976 .enable_mask
= ENABLE_ALL
,
2977 .ib
= pipeline
->ds
.state_ib
,
2979 draw_state_groups
[draw_state_group_count
++] =
2980 (struct tu_draw_state_group
) {
2981 .id
= TU_DRAW_STATE_BLEND
,
2982 .enable_mask
= ENABLE_ALL
,
2983 .ib
= pipeline
->blend
.state_ib
,
2987 if (cmd
->state
.dirty
&
2988 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
2989 draw_state_groups
[draw_state_group_count
++] =
2990 (struct tu_draw_state_group
) {
2991 .id
= TU_DRAW_STATE_VS_CONST
,
2992 .enable_mask
= ENABLE_ALL
,
2993 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
2995 draw_state_groups
[draw_state_group_count
++] =
2996 (struct tu_draw_state_group
) {
2997 .id
= TU_DRAW_STATE_GS_CONST
,
2998 .enable_mask
= ENABLE_ALL
,
2999 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
)
3001 draw_state_groups
[draw_state_group_count
++] =
3002 (struct tu_draw_state_group
) {
3003 .id
= TU_DRAW_STATE_FS_CONST
,
3004 .enable_mask
= ENABLE_DRAW
,
3005 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3009 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3010 tu6_emit_streamout(cmd
, cs
);
3012 /* If there are any any dynamic descriptors, then we may need to re-emit
3013 * them after every pipeline change in case the number of input attachments
3014 * changes. We also always need to re-emit after a pipeline change if there
3015 * are any input attachments, because the input attachment index comes from
3016 * the pipeline. Finally, it can also happen that the subpass changes
3017 * without the pipeline changing, in which case the GMEM descriptors need
3018 * to be patched differently.
3020 * TODO: We could probably be clever and avoid re-emitting state on
3021 * pipeline changes if the number of input attachments is always 0. We
3022 * could also only re-emit dynamic state.
3024 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
||
3025 ((pipeline
->layout
->dynamic_offset_count
+
3026 pipeline
->layout
->input_attachment_count
> 0) &&
3027 cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) ||
3028 (pipeline
->layout
->input_attachment_count
> 0 &&
3029 cmd
->state
.dirty
& TU_CMD_DIRTY_INPUT_ATTACHMENTS
)) {
3030 struct tu_cs_entry desc_sets
, desc_sets_gmem
;
3031 bool need_gmem_desc_set
= pipeline
->layout
->input_attachment_count
> 0;
3033 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3034 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3036 if (result
!= VK_SUCCESS
)
3039 draw_state_groups
[draw_state_group_count
++] =
3040 (struct tu_draw_state_group
) {
3041 .id
= TU_DRAW_STATE_DESC_SETS
,
3042 .enable_mask
= need_gmem_desc_set
? ENABLE_NON_GMEM
: ENABLE_ALL
,
3046 if (need_gmem_desc_set
) {
3047 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3048 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3049 &desc_sets_gmem
, true);
3050 if (result
!= VK_SUCCESS
)
3053 draw_state_groups
[draw_state_group_count
++] =
3054 (struct tu_draw_state_group
) {
3055 .id
= TU_DRAW_STATE_DESC_SETS_GMEM
,
3056 .enable_mask
= CP_SET_DRAW_STATE__0_GMEM
,
3057 .ib
= desc_sets_gmem
,
3061 /* We need to reload the descriptors every time the descriptor sets
3062 * change. However, the commands we send only depend on the pipeline
3063 * because the whole point is to cache descriptors which are used by the
3064 * pipeline. There's a problem here, in that the firmware has an
3065 * "optimization" which skips executing groups that are set to the same
3066 * value as the last draw. This means that if the descriptor sets change
3067 * but not the pipeline, we'd try to re-execute the same buffer which
3068 * the firmware would ignore and we wouldn't pre-load the new
3069 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3070 * the descriptor sets change, which we emulate here by copying the
3071 * pre-prepared buffer.
3073 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3074 if (load_entry
->size
> 0) {
3075 struct tu_cs load_cs
;
3076 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3077 if (result
!= VK_SUCCESS
)
3079 tu_cs_emit_array(&load_cs
,
3080 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3081 load_entry
->size
/ 4);
3082 struct tu_cs_entry load_copy
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3084 draw_state_groups
[draw_state_group_count
++] =
3085 (struct tu_draw_state_group
) {
3086 .id
= TU_DRAW_STATE_DESC_SETS_LOAD
,
3087 /* The blob seems to not enable this for binning, even when
3088 * resources would actually be used in the binning shader.
3089 * Presumably the overhead of prefetching the resources isn't
3092 .enable_mask
= ENABLE_DRAW
,
3098 struct tu_cs_entry vs_params
;
3099 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3100 if (result
!= VK_SUCCESS
)
3103 draw_state_groups
[draw_state_group_count
++] =
3104 (struct tu_draw_state_group
) {
3105 .id
= TU_DRAW_STATE_VS_PARAMS
,
3106 .enable_mask
= ENABLE_ALL
,
3110 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3111 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3112 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3113 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3114 uint32_t cp_set_draw_state
=
3115 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3116 group
->enable_mask
|
3117 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3119 if (group
->ib
.size
) {
3120 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3122 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3126 tu_cs_emit(cs
, cp_set_draw_state
);
3127 tu_cs_emit_qw(cs
, iova
);
3130 tu_cs_sanity_check(cs
);
3133 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3134 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3135 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3137 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3140 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3142 for_each_bit(i
, descriptors_state
->valid
) {
3143 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3144 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3145 if (set
->buffers
[j
]) {
3146 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3147 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3150 if (set
->size
> 0) {
3151 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3152 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3156 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3157 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3158 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3160 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3161 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3166 /* There are too many graphics dirty bits to list here, so just list the
3167 * bits to preserve instead. The only things not emitted here are
3168 * compute-related state.
3170 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
3172 /* Fragment shader state overwrites compute shader state, so flag the
3173 * compute pipeline for re-emit.
3175 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3180 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3182 const struct tu_draw_info
*draw
)
3184 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3185 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3186 VK_SHADER_STAGE_GEOMETRY_BIT
;
3189 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3190 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3192 if (draw
->indexed
) {
3193 const enum a4xx_index_size index_size
=
3194 tu6_index_size(cmd
->state
.index_type
);
3195 const uint32_t index_bytes
=
3196 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3197 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3198 unsigned max_indicies
=
3199 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3201 const uint32_t cp_draw_indx
=
3202 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3203 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3204 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3205 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3206 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3208 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3209 tu_cs_emit(cs
, cp_draw_indx
);
3210 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3211 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3212 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3214 const uint32_t cp_draw_indx
=
3215 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3216 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3217 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3218 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3220 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3221 tu_cs_emit(cs
, cp_draw_indx
);
3222 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3225 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3229 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3231 const struct tu_draw_info
*draw
)
3234 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3235 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3236 VK_SHADER_STAGE_GEOMETRY_BIT
;
3239 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3240 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3242 /* TODO hw binning */
3243 if (draw
->indexed
) {
3244 const enum a4xx_index_size index_size
=
3245 tu6_index_size(cmd
->state
.index_type
);
3246 const uint32_t index_bytes
=
3247 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3248 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3249 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3250 index_bytes
* draw
->first_index
;
3251 const uint32_t size
= index_bytes
* draw
->count
;
3253 const uint32_t cp_draw_indx
=
3254 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3255 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3256 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3257 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3258 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3260 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3261 tu_cs_emit(cs
, cp_draw_indx
);
3262 tu_cs_emit(cs
, draw
->instance_count
);
3263 tu_cs_emit(cs
, draw
->count
);
3264 tu_cs_emit(cs
, 0x0); /* XXX */
3265 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3266 tu_cs_emit(cs
, size
);
3268 const uint32_t cp_draw_indx
=
3269 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3270 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3271 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3272 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3274 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3275 tu_cs_emit(cs
, cp_draw_indx
);
3276 tu_cs_emit(cs
, draw
->instance_count
);
3277 tu_cs_emit(cs
, draw
->count
);
3282 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3284 struct tu_cs
*cs
= &cmd
->draw_cs
;
3287 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3288 if (result
!= VK_SUCCESS
) {
3289 cmd
->record_result
= result
;
3294 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3296 tu6_emit_draw_direct(cmd
, cs
, draw
);
3298 if (cmd
->state
.streamout_enabled
) {
3299 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3300 if (cmd
->state
.streamout_enabled
& (1 << i
))
3301 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
, false);
3305 cmd
->wait_for_idle
= true;
3307 tu_cs_sanity_check(cs
);
3311 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3312 uint32_t vertexCount
,
3313 uint32_t instanceCount
,
3314 uint32_t firstVertex
,
3315 uint32_t firstInstance
)
3317 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3318 struct tu_draw_info info
= {};
3320 info
.count
= vertexCount
;
3321 info
.instance_count
= instanceCount
;
3322 info
.first_instance
= firstInstance
;
3323 info
.vertex_offset
= firstVertex
;
3325 tu_draw(cmd_buffer
, &info
);
3329 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3330 uint32_t indexCount
,
3331 uint32_t instanceCount
,
3332 uint32_t firstIndex
,
3333 int32_t vertexOffset
,
3334 uint32_t firstInstance
)
3336 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3337 struct tu_draw_info info
= {};
3339 info
.indexed
= true;
3340 info
.count
= indexCount
;
3341 info
.instance_count
= instanceCount
;
3342 info
.first_index
= firstIndex
;
3343 info
.vertex_offset
= vertexOffset
;
3344 info
.first_instance
= firstInstance
;
3346 tu_draw(cmd_buffer
, &info
);
3350 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3352 VkDeviceSize offset
,
3356 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3357 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3358 struct tu_draw_info info
= {};
3360 info
.count
= drawCount
;
3361 info
.indirect
= buffer
;
3362 info
.indirect_offset
= offset
;
3363 info
.stride
= stride
;
3365 tu_draw(cmd_buffer
, &info
);
3369 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3371 VkDeviceSize offset
,
3375 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3376 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3377 struct tu_draw_info info
= {};
3379 info
.indexed
= true;
3380 info
.count
= drawCount
;
3381 info
.indirect
= buffer
;
3382 info
.indirect_offset
= offset
;
3383 info
.stride
= stride
;
3385 tu_draw(cmd_buffer
, &info
);
3388 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3389 uint32_t instanceCount
,
3390 uint32_t firstInstance
,
3391 VkBuffer _counterBuffer
,
3392 VkDeviceSize counterBufferOffset
,
3393 uint32_t counterOffset
,
3394 uint32_t vertexStride
)
3396 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3397 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3399 struct tu_draw_info info
= {};
3401 info
.instance_count
= instanceCount
;
3402 info
.first_instance
= firstInstance
;
3403 info
.streamout_buffer
= buffer
;
3404 info
.streamout_buffer_offset
= counterBufferOffset
;
3405 info
.stride
= vertexStride
;
3407 tu_draw(cmd_buffer
, &info
);
3410 struct tu_dispatch_info
3413 * Determine the layout of the grid (in block units) to be used.
3418 * A starting offset for the grid. If unaligned is set, the offset
3419 * must still be aligned.
3421 uint32_t offsets
[3];
3423 * Whether it's an unaligned compute dispatch.
3428 * Indirect compute parameters resource.
3430 struct tu_buffer
*indirect
;
3431 uint64_t indirect_offset
;
3435 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3436 const struct tu_dispatch_info
*info
)
3438 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3439 const struct tu_program_descriptor_linkage
*link
=
3440 &pipeline
->program
.link
[type
];
3441 const struct ir3_const_state
*const_state
= &link
->const_state
;
3442 uint32_t offset
= const_state
->offsets
.driver_param
;
3444 if (link
->constlen
<= offset
)
3447 if (!info
->indirect
) {
3448 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3449 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3450 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3451 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3452 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3453 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3454 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3457 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3458 (link
->constlen
- offset
) * 4);
3459 /* push constants */
3460 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3461 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3462 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3463 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3464 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3465 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3469 for (i
= 0; i
< num_consts
; i
++)
3470 tu_cs_emit(cs
, driver_params
[i
]);
3472 tu_finishme("Indirect driver params");
3477 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3478 const struct tu_dispatch_info
*info
)
3480 struct tu_cs
*cs
= &cmd
->cs
;
3481 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3482 struct tu_descriptor_state
*descriptors_state
=
3483 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3486 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3487 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3489 struct tu_cs_entry ib
;
3491 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3493 tu_cs_emit_ib(cs
, &ib
);
3495 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3497 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) {
3498 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3499 VK_PIPELINE_BIND_POINT_COMPUTE
, &ib
,
3501 if (result
!= VK_SUCCESS
) {
3502 cmd
->record_result
= result
;
3508 for_each_bit(i
, descriptors_state
->valid
) {
3509 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3510 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3511 if (set
->buffers
[j
]) {
3512 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3513 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3517 if (set
->size
> 0) {
3518 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3519 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3525 tu_cs_emit_ib(cs
, &ib
);
3527 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
)
3528 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3531 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3533 /* Compute shader state overwrites fragment shader state, so we flag the
3534 * graphics pipeline for re-emit.
3536 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
3538 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3539 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3541 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3542 const uint32_t *num_groups
= info
->blocks
;
3544 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3545 .localsizex
= local_size
[0] - 1,
3546 .localsizey
= local_size
[1] - 1,
3547 .localsizez
= local_size
[2] - 1),
3548 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3549 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3550 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3551 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3552 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3553 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3556 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3557 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3558 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3560 if (info
->indirect
) {
3561 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3563 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3564 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3566 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3567 tu_cs_emit(cs
, 0x00000000);
3568 tu_cs_emit_qw(cs
, iova
);
3570 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3571 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3572 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3574 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3575 tu_cs_emit(cs
, 0x00000000);
3576 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3577 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3578 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3583 tu6_emit_cache_flush(cmd
, cs
);
3587 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3595 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3596 struct tu_dispatch_info info
= {};
3602 info
.offsets
[0] = base_x
;
3603 info
.offsets
[1] = base_y
;
3604 info
.offsets
[2] = base_z
;
3605 tu_dispatch(cmd_buffer
, &info
);
3609 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3614 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3618 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3620 VkDeviceSize offset
)
3622 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3623 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3624 struct tu_dispatch_info info
= {};
3626 info
.indirect
= buffer
;
3627 info
.indirect_offset
= offset
;
3629 tu_dispatch(cmd_buffer
, &info
);
3633 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3635 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3637 tu_cs_end(&cmd_buffer
->draw_cs
);
3638 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3640 if (use_sysmem_rendering(cmd_buffer
))
3641 tu_cmd_render_sysmem(cmd_buffer
);
3643 tu_cmd_render_tiles(cmd_buffer
);
3645 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3647 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3648 tu_cs_begin(&cmd_buffer
->draw_cs
);
3649 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3650 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3652 cmd_buffer
->state
.pass
= NULL
;
3653 cmd_buffer
->state
.subpass
= NULL
;
3654 cmd_buffer
->state
.framebuffer
= NULL
;
3658 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3659 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3661 tu_CmdEndRenderPass(commandBuffer
);
3664 struct tu_barrier_info
3666 uint32_t eventCount
;
3667 const VkEvent
*pEvents
;
3668 VkPipelineStageFlags srcStageMask
;
3672 tu_barrier(struct tu_cmd_buffer
*cmd
,
3673 uint32_t memoryBarrierCount
,
3674 const VkMemoryBarrier
*pMemoryBarriers
,
3675 uint32_t bufferMemoryBarrierCount
,
3676 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3677 uint32_t imageMemoryBarrierCount
,
3678 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3679 const struct tu_barrier_info
*info
)
3681 /* renderpass case is only for subpass self-dependencies
3682 * which means syncing the render output with texture cache
3683 * note: only the CACHE_INVALIDATE is needed in GMEM mode
3684 * and in sysmem mode we might not need either color/depth flush
3686 if (cmd
->state
.pass
) {
3687 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_COLOR_TS
, true);
3688 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_DEPTH_TS
, true);
3689 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, CACHE_INVALIDATE
, false);
3695 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3696 VkPipelineStageFlags srcStageMask
,
3697 VkPipelineStageFlags dstStageMask
,
3698 VkDependencyFlags dependencyFlags
,
3699 uint32_t memoryBarrierCount
,
3700 const VkMemoryBarrier
*pMemoryBarriers
,
3701 uint32_t bufferMemoryBarrierCount
,
3702 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3703 uint32_t imageMemoryBarrierCount
,
3704 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3706 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3707 struct tu_barrier_info info
;
3709 info
.eventCount
= 0;
3710 info
.pEvents
= NULL
;
3711 info
.srcStageMask
= srcStageMask
;
3713 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3714 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3715 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3719 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
, unsigned value
)
3721 struct tu_cs
*cs
= &cmd
->cs
;
3723 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3725 /* TODO: any flush required before/after ? */
3727 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3728 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3729 tu_cs_emit(cs
, value
);
3733 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3735 VkPipelineStageFlags stageMask
)
3737 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3738 TU_FROM_HANDLE(tu_event
, event
, _event
);
3740 write_event(cmd
, event
, 1);
3744 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3746 VkPipelineStageFlags stageMask
)
3748 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3749 TU_FROM_HANDLE(tu_event
, event
, _event
);
3751 write_event(cmd
, event
, 0);
3755 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3756 uint32_t eventCount
,
3757 const VkEvent
*pEvents
,
3758 VkPipelineStageFlags srcStageMask
,
3759 VkPipelineStageFlags dstStageMask
,
3760 uint32_t memoryBarrierCount
,
3761 const VkMemoryBarrier
*pMemoryBarriers
,
3762 uint32_t bufferMemoryBarrierCount
,
3763 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3764 uint32_t imageMemoryBarrierCount
,
3765 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3767 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3768 struct tu_cs
*cs
= &cmd
->cs
;
3770 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3772 for (uint32_t i
= 0; i
< eventCount
; i
++) {
3773 TU_FROM_HANDLE(tu_event
, event
, pEvents
[i
]);
3775 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3777 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3778 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3779 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3780 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3781 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3782 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3783 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3788 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)