src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36 #include "tu_blit.h"
  37
  38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  39
  40 void
  41 tu_bo_list_init(struct tu_bo_list *list)
  42 {
  43    list->count = list->capacity = 0;
  44    list->bo_infos = NULL;
  45 }
  46
  47 void
  48 tu_bo_list_destroy(struct tu_bo_list *list)
  49 {
  50    free(list->bo_infos);
  51 }
  52
  53 void
  54 tu_bo_list_reset(struct tu_bo_list *list)
  55 {
  56    list->count = 0;
  57 }
  58
  59 /**
  60  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  61  */
  62 static uint32_t
  63 tu_bo_list_add_info(struct tu_bo_list *list,
  64                     const struct drm_msm_gem_submit_bo *bo_info)
  65 {
  66    assert(bo_info->handle != 0);
  67
  68    for (uint32_t i = 0; i < list->count; ++i) {
  69       if (list->bo_infos[i].handle == bo_info->handle) {
  70          assert(list->bo_infos[i].presumed == bo_info->presumed);
  71          list->bo_infos[i].flags |= bo_info->flags;
  72          return i;
  73       }
  74    }
  75
  76    /* grow list->bo_infos if needed */
  77    if (list->count == list->capacity) {
  78       uint32_t new_capacity = MAX2(2 * list->count, 16);
  79       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  80          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  81       if (!new_bo_infos)
  82          return TU_BO_LIST_FAILED;
  83       list->bo_infos = new_bo_infos;
  84       list->capacity = new_capacity;
  85    }
  86
  87    list->bo_infos[list->count] = *bo_info;
  88    return list->count++;
  89 }
  90
  91 uint32_t
  92 tu_bo_list_add(struct tu_bo_list *list,
  93                const struct tu_bo *bo,
  94                uint32_t flags)
  95 {
  96    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  97                                        .flags = flags,
  98                                        .handle = bo->gem_handle,
  99                                        .presumed = bo->iova,
 100                                     });
 101 }
 102
 103 VkResult
 104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 105 {
 106    for (uint32_t i = 0; i < other->count; i++) {
 107       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 108          return VK_ERROR_OUT_OF_HOST_MEMORY;
 109    }
 110
 111    return VK_SUCCESS;
 112 }
 113
 114 static bool
 115 is_linear_mipmapped(const struct tu_image_view *iview)
 116 {
 117    return iview->image->layout.tile_mode == TILE6_LINEAR &&
 118           iview->base_mip != iview->image->level_count - 1;
 119 }
 120
 121 static bool
 122 force_sysmem(const struct tu_cmd_buffer *cmd,
 123              const struct VkRect2D *render_area)
 124 {
 125    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 126    const struct tu_physical_device *device = cmd->device->physical_device;
 127    bool has_linear_mipmapped_store = false;
 128    const struct tu_render_pass *pass = cmd->state.pass;
 129
 130    /* Iterate over all the places we call tu6_emit_store_attachment() */
 131    for (unsigned i = 0; i < pass->subpass_count; i++) {
 132       const struct tu_subpass *subpass = &pass->subpasses[i];
 133       if (subpass->resolve_attachments) {
 134          for (unsigned i = 0; i < subpass->color_count; i++) {
 135             uint32_t a = subpass->resolve_attachments[i].attachment;
 136             if (a != VK_ATTACHMENT_UNUSED &&
 137                 cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 138                const struct tu_image_view *iview = fb->attachments[a].attachment;
 139                if (is_linear_mipmapped(iview)) {
 140                   has_linear_mipmapped_store = true;
 141                   break;
 142                }
 143             }
 144          }
 145       }
 146    }
 147
 148    for (unsigned i = 0; i < pass->attachment_count; i++) {
 149       if (pass->attachments[i].gmem_offset >= 0 &&
 150           cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 151          const struct tu_image_view *iview = fb->attachments[i].attachment;
 152          if (is_linear_mipmapped(iview)) {
 153             has_linear_mipmapped_store = true;
 154             break;
 155          }
 156       }
 157    }
 158
 159    /* Linear textures cannot have any padding between mipmap levels and their
 160     * height isn't padded, while at the same time the GMEM->MEM resolve does
 161     * not have per-pixel granularity, so if the image height isn't aligned to
 162     * the resolve granularity and the render area is tall enough, we may wind
 163     * up writing past the bottom of the image into the next miplevel or even
 164     * past the end of the image. For the last miplevel, the layout code should
 165     * insert enough padding so that the overdraw writes to the padding.  To
 166     * work around this, we force-enable sysmem rendering.
 167     */
 168    const uint32_t y2 = render_area->offset.y + render_area->extent.height;
 169    const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
 170
 171    return has_linear_mipmapped_store && aligned_y2 > fb->height;
 172 }
 173
 174 static void
 175 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 176                                     const struct tu_device *dev,
 177                                     uint32_t pixels)
 178 {
 179    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 180    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 181    const uint32_t max_tile_width = 1024; /* A6xx */
 182
 183    /* note: don't offset the tiling config by render_area.offset,
 184     * because binning pass can't deal with it
 185     * this means we might end up with more tiles than necessary,
 186     * but load/store/etc are still scissored to the render_area
 187     */
 188    tiling->tile0.offset = (VkOffset2D) {};
 189
 190    const uint32_t ra_width =
 191       tiling->render_area.extent.width +
 192       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 193    const uint32_t ra_height =
 194       tiling->render_area.extent.height +
 195       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 196
 197    /* start from 1 tile */
 198    tiling->tile_count = (VkExtent2D) {
 199       .width = 1,
 200       .height = 1,
 201    };
 202    tiling->tile0.extent = (VkExtent2D) {
 203       .width = align(ra_width, tile_align_w),
 204       .height = align(ra_height, tile_align_h),
 205    };
 206
 207    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 208       /* start with 2x2 tiles */
 209       tiling->tile_count.width = 2;
 210       tiling->tile_count.height = 2;
 211       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 212       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 213    }
 214
 215    /* do not exceed max tile width */
 216    while (tiling->tile0.extent.width > max_tile_width) {
 217       tiling->tile_count.width++;
 218       tiling->tile0.extent.width =
 219          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 220    }
 221
 222    /* will force to sysmem, don't bother trying to have a valid tile config
 223     * TODO: just skip all GMEM stuff when sysmem is forced?
 224     */
 225    if (!pixels)
 226       return;
 227
 228    /* do not exceed gmem size */
 229    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 230       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 231          tiling->tile_count.width++;
 232          tiling->tile0.extent.width =
 233             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 234       } else {
 235          /* if this assert fails then layout is impossible.. */
 236          assert(tiling->tile0.extent.height > tile_align_h);
 237          tiling->tile_count.height++;
 238          tiling->tile0.extent.height =
 239             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 240       }
 241    }
 242 }
 243
 244 static void
 245 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 246                                     const struct tu_device *dev)
 247 {
 248    const uint32_t max_pipe_count = 32; /* A6xx */
 249
 250    /* start from 1 tile per pipe */
 251    tiling->pipe0 = (VkExtent2D) {
 252       .width = 1,
 253       .height = 1,
 254    };
 255    tiling->pipe_count = tiling->tile_count;
 256
 257    while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
 258       if (tiling->pipe0.width < tiling->pipe0.height) {
 259          tiling->pipe0.width += 1;
 260          tiling->pipe_count.width =
 261             DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
 262       } else {
 263          tiling->pipe0.height += 1;
 264          tiling->pipe_count.height =
 265             DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
 266       }
 267    }
 268 }
 269
 270 static void
 271 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 272                               const struct tu_device *dev)
 273 {
 274    const uint32_t max_pipe_count = 32; /* A6xx */
 275    const uint32_t used_pipe_count =
 276       tiling->pipe_count.width * tiling->pipe_count.height;
 277    const VkExtent2D last_pipe = {
 278       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 279       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 280    };
 281
 282    assert(used_pipe_count <= max_pipe_count);
 283    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 284
 285    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 286       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 287          const uint32_t pipe_x = tiling->pipe0.width * x;
 288          const uint32_t pipe_y = tiling->pipe0.height * y;
 289          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 290                                     ? last_pipe.width
 291                                     : tiling->pipe0.width;
 292          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 293                                     ? last_pipe.height
 294                                     : tiling->pipe0.height;
 295          const uint32_t n = tiling->pipe_count.width * y + x;
 296
 297          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 298                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 299                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 300                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 301          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 302       }
 303    }
 304
 305    memset(tiling->pipe_config + used_pipe_count, 0,
 306           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 307 }
 308
 309 static void
 310 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 311                           const struct tu_device *dev,
 312                           uint32_t tx,
 313                           uint32_t ty,
 314                           struct tu_tile *tile)
 315 {
 316    /* find the pipe and the slot for tile (tx, ty) */
 317    const uint32_t px = tx / tiling->pipe0.width;
 318    const uint32_t py = ty / tiling->pipe0.height;
 319    const uint32_t sx = tx - tiling->pipe0.width * px;
 320    const uint32_t sy = ty - tiling->pipe0.height * py;
 321
 322    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 323    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 324    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 325
 326    /* convert to 1D indices */
 327    tile->pipe = tiling->pipe_count.width * py + px;
 328    tile->slot = tiling->pipe0.width * sy + sx;
 329
 330    /* get the blit area for the tile */
 331    tile->begin = (VkOffset2D) {
 332       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 333       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 334    };
 335    tile->end.x =
 336       (tx == tiling->tile_count.width - 1)
 337          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 338          : tile->begin.x + tiling->tile0.extent.width;
 339    tile->end.y =
 340       (ty == tiling->tile_count.height - 1)
 341          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 342          : tile->begin.y + tiling->tile0.extent.height;
 343 }
 344
 345 enum a3xx_msaa_samples
 346 tu_msaa_samples(uint32_t samples)
 347 {
 348    switch (samples) {
 349    case 1:
 350       return MSAA_ONE;
 351    case 2:
 352       return MSAA_TWO;
 353    case 4:
 354       return MSAA_FOUR;
 355    case 8:
 356       return MSAA_EIGHT;
 357    default:
 358       assert(!"invalid sample count");
 359       return MSAA_ONE;
 360    }
 361 }
 362
 363 static enum a4xx_index_size
 364 tu6_index_size(VkIndexType type)
 365 {
 366    switch (type) {
 367    case VK_INDEX_TYPE_UINT16:
 368       return INDEX4_SIZE_16_BIT;
 369    case VK_INDEX_TYPE_UINT32:
 370       return INDEX4_SIZE_32_BIT;
 371    default:
 372       unreachable("invalid VkIndexType");
 373       return INDEX4_SIZE_8_BIT;
 374    }
 375 }
 376
 377 unsigned
 378 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 379                      struct tu_cs *cs,
 380                      enum vgt_event_type event,
 381                      bool need_seqno)
 382 {
 383    unsigned seqno = 0;
 384
 385    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 386    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 387    if (need_seqno) {
 388       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 389       seqno = ++cmd->scratch_seqno;
 390       tu_cs_emit(cs, seqno);
 391    }
 392
 393    return seqno;
 394 }
 395
 396 static void
 397 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 398 {
 399    tu6_emit_event_write(cmd, cs, 0x31, false);
 400 }
 401
 402 static void
 403 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 404 {
 405    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 406 }
 407
 408 static void
 409 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 410 {
 411    if (cmd->wait_for_idle) {
 412       tu_cs_emit_wfi(cs);
 413       cmd->wait_for_idle = false;
 414    }
 415 }
 416
 417 #define tu_image_view_ubwc_pitches(iview)                                \
 418    .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip),          \
 419    .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
 420
 421 static void
 422 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 423             const struct tu_subpass *subpass,
 424             struct tu_cs *cs)
 425 {
 426    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 427
 428    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 429    if (a == VK_ATTACHMENT_UNUSED) {
 430       tu_cs_emit_regs(cs,
 431                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 432                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 433                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 434                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 435                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 436
 437       tu_cs_emit_regs(cs,
 438                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 439
 440       tu_cs_emit_regs(cs,
 441                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 442                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 443                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 444
 445       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 446
 447       return;
 448    }
 449
 450    const struct tu_image_view *iview = fb->attachments[a].attachment;
 451    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 452
 453    tu_cs_emit_regs(cs,
 454                    A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
 455                    A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 456                    A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
 457                    A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
 458                    A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
 459
 460    tu_cs_emit_regs(cs,
 461                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 462
 463    tu_cs_emit_regs(cs,
 464                    A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
 465                    A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
 466
 467    tu_cs_emit_regs(cs,
 468                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 469                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 470                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 471
 472    tu_cs_emit_regs(cs,
 473                    A6XX_RB_STENCIL_INFO(0));
 474
 475    /* enable zs? */
 476 }
 477
 478 static void
 479 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 480              const struct tu_subpass *subpass,
 481              struct tu_cs *cs)
 482 {
 483    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 484    unsigned char mrt_comp[MAX_RTS] = { 0 };
 485    unsigned srgb_cntl = 0;
 486
 487    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 488       uint32_t a = subpass->color_attachments[i].attachment;
 489       if (a == VK_ATTACHMENT_UNUSED)
 490          continue;
 491
 492       const struct tu_image_view *iview = fb->attachments[a].attachment;
 493       const enum a6xx_tile_mode tile_mode =
 494          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 495
 496       mrt_comp[i] = 0xf;
 497
 498       if (vk_format_is_srgb(iview->vk_format))
 499          srgb_cntl |= (1 << i);
 500
 501       const struct tu_native_format format =
 502          tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 503
 504       tu_cs_emit_regs(cs,
 505                       A6XX_RB_MRT_BUF_INFO(i,
 506                                            .color_tile_mode = tile_mode,
 507                                            .color_format = format.fmt,
 508                                            .color_swap = format.swap),
 509                       A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
 510                       A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
 511                       A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
 512                       A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
 513
 514       tu_cs_emit_regs(cs,
 515                       A6XX_SP_FS_MRT_REG(i,
 516                                          .color_format = format.fmt,
 517                                          .color_sint = vk_format_is_sint(iview->vk_format),
 518                                          .color_uint = vk_format_is_uint(iview->vk_format)));
 519
 520       tu_cs_emit_regs(cs,
 521                       A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
 522                       A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
 523    }
 524
 525    tu_cs_emit_regs(cs,
 526                    A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
 527
 528    tu_cs_emit_regs(cs,
 529                    A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
 530
 531    tu_cs_emit_regs(cs,
 532                    A6XX_RB_RENDER_COMPONENTS(
 533                       .rt0 = mrt_comp[0],
 534                       .rt1 = mrt_comp[1],
 535                       .rt2 = mrt_comp[2],
 536                       .rt3 = mrt_comp[3],
 537                       .rt4 = mrt_comp[4],
 538                       .rt5 = mrt_comp[5],
 539                       .rt6 = mrt_comp[6],
 540                       .rt7 = mrt_comp[7]));
 541
 542    tu_cs_emit_regs(cs,
 543                    A6XX_SP_FS_RENDER_COMPONENTS(
 544                       .rt0 = mrt_comp[0],
 545                       .rt1 = mrt_comp[1],
 546                       .rt2 = mrt_comp[2],
 547                       .rt3 = mrt_comp[3],
 548                       .rt4 = mrt_comp[4],
 549                       .rt5 = mrt_comp[5],
 550                       .rt6 = mrt_comp[6],
 551                       .rt7 = mrt_comp[7]));
 552 }
 553
 554 static void
 555 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
 556               const struct tu_subpass *subpass,
 557               struct tu_cs *cs)
 558 {
 559    const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
 560    bool msaa_disable = samples == MSAA_ONE;
 561
 562    tu_cs_emit_regs(cs,
 563                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 564                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 565                                              .msaa_disable = msaa_disable));
 566
 567    tu_cs_emit_regs(cs,
 568                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 569                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 570                                             .msaa_disable = msaa_disable));
 571
 572    tu_cs_emit_regs(cs,
 573                    A6XX_RB_RAS_MSAA_CNTL(samples),
 574                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 575                                           .msaa_disable = msaa_disable));
 576
 577    tu_cs_emit_regs(cs,
 578                    A6XX_RB_MSAA_CNTL(samples));
 579 }
 580
 581 static void
 582 tu6_emit_bin_size(struct tu_cs *cs,
 583                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 584 {
 585    tu_cs_emit_regs(cs,
 586                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 587                                          .binh = bin_h,
 588                                          .dword = flags));
 589
 590    tu_cs_emit_regs(cs,
 591                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 592                                        .binh = bin_h,
 593                                        .dword = flags));
 594
 595    /* no flag for RB_BIN_CONTROL2... */
 596    tu_cs_emit_regs(cs,
 597                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 598                                         .binh = bin_h));
 599 }
 600
 601 static void
 602 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 603                      const struct tu_subpass *subpass,
 604                      struct tu_cs *cs,
 605                      bool binning)
 606 {
 607    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 608    uint32_t cntl = 0;
 609    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 610    if (binning) {
 611       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 612    } else {
 613       uint32_t mrts_ubwc_enable = 0;
 614       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 615          uint32_t a = subpass->color_attachments[i].attachment;
 616          if (a == VK_ATTACHMENT_UNUSED)
 617             continue;
 618
 619          const struct tu_image_view *iview = fb->attachments[a].attachment;
 620          if (iview->image->layout.ubwc_layer_size != 0)
 621             mrts_ubwc_enable |= 1 << i;
 622       }
 623
 624       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 625
 626       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 627       if (a != VK_ATTACHMENT_UNUSED) {
 628          const struct tu_image_view *iview = fb->attachments[a].attachment;
 629          if (iview->image->layout.ubwc_layer_size != 0)
 630             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 631       }
 632
 633       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 634        * in order to set it correctly for the different subpasses. However,
 635        * that means the packets we're emitting also happen during binning. So
 636        * we need to guard the write on !BINNING at CP execution time.
 637        */
 638       tu_cs_reserve(cs, 3 + 4);
 639       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 640       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 641                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 642       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 643    }
 644
 645    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 646    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 647    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 648    tu_cs_emit(cs, cntl);
 649 }
 650
 651 static void
 652 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 653 {
 654    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 655    uint32_t x1 = render_area->offset.x;
 656    uint32_t y1 = render_area->offset.y;
 657    uint32_t x2 = x1 + render_area->extent.width - 1;
 658    uint32_t y2 = y1 + render_area->extent.height - 1;
 659
 660    /* TODO: alignment requirement seems to be less than tile_align_w/h */
 661    if (align) {
 662       x1 = x1 & ~cmd->device->physical_device->tile_align_w;
 663       y1 = y1 & ~cmd->device->physical_device->tile_align_h;
 664       x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
 665       y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
 666    }
 667
 668    tu_cs_emit_regs(cs,
 669                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 670                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 671 }
 672
 673 static void
 674 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 675                    struct tu_cs *cs,
 676                    const struct tu_image_view *iview,
 677                    uint32_t gmem_offset,
 678                    bool resolve)
 679 {
 680    tu_cs_emit_regs(cs,
 681                    A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
 682
 683    const struct tu_native_format format =
 684       tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 685
 686    enum a6xx_tile_mode tile_mode =
 687       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 688    tu_cs_emit_regs(cs,
 689                    A6XX_RB_BLIT_DST_INFO(
 690                       .tile_mode = tile_mode,
 691                       .samples = tu_msaa_samples(iview->image->samples),
 692                       .color_format = format.fmt,
 693                       .color_swap = format.swap,
 694                       .flags = iview->image->layout.ubwc_layer_size != 0),
 695                    A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
 696                    A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 697                    A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
 698
 699    if (iview->image->layout.ubwc_layer_size) {
 700       tu_cs_emit_regs(cs,
 701                       A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
 702                       A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
 703    }
 704
 705    tu_cs_emit_regs(cs,
 706                    A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
 707 }
 708
 709 static void
 710 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 711 {
 712    tu6_emit_event_write(cmd, cs, BLIT, false);
 713 }
 714
 715 static void
 716 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 717                         struct tu_cs *cs,
 718                         uint32_t x1,
 719                         uint32_t y1,
 720                         uint32_t x2,
 721                         uint32_t y2)
 722 {
 723    tu_cs_emit_regs(cs,
 724                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 725                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 726
 727    tu_cs_emit_regs(cs,
 728                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 729                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 730 }
 731
 732 static void
 733 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 734                        struct tu_cs *cs,
 735                        uint32_t x1,
 736                        uint32_t y1)
 737 {
 738    tu_cs_emit_regs(cs,
 739                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 740
 741    tu_cs_emit_regs(cs,
 742                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 743
 744    tu_cs_emit_regs(cs,
 745                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 746
 747    tu_cs_emit_regs(cs,
 748                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 749 }
 750
 751 static bool
 752 use_hw_binning(struct tu_cmd_buffer *cmd)
 753 {
 754    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 755
 756    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 757       return false;
 758
 759    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 760       return true;
 761
 762    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 763 }
 764
 765 static bool
 766 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 767 {
 768    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 769       return true;
 770
 771    /* can't fit attachments into gmem */
 772    if (!cmd->state.pass->gmem_pixels)
 773       return true;
 774
 775    return cmd->state.tiling_config.force_sysmem;
 776 }
 777
 778 static void
 779 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 780                      struct tu_cs *cs,
 781                      const struct tu_tile *tile)
 782 {
 783    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 784    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 785
 786    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 787    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 788
 789    const uint32_t x1 = tile->begin.x;
 790    const uint32_t y1 = tile->begin.y;
 791    const uint32_t x2 = tile->end.x - 1;
 792    const uint32_t y2 = tile->end.y - 1;
 793    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 794    tu6_emit_window_offset(cmd, cs, x1, y1);
 795
 796    tu_cs_emit_regs(cs,
 797                    A6XX_VPC_SO_OVERRIDE(.so_disable = true));
 798
 799    if (use_hw_binning(cmd)) {
 800       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 801
 802       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 803       tu_cs_emit(cs, 0x0);
 804
 805       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 806       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 807                      A6XX_CP_REG_TEST_0_BIT(0) |
 808                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 809
 810       tu_cs_reserve(cs, 3 + 11);
 811       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 812       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 813       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 814
 815       /* if (no overflow) */ {
 816          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 817          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 818                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 819          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 820          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 821          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 822
 823          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 824          tu_cs_emit(cs, 0x0);
 825
 826          /* use a NOP packet to skip over the 'else' side: */
 827          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 828       } /* else */ {
 829          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 830          tu_cs_emit(cs, 0x1);
 831       }
 832
 833       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 834       tu_cs_emit(cs, 0x0);
 835
 836       tu_cs_emit_regs(cs,
 837                       A6XX_RB_UNKNOWN_8804(0));
 838
 839       tu_cs_emit_regs(cs,
 840                       A6XX_SP_TP_UNKNOWN_B304(0));
 841
 842       tu_cs_emit_regs(cs,
 843                       A6XX_GRAS_UNKNOWN_80A4(0));
 844    } else {
 845       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 846       tu_cs_emit(cs, 0x1);
 847
 848       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 849       tu_cs_emit(cs, 0x0);
 850    }
 851 }
 852
 853 static void
 854 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
 855 {
 856    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 857    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 858    const struct tu_image_view *iview = fb->attachments[a].attachment;
 859    const struct tu_render_pass_attachment *attachment =
 860       &cmd->state.pass->attachments[a];
 861
 862    if (attachment->gmem_offset < 0)
 863       return;
 864
 865    const uint32_t x1 = tiling->render_area.offset.x;
 866    const uint32_t y1 = tiling->render_area.offset.y;
 867    const uint32_t x2 = x1 + tiling->render_area.extent.width;
 868    const uint32_t y2 = y1 + tiling->render_area.extent.height;
 869    const uint32_t tile_x2 =
 870       tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
 871    const uint32_t tile_y2 =
 872       tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
 873    bool need_load =
 874       x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
 875       y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
 876
 877    if (need_load)
 878       tu_finishme("improve handling of unaligned render area");
 879
 880    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 881       need_load = true;
 882
 883    if (vk_format_has_stencil(iview->vk_format) &&
 884        attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 885       need_load = true;
 886
 887    if (need_load) {
 888       tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
 889       tu6_emit_blit(cmd, cs);
 890    }
 891 }
 892
 893 static void
 894 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 895                           uint32_t a,
 896                           const VkRenderPassBeginInfo *info)
 897 {
 898    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 899    const struct tu_image_view *iview = fb->attachments[a].attachment;
 900    const struct tu_render_pass_attachment *attachment =
 901       &cmd->state.pass->attachments[a];
 902    unsigned clear_mask = 0;
 903
 904    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
 905    if (attachment->gmem_offset < 0)
 906       return;
 907
 908    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 909       clear_mask = 0xf;
 910
 911    if (vk_format_has_stencil(iview->vk_format)) {
 912       clear_mask &= 0x1;
 913       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 914          clear_mask |= 0x2;
 915    }
 916    if (!clear_mask)
 917       return;
 918
 919    tu_clear_gmem_attachment(cmd, cs, a, clear_mask,
 920                             &info->pClearValues[a]);
 921 }
 922
 923 static void
 924 tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
 925                          struct tu_cs *cs,
 926                          uint32_t a,
 927                          uint32_t gmem_a,
 928                          bool resolve)
 929 {
 930    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
 931
 932    tu6_emit_blit_info(cmd, cs,
 933                       cmd->state.framebuffer->attachments[a].attachment,
 934                       cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
 935    tu6_emit_blit(cmd, cs);
 936
 937    tu_cond_exec_end(cs);
 938 }
 939
 940 static void
 941 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 942                         struct tu_cs *cs,
 943                         uint32_t a,
 944                         uint32_t gmem_a)
 945 {
 946    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 947    const struct tu_image_view *dst = fb->attachments[a].attachment;
 948    const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 949
 950    tu_blit(cmd, cs, &(struct tu_blit) {
 951       .dst = sysmem_attachment_surf(dst, dst->base_layer,
 952                                     &cmd->state.tiling_config.render_area),
 953       .src = sysmem_attachment_surf(src, src->base_layer,
 954                                     &cmd->state.tiling_config.render_area),
 955       .layers = fb->layers,
 956    });
 957 }
 958
 959
 960 /* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
 961 static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
 962                              struct tu_cs *cs,
 963                              uint32_t a,
 964                              uint32_t gmem_a)
 965 {
 966    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 967       return;
 968
 969    tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
 970
 971    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
 972    tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
 973    tu_cond_exec_end(cs);
 974 }
 975
 976 static void
 977 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
 978                           struct tu_cs *cs,
 979                           uint32_t a,
 980                           uint32_t gmem_a)
 981 {
 982    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 983       return;
 984
 985    tu6_emit_blit_info(cmd, cs,
 986                       cmd->state.framebuffer->attachments[a].attachment,
 987                       cmd->state.pass->attachments[gmem_a].gmem_offset, true);
 988    tu6_emit_blit(cmd, cs);
 989 }
 990
 991 static void
 992 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 993 {
 994    const struct tu_render_pass *pass = cmd->state.pass;
 995    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 996
 997    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 998    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 999                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1000                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1001    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1002    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1003
1004    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1005    tu_cs_emit(cs, 0x0);
1006
1007    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1008    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1009
1010    tu6_emit_blit_scissor(cmd, cs, true);
1011
1012    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1013       if (pass->attachments[a].gmem_offset >= 0)
1014          tu6_emit_store_attachment(cmd, cs, a, a);
1015    }
1016
1017    if (subpass->resolve_attachments) {
1018       for (unsigned i = 0; i < subpass->color_count; i++) {
1019          uint32_t a = subpass->resolve_attachments[i].attachment;
1020          if (a != VK_ATTACHMENT_UNUSED)
1021             tu6_emit_store_attachment(cmd, cs, a,
1022                                       subpass->color_attachments[i].attachment);
1023       }
1024    }
1025 }
1026
1027 static void
1028 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
1029 {
1030    tu_cs_emit_regs(cs,
1031                    A6XX_PC_RESTART_INDEX(restart_index));
1032 }
1033
1034 static void
1035 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1036 {
1037    tu6_emit_cache_flush(cmd, cs);
1038
1039    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
1040
1041    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x10000000);
1042    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1043    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1044    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
1045    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1046    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
1047    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1048    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1049    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1050
1051    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
1052    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1053    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1054    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1055    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
1056    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1057    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1058    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1059    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
1060    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1061    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
1062    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
1063    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1064    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
1065
1066    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1067    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1068    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
1069
1070    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
1071
1072    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1073
1074    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1075    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
1076    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1077    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1078    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1079    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1080    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1081    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1082    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1083    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1084    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1085
1086    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1087    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
1088
1089    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1090    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1091
1092    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1093                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1094
1095    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1096    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1097    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1098    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
1099
1100    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1101    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1102
1103    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1104
1105    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1106
1107    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1108    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1109    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1110    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1111    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1112    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1113    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1114    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1115    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1116    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1117    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1118    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1119    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1120    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1121    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1122    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1123    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1124    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1125    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1126    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1127    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1128
1129    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1130
1131    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1132
1133    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1134
1135    /* we don't use this yet.. probably best to disable.. */
1136    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1137    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1138                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1139                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1140    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1141    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1142
1143    tu_cs_emit_regs(cs,
1144                    A6XX_VPC_SO_BUFFER_BASE(0),
1145                    A6XX_VPC_SO_BUFFER_SIZE(0));
1146
1147    tu_cs_emit_regs(cs,
1148                    A6XX_VPC_SO_FLUSH_BASE(0));
1149
1150    tu_cs_emit_regs(cs,
1151                    A6XX_VPC_SO_BUF_CNTL(0));
1152
1153    tu_cs_emit_regs(cs,
1154                    A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1155
1156    tu_cs_emit_regs(cs,
1157                    A6XX_VPC_SO_BUFFER_BASE(1, 0),
1158                    A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1159
1160    tu_cs_emit_regs(cs,
1161                    A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1162                    A6XX_VPC_SO_FLUSH_BASE(1, 0),
1163                    A6XX_VPC_SO_BUFFER_BASE(2, 0),
1164                    A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1165
1166    tu_cs_emit_regs(cs,
1167                    A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1168                    A6XX_VPC_SO_FLUSH_BASE(2, 0),
1169                    A6XX_VPC_SO_BUFFER_BASE(3, 0),
1170                    A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1171
1172    tu_cs_emit_regs(cs,
1173                    A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1174                    A6XX_VPC_SO_FLUSH_BASE(3, 0));
1175
1176    tu_cs_emit_regs(cs,
1177                    A6XX_SP_HS_CTRL_REG0(0));
1178
1179    tu_cs_emit_regs(cs,
1180                    A6XX_SP_GS_CTRL_REG0(0));
1181
1182    tu_cs_emit_regs(cs,
1183                    A6XX_GRAS_LRZ_CNTL(0));
1184
1185    tu_cs_emit_regs(cs,
1186                    A6XX_RB_LRZ_CNTL(0));
1187
1188    tu_cs_sanity_check(cs);
1189 }
1190
1191 static void
1192 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1193 {
1194    unsigned seqno;
1195
1196    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1197
1198    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1199    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1200                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
1201    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1202    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1203    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1204    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1205
1206    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1207
1208    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1209    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1210    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1211    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1212 }
1213
1214 static void
1215 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1216 {
1217    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1218
1219    tu_cs_emit_regs(cs,
1220                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1221                                      .height = tiling->tile0.extent.height),
1222                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
1223                                          .bo_offset = 32 * cmd->vsc_data_pitch));
1224
1225    tu_cs_emit_regs(cs,
1226                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1227                                       .ny = tiling->tile_count.height));
1228
1229    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1230    for (unsigned i = 0; i < 32; i++)
1231       tu_cs_emit(cs, tiling->pipe_config[i]);
1232
1233    tu_cs_emit_regs(cs,
1234                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1235                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1236                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1237
1238    tu_cs_emit_regs(cs,
1239                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1240                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1241                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1242 }
1243
1244 static void
1245 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1246 {
1247    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1248    const uint32_t used_pipe_count =
1249       tiling->pipe_count.width * tiling->pipe_count.height;
1250
1251    /* Clear vsc_scratch: */
1252    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1253    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1254    tu_cs_emit(cs, 0x0);
1255
1256    /* Check for overflow, write vsc_scratch if detected: */
1257    for (int i = 0; i < used_pipe_count; i++) {
1258       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1259       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1260             CP_COND_WRITE5_0_WRITE_MEMORY);
1261       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1262       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1263       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1264       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1265       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1266       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1267
1268       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1269       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1270             CP_COND_WRITE5_0_WRITE_MEMORY);
1271       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1272       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1273       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1274       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1275       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1276       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1277    }
1278
1279    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1280
1281    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1282
1283    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1284    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1285          CP_MEM_TO_REG_0_CNT(1 - 1));
1286    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1287
1288    /*
1289     * This is a bit awkward, we really want a way to invert the
1290     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1291     * execute cmds to use hwbinning when a bit is *not* set.  This
1292     * dance is to invert OVERFLOW_FLAG_REG
1293     *
1294     * A CP_NOP packet is used to skip executing the 'else' clause
1295     * if (b0 set)..
1296     */
1297
1298    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1299    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1300    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1301          A6XX_CP_REG_TEST_0_BIT(0) |
1302          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1303
1304    tu_cs_reserve(cs, 3 + 7);
1305    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1306    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1307    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1308
1309    /* if (b0 set) */ {
1310       /*
1311        * On overflow, mirror the value to control->vsc_overflow
1312        * which CPU is checking to detect overflow (see
1313        * check_vsc_overflow())
1314        */
1315       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1316       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1317             CP_REG_TO_MEM_0_CNT(0));
1318       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1319
1320       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1321       tu_cs_emit(cs, 0x0);
1322
1323       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1324    } /* else */ {
1325       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1326       tu_cs_emit(cs, 0x1);
1327    }
1328 }
1329
1330 static void
1331 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1332 {
1333    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1334    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1335
1336    uint32_t x1 = tiling->tile0.offset.x;
1337    uint32_t y1 = tiling->tile0.offset.y;
1338    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1339    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1340
1341    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1342
1343    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1344    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1345
1346    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1347    tu_cs_emit(cs, 0x1);
1348
1349    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1350    tu_cs_emit(cs, 0x1);
1351
1352    tu_cs_emit_wfi(cs);
1353
1354    tu_cs_emit_regs(cs,
1355                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1356
1357    update_vsc_pipe(cmd, cs);
1358
1359    tu_cs_emit_regs(cs,
1360                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1361
1362    tu_cs_emit_regs(cs,
1363                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1364
1365    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1366    tu_cs_emit(cs, UNK_2C);
1367
1368    tu_cs_emit_regs(cs,
1369                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1370
1371    tu_cs_emit_regs(cs,
1372                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1373
1374    /* emit IB to binning drawcmds: */
1375    tu_cs_emit_call(cs, &cmd->draw_cs);
1376
1377    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1378    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1379                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1380                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1381    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1382    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1383
1384    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1385    tu_cs_emit(cs, UNK_2D);
1386
1387    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1388    tu6_cache_flush(cmd, cs);
1389
1390    tu_cs_emit_wfi(cs);
1391
1392    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1393
1394    emit_vsc_overflow_test(cmd, cs);
1395
1396    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1397    tu_cs_emit(cs, 0x0);
1398
1399    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1400    tu_cs_emit(cs, 0x0);
1401
1402    tu_cs_emit_wfi(cs);
1403
1404    tu_cs_emit_regs(cs,
1405                    A6XX_RB_CCU_CNTL(.unknown = phys_dev->magic.RB_CCU_CNTL_gmem));
1406
1407    cmd->wait_for_idle = false;
1408 }
1409
1410 static void
1411 tu_emit_sysmem_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1412                                 uint32_t a,
1413                                 const VkRenderPassBeginInfo *info)
1414 {
1415    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1416    const struct tu_image_view *iview = fb->attachments[a].attachment;
1417    const struct tu_render_pass_attachment *attachment =
1418       &cmd->state.pass->attachments[a];
1419    unsigned clear_mask = 0;
1420
1421    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
1422    if (attachment->gmem_offset < 0)
1423       return;
1424
1425    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1426       clear_mask = 0xf;
1427    }
1428
1429    if (vk_format_has_stencil(iview->vk_format)) {
1430       clear_mask &= 0x1;
1431       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1432          clear_mask |= 0x2;
1433       if (clear_mask != 0x3)
1434          tu_finishme("depth/stencil only load op");
1435    }
1436
1437    if (!clear_mask)
1438       return;
1439
1440    tu_clear_sysmem_attachment(cmd, cs, a,
1441                               &info->pClearValues[a], &(struct VkClearRect) {
1442       .rect = info->renderArea,
1443       .baseArrayLayer = iview->base_layer,
1444       .layerCount = iview->layer_count,
1445    });
1446 }
1447
1448 static void
1449 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1450                    const VkRenderPassBeginInfo *info)
1451 {
1452    struct tu_cs *cs = &cmd->draw_cs;
1453
1454    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1455
1456    tu6_emit_blit_scissor(cmd, cs, true);
1457
1458    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1459       tu6_emit_load_attachment(cmd, cs, i);
1460
1461    tu6_emit_blit_scissor(cmd, cs, false);
1462
1463    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1464       tu6_emit_clear_attachment(cmd, cs, i, info);
1465
1466    tu_cond_exec_end(cs);
1467
1468    /* invalidate because reading input attachments will cache GMEM and
1469     * the cache isn''t updated when GMEM is written
1470     * TODO: is there a no-cache bit for textures?
1471     */
1472    if (cmd->state.subpass->input_count)
1473       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1474
1475    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1476
1477    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1478       tu_emit_sysmem_clear_attachment(cmd, cs, i, info);
1479
1480    tu_cond_exec_end(cs);
1481 }
1482
1483 static void
1484 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1485                         const struct VkRect2D *renderArea)
1486 {
1487    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1488
1489    assert(fb->width > 0 && fb->height > 0);
1490    tu6_emit_window_scissor(cmd, cs, 0, 0, fb->width - 1, fb->height - 1);
1491    tu6_emit_window_offset(cmd, cs, 0, 0);
1492
1493    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1494
1495    tu6_emit_lrz_flush(cmd, cs);
1496
1497    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1498    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1499
1500    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1501    tu_cs_emit(cs, 0x0);
1502
1503    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1504    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1505    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1506
1507    tu6_emit_wfi(cmd, cs);
1508    tu_cs_emit_regs(cs,
1509                    A6XX_RB_CCU_CNTL(0x10000000));
1510
1511    /* enable stream-out, with sysmem there is only one pass: */
1512    tu_cs_emit_regs(cs,
1513                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1514
1515    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1516    tu_cs_emit(cs, 0x1);
1517
1518    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1519    tu_cs_emit(cs, 0x0);
1520
1521    tu_cs_sanity_check(cs);
1522 }
1523
1524 static void
1525 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1526 {
1527    /* Do any resolves of the last subpass. These are handled in the
1528     * tile_store_ib in the gmem path.
1529     */
1530
1531    const struct tu_subpass *subpass = cmd->state.subpass;
1532    if (subpass->resolve_attachments) {
1533       for (unsigned i = 0; i < subpass->color_count; i++) {
1534          uint32_t a = subpass->resolve_attachments[i].attachment;
1535          if (a != VK_ATTACHMENT_UNUSED)
1536             tu6_emit_sysmem_resolve(cmd, cs, a,
1537                                     subpass->color_attachments[i].attachment);
1538       }
1539    }
1540
1541    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1542
1543    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1544    tu_cs_emit(cs, 0x0);
1545
1546    tu6_emit_lrz_flush(cmd, cs);
1547
1548    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1549    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1550
1551    tu_cs_sanity_check(cs);
1552 }
1553
1554
1555 static void
1556 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1557 {
1558    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1559
1560    tu6_emit_lrz_flush(cmd, cs);
1561
1562    /* lrz clear? */
1563
1564    tu6_emit_cache_flush(cmd, cs);
1565
1566    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1567    tu_cs_emit(cs, 0x0);
1568
1569    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1570    tu6_emit_wfi(cmd, cs);
1571    tu_cs_emit_regs(cs,
1572                    A6XX_RB_CCU_CNTL(phys_dev->magic.RB_CCU_CNTL_gmem));
1573
1574    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1575    if (use_hw_binning(cmd)) {
1576       tu6_emit_bin_size(cs,
1577                         tiling->tile0.extent.width,
1578                         tiling->tile0.extent.height,
1579                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1580
1581       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1582
1583       tu6_emit_binning_pass(cmd, cs);
1584
1585       tu6_emit_bin_size(cs,
1586                         tiling->tile0.extent.width,
1587                         tiling->tile0.extent.height,
1588                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1589
1590       tu_cs_emit_regs(cs,
1591                       A6XX_VFD_MODE_CNTL(0));
1592
1593       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1594
1595       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1596
1597       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1598       tu_cs_emit(cs, 0x1);
1599    } else {
1600       tu6_emit_bin_size(cs,
1601                         tiling->tile0.extent.width,
1602                         tiling->tile0.extent.height,
1603                         0x6000000);
1604    }
1605
1606    tu_cs_sanity_check(cs);
1607 }
1608
1609 static void
1610 tu6_render_tile(struct tu_cmd_buffer *cmd,
1611                 struct tu_cs *cs,
1612                 const struct tu_tile *tile)
1613 {
1614    tu6_emit_tile_select(cmd, cs, tile);
1615
1616    tu_cs_emit_call(cs, &cmd->draw_cs);
1617    cmd->wait_for_idle = true;
1618
1619    if (use_hw_binning(cmd)) {
1620       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1621       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1622                      A6XX_CP_REG_TEST_0_BIT(0) |
1623                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1624
1625       tu_cs_reserve(cs, 3 + 2);
1626       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1627       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1628       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1629
1630       /* if (no overflow) */ {
1631          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1632          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1633       }
1634    }
1635
1636    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1637
1638    tu_cs_sanity_check(cs);
1639 }
1640
1641 static void
1642 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1643 {
1644    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1645
1646    tu_cs_emit_regs(cs,
1647                    A6XX_GRAS_LRZ_CNTL(0));
1648
1649    tu6_emit_lrz_flush(cmd, cs);
1650
1651    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1652
1653    tu_cs_sanity_check(cs);
1654 }
1655
1656 static void
1657 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1658 {
1659    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1660
1661    tu6_tile_render_begin(cmd, &cmd->cs);
1662
1663    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1664       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1665          struct tu_tile tile;
1666          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1667          tu6_render_tile(cmd, &cmd->cs, &tile);
1668       }
1669    }
1670
1671    tu6_tile_render_end(cmd, &cmd->cs);
1672 }
1673
1674 static void
1675 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1676 {
1677    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1678
1679    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1680
1681    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1682    cmd->wait_for_idle = true;
1683
1684    tu6_sysmem_render_end(cmd, &cmd->cs);
1685 }
1686
1687 static void
1688 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1689 {
1690    const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1691    struct tu_cs sub_cs;
1692
1693    VkResult result =
1694       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1695    if (result != VK_SUCCESS) {
1696       cmd->record_result = result;
1697       return;
1698    }
1699
1700    /* emit to tile-store sub_cs */
1701    tu6_emit_tile_store(cmd, &sub_cs);
1702
1703    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1704 }
1705
1706 static void
1707 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1708                             const VkRect2D *render_area)
1709 {
1710    const struct tu_device *dev = cmd->device;
1711    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1712
1713    tiling->render_area = *render_area;
1714    tiling->force_sysmem = force_sysmem(cmd, render_area);
1715
1716    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1717    tu_tiling_config_update_pipe_layout(tiling, dev);
1718    tu_tiling_config_update_pipes(tiling, dev);
1719 }
1720
1721 const struct tu_dynamic_state default_dynamic_state = {
1722    .viewport =
1723      {
1724        .count = 0,
1725      },
1726    .scissor =
1727      {
1728        .count = 0,
1729      },
1730    .line_width = 1.0f,
1731    .depth_bias =
1732      {
1733        .bias = 0.0f,
1734        .clamp = 0.0f,
1735        .slope = 0.0f,
1736      },
1737    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1738    .depth_bounds =
1739      {
1740        .min = 0.0f,
1741        .max = 1.0f,
1742      },
1743    .stencil_compare_mask =
1744      {
1745        .front = ~0u,
1746        .back = ~0u,
1747      },
1748    .stencil_write_mask =
1749      {
1750        .front = ~0u,
1751        .back = ~0u,
1752      },
1753    .stencil_reference =
1754      {
1755        .front = 0u,
1756        .back = 0u,
1757      },
1758 };
1759
1760 static void UNUSED /* FINISHME */
1761 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1762                       const struct tu_dynamic_state *src)
1763 {
1764    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1765    uint32_t copy_mask = src->mask;
1766    uint32_t dest_mask = 0;
1767
1768    tu_use_args(cmd_buffer); /* FINISHME */
1769
1770    /* Make sure to copy the number of viewports/scissors because they can
1771     * only be specified at pipeline creation time.
1772     */
1773    dest->viewport.count = src->viewport.count;
1774    dest->scissor.count = src->scissor.count;
1775    dest->discard_rectangle.count = src->discard_rectangle.count;
1776
1777    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1778       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1779                  src->viewport.count * sizeof(VkViewport))) {
1780          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1781                       src->viewport.count);
1782          dest_mask |= TU_DYNAMIC_VIEWPORT;
1783       }
1784    }
1785
1786    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1787       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1788                  src->scissor.count * sizeof(VkRect2D))) {
1789          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1790                       src->scissor.count);
1791          dest_mask |= TU_DYNAMIC_SCISSOR;
1792       }
1793    }
1794
1795    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1796       if (dest->line_width != src->line_width) {
1797          dest->line_width = src->line_width;
1798          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1799       }
1800    }
1801
1802    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1803       if (memcmp(&dest->depth_bias, &src->depth_bias,
1804                  sizeof(src->depth_bias))) {
1805          dest->depth_bias = src->depth_bias;
1806          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1807       }
1808    }
1809
1810    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1811       if (memcmp(&dest->blend_constants, &src->blend_constants,
1812                  sizeof(src->blend_constants))) {
1813          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1814          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1815       }
1816    }
1817
1818    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1819       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1820                  sizeof(src->depth_bounds))) {
1821          dest->depth_bounds = src->depth_bounds;
1822          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1823       }
1824    }
1825
1826    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1827       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1828                  sizeof(src->stencil_compare_mask))) {
1829          dest->stencil_compare_mask = src->stencil_compare_mask;
1830          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1831       }
1832    }
1833
1834    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1835       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1836                  sizeof(src->stencil_write_mask))) {
1837          dest->stencil_write_mask = src->stencil_write_mask;
1838          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1839       }
1840    }
1841
1842    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1843       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1844                  sizeof(src->stencil_reference))) {
1845          dest->stencil_reference = src->stencil_reference;
1846          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1847       }
1848    }
1849
1850    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1851       if (memcmp(&dest->discard_rectangle.rectangles,
1852                  &src->discard_rectangle.rectangles,
1853                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1854          typed_memcpy(dest->discard_rectangle.rectangles,
1855                       src->discard_rectangle.rectangles,
1856                       src->discard_rectangle.count);
1857          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1858       }
1859    }
1860 }
1861
1862 static VkResult
1863 tu_create_cmd_buffer(struct tu_device *device,
1864                      struct tu_cmd_pool *pool,
1865                      VkCommandBufferLevel level,
1866                      VkCommandBuffer *pCommandBuffer)
1867 {
1868    struct tu_cmd_buffer *cmd_buffer;
1869    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1870                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1871    if (cmd_buffer == NULL)
1872       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1873
1874    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1875    cmd_buffer->device = device;
1876    cmd_buffer->pool = pool;
1877    cmd_buffer->level = level;
1878
1879    if (pool) {
1880       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1881       cmd_buffer->queue_family_index = pool->queue_family_index;
1882
1883    } else {
1884       /* Init the pool_link so we can safely call list_del when we destroy
1885        * the command buffer
1886        */
1887       list_inithead(&cmd_buffer->pool_link);
1888       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1889    }
1890
1891    tu_bo_list_init(&cmd_buffer->bo_list);
1892    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1893    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1894    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1895    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1896
1897    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1898
1899    list_inithead(&cmd_buffer->upload.list);
1900
1901    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1902    if (result != VK_SUCCESS)
1903       goto fail_scratch_bo;
1904
1905    /* TODO: resize on overflow */
1906    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1907    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1908    cmd_buffer->vsc_data = device->vsc_data;
1909    cmd_buffer->vsc_data2 = device->vsc_data2;
1910
1911    return VK_SUCCESS;
1912
1913 fail_scratch_bo:
1914    list_del(&cmd_buffer->pool_link);
1915    return result;
1916 }
1917
1918 static void
1919 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1920 {
1921    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1922
1923    list_del(&cmd_buffer->pool_link);
1924
1925    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1926       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1927
1928    tu_cs_finish(&cmd_buffer->cs);
1929    tu_cs_finish(&cmd_buffer->draw_cs);
1930    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1931    tu_cs_finish(&cmd_buffer->sub_cs);
1932
1933    tu_bo_list_destroy(&cmd_buffer->bo_list);
1934    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1935 }
1936
1937 static VkResult
1938 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1939 {
1940    cmd_buffer->wait_for_idle = true;
1941
1942    cmd_buffer->record_result = VK_SUCCESS;
1943
1944    tu_bo_list_reset(&cmd_buffer->bo_list);
1945    tu_cs_reset(&cmd_buffer->cs);
1946    tu_cs_reset(&cmd_buffer->draw_cs);
1947    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1948    tu_cs_reset(&cmd_buffer->sub_cs);
1949
1950    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1951       cmd_buffer->descriptors[i].valid = 0;
1952       cmd_buffer->descriptors[i].push_dirty = false;
1953    }
1954
1955    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1956
1957    return cmd_buffer->record_result;
1958 }
1959
1960 VkResult
1961 tu_AllocateCommandBuffers(VkDevice _device,
1962                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1963                           VkCommandBuffer *pCommandBuffers)
1964 {
1965    TU_FROM_HANDLE(tu_device, device, _device);
1966    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1967
1968    VkResult result = VK_SUCCESS;
1969    uint32_t i;
1970
1971    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1972
1973       if (!list_is_empty(&pool->free_cmd_buffers)) {
1974          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1975             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1976
1977          list_del(&cmd_buffer->pool_link);
1978          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1979
1980          result = tu_reset_cmd_buffer(cmd_buffer);
1981          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1982          cmd_buffer->level = pAllocateInfo->level;
1983
1984          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1985       } else {
1986          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1987                                        &pCommandBuffers[i]);
1988       }
1989       if (result != VK_SUCCESS)
1990          break;
1991    }
1992
1993    if (result != VK_SUCCESS) {
1994       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1995                             pCommandBuffers);
1996
1997       /* From the Vulkan 1.0.66 spec:
1998        *
1999        * "vkAllocateCommandBuffers can be used to create multiple
2000        *  command buffers. If the creation of any of those command
2001        *  buffers fails, the implementation must destroy all
2002        *  successfully created command buffer objects from this
2003        *  command, set all entries of the pCommandBuffers array to
2004        *  NULL and return the error."
2005        */
2006       memset(pCommandBuffers, 0,
2007              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2008    }
2009
2010    return result;
2011 }
2012
2013 void
2014 tu_FreeCommandBuffers(VkDevice device,
2015                       VkCommandPool commandPool,
2016                       uint32_t commandBufferCount,
2017                       const VkCommandBuffer *pCommandBuffers)
2018 {
2019    for (uint32_t i = 0; i < commandBufferCount; i++) {
2020       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2021
2022       if (cmd_buffer) {
2023          if (cmd_buffer->pool) {
2024             list_del(&cmd_buffer->pool_link);
2025             list_addtail(&cmd_buffer->pool_link,
2026                          &cmd_buffer->pool->free_cmd_buffers);
2027          } else
2028             tu_cmd_buffer_destroy(cmd_buffer);
2029       }
2030    }
2031 }
2032
2033 VkResult
2034 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
2035                       VkCommandBufferResetFlags flags)
2036 {
2037    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2038    return tu_reset_cmd_buffer(cmd_buffer);
2039 }
2040
2041 VkResult
2042 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2043                       const VkCommandBufferBeginInfo *pBeginInfo)
2044 {
2045    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2046    VkResult result = VK_SUCCESS;
2047
2048    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
2049       /* If the command buffer has already been resetted with
2050        * vkResetCommandBuffer, no need to do it again.
2051        */
2052       result = tu_reset_cmd_buffer(cmd_buffer);
2053       if (result != VK_SUCCESS)
2054          return result;
2055    }
2056
2057    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2058    cmd_buffer->usage_flags = pBeginInfo->flags;
2059
2060    tu_cs_begin(&cmd_buffer->cs);
2061    tu_cs_begin(&cmd_buffer->draw_cs);
2062    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2063
2064    cmd_buffer->scratch_seqno = 0;
2065
2066    /* setup initial configuration into command buffer */
2067    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2068       switch (cmd_buffer->queue_family_index) {
2069       case TU_QUEUE_GENERAL:
2070          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
2071          break;
2072       default:
2073          break;
2074       }
2075    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2076               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2077       assert(pBeginInfo->pInheritanceInfo);
2078       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2079       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2080    }
2081
2082    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
2083
2084    return VK_SUCCESS;
2085 }
2086
2087 void
2088 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
2089                         uint32_t firstBinding,
2090                         uint32_t bindingCount,
2091                         const VkBuffer *pBuffers,
2092                         const VkDeviceSize *pOffsets)
2093 {
2094    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2095
2096    assert(firstBinding + bindingCount <= MAX_VBS);
2097
2098    for (uint32_t i = 0; i < bindingCount; i++) {
2099       cmd->state.vb.buffers[firstBinding + i] =
2100          tu_buffer_from_handle(pBuffers[i]);
2101       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
2102    }
2103
2104    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
2105    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2106 }
2107
2108 void
2109 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
2110                       VkBuffer buffer,
2111                       VkDeviceSize offset,
2112                       VkIndexType indexType)
2113 {
2114    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2115    TU_FROM_HANDLE(tu_buffer, buf, buffer);
2116
2117    /* initialize/update the restart index */
2118    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
2119       struct tu_cs *draw_cs = &cmd->draw_cs;
2120
2121       tu6_emit_restart_index(
2122          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
2123
2124       tu_cs_sanity_check(draw_cs);
2125    }
2126
2127    /* track the BO */
2128    if (cmd->state.index_buffer != buf)
2129       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2130
2131    cmd->state.index_buffer = buf;
2132    cmd->state.index_offset = offset;
2133    cmd->state.index_type = indexType;
2134 }
2135
2136 void
2137 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
2138                          VkPipelineBindPoint pipelineBindPoint,
2139                          VkPipelineLayout _layout,
2140                          uint32_t firstSet,
2141                          uint32_t descriptorSetCount,
2142                          const VkDescriptorSet *pDescriptorSets,
2143                          uint32_t dynamicOffsetCount,
2144                          const uint32_t *pDynamicOffsets)
2145 {
2146    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2147    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
2148    unsigned dyn_idx = 0;
2149
2150    struct tu_descriptor_state *descriptors_state =
2151       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2152
2153    for (unsigned i = 0; i < descriptorSetCount; ++i) {
2154       unsigned idx = i + firstSet;
2155       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
2156
2157       descriptors_state->sets[idx] = set;
2158       descriptors_state->valid |= (1u << idx);
2159
2160       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2161          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2162          assert(dyn_idx < dynamicOffsetCount);
2163
2164          descriptors_state->dynamic_buffers[idx] =
2165          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
2166       }
2167    }
2168
2169    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
2170 }
2171
2172 void
2173 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2174                     VkPipelineLayout layout,
2175                     VkShaderStageFlags stageFlags,
2176                     uint32_t offset,
2177                     uint32_t size,
2178                     const void *pValues)
2179 {
2180    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2181    memcpy((void*) cmd->push_constants + offset, pValues, size);
2182    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2183 }
2184
2185 VkResult
2186 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2187 {
2188    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2189
2190    if (cmd_buffer->scratch_seqno) {
2191       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2192                      MSM_SUBMIT_BO_WRITE);
2193    }
2194
2195    if (cmd_buffer->use_vsc_data) {
2196       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2197                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2198       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2199                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2200    }
2201
2202    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2203       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2204                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2205    }
2206
2207    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
2208       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
2209                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2210    }
2211
2212    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2213       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2214                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2215    }
2216
2217    tu_cs_end(&cmd_buffer->cs);
2218    tu_cs_end(&cmd_buffer->draw_cs);
2219    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2220
2221    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2222
2223    return cmd_buffer->record_result;
2224 }
2225
2226 void
2227 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2228                    VkPipelineBindPoint pipelineBindPoint,
2229                    VkPipeline _pipeline)
2230 {
2231    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2232    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2233
2234    switch (pipelineBindPoint) {
2235    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2236       cmd->state.pipeline = pipeline;
2237       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2238       break;
2239    case VK_PIPELINE_BIND_POINT_COMPUTE:
2240       cmd->state.compute_pipeline = pipeline;
2241       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2242       break;
2243    default:
2244       unreachable("unrecognized pipeline bind point");
2245       break;
2246    }
2247
2248    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2249                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2250    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2251       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2252                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2253    }
2254 }
2255
2256 void
2257 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2258                   uint32_t firstViewport,
2259                   uint32_t viewportCount,
2260                   const VkViewport *pViewports)
2261 {
2262    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2263    struct tu_cs *draw_cs = &cmd->draw_cs;
2264
2265    assert(firstViewport == 0 && viewportCount == 1);
2266    tu6_emit_viewport(draw_cs, pViewports);
2267
2268    tu_cs_sanity_check(draw_cs);
2269 }
2270
2271 void
2272 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2273                  uint32_t firstScissor,
2274                  uint32_t scissorCount,
2275                  const VkRect2D *pScissors)
2276 {
2277    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2278    struct tu_cs *draw_cs = &cmd->draw_cs;
2279
2280    assert(firstScissor == 0 && scissorCount == 1);
2281    tu6_emit_scissor(draw_cs, pScissors);
2282
2283    tu_cs_sanity_check(draw_cs);
2284 }
2285
2286 void
2287 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2288 {
2289    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2290
2291    cmd->state.dynamic.line_width = lineWidth;
2292
2293    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2294    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2295 }
2296
2297 void
2298 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2299                    float depthBiasConstantFactor,
2300                    float depthBiasClamp,
2301                    float depthBiasSlopeFactor)
2302 {
2303    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2304    struct tu_cs *draw_cs = &cmd->draw_cs;
2305
2306    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2307                        depthBiasSlopeFactor);
2308
2309    tu_cs_sanity_check(draw_cs);
2310 }
2311
2312 void
2313 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2314                         const float blendConstants[4])
2315 {
2316    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2317    struct tu_cs *draw_cs = &cmd->draw_cs;
2318
2319    tu6_emit_blend_constants(draw_cs, blendConstants);
2320
2321    tu_cs_sanity_check(draw_cs);
2322 }
2323
2324 void
2325 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2326                      float minDepthBounds,
2327                      float maxDepthBounds)
2328 {
2329 }
2330
2331 void
2332 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2333                             VkStencilFaceFlags faceMask,
2334                             uint32_t compareMask)
2335 {
2336    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2337
2338    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2339       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2340    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2341       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2342
2343    /* the front/back compare masks must be updated together */
2344    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2345 }
2346
2347 void
2348 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2349                           VkStencilFaceFlags faceMask,
2350                           uint32_t writeMask)
2351 {
2352    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2353
2354    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2355       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2356    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2357       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2358
2359    /* the front/back write masks must be updated together */
2360    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2361 }
2362
2363 void
2364 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2365                           VkStencilFaceFlags faceMask,
2366                           uint32_t reference)
2367 {
2368    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2369
2370    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2371       cmd->state.dynamic.stencil_reference.front = reference;
2372    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2373       cmd->state.dynamic.stencil_reference.back = reference;
2374
2375    /* the front/back references must be updated together */
2376    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2377 }
2378
2379 void
2380 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2381                       uint32_t commandBufferCount,
2382                       const VkCommandBuffer *pCmdBuffers)
2383 {
2384    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2385    VkResult result;
2386
2387    assert(commandBufferCount > 0);
2388
2389    for (uint32_t i = 0; i < commandBufferCount; i++) {
2390       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2391
2392       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2393       if (result != VK_SUCCESS) {
2394          cmd->record_result = result;
2395          break;
2396       }
2397
2398       if (secondary->usage_flags &
2399           VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2400          assert(tu_cs_is_empty(&secondary->cs));
2401
2402          result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2403          if (result != VK_SUCCESS) {
2404             cmd->record_result = result;
2405             break;
2406          }
2407
2408          result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2409                &secondary->draw_epilogue_cs);
2410          if (result != VK_SUCCESS) {
2411             cmd->record_result = result;
2412             break;
2413          }
2414       } else {
2415          assert(tu_cs_is_empty(&secondary->draw_cs));
2416          assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
2417
2418          for (uint32_t j = 0; j < secondary->cs.bo_count; j++) {
2419             tu_bo_list_add(&cmd->bo_list, secondary->cs.bos[j],
2420                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2421          }
2422
2423          tu_cs_emit_call(&cmd->cs, &secondary->cs);
2424       }
2425    }
2426    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2427 }
2428
2429 VkResult
2430 tu_CreateCommandPool(VkDevice _device,
2431                      const VkCommandPoolCreateInfo *pCreateInfo,
2432                      const VkAllocationCallbacks *pAllocator,
2433                      VkCommandPool *pCmdPool)
2434 {
2435    TU_FROM_HANDLE(tu_device, device, _device);
2436    struct tu_cmd_pool *pool;
2437
2438    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2439                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2440    if (pool == NULL)
2441       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2442
2443    if (pAllocator)
2444       pool->alloc = *pAllocator;
2445    else
2446       pool->alloc = device->alloc;
2447
2448    list_inithead(&pool->cmd_buffers);
2449    list_inithead(&pool->free_cmd_buffers);
2450
2451    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2452
2453    *pCmdPool = tu_cmd_pool_to_handle(pool);
2454
2455    return VK_SUCCESS;
2456 }
2457
2458 void
2459 tu_DestroyCommandPool(VkDevice _device,
2460                       VkCommandPool commandPool,
2461                       const VkAllocationCallbacks *pAllocator)
2462 {
2463    TU_FROM_HANDLE(tu_device, device, _device);
2464    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2465
2466    if (!pool)
2467       return;
2468
2469    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2470                             &pool->cmd_buffers, pool_link)
2471    {
2472       tu_cmd_buffer_destroy(cmd_buffer);
2473    }
2474
2475    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2476                             &pool->free_cmd_buffers, pool_link)
2477    {
2478       tu_cmd_buffer_destroy(cmd_buffer);
2479    }
2480
2481    vk_free2(&device->alloc, pAllocator, pool);
2482 }
2483
2484 VkResult
2485 tu_ResetCommandPool(VkDevice device,
2486                     VkCommandPool commandPool,
2487                     VkCommandPoolResetFlags flags)
2488 {
2489    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2490    VkResult result;
2491
2492    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2493                        pool_link)
2494    {
2495       result = tu_reset_cmd_buffer(cmd_buffer);
2496       if (result != VK_SUCCESS)
2497          return result;
2498    }
2499
2500    return VK_SUCCESS;
2501 }
2502
2503 void
2504 tu_TrimCommandPool(VkDevice device,
2505                    VkCommandPool commandPool,
2506                    VkCommandPoolTrimFlags flags)
2507 {
2508    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2509
2510    if (!pool)
2511       return;
2512
2513    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2514                             &pool->free_cmd_buffers, pool_link)
2515    {
2516       tu_cmd_buffer_destroy(cmd_buffer);
2517    }
2518 }
2519
2520 void
2521 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2522                       const VkRenderPassBeginInfo *pRenderPassBegin,
2523                       VkSubpassContents contents)
2524 {
2525    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2526    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2527    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2528
2529    cmd->state.pass = pass;
2530    cmd->state.subpass = pass->subpasses;
2531    cmd->state.framebuffer = fb;
2532
2533    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2534    tu_cmd_prepare_tile_store_ib(cmd);
2535
2536    tu_emit_load_clear(cmd, pRenderPassBegin);
2537
2538    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2539    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2540    tu6_emit_msaa(cmd, cmd->state.subpass, &cmd->draw_cs);
2541    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2542
2543    /* note: use_hw_binning only checks tiling config */
2544    if (use_hw_binning(cmd))
2545       cmd->use_vsc_data = true;
2546
2547    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2548       const struct tu_image_view *iview = fb->attachments[i].attachment;
2549       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2550                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2551    }
2552 }
2553
2554 void
2555 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2556                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2557                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2558 {
2559    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2560                          pSubpassBeginInfo->contents);
2561 }
2562
2563 void
2564 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2565 {
2566    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2567    const struct tu_render_pass *pass = cmd->state.pass;
2568    struct tu_cs *cs = &cmd->draw_cs;
2569
2570    const struct tu_subpass *subpass = cmd->state.subpass++;
2571    /* TODO:
2572     * if msaa samples change between subpasses,
2573     * attachment store is broken for some attachments
2574     */
2575    if (subpass->resolve_attachments) {
2576       tu6_emit_blit_scissor(cmd, cs, true);
2577       for (unsigned i = 0; i < subpass->color_count; i++) {
2578          uint32_t a = subpass->resolve_attachments[i].attachment;
2579          if (a != VK_ATTACHMENT_UNUSED) {
2580             tu6_emit_resolve(cmd, cs, a,
2581                              subpass->color_attachments[i].attachment);
2582          }
2583       }
2584    }
2585
2586    /* invalidate because reading input attachments will cache GMEM and
2587     * the cache isn''t updated when GMEM is written
2588     * TODO: is there a no-cache bit for textures?
2589     */
2590    if (cmd->state.subpass->input_count)
2591       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2592
2593    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2594    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2595    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2596    tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2597    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2598
2599    /* Emit flushes so that input attachments will read the correct value. This
2600     * is for sysmem only, although it shouldn't do much harm on gmem.
2601     */
2602    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2603    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2604
2605    /* TODO:
2606     * since we don't know how to do GMEM->GMEM resolve,
2607     * resolve attachments are resolved to memory then loaded to GMEM again if needed
2608     */
2609    if (subpass->resolve_attachments) {
2610       for (unsigned i = 0; i < subpass->color_count; i++) {
2611          uint32_t a = subpass->resolve_attachments[i].attachment;
2612          if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2613                tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2614                tu6_emit_predicated_blit(cmd, cs, a, a, false);
2615          }
2616       }
2617    }
2618 }
2619
2620 void
2621 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2622                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2623                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2624 {
2625    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2626 }
2627
2628 struct tu_draw_info
2629 {
2630    /**
2631     * Number of vertices.
2632     */
2633    uint32_t count;
2634
2635    /**
2636     * Index of the first vertex.
2637     */
2638    int32_t vertex_offset;
2639
2640    /**
2641     * First instance id.
2642     */
2643    uint32_t first_instance;
2644
2645    /**
2646     * Number of instances.
2647     */
2648    uint32_t instance_count;
2649
2650    /**
2651     * First index (indexed draws only).
2652     */
2653    uint32_t first_index;
2654
2655    /**
2656     * Whether it's an indexed draw.
2657     */
2658    bool indexed;
2659
2660    /**
2661     * Indirect draw parameters resource.
2662     */
2663    struct tu_buffer *indirect;
2664    uint64_t indirect_offset;
2665    uint32_t stride;
2666
2667    /**
2668     * Draw count parameters resource.
2669     */
2670    struct tu_buffer *count_buffer;
2671    uint64_t count_buffer_offset;
2672 };
2673
2674 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2675 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2676
2677 enum tu_draw_state_group_id
2678 {
2679    TU_DRAW_STATE_PROGRAM,
2680    TU_DRAW_STATE_PROGRAM_BINNING,
2681    TU_DRAW_STATE_VI,
2682    TU_DRAW_STATE_VI_BINNING,
2683    TU_DRAW_STATE_VP,
2684    TU_DRAW_STATE_RAST,
2685    TU_DRAW_STATE_DS,
2686    TU_DRAW_STATE_BLEND,
2687    TU_DRAW_STATE_VS_CONST,
2688    TU_DRAW_STATE_FS_CONST,
2689    TU_DRAW_STATE_VS_TEX,
2690    TU_DRAW_STATE_FS_TEX_SYSMEM,
2691    TU_DRAW_STATE_FS_TEX_GMEM,
2692    TU_DRAW_STATE_FS_IBO,
2693    TU_DRAW_STATE_VS_PARAMS,
2694
2695    TU_DRAW_STATE_COUNT,
2696 };
2697
2698 struct tu_draw_state_group
2699 {
2700    enum tu_draw_state_group_id id;
2701    uint32_t enable_mask;
2702    struct tu_cs_entry ib;
2703 };
2704
2705 const static struct tu_sampler*
2706 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2707             const struct tu_descriptor_map *map, unsigned i,
2708             unsigned array_index)
2709 {
2710    assert(descriptors_state->valid & (1 << map->set[i]));
2711
2712    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2713    assert(map->binding[i] < set->layout->binding_count);
2714
2715    const struct tu_descriptor_set_binding_layout *layout =
2716       &set->layout->binding[map->binding[i]];
2717
2718    if (layout->immutable_samplers_offset) {
2719       const struct tu_sampler *immutable_samplers =
2720          tu_immutable_samplers(set->layout, layout);
2721
2722       return &immutable_samplers[array_index];
2723    }
2724
2725    switch (layout->type) {
2726    case VK_DESCRIPTOR_TYPE_SAMPLER:
2727       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2728    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2729       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2730                                                    array_index *
2731                                                    (A6XX_TEX_CONST_DWORDS +
2732                                                     sizeof(struct tu_sampler) / 4)];
2733    default:
2734       unreachable("unimplemented descriptor type");
2735       break;
2736    }
2737 }
2738
2739 static void
2740 write_tex_const(struct tu_cmd_buffer *cmd,
2741                 uint32_t *dst,
2742                 struct tu_descriptor_state *descriptors_state,
2743                 const struct tu_descriptor_map *map,
2744                 unsigned i, unsigned array_index, bool is_sysmem)
2745 {
2746    assert(descriptors_state->valid & (1 << map->set[i]));
2747
2748    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2749    assert(map->binding[i] < set->layout->binding_count);
2750
2751    const struct tu_descriptor_set_binding_layout *layout =
2752       &set->layout->binding[map->binding[i]];
2753
2754    switch (layout->type) {
2755    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2756    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2757    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2758    case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2759       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2760                                    array_index * A6XX_TEX_CONST_DWORDS],
2761              A6XX_TEX_CONST_DWORDS * 4);
2762       break;
2763    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2764       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2765                                    array_index *
2766                                    (A6XX_TEX_CONST_DWORDS +
2767                                     sizeof(struct tu_sampler) / 4)],
2768              A6XX_TEX_CONST_DWORDS * 4);
2769       break;
2770    default:
2771       unreachable("unimplemented descriptor type");
2772       break;
2773    }
2774
2775    if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
2776       const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2777       uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2778                                                          array_index].attachment;
2779       const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2780
2781       assert(att->gmem_offset >= 0);
2782
2783       dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2784       dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2785       dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2786       dst[2] |=
2787          A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2788          A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2789       dst[3] = 0;
2790       dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
2791       dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2792       for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2793          dst[i] = 0;
2794
2795       if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2796          tu_finishme("patch input attachment pitch for secondary cmd buffer");
2797    }
2798 }
2799
2800 static void
2801 write_image_ibo(struct tu_cmd_buffer *cmd,
2802                 uint32_t *dst,
2803                 struct tu_descriptor_state *descriptors_state,
2804                 const struct tu_descriptor_map *map,
2805                 unsigned i, unsigned array_index)
2806 {
2807    assert(descriptors_state->valid & (1 << map->set[i]));
2808
2809    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2810    assert(map->binding[i] < set->layout->binding_count);
2811
2812    const struct tu_descriptor_set_binding_layout *layout =
2813       &set->layout->binding[map->binding[i]];
2814
2815    assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2816
2817    memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2818                                 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2819           A6XX_TEX_CONST_DWORDS * 4);
2820 }
2821
2822 static uint64_t
2823 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2824            const struct tu_descriptor_map *map,
2825            unsigned i, unsigned array_index)
2826 {
2827    assert(descriptors_state->valid & (1 << map->set[i]));
2828
2829    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2830    assert(map->binding[i] < set->layout->binding_count);
2831
2832    const struct tu_descriptor_set_binding_layout *layout =
2833       &set->layout->binding[map->binding[i]];
2834
2835    switch (layout->type) {
2836    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2837    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2838       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2839                                                 array_index];
2840    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2841    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2842       return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2843                         set->mapped_ptr[layout->offset / 4 + array_index * 2];
2844    default:
2845       unreachable("unimplemented descriptor type");
2846       break;
2847    }
2848 }
2849
2850 static inline uint32_t
2851 tu6_stage2opcode(gl_shader_stage type)
2852 {
2853    switch (type) {
2854    case MESA_SHADER_VERTEX:
2855    case MESA_SHADER_TESS_CTRL:
2856    case MESA_SHADER_TESS_EVAL:
2857    case MESA_SHADER_GEOMETRY:
2858       return CP_LOAD_STATE6_GEOM;
2859    case MESA_SHADER_FRAGMENT:
2860    case MESA_SHADER_COMPUTE:
2861    case MESA_SHADER_KERNEL:
2862       return CP_LOAD_STATE6_FRAG;
2863    default:
2864       unreachable("bad shader type");
2865    }
2866 }
2867
2868 static inline enum a6xx_state_block
2869 tu6_stage2shadersb(gl_shader_stage type)
2870 {
2871    switch (type) {
2872    case MESA_SHADER_VERTEX:
2873       return SB6_VS_SHADER;
2874    case MESA_SHADER_FRAGMENT:
2875       return SB6_FS_SHADER;
2876    case MESA_SHADER_COMPUTE:
2877    case MESA_SHADER_KERNEL:
2878       return SB6_CS_SHADER;
2879    default:
2880       unreachable("bad shader type");
2881       return ~0;
2882    }
2883 }
2884
2885 static void
2886 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2887                      struct tu_descriptor_state *descriptors_state,
2888                      gl_shader_stage type,
2889                      uint32_t *push_constants)
2890 {
2891    const struct tu_program_descriptor_linkage *link =
2892       &pipeline->program.link[type];
2893    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2894
2895    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2896       if (state->range[i].start < state->range[i].end) {
2897          uint32_t size = state->range[i].end - state->range[i].start;
2898          uint32_t offset = state->range[i].start;
2899
2900          /* and even if the start of the const buffer is before
2901           * first_immediate, the end may not be:
2902           */
2903          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2904
2905          if (size == 0)
2906             continue;
2907
2908          /* things should be aligned to vec4: */
2909          debug_assert((state->range[i].offset % 16) == 0);
2910          debug_assert((size % 16) == 0);
2911          debug_assert((offset % 16) == 0);
2912
2913          if (i == 0) {
2914             /* push constants */
2915             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2916             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2917                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2918                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2919                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2920                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2921             tu_cs_emit(cs, 0);
2922             tu_cs_emit(cs, 0);
2923             for (unsigned i = 0; i < size / 4; i++)
2924                tu_cs_emit(cs, push_constants[i + offset / 4]);
2925             continue;
2926          }
2927
2928          /* Look through the UBO map to find our UBO index, and get the VA for
2929           * that UBO.
2930           */
2931          uint64_t va = 0;
2932          uint32_t ubo_idx = i - 1;
2933          uint32_t ubo_map_base = 0;
2934          for (int j = 0; j < link->ubo_map.num; j++) {
2935             if (ubo_idx >= ubo_map_base &&
2936                 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2937                va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2938                                ubo_idx - ubo_map_base);
2939                break;
2940             }
2941             ubo_map_base += link->ubo_map.array_size[j];
2942          }
2943          assert(va);
2944
2945          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2946          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2947                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2948                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2949                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2950                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2951          tu_cs_emit_qw(cs, va + offset);
2952       }
2953    }
2954 }
2955
2956 static void
2957 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2958               struct tu_descriptor_state *descriptors_state,
2959               gl_shader_stage type)
2960 {
2961    const struct tu_program_descriptor_linkage *link =
2962       &pipeline->program.link[type];
2963
2964    uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2965    uint32_t anum = align(num, 2);
2966
2967    if (!num)
2968       return;
2969
2970    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2971    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2972          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2973          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2974          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2975          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2976    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2977    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2978
2979    unsigned emitted = 0;
2980    for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2981       for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2982          tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2983          emitted++;
2984       }
2985    }
2986
2987    for (; emitted < anum; emitted++) {
2988       tu_cs_emit(cs, 0xffffffff);
2989       tu_cs_emit(cs, 0xffffffff);
2990    }
2991 }
2992
2993 static struct tu_cs_entry
2994 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2995                 const struct tu_pipeline *pipeline,
2996                 struct tu_descriptor_state *descriptors_state,
2997                 gl_shader_stage type)
2998 {
2999    struct tu_cs cs;
3000    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
3001
3002    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
3003    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
3004
3005    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3006 }
3007
3008 static VkResult
3009 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
3010                    const struct tu_draw_info *draw,
3011                    struct tu_cs_entry *entry)
3012 {
3013    /* TODO: fill out more than just base instance */
3014    const struct tu_program_descriptor_linkage *link =
3015       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
3016    const struct ir3_const_state *const_state = &link->const_state;
3017    struct tu_cs cs;
3018
3019    if (const_state->offsets.driver_param >= link->constlen) {
3020       *entry = (struct tu_cs_entry) {};
3021       return VK_SUCCESS;
3022    }
3023
3024    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
3025    if (result != VK_SUCCESS)
3026       return result;
3027
3028    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3029    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
3030          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3031          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3032          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
3033          CP_LOAD_STATE6_0_NUM_UNIT(1));
3034    tu_cs_emit(&cs, 0);
3035    tu_cs_emit(&cs, 0);
3036
3037    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
3038
3039    tu_cs_emit(&cs, 0);
3040    tu_cs_emit(&cs, 0);
3041    tu_cs_emit(&cs, draw->first_instance);
3042    tu_cs_emit(&cs, 0);
3043
3044    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3045    return VK_SUCCESS;
3046 }
3047
3048 static VkResult
3049 tu6_emit_textures(struct tu_cmd_buffer *cmd,
3050                   const struct tu_pipeline *pipeline,
3051                   struct tu_descriptor_state *descriptors_state,
3052                   gl_shader_stage type,
3053                   struct tu_cs_entry *entry,
3054                   bool *needs_border,
3055                   bool is_sysmem)
3056 {
3057    struct tu_cs *draw_state = &cmd->sub_cs;
3058    const struct tu_program_descriptor_linkage *link =
3059       &pipeline->program.link[type];
3060    VkResult result;
3061
3062    if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
3063       *entry = (struct tu_cs_entry) {};
3064       return VK_SUCCESS;
3065    }
3066
3067    /* allocate and fill texture state */
3068    struct ts_cs_memory tex_const;
3069    result = tu_cs_alloc(draw_state, link->texture_map.num_desc,
3070                         A6XX_TEX_CONST_DWORDS, &tex_const);
3071    if (result != VK_SUCCESS)
3072       return result;
3073
3074    int tex_index = 0;
3075    for (unsigned i = 0; i < link->texture_map.num; i++) {
3076       for (int j = 0; j < link->texture_map.array_size[i]; j++) {
3077          write_tex_const(cmd,
3078                          &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
3079                          descriptors_state, &link->texture_map, i, j,
3080                          is_sysmem);
3081       }
3082    }
3083
3084    /* allocate and fill sampler state */
3085    struct ts_cs_memory tex_samp = { 0 };
3086    if (link->sampler_map.num_desc) {
3087       result = tu_cs_alloc(draw_state, link->sampler_map.num_desc,
3088                            A6XX_TEX_SAMP_DWORDS, &tex_samp);
3089       if (result != VK_SUCCESS)
3090          return result;
3091
3092       int sampler_index = 0;
3093       for (unsigned i = 0; i < link->sampler_map.num; i++) {
3094          for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
3095             const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3096                                                            &link->sampler_map,
3097                                                            i, j);
3098             memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
3099                    sampler->state, sizeof(sampler->state));
3100             *needs_border |= sampler->needs_border;
3101          }
3102       }
3103    }
3104
3105    unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
3106    enum a6xx_state_block sb;
3107
3108    switch (type) {
3109    case MESA_SHADER_VERTEX:
3110       sb = SB6_VS_TEX;
3111       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
3112       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
3113       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
3114       break;
3115    case MESA_SHADER_FRAGMENT:
3116       sb = SB6_FS_TEX;
3117       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
3118       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
3119       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
3120       break;
3121    case MESA_SHADER_COMPUTE:
3122       sb = SB6_CS_TEX;
3123       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
3124       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
3125       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
3126       break;
3127    default:
3128       unreachable("bad state block");
3129    }
3130
3131    struct tu_cs cs;
3132    result = tu_cs_begin_sub_stream(draw_state, 16, &cs);
3133    if (result != VK_SUCCESS)
3134       return result;
3135
3136    if (link->sampler_map.num_desc) {
3137       /* output sampler state: */
3138       tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3139       tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3140                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
3141                  CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3142                  CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3143                  CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
3144       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3145
3146       tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
3147       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3148    }
3149
3150    /* emit texture state: */
3151    tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3152    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3153       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3154       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3155       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3156       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
3157    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3158
3159    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
3160    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3161
3162    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
3163    tu_cs_emit(&cs, link->texture_map.num_desc);
3164
3165    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3166    return VK_SUCCESS;
3167 }
3168
3169 static VkResult
3170 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
3171              const struct tu_pipeline *pipeline,
3172              struct tu_descriptor_state *descriptors_state,
3173              gl_shader_stage type,
3174              struct tu_cs_entry *entry)
3175 {
3176    struct tu_cs *draw_state = &cmd->sub_cs;
3177    const struct tu_program_descriptor_linkage *link =
3178       &pipeline->program.link[type];
3179    VkResult result;
3180
3181    unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
3182
3183    if (num_desc == 0) {
3184       *entry = (struct tu_cs_entry) {};
3185       return VK_SUCCESS;
3186    }
3187
3188    struct ts_cs_memory ibo_const;
3189    result = tu_cs_alloc(draw_state, num_desc,
3190                         A6XX_TEX_CONST_DWORDS, &ibo_const);
3191    if (result != VK_SUCCESS)
3192       return result;
3193
3194    int ssbo_index = 0;
3195    for (unsigned i = 0; i < link->ssbo_map.num; i++) {
3196       for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
3197          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3198
3199          uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
3200          /* We don't expose robustBufferAccess, so leave the size unlimited. */
3201          uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
3202
3203          dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
3204          dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
3205                   A6XX_IBO_1_HEIGHT(sz >> 15);
3206          dst[2] = A6XX_IBO_2_UNK4 |
3207                   A6XX_IBO_2_UNK31 |
3208                   A6XX_IBO_2_TYPE(A6XX_TEX_1D);
3209          dst[3] = 0;
3210          dst[4] = va;
3211          dst[5] = va >> 32;
3212          for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
3213             dst[i] = 0;
3214
3215          ssbo_index++;
3216       }
3217    }
3218
3219    for (unsigned i = 0; i < link->image_map.num; i++) {
3220       for (int j = 0; j < link->image_map.array_size[i]; j++) {
3221          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3222
3223          write_image_ibo(cmd, dst,
3224                          descriptors_state, &link->image_map, i, j);
3225
3226          ssbo_index++;
3227       }
3228    }
3229
3230    assert(ssbo_index == num_desc);
3231
3232    struct tu_cs cs;
3233    result = tu_cs_begin_sub_stream(draw_state, 7, &cs);
3234    if (result != VK_SUCCESS)
3235       return result;
3236
3237    uint32_t opcode, ibo_addr_reg;
3238    enum a6xx_state_block sb;
3239    enum a6xx_state_type st;
3240
3241    switch (type) {
3242    case MESA_SHADER_FRAGMENT:
3243       opcode = CP_LOAD_STATE6;
3244       st = ST6_SHADER;
3245       sb = SB6_IBO;
3246       ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3247       break;
3248    case MESA_SHADER_COMPUTE:
3249       opcode = CP_LOAD_STATE6_FRAG;
3250       st = ST6_IBO;
3251       sb = SB6_CS_SHADER;
3252       ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3253       break;
3254    default:
3255       unreachable("unsupported stage for ibos");
3256    }
3257
3258    /* emit texture state: */
3259    tu_cs_emit_pkt7(&cs, opcode, 3);
3260    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3261               CP_LOAD_STATE6_0_STATE_TYPE(st) |
3262               CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3263               CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3264               CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3265    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3266
3267    tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3268    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3269
3270    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3271    return VK_SUCCESS;
3272 }
3273
3274 struct PACKED bcolor_entry {
3275    uint32_t fp32[4];
3276    uint16_t ui16[4];
3277    int16_t  si16[4];
3278    uint16_t fp16[4];
3279    uint16_t rgb565;
3280    uint16_t rgb5a1;
3281    uint16_t rgba4;
3282    uint8_t __pad0[2];
3283    uint8_t  ui8[4];
3284    int8_t   si8[4];
3285    uint32_t rgb10a2;
3286    uint32_t z24; /* also s8? */
3287    uint16_t srgb[4];      /* appears to duplicate fp16[], but clamped, used for srgb */
3288    uint8_t  __pad1[56];
3289 } border_color[] = {
3290    [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3291    [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3292    [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3293       .fp32[3] = 0x3f800000,
3294       .ui16[3] = 0xffff,
3295       .si16[3] = 0x7fff,
3296       .fp16[3] = 0x3c00,
3297       .rgb5a1 = 0x8000,
3298       .rgba4 = 0xf000,
3299       .ui8[3] = 0xff,
3300       .si8[3] = 0x7f,
3301       .rgb10a2 = 0xc0000000,
3302       .srgb[3] = 0x3c00,
3303    },
3304    [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3305       .fp32[3] = 1,
3306       .fp16[3] = 1,
3307    },
3308    [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3309       .fp32[0 ... 3] = 0x3f800000,
3310       .ui16[0 ... 3] = 0xffff,
3311       .si16[0 ... 3] = 0x7fff,
3312       .fp16[0 ... 3] = 0x3c00,
3313       .rgb565 = 0xffff,
3314       .rgb5a1 = 0xffff,
3315       .rgba4 = 0xffff,
3316       .ui8[0 ... 3] = 0xff,
3317       .si8[0 ... 3] = 0x7f,
3318       .rgb10a2 = 0xffffffff,
3319       .z24 = 0xffffff,
3320       .srgb[0 ... 3] = 0x3c00,
3321    },
3322    [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3323       .fp32[0 ... 3] = 1,
3324       .fp16[0 ... 3] = 1,
3325    },
3326 };
3327
3328 static VkResult
3329 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3330                       struct tu_cs *cs)
3331 {
3332    STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3333
3334    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3335    struct tu_descriptor_state *descriptors_state =
3336       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3337    const struct tu_descriptor_map *vs_sampler =
3338       &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3339    const struct tu_descriptor_map *fs_sampler =
3340       &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3341    struct ts_cs_memory ptr;
3342
3343    VkResult result = tu_cs_alloc(&cmd->sub_cs,
3344                                  vs_sampler->num_desc + fs_sampler->num_desc,
3345                                  128 / 4,
3346                                  &ptr);
3347    if (result != VK_SUCCESS)
3348       return result;
3349
3350    for (unsigned i = 0; i < vs_sampler->num; i++) {
3351       for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3352          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3353                                                         vs_sampler, i, j);
3354          memcpy(ptr.map, &border_color[sampler->border], 128);
3355          ptr.map += 128 / 4;
3356       }
3357    }
3358
3359    for (unsigned i = 0; i < fs_sampler->num; i++) {
3360       for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3361          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3362                                                         fs_sampler, i, j);
3363          memcpy(ptr.map, &border_color[sampler->border], 128);
3364          ptr.map += 128 / 4;
3365       }
3366    }
3367
3368    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3369    tu_cs_emit_qw(cs, ptr.iova);
3370    return VK_SUCCESS;
3371 }
3372
3373 static VkResult
3374 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3375                      struct tu_cs *cs,
3376                      const struct tu_draw_info *draw)
3377 {
3378    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3379    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3380    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3381    uint32_t draw_state_group_count = 0;
3382    VkResult result;
3383
3384    struct tu_descriptor_state *descriptors_state =
3385       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3386
3387    /* TODO lrz */
3388
3389    tu_cs_emit_regs(cs,
3390                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3391                                             pipeline->ia.primitive_restart && draw->indexed));
3392
3393    if (cmd->state.dirty &
3394           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3395        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3396       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3397                             dynamic->line_width);
3398    }
3399
3400    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3401        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3402       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3403                                     dynamic->stencil_compare_mask.back);
3404    }
3405
3406    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3407        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3408       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3409                                   dynamic->stencil_write_mask.back);
3410    }
3411
3412    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3413        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3414       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3415                                  dynamic->stencil_reference.back);
3416    }
3417
3418    if (cmd->state.dirty &
3419        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3420       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3421          const uint32_t binding = pipeline->vi.bindings[i];
3422          const uint32_t stride = pipeline->vi.strides[i];
3423          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3424          const VkDeviceSize offset = buf->bo_offset +
3425                                      cmd->state.vb.offsets[binding] +
3426                                      pipeline->vi.offsets[i];
3427          const VkDeviceSize size =
3428             offset < buf->bo->size ? buf->bo->size - offset : 0;
3429
3430          tu_cs_emit_regs(cs,
3431                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3432                          A6XX_VFD_FETCH_SIZE(i, size),
3433                          A6XX_VFD_FETCH_STRIDE(i, stride));
3434       }
3435    }
3436
3437    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3438       draw_state_groups[draw_state_group_count++] =
3439          (struct tu_draw_state_group) {
3440             .id = TU_DRAW_STATE_PROGRAM,
3441             .enable_mask = ENABLE_DRAW,
3442             .ib = pipeline->program.state_ib,
3443          };
3444       draw_state_groups[draw_state_group_count++] =
3445          (struct tu_draw_state_group) {
3446             .id = TU_DRAW_STATE_PROGRAM_BINNING,
3447             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3448             .ib = pipeline->program.binning_state_ib,
3449          };
3450       draw_state_groups[draw_state_group_count++] =
3451          (struct tu_draw_state_group) {
3452             .id = TU_DRAW_STATE_VI,
3453             .enable_mask = ENABLE_DRAW,
3454             .ib = pipeline->vi.state_ib,
3455          };
3456       draw_state_groups[draw_state_group_count++] =
3457          (struct tu_draw_state_group) {
3458             .id = TU_DRAW_STATE_VI_BINNING,
3459             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3460             .ib = pipeline->vi.binning_state_ib,
3461          };
3462       draw_state_groups[draw_state_group_count++] =
3463          (struct tu_draw_state_group) {
3464             .id = TU_DRAW_STATE_VP,
3465             .enable_mask = ENABLE_ALL,
3466             .ib = pipeline->vp.state_ib,
3467          };
3468       draw_state_groups[draw_state_group_count++] =
3469          (struct tu_draw_state_group) {
3470             .id = TU_DRAW_STATE_RAST,
3471             .enable_mask = ENABLE_ALL,
3472             .ib = pipeline->rast.state_ib,
3473          };
3474       draw_state_groups[draw_state_group_count++] =
3475          (struct tu_draw_state_group) {
3476             .id = TU_DRAW_STATE_DS,
3477             .enable_mask = ENABLE_ALL,
3478             .ib = pipeline->ds.state_ib,
3479          };
3480       draw_state_groups[draw_state_group_count++] =
3481          (struct tu_draw_state_group) {
3482             .id = TU_DRAW_STATE_BLEND,
3483             .enable_mask = ENABLE_ALL,
3484             .ib = pipeline->blend.state_ib,
3485          };
3486    }
3487
3488    if (cmd->state.dirty &
3489          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3490       draw_state_groups[draw_state_group_count++] =
3491          (struct tu_draw_state_group) {
3492             .id = TU_DRAW_STATE_VS_CONST,
3493             .enable_mask = ENABLE_ALL,
3494             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3495          };
3496       draw_state_groups[draw_state_group_count++] =
3497          (struct tu_draw_state_group) {
3498             .id = TU_DRAW_STATE_FS_CONST,
3499             .enable_mask = ENABLE_DRAW,
3500             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3501          };
3502    }
3503
3504    if (cmd->state.dirty &
3505          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3506       bool needs_border = false;
3507       struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
3508
3509       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3510                                  MESA_SHADER_VERTEX, &vs_tex, &needs_border,
3511                                  false);
3512       if (result != VK_SUCCESS)
3513          return result;
3514
3515       /* TODO: we could emit just one texture descriptor draw state when there
3516        * are no input attachments, which is the most common case. We could
3517        * also split out the sampler state, which doesn't change even for input
3518        * attachments.
3519        */
3520       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3521                                  MESA_SHADER_FRAGMENT, &fs_tex_sysmem,
3522                                  &needs_border, true);
3523       if (result != VK_SUCCESS)
3524          return result;
3525
3526       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3527                                  MESA_SHADER_FRAGMENT, &fs_tex_gmem,
3528                                  &needs_border, false);
3529       if (result != VK_SUCCESS)
3530          return result;
3531
3532       result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3533                             MESA_SHADER_FRAGMENT, &fs_ibo);
3534       if (result != VK_SUCCESS)
3535          return result;
3536
3537       draw_state_groups[draw_state_group_count++] =
3538          (struct tu_draw_state_group) {
3539             .id = TU_DRAW_STATE_VS_TEX,
3540             .enable_mask = ENABLE_ALL,
3541             .ib = vs_tex,
3542          };
3543       draw_state_groups[draw_state_group_count++] =
3544          (struct tu_draw_state_group) {
3545             .id = TU_DRAW_STATE_FS_TEX_GMEM,
3546             .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3547             .ib = fs_tex_gmem,
3548          };
3549       draw_state_groups[draw_state_group_count++] =
3550          (struct tu_draw_state_group) {
3551             .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
3552             .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
3553             .ib = fs_tex_sysmem,
3554          };
3555       draw_state_groups[draw_state_group_count++] =
3556          (struct tu_draw_state_group) {
3557             .id = TU_DRAW_STATE_FS_IBO,
3558             .enable_mask = ENABLE_DRAW,
3559             .ib = fs_ibo,
3560          };
3561
3562       if (needs_border) {
3563          result = tu6_emit_border_color(cmd, cs);
3564          if (result != VK_SUCCESS)
3565             return result;
3566       }
3567    }
3568
3569    struct tu_cs_entry vs_params;
3570    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3571    if (result != VK_SUCCESS)
3572       return result;
3573
3574    draw_state_groups[draw_state_group_count++] =
3575       (struct tu_draw_state_group) {
3576          .id = TU_DRAW_STATE_VS_PARAMS,
3577          .enable_mask = ENABLE_ALL,
3578          .ib = vs_params,
3579       };
3580
3581    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3582    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3583       const struct tu_draw_state_group *group = &draw_state_groups[i];
3584       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3585       uint32_t cp_set_draw_state =
3586          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3587          group->enable_mask |
3588          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3589       uint64_t iova;
3590       if (group->ib.size) {
3591          iova = group->ib.bo->iova + group->ib.offset;
3592       } else {
3593          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3594          iova = 0;
3595       }
3596
3597       tu_cs_emit(cs, cp_set_draw_state);
3598       tu_cs_emit_qw(cs, iova);
3599    }
3600
3601    tu_cs_sanity_check(cs);
3602
3603    /* track BOs */
3604    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3605       for (uint32_t i = 0; i < MAX_VBS; i++) {
3606          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3607          if (buf)
3608             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3609       }
3610    }
3611    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3612       unsigned i;
3613       for_each_bit(i, descriptors_state->valid) {
3614          struct tu_descriptor_set *set = descriptors_state->sets[i];
3615          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3616             if (set->descriptors[j]) {
3617                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3618                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3619             }
3620       }
3621    }
3622
3623    /* Fragment shader state overwrites compute shader state, so flag the
3624     * compute pipeline for re-emit.
3625     */
3626    cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3627    return VK_SUCCESS;
3628 }
3629
3630 static void
3631 tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
3632                      struct tu_cs *cs,
3633                      const struct tu_draw_info *draw)
3634 {
3635    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3636
3637    tu_cs_emit_regs(cs,
3638                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3639                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3640
3641    if (draw->indexed) {
3642       const enum a4xx_index_size index_size =
3643          tu6_index_size(cmd->state.index_type);
3644       const uint32_t index_bytes =
3645          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3646       const struct tu_buffer *index_buf = cmd->state.index_buffer;
3647       unsigned max_indicies =
3648          (index_buf->size - cmd->state.index_offset) / index_bytes;
3649
3650       const uint32_t cp_draw_indx =
3651          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3652          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3653          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3654          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3655
3656       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
3657       tu_cs_emit(cs, cp_draw_indx);
3658       tu_cs_emit_qw(cs, index_buf->bo->iova + cmd->state.index_offset);
3659       tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
3660       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3661    } else {
3662       const uint32_t cp_draw_indx =
3663          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3664          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3665          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3666
3667       tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
3668       tu_cs_emit(cs, cp_draw_indx);
3669       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3670    }
3671
3672    tu_bo_list_add(&cmd->bo_list, draw->indirect->bo, MSM_SUBMIT_BO_READ);
3673 }
3674
3675 static void
3676 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3677                      struct tu_cs *cs,
3678                      const struct tu_draw_info *draw)
3679 {
3680
3681    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3682
3683    tu_cs_emit_regs(cs,
3684                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3685                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3686
3687    /* TODO hw binning */
3688    if (draw->indexed) {
3689       const enum a4xx_index_size index_size =
3690          tu6_index_size(cmd->state.index_type);
3691       const uint32_t index_bytes =
3692          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3693       const struct tu_buffer *buf = cmd->state.index_buffer;
3694       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3695                                   index_bytes * draw->first_index;
3696       const uint32_t size = index_bytes * draw->count;
3697
3698       const uint32_t cp_draw_indx =
3699          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3700          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3701          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3702          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3703
3704       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3705       tu_cs_emit(cs, cp_draw_indx);
3706       tu_cs_emit(cs, draw->instance_count);
3707       tu_cs_emit(cs, draw->count);
3708       tu_cs_emit(cs, 0x0); /* XXX */
3709       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3710       tu_cs_emit(cs, size);
3711    } else {
3712       const uint32_t cp_draw_indx =
3713          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3714          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3715          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3716
3717       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3718       tu_cs_emit(cs, cp_draw_indx);
3719       tu_cs_emit(cs, draw->instance_count);
3720       tu_cs_emit(cs, draw->count);
3721    }
3722 }
3723
3724 static void
3725 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3726 {
3727    struct tu_cs *cs = &cmd->draw_cs;
3728    VkResult result;
3729
3730    result = tu6_bind_draw_states(cmd, cs, draw);
3731    if (result != VK_SUCCESS) {
3732       cmd->record_result = result;
3733       return;
3734    }
3735
3736    if (draw->indirect)
3737       tu6_emit_draw_indirect(cmd, cs, draw);
3738    else
3739       tu6_emit_draw_direct(cmd, cs, draw);
3740
3741    cmd->wait_for_idle = true;
3742
3743    tu_cs_sanity_check(cs);
3744 }
3745
3746 void
3747 tu_CmdDraw(VkCommandBuffer commandBuffer,
3748            uint32_t vertexCount,
3749            uint32_t instanceCount,
3750            uint32_t firstVertex,
3751            uint32_t firstInstance)
3752 {
3753    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3754    struct tu_draw_info info = {};
3755
3756    info.count = vertexCount;
3757    info.instance_count = instanceCount;
3758    info.first_instance = firstInstance;
3759    info.vertex_offset = firstVertex;
3760
3761    tu_draw(cmd_buffer, &info);
3762 }
3763
3764 void
3765 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3766                   uint32_t indexCount,
3767                   uint32_t instanceCount,
3768                   uint32_t firstIndex,
3769                   int32_t vertexOffset,
3770                   uint32_t firstInstance)
3771 {
3772    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3773    struct tu_draw_info info = {};
3774
3775    info.indexed = true;
3776    info.count = indexCount;
3777    info.instance_count = instanceCount;
3778    info.first_index = firstIndex;
3779    info.vertex_offset = vertexOffset;
3780    info.first_instance = firstInstance;
3781
3782    tu_draw(cmd_buffer, &info);
3783 }
3784
3785 void
3786 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3787                    VkBuffer _buffer,
3788                    VkDeviceSize offset,
3789                    uint32_t drawCount,
3790                    uint32_t stride)
3791 {
3792    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3793    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3794    struct tu_draw_info info = {};
3795
3796    info.count = drawCount;
3797    info.indirect = buffer;
3798    info.indirect_offset = offset;
3799    info.stride = stride;
3800
3801    tu_draw(cmd_buffer, &info);
3802 }
3803
3804 void
3805 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3806                           VkBuffer _buffer,
3807                           VkDeviceSize offset,
3808                           uint32_t drawCount,
3809                           uint32_t stride)
3810 {
3811    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3812    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3813    struct tu_draw_info info = {};
3814
3815    info.indexed = true;
3816    info.count = drawCount;
3817    info.indirect = buffer;
3818    info.indirect_offset = offset;
3819    info.stride = stride;
3820
3821    tu_draw(cmd_buffer, &info);
3822 }
3823
3824 struct tu_dispatch_info
3825 {
3826    /**
3827     * Determine the layout of the grid (in block units) to be used.
3828     */
3829    uint32_t blocks[3];
3830
3831    /**
3832     * A starting offset for the grid. If unaligned is set, the offset
3833     * must still be aligned.
3834     */
3835    uint32_t offsets[3];
3836    /**
3837     * Whether it's an unaligned compute dispatch.
3838     */
3839    bool unaligned;
3840
3841    /**
3842     * Indirect compute parameters resource.
3843     */
3844    struct tu_buffer *indirect;
3845    uint64_t indirect_offset;
3846 };
3847
3848 static void
3849 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3850                               const struct tu_dispatch_info *info)
3851 {
3852    gl_shader_stage type = MESA_SHADER_COMPUTE;
3853    const struct tu_program_descriptor_linkage *link =
3854       &pipeline->program.link[type];
3855    const struct ir3_const_state *const_state = &link->const_state;
3856    uint32_t offset = const_state->offsets.driver_param;
3857
3858    if (link->constlen <= offset)
3859       return;
3860
3861    if (!info->indirect) {
3862       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3863          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3864          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3865          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3866          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3867          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3868          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3869       };
3870
3871       uint32_t num_consts = MIN2(const_state->num_driver_params,
3872                                  (link->constlen - offset) * 4);
3873       /* push constants */
3874       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3875       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3876                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3877                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3878                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3879                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3880       tu_cs_emit(cs, 0);
3881       tu_cs_emit(cs, 0);
3882       uint32_t i;
3883       for (i = 0; i < num_consts; i++)
3884          tu_cs_emit(cs, driver_params[i]);
3885    } else {
3886       tu_finishme("Indirect driver params");
3887    }
3888 }
3889
3890 static void
3891 tu_dispatch(struct tu_cmd_buffer *cmd,
3892             const struct tu_dispatch_info *info)
3893 {
3894    struct tu_cs *cs = &cmd->cs;
3895    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3896    struct tu_descriptor_state *descriptors_state =
3897       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3898    VkResult result;
3899
3900    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3901       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3902
3903    struct tu_cs_entry ib;
3904
3905    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3906    if (ib.size)
3907       tu_cs_emit_ib(cs, &ib);
3908
3909    tu_emit_compute_driver_params(cs, pipeline, info);
3910
3911    bool needs_border;
3912    result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3913                               MESA_SHADER_COMPUTE, &ib, &needs_border, false);
3914    if (result != VK_SUCCESS) {
3915       cmd->record_result = result;
3916       return;
3917    }
3918
3919    if (ib.size)
3920       tu_cs_emit_ib(cs, &ib);
3921
3922    if (needs_border)
3923       tu_finishme("compute border color");
3924
3925    result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3926    if (result != VK_SUCCESS) {
3927       cmd->record_result = result;
3928       return;
3929    }
3930
3931    if (ib.size)
3932       tu_cs_emit_ib(cs, &ib);
3933
3934    /* track BOs */
3935    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3936       unsigned i;
3937       for_each_bit(i, descriptors_state->valid) {
3938          struct tu_descriptor_set *set = descriptors_state->sets[i];
3939          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3940             if (set->descriptors[j]) {
3941                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3942                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3943             }
3944       }
3945    }
3946
3947    /* Compute shader state overwrites fragment shader state, so we flag the
3948     * graphics pipeline for re-emit.
3949     */
3950    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3951
3952    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3953    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3954
3955    const uint32_t *local_size = pipeline->compute.local_size;
3956    const uint32_t *num_groups = info->blocks;
3957    tu_cs_emit_regs(cs,
3958                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3959                                           .localsizex = local_size[0] - 1,
3960                                           .localsizey = local_size[1] - 1,
3961                                           .localsizez = local_size[2] - 1),
3962                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3963                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3964                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3965                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3966                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3967                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3968
3969    tu_cs_emit_regs(cs,
3970                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3971                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3972                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3973
3974    if (info->indirect) {
3975       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3976
3977       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3978                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3979
3980       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3981       tu_cs_emit(cs, 0x00000000);
3982       tu_cs_emit_qw(cs, iova);
3983       tu_cs_emit(cs,
3984                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3985                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3986                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3987    } else {
3988       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3989       tu_cs_emit(cs, 0x00000000);
3990       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3991       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3992       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3993    }
3994
3995    tu_cs_emit_wfi(cs);
3996
3997    tu6_emit_cache_flush(cmd, cs);
3998 }
3999
4000 void
4001 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
4002                    uint32_t base_x,
4003                    uint32_t base_y,
4004                    uint32_t base_z,
4005                    uint32_t x,
4006                    uint32_t y,
4007                    uint32_t z)
4008 {
4009    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4010    struct tu_dispatch_info info = {};
4011
4012    info.blocks[0] = x;
4013    info.blocks[1] = y;
4014    info.blocks[2] = z;
4015
4016    info.offsets[0] = base_x;
4017    info.offsets[1] = base_y;
4018    info.offsets[2] = base_z;
4019    tu_dispatch(cmd_buffer, &info);
4020 }
4021
4022 void
4023 tu_CmdDispatch(VkCommandBuffer commandBuffer,
4024                uint32_t x,
4025                uint32_t y,
4026                uint32_t z)
4027 {
4028    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4029 }
4030
4031 void
4032 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
4033                        VkBuffer _buffer,
4034                        VkDeviceSize offset)
4035 {
4036    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4037    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
4038    struct tu_dispatch_info info = {};
4039
4040    info.indirect = buffer;
4041    info.indirect_offset = offset;
4042
4043    tu_dispatch(cmd_buffer, &info);
4044 }
4045
4046 void
4047 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
4048 {
4049    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4050
4051    tu_cs_end(&cmd_buffer->draw_cs);
4052    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
4053
4054    if (use_sysmem_rendering(cmd_buffer))
4055       tu_cmd_render_sysmem(cmd_buffer);
4056    else
4057       tu_cmd_render_tiles(cmd_buffer);
4058
4059    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
4060       rendered */
4061    tu_cs_discard_entries(&cmd_buffer->draw_cs);
4062    tu_cs_begin(&cmd_buffer->draw_cs);
4063    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
4064    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
4065
4066    cmd_buffer->state.pass = NULL;
4067    cmd_buffer->state.subpass = NULL;
4068    cmd_buffer->state.framebuffer = NULL;
4069 }
4070
4071 void
4072 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
4073                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
4074 {
4075    tu_CmdEndRenderPass(commandBuffer);
4076 }
4077
4078 struct tu_barrier_info
4079 {
4080    uint32_t eventCount;
4081    const VkEvent *pEvents;
4082    VkPipelineStageFlags srcStageMask;
4083 };
4084
4085 static void
4086 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
4087            uint32_t memoryBarrierCount,
4088            const VkMemoryBarrier *pMemoryBarriers,
4089            uint32_t bufferMemoryBarrierCount,
4090            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4091            uint32_t imageMemoryBarrierCount,
4092            const VkImageMemoryBarrier *pImageMemoryBarriers,
4093            const struct tu_barrier_info *info)
4094 {
4095 }
4096
4097 void
4098 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
4099                       VkPipelineStageFlags srcStageMask,
4100                       VkPipelineStageFlags destStageMask,
4101                       VkBool32 byRegion,
4102                       uint32_t memoryBarrierCount,
4103                       const VkMemoryBarrier *pMemoryBarriers,
4104                       uint32_t bufferMemoryBarrierCount,
4105                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4106                       uint32_t imageMemoryBarrierCount,
4107                       const VkImageMemoryBarrier *pImageMemoryBarriers)
4108 {
4109    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4110    struct tu_barrier_info info;
4111
4112    info.eventCount = 0;
4113    info.pEvents = NULL;
4114    info.srcStageMask = srcStageMask;
4115
4116    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4117               bufferMemoryBarrierCount, pBufferMemoryBarriers,
4118               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4119 }
4120
4121 static void
4122 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
4123 {
4124    struct tu_cs *cs = &cmd->cs;
4125
4126    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
4127
4128    /* TODO: any flush required before/after ? */
4129
4130    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
4131    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
4132    tu_cs_emit(cs, value);
4133 }
4134
4135 void
4136 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
4137                VkEvent _event,
4138                VkPipelineStageFlags stageMask)
4139 {
4140    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4141    TU_FROM_HANDLE(tu_event, event, _event);
4142
4143    write_event(cmd, event, 1);
4144 }
4145
4146 void
4147 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
4148                  VkEvent _event,
4149                  VkPipelineStageFlags stageMask)
4150 {
4151    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4152    TU_FROM_HANDLE(tu_event, event, _event);
4153
4154    write_event(cmd, event, 0);
4155 }
4156
4157 void
4158 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
4159                  uint32_t eventCount,
4160                  const VkEvent *pEvents,
4161                  VkPipelineStageFlags srcStageMask,
4162                  VkPipelineStageFlags dstStageMask,
4163                  uint32_t memoryBarrierCount,
4164                  const VkMemoryBarrier *pMemoryBarriers,
4165                  uint32_t bufferMemoryBarrierCount,
4166                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4167                  uint32_t imageMemoryBarrierCount,
4168                  const VkImageMemoryBarrier *pImageMemoryBarriers)
4169 {
4170    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4171    struct tu_cs *cs = &cmd->cs;
4172
4173    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
4174
4175    for (uint32_t i = 0; i < eventCount; i++) {
4176       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
4177
4178       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
4179
4180       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
4181       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
4182                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
4183       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
4184       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
4185       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
4186       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
4187    }
4188 }
4189
4190 void
4191 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
4192 {
4193    /* No-op */
4194 }