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turnip: update setup_slices
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37
38 void
39 tu_bo_list_init(struct tu_bo_list *list)
40 {
41 list->count = list->capacity = 0;
42 list->bo_infos = NULL;
43 }
44
45 void
46 tu_bo_list_destroy(struct tu_bo_list *list)
47 {
48 free(list->bo_infos);
49 }
50
51 void
52 tu_bo_list_reset(struct tu_bo_list *list)
53 {
54 list->count = 0;
55 }
56
57 /**
58 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
59 */
60 static uint32_t
61 tu_bo_list_add_info(struct tu_bo_list *list,
62 const struct drm_msm_gem_submit_bo *bo_info)
63 {
64 for (uint32_t i = 0; i < list->count; ++i) {
65 if (list->bo_infos[i].handle == bo_info->handle) {
66 assert(list->bo_infos[i].presumed == bo_info->presumed);
67 list->bo_infos[i].flags |= bo_info->flags;
68 return i;
69 }
70 }
71
72 /* grow list->bo_infos if needed */
73 if (list->count == list->capacity) {
74 uint32_t new_capacity = MAX2(2 * list->count, 16);
75 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
76 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
77 if (!new_bo_infos)
78 return TU_BO_LIST_FAILED;
79 list->bo_infos = new_bo_infos;
80 list->capacity = new_capacity;
81 }
82
83 list->bo_infos[list->count] = *bo_info;
84 return list->count++;
85 }
86
87 uint32_t
88 tu_bo_list_add(struct tu_bo_list *list,
89 const struct tu_bo *bo,
90 uint32_t flags)
91 {
92 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
93 .flags = flags,
94 .handle = bo->gem_handle,
95 .presumed = bo->iova,
96 });
97 }
98
99 VkResult
100 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
101 {
102 for (uint32_t i = 0; i < other->count; i++) {
103 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
104 return VK_ERROR_OUT_OF_HOST_MEMORY;
105 }
106
107 return VK_SUCCESS;
108 }
109
110 static VkResult
111 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
112 const struct tu_device *dev)
113 {
114 const uint32_t gmem_size = dev->physical_device->gmem_size;
115 uint32_t offset = 0;
116
117 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
118 /* 16KB-aligned */
119 offset = align(offset, 0x4000);
120
121 tiling->gmem_offsets[i] = offset;
122 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
123 tiling->buffer_cpp[i];
124 }
125
126 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
127 }
128
129 static void
130 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
131 const struct tu_device *dev)
132 {
133 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
134 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
135 const uint32_t max_tile_width = 1024; /* A6xx */
136
137 tiling->tile0.offset = (VkOffset2D) {
138 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
139 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
140 };
141
142 const uint32_t ra_width =
143 tiling->render_area.extent.width +
144 (tiling->render_area.offset.x - tiling->tile0.offset.x);
145 const uint32_t ra_height =
146 tiling->render_area.extent.height +
147 (tiling->render_area.offset.y - tiling->tile0.offset.y);
148
149 /* start from 1 tile */
150 tiling->tile_count = (VkExtent2D) {
151 .width = 1,
152 .height = 1,
153 };
154 tiling->tile0.extent = (VkExtent2D) {
155 .width = align(ra_width, tile_align_w),
156 .height = align(ra_height, tile_align_h),
157 };
158
159 /* do not exceed max tile width */
160 while (tiling->tile0.extent.width > max_tile_width) {
161 tiling->tile_count.width++;
162 tiling->tile0.extent.width =
163 align(ra_width / tiling->tile_count.width, tile_align_w);
164 }
165
166 /* do not exceed gmem size */
167 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
168 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
169 tiling->tile_count.width++;
170 tiling->tile0.extent.width =
171 align(ra_width / tiling->tile_count.width, tile_align_w);
172 } else {
173 tiling->tile_count.height++;
174 tiling->tile0.extent.height =
175 align(ra_height / tiling->tile_count.height, tile_align_h);
176 }
177 }
178 }
179
180 static void
181 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
182 const struct tu_device *dev)
183 {
184 const uint32_t max_pipe_count = 32; /* A6xx */
185
186 /* start from 1 tile per pipe */
187 tiling->pipe0 = (VkExtent2D) {
188 .width = 1,
189 .height = 1,
190 };
191 tiling->pipe_count = tiling->tile_count;
192
193 /* do not exceed max pipe count vertically */
194 while (tiling->pipe_count.height > max_pipe_count) {
195 tiling->pipe0.height += 2;
196 tiling->pipe_count.height =
197 (tiling->tile_count.height + tiling->pipe0.height - 1) /
198 tiling->pipe0.height;
199 }
200
201 /* do not exceed max pipe count */
202 while (tiling->pipe_count.width * tiling->pipe_count.height >
203 max_pipe_count) {
204 tiling->pipe0.width += 1;
205 tiling->pipe_count.width =
206 (tiling->tile_count.width + tiling->pipe0.width - 1) /
207 tiling->pipe0.width;
208 }
209 }
210
211 static void
212 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
213 const struct tu_device *dev)
214 {
215 const uint32_t max_pipe_count = 32; /* A6xx */
216 const uint32_t used_pipe_count =
217 tiling->pipe_count.width * tiling->pipe_count.height;
218 const VkExtent2D last_pipe = {
219 .width = tiling->tile_count.width % tiling->pipe0.width,
220 .height = tiling->tile_count.height % tiling->pipe0.height,
221 };
222
223 assert(used_pipe_count <= max_pipe_count);
224 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
225
226 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
227 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
228 const uint32_t pipe_x = tiling->pipe0.width * x;
229 const uint32_t pipe_y = tiling->pipe0.height * y;
230 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
231 ? last_pipe.width
232 : tiling->pipe0.width;
233 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
234 ? last_pipe.height
235 : tiling->pipe0.height;
236 const uint32_t n = tiling->pipe_count.width * y + x;
237
238 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
239 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
240 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
241 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
242 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
243 }
244 }
245
246 memset(tiling->pipe_config + used_pipe_count, 0,
247 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
248 }
249
250 static void
251 tu_tiling_config_update(struct tu_tiling_config *tiling,
252 const struct tu_device *dev,
253 const uint32_t *buffer_cpp,
254 uint32_t buffer_count,
255 const VkRect2D *render_area)
256 {
257 /* see if there is any real change */
258 const bool ra_changed =
259 render_area &&
260 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
261 const bool buf_changed = tiling->buffer_count != buffer_count ||
262 memcmp(tiling->buffer_cpp, buffer_cpp,
263 sizeof(*buffer_cpp) * buffer_count);
264 if (!ra_changed && !buf_changed)
265 return;
266
267 if (ra_changed)
268 tiling->render_area = *render_area;
269
270 if (buf_changed) {
271 memcpy(tiling->buffer_cpp, buffer_cpp,
272 sizeof(*buffer_cpp) * buffer_count);
273 tiling->buffer_count = buffer_count;
274 }
275
276 tu_tiling_config_update_tile_layout(tiling, dev);
277 tu_tiling_config_update_pipe_layout(tiling, dev);
278 tu_tiling_config_update_pipes(tiling, dev);
279 }
280
281 static void
282 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
283 const struct tu_device *dev,
284 uint32_t tx,
285 uint32_t ty,
286 struct tu_tile *tile)
287 {
288 /* find the pipe and the slot for tile (tx, ty) */
289 const uint32_t px = tx / tiling->pipe0.width;
290 const uint32_t py = ty / tiling->pipe0.height;
291 const uint32_t sx = tx - tiling->pipe0.width * px;
292 const uint32_t sy = ty - tiling->pipe0.height * py;
293
294 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
295 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
296 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
297
298 /* convert to 1D indices */
299 tile->pipe = tiling->pipe_count.width * py + px;
300 tile->slot = tiling->pipe0.width * sy + sx;
301
302 /* get the blit area for the tile */
303 tile->begin = (VkOffset2D) {
304 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
305 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
306 };
307 tile->end.x =
308 (tx == tiling->tile_count.width - 1)
309 ? tiling->render_area.offset.x + tiling->render_area.extent.width
310 : tile->begin.x + tiling->tile0.extent.width;
311 tile->end.y =
312 (ty == tiling->tile_count.height - 1)
313 ? tiling->render_area.offset.y + tiling->render_area.extent.height
314 : tile->begin.y + tiling->tile0.extent.height;
315 }
316
317 static enum a3xx_msaa_samples
318 tu6_msaa_samples(uint32_t samples)
319 {
320 switch (samples) {
321 case 1:
322 return MSAA_ONE;
323 case 2:
324 return MSAA_TWO;
325 case 4:
326 return MSAA_FOUR;
327 case 8:
328 return MSAA_EIGHT;
329 default:
330 assert(!"invalid sample count");
331 return MSAA_ONE;
332 }
333 }
334
335 static enum a4xx_index_size
336 tu6_index_size(VkIndexType type)
337 {
338 switch (type) {
339 case VK_INDEX_TYPE_UINT16:
340 return INDEX4_SIZE_16_BIT;
341 case VK_INDEX_TYPE_UINT32:
342 return INDEX4_SIZE_32_BIT;
343 default:
344 unreachable("invalid VkIndexType");
345 return INDEX4_SIZE_8_BIT;
346 }
347 }
348
349 static void
350 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
351 {
352 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
353 }
354
355 void
356 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
357 struct tu_cs *cs,
358 enum vgt_event_type event,
359 bool need_seqno)
360 {
361 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
362 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
363 if (need_seqno) {
364 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
365 tu_cs_emit(cs, ++cmd->scratch_seqno);
366 }
367 }
368
369 static void
370 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
371 {
372 tu6_emit_event_write(cmd, cs, 0x31, false);
373 }
374
375 static void
376 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
377 {
378 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
379 }
380
381 static void
382 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
383 {
384 if (cmd->wait_for_idle) {
385 tu_cs_emit_wfi(cs);
386 cmd->wait_for_idle = false;
387 }
388 }
389
390 static void
391 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
392 {
393 const struct tu_subpass *subpass = cmd->state.subpass;
394
395 const uint32_t a = subpass->depth_stencil_attachment.attachment;
396 if (a == VK_ATTACHMENT_UNUSED) {
397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
398 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
399 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
400 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
401 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
402 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
403 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
404
405 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
406 tu_cs_emit(cs,
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
410 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
411 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
412 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
413 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
414 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
417 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
418
419 return;
420 }
421
422 /* enable zs? */
423 }
424
425 static void
426 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
427 {
428 const struct tu_framebuffer *fb = cmd->state.framebuffer;
429 const struct tu_subpass *subpass = cmd->state.subpass;
430 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
431 unsigned char mrt_comp[MAX_RTS] = { 0 };
432 unsigned srgb_cntl = 0;
433
434 uint32_t gmem_index = 0;
435 for (uint32_t i = 0; i < subpass->color_count; ++i) {
436 uint32_t a = subpass->color_attachments[i].attachment;
437 if (a == VK_ATTACHMENT_UNUSED)
438 continue;
439
440 const struct tu_image_view *iview = fb->attachments[a].attachment;
441 const struct tu_image_level *slice =
442 &iview->image->levels[iview->base_mip];
443 const enum a6xx_tile_mode tile_mode = iview->image->tile_mode;
444 uint32_t stride = 0;
445 uint32_t offset = 0;
446
447 mrt_comp[i] = 0xf;
448
449 if (vk_format_is_srgb(iview->vk_format))
450 srgb_cntl |= (1 << i);
451
452 const struct tu_native_format *format =
453 tu6_get_native_format(iview->vk_format);
454 assert(format && format->rb >= 0);
455
456 offset = slice->offset + slice->size * iview->base_layer;
457 stride = slice->pitch * iview->image->cpp;
458
459 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
460 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
461 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
462 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
463 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(stride));
464 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(slice->size));
465 tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset +
466 offset); /* BASE_LO/HI */
467 tu_cs_emit(
468 cs, tiling->gmem_offsets[gmem_index++]); /* RB_MRT[i].BASE_GMEM */
469
470 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
471 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb));
472
473 #if 0
474 /* when we support UBWC, these would be the system memory
475 * addr/pitch/etc:
476 */
477 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
478 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
479 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
480 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
481 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
482 #endif
483 }
484
485 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
486 tu_cs_emit(cs, srgb_cntl);
487
488 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
489 tu_cs_emit(cs, srgb_cntl);
490
491 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
492 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
493 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
494 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
495 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
496 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
497 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
498 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
499 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
500
501 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
502 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
503 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
504 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
505 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
506 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
507 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
508 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
509 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
510 }
511
512 static void
513 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
514 {
515 const struct tu_subpass *subpass = cmd->state.subpass;
516 const enum a3xx_msaa_samples samples =
517 tu6_msaa_samples(subpass->max_sample_count);
518
519 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
520 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
521 tu_cs_emit(
522 cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
523 ((samples == MSAA_ONE) ? A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
524 : 0));
525
526 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
527 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
528 tu_cs_emit(
529 cs,
530 A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
531 ((samples == MSAA_ONE) ? A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE : 0));
532
533 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
534 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
535 tu_cs_emit(
536 cs,
537 A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
538 ((samples == MSAA_ONE) ? A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE : 0));
539
540 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
541 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
542 }
543
544 static void
545 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
546 {
547 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
548 const uint32_t bin_w = tiling->tile0.extent.width;
549 const uint32_t bin_h = tiling->tile0.extent.height;
550
551 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
552 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
553 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
556 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
557 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
558
559 /* no flag for RB_BIN_CONTROL2... */
560 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
561 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
562 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
563 }
564
565 static void
566 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
567 struct tu_cs *cs,
568 bool binning)
569 {
570 uint32_t cntl = 0;
571 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
572 if (binning)
573 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
574
575 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
576 tu_cs_emit(cs, 0x2);
577 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
578 tu_cs_emit(cs, cntl);
579 }
580
581 static void
582 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
583 {
584 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
585 const uint32_t x1 = render_area->offset.x;
586 const uint32_t y1 = render_area->offset.y;
587 const uint32_t x2 = x1 + render_area->extent.width - 1;
588 const uint32_t y2 = y1 + render_area->extent.height - 1;
589
590 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
591 tu_cs_emit(cs,
592 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
593 tu_cs_emit(cs,
594 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
595 }
596
597 static void
598 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
599 struct tu_cs *cs,
600 const struct tu_image_view *iview,
601 uint32_t gmem_offset,
602 uint32_t blit_info)
603 {
604 const struct tu_image_level *slice =
605 &iview->image->levels[iview->base_mip];
606 const uint32_t offset = slice->offset + slice->size * iview->base_layer;
607 const uint32_t stride = slice->pitch * iview->image->cpp;
608 const enum a3xx_msaa_samples samples = tu6_msaa_samples(1);
609
610 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
611 tu_cs_emit(cs, blit_info);
612
613 /* tile mode? */
614 const struct tu_native_format *format =
615 tu6_get_native_format(iview->vk_format);
616 assert(format && format->rb >= 0);
617
618 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
619 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(iview->image->tile_mode) |
620 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
621 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
622 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap));
623 tu_cs_emit_qw(cs,
624 iview->image->bo->iova + iview->image->bo_offset + offset);
625 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(stride));
626 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(slice->size));
627
628 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
629 tu_cs_emit(cs, gmem_offset);
630 }
631
632 static void
633 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
634 struct tu_cs *cs,
635 const struct tu_image_view *iview,
636 uint32_t gmem_offset,
637 const VkClearValue *clear_value)
638 {
639 const enum a3xx_msaa_samples samples = tu6_msaa_samples(1);
640
641 const struct tu_native_format *format =
642 tu6_get_native_format(iview->vk_format);
643 assert(format && format->rb >= 0);
644 /* must be WZYX; other values are ignored */
645 const enum a3xx_color_swap swap = WZYX;
646
647 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
648 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(iview->image->tile_mode) |
649 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
650 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
651 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
652
653 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
654 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
655
656 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
657 tu_cs_emit(cs, gmem_offset);
658
659 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
660 tu_cs_emit(cs, 0);
661
662 /* pack clear_value into WZYX order */
663 uint32_t clear_vals[4] = { 0 };
664 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
665
666 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
667 tu_cs_emit(cs, clear_vals[0]);
668 tu_cs_emit(cs, clear_vals[1]);
669 tu_cs_emit(cs, clear_vals[2]);
670 tu_cs_emit(cs, clear_vals[3]);
671 }
672
673 static void
674 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
675 {
676 tu6_emit_marker(cmd, cs);
677 tu6_emit_event_write(cmd, cs, BLIT, false);
678 tu6_emit_marker(cmd, cs);
679 }
680
681 static void
682 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
683 struct tu_cs *cs,
684 uint32_t x1,
685 uint32_t y1,
686 uint32_t x2,
687 uint32_t y2)
688 {
689 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
690 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
691 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
692 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
693 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
694
695 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
696 tu_cs_emit(
697 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
698 tu_cs_emit(
699 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
700 }
701
702 static void
703 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
704 struct tu_cs *cs,
705 uint32_t x1,
706 uint32_t y1)
707 {
708 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
709 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
710
711 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
712 tu_cs_emit(cs,
713 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
714
715 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
716 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
717
718 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
719 tu_cs_emit(
720 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
721 }
722
723 static void
724 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
725 struct tu_cs *cs,
726 const struct tu_tile *tile)
727 {
728 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
729 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
730
731 tu6_emit_marker(cmd, cs);
732 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
733 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
734 tu6_emit_marker(cmd, cs);
735
736 const uint32_t x1 = tile->begin.x;
737 const uint32_t y1 = tile->begin.y;
738 const uint32_t x2 = tile->end.x - 1;
739 const uint32_t y2 = tile->end.y - 1;
740 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
741 tu6_emit_window_offset(cmd, cs, x1, y1);
742
743 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
744 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
745
746 if (false) {
747 /* hw binning? */
748 } else {
749 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
750 tu_cs_emit(cs, 0x1);
751
752 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
753 tu_cs_emit(cs, 0x0);
754 }
755 }
756
757 static void
758 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
759 {
760 const struct tu_framebuffer *fb = cmd->state.framebuffer;
761 const struct tu_subpass *subpass = cmd->state.subpass;
762 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
763 const struct tu_attachment_state *attachments = cmd->state.attachments;
764
765 tu6_emit_blit_scissor(cmd, cs);
766
767 uint32_t gmem_index = 0;
768 for (uint32_t i = 0; i < subpass->color_count; ++i) {
769 const uint32_t a = subpass->color_attachments[i].attachment;
770 if (a == VK_ATTACHMENT_UNUSED)
771 continue;
772
773 const struct tu_image_view *iview = fb->attachments[a].attachment;
774 const struct tu_attachment_state *att = attachments + a;
775 if (att->pending_clear_aspects) {
776 assert(att->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
777 tu6_emit_blit_clear(cmd, cs, iview,
778 tiling->gmem_offsets[gmem_index++],
779 &att->clear_value);
780 } else {
781 tu6_emit_blit_info(cmd, cs, iview,
782 tiling->gmem_offsets[gmem_index++],
783 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
784 }
785
786 tu6_emit_blit(cmd, cs);
787 }
788
789 /* load/clear zs? */
790 }
791
792 static void
793 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
794 {
795 const struct tu_framebuffer *fb = cmd->state.framebuffer;
796 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
797
798 if (false) {
799 /* hw binning? */
800 }
801
802 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
803 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
804 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
805 CP_SET_DRAW_STATE__0_GROUP_ID(0));
806 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
807 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
808
809 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
810 tu_cs_emit(cs, 0x0);
811
812 tu6_emit_marker(cmd, cs);
813 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
814 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
815 tu6_emit_marker(cmd, cs);
816
817 tu6_emit_blit_scissor(cmd, cs);
818
819 uint32_t gmem_index = 0;
820 for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
821 uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
822 if (a == VK_ATTACHMENT_UNUSED)
823 continue;
824
825 const struct tu_image_view *iview = fb->attachments[a].attachment;
826 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index++],
827 0);
828 tu6_emit_blit(cmd, cs);
829 }
830 }
831
832 static void
833 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
834 {
835 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
836 tu_cs_emit(cs, restart_index);
837 }
838
839 static void
840 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
841 {
842 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
843 if (result != VK_SUCCESS) {
844 cmd->record_result = result;
845 return;
846 }
847
848 tu6_emit_cache_flush(cmd, cs);
849
850 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
851
852 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
853 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
854 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
855 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
856 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
857 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
858 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
859 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
860 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
861
862 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
863 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
864 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
865 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
866 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
867 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
868 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
869 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
870 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
871 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
872 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
873 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
874 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
875 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
876
877 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
878
879 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
880 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
881 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
882
883 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
884 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
885 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
886 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
887 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
888 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
889 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
890 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
891 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
892 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
893 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
894 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
895
896 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
897 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
898
899 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
900 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
901
902 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
903 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
904
905 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
906 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
907 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
908
909 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
910 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
911
912 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
913
914 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
915
916 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
917 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
919 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
920 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
921 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
922 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
923 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
924 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
926 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
928 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
930 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
937
938 tu6_emit_marker(cmd, cs);
939
940 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
941
942 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
943
944 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
945
946 /* we don't use this yet.. probably best to disable.. */
947 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
948 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
949 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
950 CP_SET_DRAW_STATE__0_GROUP_ID(0));
951 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
952 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
953
954 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
955 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
956 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
957 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
958
959 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
960 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
961 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
962
963 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
964 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
965
966 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
967 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
968
969 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
970 tu_cs_emit(cs, 0x00000000);
971 tu_cs_emit(cs, 0x00000000);
972 tu_cs_emit(cs, 0x00000000);
973
974 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
975 tu_cs_emit(cs, 0x00000000);
976 tu_cs_emit(cs, 0x00000000);
977 tu_cs_emit(cs, 0x00000000);
978 tu_cs_emit(cs, 0x00000000);
979 tu_cs_emit(cs, 0x00000000);
980 tu_cs_emit(cs, 0x00000000);
981
982 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
983 tu_cs_emit(cs, 0x00000000);
984 tu_cs_emit(cs, 0x00000000);
985 tu_cs_emit(cs, 0x00000000);
986 tu_cs_emit(cs, 0x00000000);
987 tu_cs_emit(cs, 0x00000000);
988 tu_cs_emit(cs, 0x00000000);
989
990 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
991 tu_cs_emit(cs, 0x00000000);
992 tu_cs_emit(cs, 0x00000000);
993 tu_cs_emit(cs, 0x00000000);
994
995 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
996 tu_cs_emit(cs, 0x00000000);
997
998 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
999 tu_cs_emit(cs, 0x00000000);
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1002 tu_cs_emit(cs, 0x00000000);
1003
1004 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1005 tu_cs_emit(cs, 0x00000000);
1006
1007 tu_cs_sanity_check(cs);
1008 }
1009
1010 static void
1011 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1012 {
1013 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1014 if (result != VK_SUCCESS) {
1015 cmd->record_result = result;
1016 return;
1017 }
1018
1019 tu6_emit_lrz_flush(cmd, cs);
1020
1021 /* lrz clear? */
1022
1023 tu6_emit_cache_flush(cmd, cs);
1024
1025 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1026 tu_cs_emit(cs, 0x0);
1027
1028 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1029 tu6_emit_wfi(cmd, cs);
1030 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1031 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1032
1033 tu6_emit_zs(cmd, cs);
1034 tu6_emit_mrt(cmd, cs);
1035 tu6_emit_msaa(cmd, cs);
1036
1037 if (false) {
1038 /* hw binning? */
1039 } else {
1040 tu6_emit_bin_size(cmd, cs, 0x6000000);
1041 /* no draws */
1042 }
1043
1044 tu6_emit_render_cntl(cmd, cs, false);
1045
1046 tu_cs_sanity_check(cs);
1047 }
1048
1049 static void
1050 tu6_render_tile(struct tu_cmd_buffer *cmd,
1051 struct tu_cs *cs,
1052 const struct tu_tile *tile)
1053 {
1054 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1055 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1056 if (result != VK_SUCCESS) {
1057 cmd->record_result = result;
1058 return;
1059 }
1060
1061 tu6_emit_tile_select(cmd, cs, tile);
1062 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1063
1064 tu_cs_emit_call(cs, &cmd->draw_cs);
1065 cmd->wait_for_idle = true;
1066
1067 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1068
1069 tu_cs_sanity_check(cs);
1070 }
1071
1072 static void
1073 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1074 {
1075 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1076 if (result != VK_SUCCESS) {
1077 cmd->record_result = result;
1078 return;
1079 }
1080
1081 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1082 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1083
1084 tu6_emit_lrz_flush(cmd, cs);
1085
1086 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1087
1088 tu_cs_sanity_check(cs);
1089 }
1090
1091 static void
1092 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1093 {
1094 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1095
1096 tu6_render_begin(cmd, &cmd->cs);
1097
1098 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1099 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1100 struct tu_tile tile;
1101 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1102 tu6_render_tile(cmd, &cmd->cs, &tile);
1103 }
1104 }
1105
1106 tu6_render_end(cmd, &cmd->cs);
1107 }
1108
1109 static void
1110 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1111 {
1112 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1113 const struct tu_subpass *subpass = cmd->state.subpass;
1114 struct tu_attachment_state *attachments = cmd->state.attachments;
1115 struct tu_cs sub_cs;
1116
1117 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1118 tile_load_space, &sub_cs);
1119 if (result != VK_SUCCESS) {
1120 cmd->record_result = result;
1121 return;
1122 }
1123
1124 /* emit to tile-load sub_cs */
1125 tu6_emit_tile_load(cmd, &sub_cs);
1126
1127 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1128
1129 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1130 const uint32_t a = subpass->color_attachments[i].attachment;
1131 if (a != VK_ATTACHMENT_UNUSED)
1132 attachments[a].pending_clear_aspects = 0;
1133 }
1134 }
1135
1136 static void
1137 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1138 {
1139 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1140 struct tu_cs sub_cs;
1141
1142 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1143 tile_store_space, &sub_cs);
1144 if (result != VK_SUCCESS) {
1145 cmd->record_result = result;
1146 return;
1147 }
1148
1149 /* emit to tile-store sub_cs */
1150 tu6_emit_tile_store(cmd, &sub_cs);
1151
1152 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1153 }
1154
1155 static void
1156 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1157 const VkRect2D *render_area)
1158 {
1159 const struct tu_device *dev = cmd->device;
1160 const struct tu_render_pass *pass = cmd->state.pass;
1161 const struct tu_subpass *subpass = cmd->state.subpass;
1162 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1163
1164 uint32_t buffer_cpp[MAX_RTS + 2];
1165 uint32_t buffer_count = 0;
1166
1167 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1168 const uint32_t a = subpass->color_attachments[i].attachment;
1169 if (a == VK_ATTACHMENT_UNUSED)
1170 continue;
1171
1172 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1173 buffer_cpp[buffer_count++] =
1174 vk_format_get_blocksize(att->format) * att->samples;
1175 }
1176
1177 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1178 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1179 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1180
1181 /* TODO */
1182 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1183
1184 buffer_cpp[buffer_count++] =
1185 vk_format_get_blocksize(att->format) * att->samples;
1186 }
1187
1188 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1189 render_area);
1190 }
1191
1192 const struct tu_dynamic_state default_dynamic_state = {
1193 .viewport =
1194 {
1195 .count = 0,
1196 },
1197 .scissor =
1198 {
1199 .count = 0,
1200 },
1201 .line_width = 1.0f,
1202 .depth_bias =
1203 {
1204 .bias = 0.0f,
1205 .clamp = 0.0f,
1206 .slope = 0.0f,
1207 },
1208 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1209 .depth_bounds =
1210 {
1211 .min = 0.0f,
1212 .max = 1.0f,
1213 },
1214 .stencil_compare_mask =
1215 {
1216 .front = ~0u,
1217 .back = ~0u,
1218 },
1219 .stencil_write_mask =
1220 {
1221 .front = ~0u,
1222 .back = ~0u,
1223 },
1224 .stencil_reference =
1225 {
1226 .front = 0u,
1227 .back = 0u,
1228 },
1229 };
1230
1231 static void UNUSED /* FINISHME */
1232 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1233 const struct tu_dynamic_state *src)
1234 {
1235 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1236 uint32_t copy_mask = src->mask;
1237 uint32_t dest_mask = 0;
1238
1239 tu_use_args(cmd_buffer); /* FINISHME */
1240
1241 /* Make sure to copy the number of viewports/scissors because they can
1242 * only be specified at pipeline creation time.
1243 */
1244 dest->viewport.count = src->viewport.count;
1245 dest->scissor.count = src->scissor.count;
1246 dest->discard_rectangle.count = src->discard_rectangle.count;
1247
1248 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1249 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1250 src->viewport.count * sizeof(VkViewport))) {
1251 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1252 src->viewport.count);
1253 dest_mask |= TU_DYNAMIC_VIEWPORT;
1254 }
1255 }
1256
1257 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1258 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1259 src->scissor.count * sizeof(VkRect2D))) {
1260 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1261 src->scissor.count);
1262 dest_mask |= TU_DYNAMIC_SCISSOR;
1263 }
1264 }
1265
1266 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1267 if (dest->line_width != src->line_width) {
1268 dest->line_width = src->line_width;
1269 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1270 }
1271 }
1272
1273 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1274 if (memcmp(&dest->depth_bias, &src->depth_bias,
1275 sizeof(src->depth_bias))) {
1276 dest->depth_bias = src->depth_bias;
1277 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1278 }
1279 }
1280
1281 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1282 if (memcmp(&dest->blend_constants, &src->blend_constants,
1283 sizeof(src->blend_constants))) {
1284 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1285 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1286 }
1287 }
1288
1289 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1290 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1291 sizeof(src->depth_bounds))) {
1292 dest->depth_bounds = src->depth_bounds;
1293 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1294 }
1295 }
1296
1297 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1298 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1299 sizeof(src->stencil_compare_mask))) {
1300 dest->stencil_compare_mask = src->stencil_compare_mask;
1301 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1302 }
1303 }
1304
1305 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1306 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1307 sizeof(src->stencil_write_mask))) {
1308 dest->stencil_write_mask = src->stencil_write_mask;
1309 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1310 }
1311 }
1312
1313 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1314 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1315 sizeof(src->stencil_reference))) {
1316 dest->stencil_reference = src->stencil_reference;
1317 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1318 }
1319 }
1320
1321 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1322 if (memcmp(&dest->discard_rectangle.rectangles,
1323 &src->discard_rectangle.rectangles,
1324 src->discard_rectangle.count * sizeof(VkRect2D))) {
1325 typed_memcpy(dest->discard_rectangle.rectangles,
1326 src->discard_rectangle.rectangles,
1327 src->discard_rectangle.count);
1328 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1329 }
1330 }
1331 }
1332
1333 static VkResult
1334 tu_create_cmd_buffer(struct tu_device *device,
1335 struct tu_cmd_pool *pool,
1336 VkCommandBufferLevel level,
1337 VkCommandBuffer *pCommandBuffer)
1338 {
1339 struct tu_cmd_buffer *cmd_buffer;
1340 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1341 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1342 if (cmd_buffer == NULL)
1343 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1344
1345 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1346 cmd_buffer->device = device;
1347 cmd_buffer->pool = pool;
1348 cmd_buffer->level = level;
1349
1350 if (pool) {
1351 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1352 cmd_buffer->queue_family_index = pool->queue_family_index;
1353
1354 } else {
1355 /* Init the pool_link so we can safely call list_del when we destroy
1356 * the command buffer
1357 */
1358 list_inithead(&cmd_buffer->pool_link);
1359 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1360 }
1361
1362 tu_bo_list_init(&cmd_buffer->bo_list);
1363 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1364 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1365 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1366 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1367
1368 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1369
1370 list_inithead(&cmd_buffer->upload.list);
1371
1372 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1373 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1374
1375 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1376 if (result != VK_SUCCESS)
1377 return result;
1378
1379 return VK_SUCCESS;
1380 }
1381
1382 static void
1383 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1384 {
1385 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1386
1387 list_del(&cmd_buffer->pool_link);
1388
1389 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1390 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1391
1392 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1393 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1394 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1395 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1396
1397 tu_bo_list_destroy(&cmd_buffer->bo_list);
1398 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1399 }
1400
1401 static VkResult
1402 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1403 {
1404 cmd_buffer->wait_for_idle = true;
1405
1406 cmd_buffer->record_result = VK_SUCCESS;
1407
1408 tu_bo_list_reset(&cmd_buffer->bo_list);
1409 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1410 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1411 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1412 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1413
1414 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1415 cmd_buffer->descriptors[i].dirty = 0;
1416 cmd_buffer->descriptors[i].valid = 0;
1417 cmd_buffer->descriptors[i].push_dirty = false;
1418 }
1419
1420 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1421
1422 return cmd_buffer->record_result;
1423 }
1424
1425 static VkResult
1426 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1427 const VkRenderPassBeginInfo *info)
1428 {
1429 struct tu_cmd_state *state = &cmd_buffer->state;
1430 const struct tu_framebuffer *fb = state->framebuffer;
1431 const struct tu_render_pass *pass = state->pass;
1432
1433 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1434 const struct tu_image_view *iview = fb->attachments[i].attachment;
1435 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1436 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1437 }
1438
1439 if (pass->attachment_count == 0) {
1440 state->attachments = NULL;
1441 return VK_SUCCESS;
1442 }
1443
1444 state->attachments =
1445 vk_alloc(&cmd_buffer->pool->alloc,
1446 pass->attachment_count * sizeof(state->attachments[0]), 8,
1447 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1448 if (state->attachments == NULL) {
1449 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1450 return cmd_buffer->record_result;
1451 }
1452
1453 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1454 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1455 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1456 VkImageAspectFlags clear_aspects = 0;
1457
1458 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1459 /* color attachment */
1460 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1461 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1462 }
1463 } else {
1464 /* depthstencil attachment */
1465 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1466 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1467 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1468 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1469 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1470 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1471 }
1472 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1473 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1474 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1475 }
1476 }
1477
1478 state->attachments[i].pending_clear_aspects = clear_aspects;
1479 state->attachments[i].cleared_views = 0;
1480 if (clear_aspects && info) {
1481 assert(info->clearValueCount > i);
1482 state->attachments[i].clear_value = info->pClearValues[i];
1483 }
1484
1485 state->attachments[i].current_layout = att->initial_layout;
1486 }
1487
1488 return VK_SUCCESS;
1489 }
1490
1491 VkResult
1492 tu_AllocateCommandBuffers(VkDevice _device,
1493 const VkCommandBufferAllocateInfo *pAllocateInfo,
1494 VkCommandBuffer *pCommandBuffers)
1495 {
1496 TU_FROM_HANDLE(tu_device, device, _device);
1497 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1498
1499 VkResult result = VK_SUCCESS;
1500 uint32_t i;
1501
1502 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1503
1504 if (!list_empty(&pool->free_cmd_buffers)) {
1505 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1506 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1507
1508 list_del(&cmd_buffer->pool_link);
1509 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1510
1511 result = tu_reset_cmd_buffer(cmd_buffer);
1512 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1513 cmd_buffer->level = pAllocateInfo->level;
1514
1515 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1516 } else {
1517 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1518 &pCommandBuffers[i]);
1519 }
1520 if (result != VK_SUCCESS)
1521 break;
1522 }
1523
1524 if (result != VK_SUCCESS) {
1525 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1526 pCommandBuffers);
1527
1528 /* From the Vulkan 1.0.66 spec:
1529 *
1530 * "vkAllocateCommandBuffers can be used to create multiple
1531 * command buffers. If the creation of any of those command
1532 * buffers fails, the implementation must destroy all
1533 * successfully created command buffer objects from this
1534 * command, set all entries of the pCommandBuffers array to
1535 * NULL and return the error."
1536 */
1537 memset(pCommandBuffers, 0,
1538 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1539 }
1540
1541 return result;
1542 }
1543
1544 void
1545 tu_FreeCommandBuffers(VkDevice device,
1546 VkCommandPool commandPool,
1547 uint32_t commandBufferCount,
1548 const VkCommandBuffer *pCommandBuffers)
1549 {
1550 for (uint32_t i = 0; i < commandBufferCount; i++) {
1551 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1552
1553 if (cmd_buffer) {
1554 if (cmd_buffer->pool) {
1555 list_del(&cmd_buffer->pool_link);
1556 list_addtail(&cmd_buffer->pool_link,
1557 &cmd_buffer->pool->free_cmd_buffers);
1558 } else
1559 tu_cmd_buffer_destroy(cmd_buffer);
1560 }
1561 }
1562 }
1563
1564 VkResult
1565 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1566 VkCommandBufferResetFlags flags)
1567 {
1568 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1569 return tu_reset_cmd_buffer(cmd_buffer);
1570 }
1571
1572 VkResult
1573 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1574 const VkCommandBufferBeginInfo *pBeginInfo)
1575 {
1576 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1577 VkResult result = VK_SUCCESS;
1578
1579 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1580 /* If the command buffer has already been resetted with
1581 * vkResetCommandBuffer, no need to do it again.
1582 */
1583 result = tu_reset_cmd_buffer(cmd_buffer);
1584 if (result != VK_SUCCESS)
1585 return result;
1586 }
1587
1588 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1589 cmd_buffer->usage_flags = pBeginInfo->flags;
1590
1591 tu_cs_begin(&cmd_buffer->cs);
1592
1593 cmd_buffer->marker_seqno = 0;
1594 cmd_buffer->scratch_seqno = 0;
1595
1596 /* setup initial configuration into command buffer */
1597 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1598 switch (cmd_buffer->queue_family_index) {
1599 case TU_QUEUE_GENERAL:
1600 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1601 break;
1602 default:
1603 break;
1604 }
1605 }
1606
1607 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1608
1609 return VK_SUCCESS;
1610 }
1611
1612 void
1613 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1614 uint32_t firstBinding,
1615 uint32_t bindingCount,
1616 const VkBuffer *pBuffers,
1617 const VkDeviceSize *pOffsets)
1618 {
1619 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1620
1621 assert(firstBinding + bindingCount <= MAX_VBS);
1622
1623 for (uint32_t i = 0; i < bindingCount; i++) {
1624 cmd->state.vb.buffers[firstBinding + i] =
1625 tu_buffer_from_handle(pBuffers[i]);
1626 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1627 }
1628
1629 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1630 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1631 }
1632
1633 void
1634 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1635 VkBuffer buffer,
1636 VkDeviceSize offset,
1637 VkIndexType indexType)
1638 {
1639 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1640 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1641
1642 /* initialize/update the restart index */
1643 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1644 struct tu_cs *draw_cs = &cmd->draw_cs;
1645 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1646 if (result != VK_SUCCESS) {
1647 cmd->record_result = result;
1648 return;
1649 }
1650
1651 tu6_emit_restart_index(
1652 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1653
1654 tu_cs_sanity_check(draw_cs);
1655 }
1656
1657 /* track the BO */
1658 if (cmd->state.index_buffer != buf)
1659 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1660
1661 cmd->state.index_buffer = buf;
1662 cmd->state.index_offset = offset;
1663 cmd->state.index_type = indexType;
1664 }
1665
1666 void
1667 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1668 VkPipelineBindPoint pipelineBindPoint,
1669 VkPipelineLayout _layout,
1670 uint32_t firstSet,
1671 uint32_t descriptorSetCount,
1672 const VkDescriptorSet *pDescriptorSets,
1673 uint32_t dynamicOffsetCount,
1674 const uint32_t *pDynamicOffsets)
1675 {
1676 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1677
1678 struct tu_descriptor_state *descriptors_state =
1679 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1680
1681 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1682 unsigned idx = i + firstSet;
1683 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1684
1685 descriptors_state->sets[idx] = set;
1686 descriptors_state->valid |= (1u << idx);
1687 }
1688
1689 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1690 }
1691
1692 void
1693 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1694 VkPipelineLayout layout,
1695 VkShaderStageFlags stageFlags,
1696 uint32_t offset,
1697 uint32_t size,
1698 const void *pValues)
1699 {
1700 }
1701
1702 VkResult
1703 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1704 {
1705 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1706
1707 if (cmd_buffer->scratch_seqno) {
1708 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1709 MSM_SUBMIT_BO_WRITE);
1710 }
1711
1712 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1713 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1714 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1715 }
1716
1717 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1718 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1719 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1720 }
1721
1722 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1723 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1724 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1725 }
1726
1727 tu_cs_end(&cmd_buffer->cs);
1728
1729 assert(!cmd_buffer->state.attachments);
1730
1731 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1732
1733 return cmd_buffer->record_result;
1734 }
1735
1736 void
1737 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1738 VkPipelineBindPoint pipelineBindPoint,
1739 VkPipeline _pipeline)
1740 {
1741 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1742 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1743
1744 switch (pipelineBindPoint) {
1745 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1746 cmd->state.pipeline = pipeline;
1747 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1748 break;
1749 case VK_PIPELINE_BIND_POINT_COMPUTE:
1750 tu_finishme("binding compute pipeline");
1751 break;
1752 default:
1753 unreachable("unrecognized pipeline bind point");
1754 break;
1755 }
1756 }
1757
1758 void
1759 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1760 uint32_t firstViewport,
1761 uint32_t viewportCount,
1762 const VkViewport *pViewports)
1763 {
1764 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1765 struct tu_cs *draw_cs = &cmd->draw_cs;
1766
1767 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1768 if (result != VK_SUCCESS) {
1769 cmd->record_result = result;
1770 return;
1771 }
1772
1773 assert(firstViewport == 0 && viewportCount == 1);
1774 tu6_emit_viewport(draw_cs, pViewports);
1775
1776 tu_cs_sanity_check(draw_cs);
1777 }
1778
1779 void
1780 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1781 uint32_t firstScissor,
1782 uint32_t scissorCount,
1783 const VkRect2D *pScissors)
1784 {
1785 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1786 struct tu_cs *draw_cs = &cmd->draw_cs;
1787
1788 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1789 if (result != VK_SUCCESS) {
1790 cmd->record_result = result;
1791 return;
1792 }
1793
1794 assert(firstScissor == 0 && scissorCount == 1);
1795 tu6_emit_scissor(draw_cs, pScissors);
1796
1797 tu_cs_sanity_check(draw_cs);
1798 }
1799
1800 void
1801 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1802 {
1803 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1804
1805 cmd->state.dynamic.line_width = lineWidth;
1806
1807 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1808 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1809 }
1810
1811 void
1812 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1813 float depthBiasConstantFactor,
1814 float depthBiasClamp,
1815 float depthBiasSlopeFactor)
1816 {
1817 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1818 struct tu_cs *draw_cs = &cmd->draw_cs;
1819
1820 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1821 if (result != VK_SUCCESS) {
1822 cmd->record_result = result;
1823 return;
1824 }
1825
1826 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1827 depthBiasSlopeFactor);
1828
1829 tu_cs_sanity_check(draw_cs);
1830 }
1831
1832 void
1833 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1834 const float blendConstants[4])
1835 {
1836 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1837 struct tu_cs *draw_cs = &cmd->draw_cs;
1838
1839 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1840 if (result != VK_SUCCESS) {
1841 cmd->record_result = result;
1842 return;
1843 }
1844
1845 tu6_emit_blend_constants(draw_cs, blendConstants);
1846
1847 tu_cs_sanity_check(draw_cs);
1848 }
1849
1850 void
1851 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1852 float minDepthBounds,
1853 float maxDepthBounds)
1854 {
1855 }
1856
1857 void
1858 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1859 VkStencilFaceFlags faceMask,
1860 uint32_t compareMask)
1861 {
1862 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1863
1864 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1865 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1866 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1867 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1868
1869 /* the front/back compare masks must be updated together */
1870 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1871 }
1872
1873 void
1874 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1875 VkStencilFaceFlags faceMask,
1876 uint32_t writeMask)
1877 {
1878 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1879
1880 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1881 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1882 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1883 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1884
1885 /* the front/back write masks must be updated together */
1886 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1887 }
1888
1889 void
1890 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1891 VkStencilFaceFlags faceMask,
1892 uint32_t reference)
1893 {
1894 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1895
1896 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1897 cmd->state.dynamic.stencil_reference.front = reference;
1898 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1899 cmd->state.dynamic.stencil_reference.back = reference;
1900
1901 /* the front/back references must be updated together */
1902 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1903 }
1904
1905 void
1906 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1907 uint32_t commandBufferCount,
1908 const VkCommandBuffer *pCmdBuffers)
1909 {
1910 }
1911
1912 VkResult
1913 tu_CreateCommandPool(VkDevice _device,
1914 const VkCommandPoolCreateInfo *pCreateInfo,
1915 const VkAllocationCallbacks *pAllocator,
1916 VkCommandPool *pCmdPool)
1917 {
1918 TU_FROM_HANDLE(tu_device, device, _device);
1919 struct tu_cmd_pool *pool;
1920
1921 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1922 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1923 if (pool == NULL)
1924 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1925
1926 if (pAllocator)
1927 pool->alloc = *pAllocator;
1928 else
1929 pool->alloc = device->alloc;
1930
1931 list_inithead(&pool->cmd_buffers);
1932 list_inithead(&pool->free_cmd_buffers);
1933
1934 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1935
1936 *pCmdPool = tu_cmd_pool_to_handle(pool);
1937
1938 return VK_SUCCESS;
1939 }
1940
1941 void
1942 tu_DestroyCommandPool(VkDevice _device,
1943 VkCommandPool commandPool,
1944 const VkAllocationCallbacks *pAllocator)
1945 {
1946 TU_FROM_HANDLE(tu_device, device, _device);
1947 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1948
1949 if (!pool)
1950 return;
1951
1952 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1953 &pool->cmd_buffers, pool_link)
1954 {
1955 tu_cmd_buffer_destroy(cmd_buffer);
1956 }
1957
1958 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1959 &pool->free_cmd_buffers, pool_link)
1960 {
1961 tu_cmd_buffer_destroy(cmd_buffer);
1962 }
1963
1964 vk_free2(&device->alloc, pAllocator, pool);
1965 }
1966
1967 VkResult
1968 tu_ResetCommandPool(VkDevice device,
1969 VkCommandPool commandPool,
1970 VkCommandPoolResetFlags flags)
1971 {
1972 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1973 VkResult result;
1974
1975 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
1976 pool_link)
1977 {
1978 result = tu_reset_cmd_buffer(cmd_buffer);
1979 if (result != VK_SUCCESS)
1980 return result;
1981 }
1982
1983 return VK_SUCCESS;
1984 }
1985
1986 void
1987 tu_TrimCommandPool(VkDevice device,
1988 VkCommandPool commandPool,
1989 VkCommandPoolTrimFlags flags)
1990 {
1991 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1992
1993 if (!pool)
1994 return;
1995
1996 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1997 &pool->free_cmd_buffers, pool_link)
1998 {
1999 tu_cmd_buffer_destroy(cmd_buffer);
2000 }
2001 }
2002
2003 void
2004 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2005 const VkRenderPassBeginInfo *pRenderPassBegin,
2006 VkSubpassContents contents)
2007 {
2008 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2009 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2010 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2011 VkResult result;
2012
2013 cmd_buffer->state.pass = pass;
2014 cmd_buffer->state.subpass = pass->subpasses;
2015 cmd_buffer->state.framebuffer = framebuffer;
2016
2017 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2018 if (result != VK_SUCCESS)
2019 return;
2020
2021 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2022 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2023 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2024
2025 /* draw_cs should contain entries only for this render pass */
2026 assert(!cmd_buffer->draw_cs.entry_count);
2027 tu_cs_begin(&cmd_buffer->draw_cs);
2028 }
2029
2030 void
2031 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2032 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2033 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2034 {
2035 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2036 pSubpassBeginInfo->contents);
2037 }
2038
2039 void
2040 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2041 {
2042 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2043
2044 tu_cmd_render_tiles(cmd);
2045
2046 cmd->state.subpass++;
2047
2048 tu_cmd_update_tiling_config(cmd, NULL);
2049 tu_cmd_prepare_tile_load_ib(cmd);
2050 tu_cmd_prepare_tile_store_ib(cmd);
2051 }
2052
2053 void
2054 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2055 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2056 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2057 {
2058 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2059 }
2060
2061 struct tu_draw_info
2062 {
2063 /**
2064 * Number of vertices.
2065 */
2066 uint32_t count;
2067
2068 /**
2069 * Index of the first vertex.
2070 */
2071 int32_t vertex_offset;
2072
2073 /**
2074 * First instance id.
2075 */
2076 uint32_t first_instance;
2077
2078 /**
2079 * Number of instances.
2080 */
2081 uint32_t instance_count;
2082
2083 /**
2084 * First index (indexed draws only).
2085 */
2086 uint32_t first_index;
2087
2088 /**
2089 * Whether it's an indexed draw.
2090 */
2091 bool indexed;
2092
2093 /**
2094 * Indirect draw parameters resource.
2095 */
2096 struct tu_buffer *indirect;
2097 uint64_t indirect_offset;
2098 uint32_t stride;
2099
2100 /**
2101 * Draw count parameters resource.
2102 */
2103 struct tu_buffer *count_buffer;
2104 uint64_t count_buffer_offset;
2105 };
2106
2107 enum tu_draw_state_group_id
2108 {
2109 TU_DRAW_STATE_PROGRAM,
2110 TU_DRAW_STATE_PROGRAM_BINNING,
2111 TU_DRAW_STATE_VI,
2112 TU_DRAW_STATE_VI_BINNING,
2113 TU_DRAW_STATE_VP,
2114 TU_DRAW_STATE_RAST,
2115 TU_DRAW_STATE_DS,
2116 TU_DRAW_STATE_BLEND,
2117 TU_DRAW_STATE_VS_CONST,
2118 TU_DRAW_STATE_FS_CONST,
2119 TU_DRAW_STATE_VS_TEX,
2120 TU_DRAW_STATE_FS_TEX,
2121
2122 TU_DRAW_STATE_COUNT,
2123 };
2124
2125 struct tu_draw_state_group
2126 {
2127 enum tu_draw_state_group_id id;
2128 uint32_t enable_mask;
2129 struct tu_cs_entry ib;
2130 };
2131
2132 static uint32_t*
2133 map_get(struct tu_descriptor_state *descriptors_state,
2134 const struct tu_descriptor_map *map, unsigned i)
2135 {
2136 assert(descriptors_state->valid & (1 << map->set[i]));
2137
2138 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2139
2140 assert(map->binding[i] < set->layout->binding_count);
2141
2142 return &set->mapped_ptr[set->layout->binding[map->binding[i]].offset / 4];
2143 }
2144
2145 static inline uint32_t
2146 tu6_stage2opcode(gl_shader_stage type)
2147 {
2148 switch (type) {
2149 case MESA_SHADER_VERTEX:
2150 case MESA_SHADER_TESS_CTRL:
2151 case MESA_SHADER_TESS_EVAL:
2152 case MESA_SHADER_GEOMETRY:
2153 return CP_LOAD_STATE6_GEOM;
2154 case MESA_SHADER_FRAGMENT:
2155 case MESA_SHADER_COMPUTE:
2156 case MESA_SHADER_KERNEL:
2157 return CP_LOAD_STATE6_FRAG;
2158 default:
2159 unreachable("bad shader type");
2160 }
2161 }
2162
2163 static inline enum a6xx_state_block
2164 tu6_stage2shadersb(gl_shader_stage type)
2165 {
2166 switch (type) {
2167 case MESA_SHADER_VERTEX:
2168 return SB6_VS_SHADER;
2169 case MESA_SHADER_FRAGMENT:
2170 return SB6_FS_SHADER;
2171 case MESA_SHADER_COMPUTE:
2172 case MESA_SHADER_KERNEL:
2173 return SB6_CS_SHADER;
2174 default:
2175 unreachable("bad shader type");
2176 return ~0;
2177 }
2178 }
2179
2180 static void
2181 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2182 struct tu_descriptor_state *descriptors_state,
2183 gl_shader_stage type)
2184 {
2185 const struct tu_program_descriptor_linkage *link =
2186 &pipeline->program.link[type];
2187 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2188
2189 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2190 if (state->range[i].start < state->range[i].end) {
2191 assert(i && i - 1 < link->ubo_map.num);
2192 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i - 1);
2193
2194 uint32_t size = state->range[i].end - state->range[i].start;
2195 uint32_t offset = state->range[i].start;
2196
2197 /* and even if the start of the const buffer is before
2198 * first_immediate, the end may not be:
2199 */
2200 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2201
2202 if (size == 0)
2203 continue;
2204
2205 /* things should be aligned to vec4: */
2206 debug_assert((state->range[i].offset % 16) == 0);
2207 debug_assert((size % 16) == 0);
2208 debug_assert((offset % 16) == 0);
2209
2210 uint64_t addr = (uint64_t) ptr[1] << 32 | ptr[0];
2211 addr += state->range[i].offset;
2212
2213 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2214 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2215 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2216 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2217 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2218 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2219 tu_cs_emit_qw(cs, addr);
2220 }
2221 }
2222 }
2223
2224 static void
2225 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2226 struct tu_descriptor_state *descriptors_state,
2227 gl_shader_stage type)
2228 {
2229 const struct tu_program_descriptor_linkage *link =
2230 &pipeline->program.link[type];
2231
2232 uint32_t anum = align(link->ubo_map.num, 2);
2233 uint32_t i;
2234
2235 if (!link->ubo_map.num)
2236 return;
2237
2238 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2239 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->offset_ubo) |
2240 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2241 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2242 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2243 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2244 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2245 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2246
2247 for (i = 0; i < link->ubo_map.num; i++) {
2248 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i);
2249 tu_cs_emit(cs, ptr[0]);
2250 tu_cs_emit(cs, ptr[1]);
2251 }
2252
2253 for (; i < anum; i++) {
2254 tu_cs_emit(cs, 0xffffffff);
2255 tu_cs_emit(cs, 0xffffffff);
2256 }
2257 }
2258
2259 static struct tu_cs_entry
2260 tu6_emit_consts(struct tu_device *device, struct tu_cs *draw_state,
2261 const struct tu_pipeline *pipeline,
2262 struct tu_descriptor_state *descriptors_state,
2263 gl_shader_stage type)
2264 {
2265 struct tu_cs cs;
2266 tu_cs_begin_sub_stream(device, draw_state, 512, &cs); /* TODO: maximum size? */
2267
2268 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type);
2269 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2270
2271 return tu_cs_end_sub_stream(draw_state, &cs);
2272 }
2273
2274 static struct tu_cs_entry
2275 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2276 const struct tu_pipeline *pipeline,
2277 struct tu_descriptor_state *descriptors_state,
2278 gl_shader_stage type, bool *needs_border)
2279 {
2280 const struct tu_program_descriptor_linkage *link =
2281 &pipeline->program.link[type];
2282
2283 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2284 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2285 if (!size)
2286 return (struct tu_cs_entry) {};
2287
2288 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2289 enum a6xx_state_block sb;
2290
2291 switch (type) {
2292 case MESA_SHADER_VERTEX:
2293 sb = SB6_VS_TEX;
2294 opcode = CP_LOAD_STATE6_GEOM;
2295 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2296 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2297 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2298 break;
2299 case MESA_SHADER_FRAGMENT:
2300 sb = SB6_FS_TEX;
2301 opcode = CP_LOAD_STATE6_FRAG;
2302 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2303 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2304 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2305 break;
2306 case MESA_SHADER_COMPUTE:
2307 sb = SB6_CS_TEX;
2308 opcode = CP_LOAD_STATE6_FRAG;
2309 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2310 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2311 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2312 break;
2313 default:
2314 unreachable("bad state block");
2315 }
2316
2317 struct tu_cs cs;
2318 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2319
2320 for (unsigned i = 0; i < link->texture_map.num; i++) {
2321 uint32_t *ptr = map_get(descriptors_state, &link->texture_map, i);
2322
2323 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2324 tu_cs_emit(&cs, ptr[j]);
2325 }
2326
2327 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2328 uint32_t *ptr = map_get(descriptors_state, &link->sampler_map, i);
2329 struct tu_sampler *sampler = (void*) &ptr[A6XX_TEX_CONST_DWORDS];
2330
2331 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2332 tu_cs_emit(&cs, sampler->state[j]);
2333
2334 *needs_border |= sampler->needs_border;
2335 }
2336
2337 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2338
2339 uint64_t tex_addr = entry.bo->iova + entry.offset;
2340 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2341
2342 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2343
2344 /* output sampler state: */
2345 tu_cs_emit_pkt7(&cs, opcode, 3);
2346 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2347 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2348 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2349 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2350 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2351 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2352
2353 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2354 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2355
2356 /* emit texture state: */
2357 tu_cs_emit_pkt7(&cs, opcode, 3);
2358 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2359 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2360 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2361 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2362 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2363 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2364
2365 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2366 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2367
2368 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2369 tu_cs_emit(&cs, link->texture_map.num);
2370
2371 return tu_cs_end_sub_stream(draw_state, &cs);
2372 }
2373
2374 static void
2375 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2376 struct tu_cs *cs)
2377 {
2378 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2379
2380 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2381 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2382 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2383 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2384 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2385
2386 struct tu_cs border_cs;
2387 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2388
2389 /* TODO: actually fill with border color */
2390 for (unsigned i = 0; i < size; i++)
2391 tu_cs_emit(&border_cs, 0);
2392
2393 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2394
2395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2396 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2397 }
2398
2399 static void
2400 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2401 struct tu_cs *cs,
2402 const struct tu_draw_info *draw)
2403 {
2404 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2405 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2406 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2407 uint32_t draw_state_group_count = 0;
2408
2409 struct tu_descriptor_state *descriptors_state =
2410 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2411
2412 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2413 if (result != VK_SUCCESS) {
2414 cmd->record_result = result;
2415 return;
2416 }
2417
2418 /* TODO lrz */
2419
2420 uint32_t pc_primitive_cntl = 0;
2421 if (pipeline->ia.primitive_restart && draw->indexed)
2422 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2423
2424 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2425 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2426 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2427
2428 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2429 tu_cs_emit(cs, pc_primitive_cntl);
2430
2431 if (cmd->state.dirty &
2432 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2433 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2434 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2435 dynamic->line_width);
2436 }
2437
2438 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2439 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2440 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2441 dynamic->stencil_compare_mask.back);
2442 }
2443
2444 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2445 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2446 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2447 dynamic->stencil_write_mask.back);
2448 }
2449
2450 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2451 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2452 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2453 dynamic->stencil_reference.back);
2454 }
2455
2456 if (cmd->state.dirty &
2457 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2458 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2459 const uint32_t binding = pipeline->vi.bindings[i];
2460 const uint32_t stride = pipeline->vi.strides[i];
2461 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2462 const VkDeviceSize offset = buf->bo_offset +
2463 cmd->state.vb.offsets[binding] +
2464 pipeline->vi.offsets[i];
2465 const VkDeviceSize size =
2466 offset < buf->bo->size ? buf->bo->size - offset : 0;
2467
2468 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2469 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2470 tu_cs_emit(cs, size);
2471 tu_cs_emit(cs, stride);
2472 }
2473 }
2474
2475 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2476 draw_state_groups[draw_state_group_count++] =
2477 (struct tu_draw_state_group) {
2478 .id = TU_DRAW_STATE_PROGRAM,
2479 .enable_mask = 0x6,
2480 .ib = pipeline->program.state_ib,
2481 };
2482 draw_state_groups[draw_state_group_count++] =
2483 (struct tu_draw_state_group) {
2484 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2485 .enable_mask = 0x1,
2486 .ib = pipeline->program.binning_state_ib,
2487 };
2488 draw_state_groups[draw_state_group_count++] =
2489 (struct tu_draw_state_group) {
2490 .id = TU_DRAW_STATE_VI,
2491 .enable_mask = 0x6,
2492 .ib = pipeline->vi.state_ib,
2493 };
2494 draw_state_groups[draw_state_group_count++] =
2495 (struct tu_draw_state_group) {
2496 .id = TU_DRAW_STATE_VI_BINNING,
2497 .enable_mask = 0x1,
2498 .ib = pipeline->vi.binning_state_ib,
2499 };
2500 draw_state_groups[draw_state_group_count++] =
2501 (struct tu_draw_state_group) {
2502 .id = TU_DRAW_STATE_VP,
2503 .enable_mask = 0x7,
2504 .ib = pipeline->vp.state_ib,
2505 };
2506 draw_state_groups[draw_state_group_count++] =
2507 (struct tu_draw_state_group) {
2508 .id = TU_DRAW_STATE_RAST,
2509 .enable_mask = 0x7,
2510 .ib = pipeline->rast.state_ib,
2511 };
2512 draw_state_groups[draw_state_group_count++] =
2513 (struct tu_draw_state_group) {
2514 .id = TU_DRAW_STATE_DS,
2515 .enable_mask = 0x7,
2516 .ib = pipeline->ds.state_ib,
2517 };
2518 draw_state_groups[draw_state_group_count++] =
2519 (struct tu_draw_state_group) {
2520 .id = TU_DRAW_STATE_BLEND,
2521 .enable_mask = 0x7,
2522 .ib = pipeline->blend.state_ib,
2523 };
2524 }
2525
2526 if (cmd->state.dirty &
2527 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2528 bool needs_border = false;
2529
2530 draw_state_groups[draw_state_group_count++] =
2531 (struct tu_draw_state_group) {
2532 .id = TU_DRAW_STATE_VS_CONST,
2533 .enable_mask = 0x7,
2534 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2535 descriptors_state, MESA_SHADER_VERTEX)
2536 };
2537 draw_state_groups[draw_state_group_count++] =
2538 (struct tu_draw_state_group) {
2539 .id = TU_DRAW_STATE_FS_CONST,
2540 .enable_mask = 0x6,
2541 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2542 descriptors_state, MESA_SHADER_FRAGMENT)
2543 };
2544 draw_state_groups[draw_state_group_count++] =
2545 (struct tu_draw_state_group) {
2546 .id = TU_DRAW_STATE_VS_TEX,
2547 .enable_mask = 0x7,
2548 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2549 descriptors_state, MESA_SHADER_VERTEX,
2550 &needs_border)
2551 };
2552 draw_state_groups[draw_state_group_count++] =
2553 (struct tu_draw_state_group) {
2554 .id = TU_DRAW_STATE_FS_TEX,
2555 .enable_mask = 0x6,
2556 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2557 descriptors_state, MESA_SHADER_FRAGMENT,
2558 &needs_border)
2559 };
2560
2561 if (needs_border)
2562 tu6_emit_border_color(cmd, cs);
2563 }
2564
2565 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2566 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2567 const struct tu_draw_state_group *group = &draw_state_groups[i];
2568
2569 uint32_t cp_set_draw_state =
2570 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2571 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2572 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2573 uint64_t iova;
2574 if (group->ib.size) {
2575 iova = group->ib.bo->iova + group->ib.offset;
2576 } else {
2577 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2578 iova = 0;
2579 }
2580
2581 tu_cs_emit(cs, cp_set_draw_state);
2582 tu_cs_emit_qw(cs, iova);
2583 }
2584
2585 tu_cs_sanity_check(cs);
2586
2587 /* track BOs */
2588 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2589 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2590 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2591 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2592 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2593 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2594 }
2595 }
2596 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2597 for (uint32_t i = 0; i < MAX_VBS; i++) {
2598 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2599 if (buf)
2600 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2601 }
2602 }
2603 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2604 unsigned i;
2605 for_each_bit(i, descriptors_state->valid) {
2606 struct tu_descriptor_set *set = descriptors_state->sets[i];
2607 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2608 if (set->descriptors[j]) {
2609 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2610 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2611 }
2612 }
2613 }
2614 cmd->state.dirty = 0;
2615 }
2616
2617 static void
2618 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2619 struct tu_cs *cs,
2620 const struct tu_draw_info *draw)
2621 {
2622
2623 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2624
2625 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2626 tu_cs_emit(cs, draw->vertex_offset);
2627 tu_cs_emit(cs, draw->first_instance);
2628
2629 /* TODO hw binning */
2630 if (draw->indexed) {
2631 const enum a4xx_index_size index_size =
2632 tu6_index_size(cmd->state.index_type);
2633 const uint32_t index_bytes =
2634 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2635 const struct tu_buffer *buf = cmd->state.index_buffer;
2636 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2637 index_bytes * draw->first_index;
2638 const uint32_t size = index_bytes * draw->count;
2639
2640 const uint32_t cp_draw_indx =
2641 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2642 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2643 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2644 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2645
2646 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2647 tu_cs_emit(cs, cp_draw_indx);
2648 tu_cs_emit(cs, draw->instance_count);
2649 tu_cs_emit(cs, draw->count);
2650 tu_cs_emit(cs, 0x0); /* XXX */
2651 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2652 tu_cs_emit(cs, size);
2653 } else {
2654 const uint32_t cp_draw_indx =
2655 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2656 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2657 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2658
2659 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2660 tu_cs_emit(cs, cp_draw_indx);
2661 tu_cs_emit(cs, draw->instance_count);
2662 tu_cs_emit(cs, draw->count);
2663 }
2664 }
2665
2666 static void
2667 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2668 {
2669 struct tu_cs *cs = &cmd->draw_cs;
2670
2671 tu6_bind_draw_states(cmd, cs, draw);
2672
2673 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2674 if (result != VK_SUCCESS) {
2675 cmd->record_result = result;
2676 return;
2677 }
2678
2679 if (draw->indirect) {
2680 tu_finishme("indirect draw");
2681 return;
2682 }
2683
2684 /* TODO tu6_emit_marker should pick different regs depending on cs */
2685 tu6_emit_marker(cmd, cs);
2686 tu6_emit_draw_direct(cmd, cs, draw);
2687 tu6_emit_marker(cmd, cs);
2688
2689 cmd->wait_for_idle = true;
2690
2691 tu_cs_sanity_check(cs);
2692 }
2693
2694 void
2695 tu_CmdDraw(VkCommandBuffer commandBuffer,
2696 uint32_t vertexCount,
2697 uint32_t instanceCount,
2698 uint32_t firstVertex,
2699 uint32_t firstInstance)
2700 {
2701 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2702 struct tu_draw_info info = {};
2703
2704 info.count = vertexCount;
2705 info.instance_count = instanceCount;
2706 info.first_instance = firstInstance;
2707 info.vertex_offset = firstVertex;
2708
2709 tu_draw(cmd_buffer, &info);
2710 }
2711
2712 void
2713 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2714 uint32_t indexCount,
2715 uint32_t instanceCount,
2716 uint32_t firstIndex,
2717 int32_t vertexOffset,
2718 uint32_t firstInstance)
2719 {
2720 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2721 struct tu_draw_info info = {};
2722
2723 info.indexed = true;
2724 info.count = indexCount;
2725 info.instance_count = instanceCount;
2726 info.first_index = firstIndex;
2727 info.vertex_offset = vertexOffset;
2728 info.first_instance = firstInstance;
2729
2730 tu_draw(cmd_buffer, &info);
2731 }
2732
2733 void
2734 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2735 VkBuffer _buffer,
2736 VkDeviceSize offset,
2737 uint32_t drawCount,
2738 uint32_t stride)
2739 {
2740 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2741 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2742 struct tu_draw_info info = {};
2743
2744 info.count = drawCount;
2745 info.indirect = buffer;
2746 info.indirect_offset = offset;
2747 info.stride = stride;
2748
2749 tu_draw(cmd_buffer, &info);
2750 }
2751
2752 void
2753 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2754 VkBuffer _buffer,
2755 VkDeviceSize offset,
2756 uint32_t drawCount,
2757 uint32_t stride)
2758 {
2759 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2760 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2761 struct tu_draw_info info = {};
2762
2763 info.indexed = true;
2764 info.count = drawCount;
2765 info.indirect = buffer;
2766 info.indirect_offset = offset;
2767 info.stride = stride;
2768
2769 tu_draw(cmd_buffer, &info);
2770 }
2771
2772 struct tu_dispatch_info
2773 {
2774 /**
2775 * Determine the layout of the grid (in block units) to be used.
2776 */
2777 uint32_t blocks[3];
2778
2779 /**
2780 * A starting offset for the grid. If unaligned is set, the offset
2781 * must still be aligned.
2782 */
2783 uint32_t offsets[3];
2784 /**
2785 * Whether it's an unaligned compute dispatch.
2786 */
2787 bool unaligned;
2788
2789 /**
2790 * Indirect compute parameters resource.
2791 */
2792 struct tu_buffer *indirect;
2793 uint64_t indirect_offset;
2794 };
2795
2796 static void
2797 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2798 const struct tu_dispatch_info *info)
2799 {
2800 }
2801
2802 void
2803 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2804 uint32_t base_x,
2805 uint32_t base_y,
2806 uint32_t base_z,
2807 uint32_t x,
2808 uint32_t y,
2809 uint32_t z)
2810 {
2811 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2812 struct tu_dispatch_info info = {};
2813
2814 info.blocks[0] = x;
2815 info.blocks[1] = y;
2816 info.blocks[2] = z;
2817
2818 info.offsets[0] = base_x;
2819 info.offsets[1] = base_y;
2820 info.offsets[2] = base_z;
2821 tu_dispatch(cmd_buffer, &info);
2822 }
2823
2824 void
2825 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2826 uint32_t x,
2827 uint32_t y,
2828 uint32_t z)
2829 {
2830 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2831 }
2832
2833 void
2834 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2835 VkBuffer _buffer,
2836 VkDeviceSize offset)
2837 {
2838 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2839 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2840 struct tu_dispatch_info info = {};
2841
2842 info.indirect = buffer;
2843 info.indirect_offset = offset;
2844
2845 tu_dispatch(cmd_buffer, &info);
2846 }
2847
2848 void
2849 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2850 {
2851 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2852
2853 tu_cs_end(&cmd_buffer->draw_cs);
2854
2855 tu_cmd_render_tiles(cmd_buffer);
2856
2857 /* discard draw_cs entries now that the tiles are rendered */
2858 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2859
2860 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2861 cmd_buffer->state.attachments = NULL;
2862
2863 cmd_buffer->state.pass = NULL;
2864 cmd_buffer->state.subpass = NULL;
2865 cmd_buffer->state.framebuffer = NULL;
2866 }
2867
2868 void
2869 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
2870 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2871 {
2872 tu_CmdEndRenderPass(commandBuffer);
2873 }
2874
2875 struct tu_barrier_info
2876 {
2877 uint32_t eventCount;
2878 const VkEvent *pEvents;
2879 VkPipelineStageFlags srcStageMask;
2880 };
2881
2882 static void
2883 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
2884 uint32_t memoryBarrierCount,
2885 const VkMemoryBarrier *pMemoryBarriers,
2886 uint32_t bufferMemoryBarrierCount,
2887 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2888 uint32_t imageMemoryBarrierCount,
2889 const VkImageMemoryBarrier *pImageMemoryBarriers,
2890 const struct tu_barrier_info *info)
2891 {
2892 }
2893
2894 void
2895 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
2896 VkPipelineStageFlags srcStageMask,
2897 VkPipelineStageFlags destStageMask,
2898 VkBool32 byRegion,
2899 uint32_t memoryBarrierCount,
2900 const VkMemoryBarrier *pMemoryBarriers,
2901 uint32_t bufferMemoryBarrierCount,
2902 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2903 uint32_t imageMemoryBarrierCount,
2904 const VkImageMemoryBarrier *pImageMemoryBarriers)
2905 {
2906 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2907 struct tu_barrier_info info;
2908
2909 info.eventCount = 0;
2910 info.pEvents = NULL;
2911 info.srcStageMask = srcStageMask;
2912
2913 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
2914 bufferMemoryBarrierCount, pBufferMemoryBarriers,
2915 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
2916 }
2917
2918 static void
2919 write_event(struct tu_cmd_buffer *cmd_buffer,
2920 struct tu_event *event,
2921 VkPipelineStageFlags stageMask,
2922 unsigned value)
2923 {
2924 }
2925
2926 void
2927 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
2928 VkEvent _event,
2929 VkPipelineStageFlags stageMask)
2930 {
2931 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2932 TU_FROM_HANDLE(tu_event, event, _event);
2933
2934 write_event(cmd_buffer, event, stageMask, 1);
2935 }
2936
2937 void
2938 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
2939 VkEvent _event,
2940 VkPipelineStageFlags stageMask)
2941 {
2942 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2943 TU_FROM_HANDLE(tu_event, event, _event);
2944
2945 write_event(cmd_buffer, event, stageMask, 0);
2946 }
2947
2948 void
2949 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
2950 uint32_t eventCount,
2951 const VkEvent *pEvents,
2952 VkPipelineStageFlags srcStageMask,
2953 VkPipelineStageFlags dstStageMask,
2954 uint32_t memoryBarrierCount,
2955 const VkMemoryBarrier *pMemoryBarriers,
2956 uint32_t bufferMemoryBarrierCount,
2957 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2958 uint32_t imageMemoryBarrierCount,
2959 const VkImageMemoryBarrier *pImageMemoryBarriers)
2960 {
2961 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2962 struct tu_barrier_info info;
2963
2964 info.eventCount = eventCount;
2965 info.pEvents = pEvents;
2966 info.srcStageMask = 0;
2967
2968 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
2969 bufferMemoryBarrierCount, pBufferMemoryBarriers,
2970 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
2971 }
2972
2973 void
2974 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
2975 {
2976 /* No-op */
2977 }