src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36
  37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  38
  39 void
  40 tu_bo_list_init(struct tu_bo_list *list)
  41 {
  42    list->count = list->capacity = 0;
  43    list->bo_infos = NULL;
  44 }
  45
  46 void
  47 tu_bo_list_destroy(struct tu_bo_list *list)
  48 {
  49    free(list->bo_infos);
  50 }
  51
  52 void
  53 tu_bo_list_reset(struct tu_bo_list *list)
  54 {
  55    list->count = 0;
  56 }
  57
  58 /**
  59  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  60  */
  61 static uint32_t
  62 tu_bo_list_add_info(struct tu_bo_list *list,
  63                     const struct drm_msm_gem_submit_bo *bo_info)
  64 {
  65    assert(bo_info->handle != 0);
  66
  67    for (uint32_t i = 0; i < list->count; ++i) {
  68       if (list->bo_infos[i].handle == bo_info->handle) {
  69          assert(list->bo_infos[i].presumed == bo_info->presumed);
  70          list->bo_infos[i].flags |= bo_info->flags;
  71          return i;
  72       }
  73    }
  74
  75    /* grow list->bo_infos if needed */
  76    if (list->count == list->capacity) {
  77       uint32_t new_capacity = MAX2(2 * list->count, 16);
  78       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  79          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  80       if (!new_bo_infos)
  81          return TU_BO_LIST_FAILED;
  82       list->bo_infos = new_bo_infos;
  83       list->capacity = new_capacity;
  84    }
  85
  86    list->bo_infos[list->count] = *bo_info;
  87    return list->count++;
  88 }
  89
  90 uint32_t
  91 tu_bo_list_add(struct tu_bo_list *list,
  92                const struct tu_bo *bo,
  93                uint32_t flags)
  94 {
  95    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  96                                        .flags = flags,
  97                                        .handle = bo->gem_handle,
  98                                        .presumed = bo->iova,
  99                                     });
 100 }
 101
 102 VkResult
 103 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 104 {
 105    for (uint32_t i = 0; i < other->count; i++) {
 106       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 107          return VK_ERROR_OUT_OF_HOST_MEMORY;
 108    }
 109
 110    return VK_SUCCESS;
 111 }
 112
 113 static void
 114 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 115                                     const struct tu_device *dev,
 116                                     const struct tu_render_pass *pass)
 117 {
 118    const uint32_t tile_align_w = pass->tile_align_w;
 119    const uint32_t max_tile_width = 1024;
 120
 121    /* note: don't offset the tiling config by render_area.offset,
 122     * because binning pass can't deal with it
 123     * this means we might end up with more tiles than necessary,
 124     * but load/store/etc are still scissored to the render_area
 125     */
 126    tiling->tile0.offset = (VkOffset2D) {};
 127
 128    const uint32_t ra_width =
 129       tiling->render_area.extent.width +
 130       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 131    const uint32_t ra_height =
 132       tiling->render_area.extent.height +
 133       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 134
 135    /* start from 1 tile */
 136    tiling->tile_count = (VkExtent2D) {
 137       .width = 1,
 138       .height = 1,
 139    };
 140    tiling->tile0.extent = (VkExtent2D) {
 141       .width = util_align_npot(ra_width, tile_align_w),
 142       .height = align(ra_height, TILE_ALIGN_H),
 143    };
 144
 145    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 146       /* start with 2x2 tiles */
 147       tiling->tile_count.width = 2;
 148       tiling->tile_count.height = 2;
 149       tiling->tile0.extent.width = util_align_npot(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 150       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), TILE_ALIGN_H);
 151    }
 152
 153    /* do not exceed max tile width */
 154    while (tiling->tile0.extent.width > max_tile_width) {
 155       tiling->tile_count.width++;
 156       tiling->tile0.extent.width =
 157          util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 158    }
 159
 160    /* will force to sysmem, don't bother trying to have a valid tile config
 161     * TODO: just skip all GMEM stuff when sysmem is forced?
 162     */
 163    if (!pass->gmem_pixels)
 164       return;
 165
 166    /* do not exceed gmem size */
 167    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pass->gmem_pixels) {
 168       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 169          tiling->tile_count.width++;
 170          tiling->tile0.extent.width =
 171             util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 172       } else {
 173          /* if this assert fails then layout is impossible.. */
 174          assert(tiling->tile0.extent.height > TILE_ALIGN_H);
 175          tiling->tile_count.height++;
 176          tiling->tile0.extent.height =
 177             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), TILE_ALIGN_H);
 178       }
 179    }
 180 }
 181
 182 static void
 183 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 184                                     const struct tu_device *dev)
 185 {
 186    const uint32_t max_pipe_count = 32; /* A6xx */
 187
 188    /* start from 1 tile per pipe */
 189    tiling->pipe0 = (VkExtent2D) {
 190       .width = 1,
 191       .height = 1,
 192    };
 193    tiling->pipe_count = tiling->tile_count;
 194
 195    while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
 196       if (tiling->pipe0.width < tiling->pipe0.height) {
 197          tiling->pipe0.width += 1;
 198          tiling->pipe_count.width =
 199             DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
 200       } else {
 201          tiling->pipe0.height += 1;
 202          tiling->pipe_count.height =
 203             DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
 204       }
 205    }
 206 }
 207
 208 static void
 209 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 210                               const struct tu_device *dev)
 211 {
 212    const uint32_t max_pipe_count = 32; /* A6xx */
 213    const uint32_t used_pipe_count =
 214       tiling->pipe_count.width * tiling->pipe_count.height;
 215    const VkExtent2D last_pipe = {
 216       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 217       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 218    };
 219
 220    assert(used_pipe_count <= max_pipe_count);
 221    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 222
 223    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 224       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 225          const uint32_t pipe_x = tiling->pipe0.width * x;
 226          const uint32_t pipe_y = tiling->pipe0.height * y;
 227          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 228                                     ? last_pipe.width
 229                                     : tiling->pipe0.width;
 230          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 231                                     ? last_pipe.height
 232                                     : tiling->pipe0.height;
 233          const uint32_t n = tiling->pipe_count.width * y + x;
 234
 235          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 236                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 237                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 238                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 239          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 240       }
 241    }
 242
 243    memset(tiling->pipe_config + used_pipe_count, 0,
 244           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 245 }
 246
 247 static void
 248 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 249                           const struct tu_device *dev,
 250                           uint32_t tx,
 251                           uint32_t ty,
 252                           struct tu_tile *tile)
 253 {
 254    /* find the pipe and the slot for tile (tx, ty) */
 255    const uint32_t px = tx / tiling->pipe0.width;
 256    const uint32_t py = ty / tiling->pipe0.height;
 257    const uint32_t sx = tx - tiling->pipe0.width * px;
 258    const uint32_t sy = ty - tiling->pipe0.height * py;
 259    /* last pipe has different width */
 260    const uint32_t pipe_width =
 261       MIN2(tiling->pipe0.width,
 262            tiling->tile_count.width - px * tiling->pipe0.width);
 263
 264    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 265    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 266    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 267
 268    /* convert to 1D indices */
 269    tile->pipe = tiling->pipe_count.width * py + px;
 270    tile->slot = pipe_width * sy + sx;
 271
 272    /* get the blit area for the tile */
 273    tile->begin = (VkOffset2D) {
 274       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 275       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 276    };
 277    tile->end.x =
 278       (tx == tiling->tile_count.width - 1)
 279          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 280          : tile->begin.x + tiling->tile0.extent.width;
 281    tile->end.y =
 282       (ty == tiling->tile_count.height - 1)
 283          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 284          : tile->begin.y + tiling->tile0.extent.height;
 285 }
 286
 287 enum a3xx_msaa_samples
 288 tu_msaa_samples(uint32_t samples)
 289 {
 290    switch (samples) {
 291    case 1:
 292       return MSAA_ONE;
 293    case 2:
 294       return MSAA_TWO;
 295    case 4:
 296       return MSAA_FOUR;
 297    case 8:
 298       return MSAA_EIGHT;
 299    default:
 300       assert(!"invalid sample count");
 301       return MSAA_ONE;
 302    }
 303 }
 304
 305 static enum a4xx_index_size
 306 tu6_index_size(VkIndexType type)
 307 {
 308    switch (type) {
 309    case VK_INDEX_TYPE_UINT16:
 310       return INDEX4_SIZE_16_BIT;
 311    case VK_INDEX_TYPE_UINT32:
 312       return INDEX4_SIZE_32_BIT;
 313    default:
 314       unreachable("invalid VkIndexType");
 315       return INDEX4_SIZE_8_BIT;
 316    }
 317 }
 318
 319 unsigned
 320 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 321                      struct tu_cs *cs,
 322                      enum vgt_event_type event,
 323                      bool need_seqno)
 324 {
 325    unsigned seqno = 0;
 326
 327    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 328    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 329    if (need_seqno) {
 330       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 331       seqno = ++cmd->scratch_seqno;
 332       tu_cs_emit(cs, seqno);
 333    }
 334
 335    return seqno;
 336 }
 337
 338 static void
 339 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 340 {
 341    tu6_emit_event_write(cmd, cs, 0x31, false);
 342 }
 343
 344 static void
 345 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 346 {
 347    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 348 }
 349
 350 static void
 351 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 352 {
 353    if (cmd->wait_for_idle) {
 354       tu_cs_emit_wfi(cs);
 355       cmd->wait_for_idle = false;
 356    }
 357 }
 358
 359 static void
 360 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 361             const struct tu_subpass *subpass,
 362             struct tu_cs *cs)
 363 {
 364    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 365
 366    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 367    if (a == VK_ATTACHMENT_UNUSED) {
 368       tu_cs_emit_regs(cs,
 369                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 370                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 371                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 372                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 373                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 374
 375       tu_cs_emit_regs(cs,
 376                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 377
 378       tu_cs_emit_regs(cs,
 379                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 380                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 381                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 382
 383       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 384
 385       return;
 386    }
 387
 388    const struct tu_image_view *iview = fb->attachments[a].attachment;
 389    const struct tu_render_pass_attachment *attachment =
 390       &cmd->state.pass->attachments[a];
 391    enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
 392
 393    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 394    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
 395    tu_cs_image_ref(cs, iview, 0);
 396    tu_cs_emit(cs, attachment->gmem_offset);
 397
 398    tu_cs_emit_regs(cs,
 399                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 400
 401    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
 402    tu_cs_image_flag_ref(cs, iview, 0);
 403
 404    tu_cs_emit_regs(cs,
 405                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 406                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 407                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 408
 409    if (attachment->format == VK_FORMAT_S8_UINT) {
 410       tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
 411       tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value);
 412       tu_cs_image_ref(cs, iview, 0);
 413       tu_cs_emit(cs, attachment->gmem_offset);
 414    } else {
 415       tu_cs_emit_regs(cs,
 416                      A6XX_RB_STENCIL_INFO(0));
 417    }
 418 }
 419
 420 static void
 421 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 422              const struct tu_subpass *subpass,
 423              struct tu_cs *cs)
 424 {
 425    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 426
 427    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 428       uint32_t a = subpass->color_attachments[i].attachment;
 429       if (a == VK_ATTACHMENT_UNUSED)
 430          continue;
 431
 432       const struct tu_image_view *iview = fb->attachments[a].attachment;
 433
 434       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
 435       tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
 436       tu_cs_image_ref(cs, iview, 0);
 437       tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
 438
 439       tu_cs_emit_regs(cs,
 440                       A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
 441
 442       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i), 3);
 443       tu_cs_image_flag_ref(cs, iview, 0);
 444    }
 445
 446    tu_cs_emit_regs(cs,
 447                    A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
 448    tu_cs_emit_regs(cs,
 449                    A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
 450
 451    tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(fb->layers - 1));
 452 }
 453
 454 void
 455 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples)
 456 {
 457    const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
 458    bool msaa_disable = samples == MSAA_ONE;
 459
 460    tu_cs_emit_regs(cs,
 461                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 462                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 463                                              .msaa_disable = msaa_disable));
 464
 465    tu_cs_emit_regs(cs,
 466                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 467                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 468                                             .msaa_disable = msaa_disable));
 469
 470    tu_cs_emit_regs(cs,
 471                    A6XX_RB_RAS_MSAA_CNTL(samples),
 472                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 473                                           .msaa_disable = msaa_disable));
 474
 475    tu_cs_emit_regs(cs,
 476                    A6XX_RB_MSAA_CNTL(samples));
 477 }
 478
 479 static void
 480 tu6_emit_bin_size(struct tu_cs *cs,
 481                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 482 {
 483    tu_cs_emit_regs(cs,
 484                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 485                                          .binh = bin_h,
 486                                          .dword = flags));
 487
 488    tu_cs_emit_regs(cs,
 489                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 490                                        .binh = bin_h,
 491                                        .dword = flags));
 492
 493    /* no flag for RB_BIN_CONTROL2... */
 494    tu_cs_emit_regs(cs,
 495                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 496                                         .binh = bin_h));
 497 }
 498
 499 static void
 500 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 501                      const struct tu_subpass *subpass,
 502                      struct tu_cs *cs,
 503                      bool binning)
 504 {
 505    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 506    uint32_t cntl = 0;
 507    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 508    if (binning) {
 509       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 510    } else {
 511       uint32_t mrts_ubwc_enable = 0;
 512       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 513          uint32_t a = subpass->color_attachments[i].attachment;
 514          if (a == VK_ATTACHMENT_UNUSED)
 515             continue;
 516
 517          const struct tu_image_view *iview = fb->attachments[a].attachment;
 518          if (iview->ubwc_enabled)
 519             mrts_ubwc_enable |= 1 << i;
 520       }
 521
 522       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 523
 524       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 525       if (a != VK_ATTACHMENT_UNUSED) {
 526          const struct tu_image_view *iview = fb->attachments[a].attachment;
 527          if (iview->ubwc_enabled)
 528             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 529       }
 530
 531       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 532        * in order to set it correctly for the different subpasses. However,
 533        * that means the packets we're emitting also happen during binning. So
 534        * we need to guard the write on !BINNING at CP execution time.
 535        */
 536       tu_cs_reserve(cs, 3 + 4);
 537       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 538       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 539                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 540       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 541    }
 542
 543    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 544    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 545    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 546    tu_cs_emit(cs, cntl);
 547 }
 548
 549 static void
 550 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 551 {
 552    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 553    uint32_t x1 = render_area->offset.x;
 554    uint32_t y1 = render_area->offset.y;
 555    uint32_t x2 = x1 + render_area->extent.width - 1;
 556    uint32_t y2 = y1 + render_area->extent.height - 1;
 557
 558    if (align) {
 559       x1 = x1 & ~(GMEM_ALIGN_W - 1);
 560       y1 = y1 & ~(GMEM_ALIGN_H - 1);
 561       x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
 562       y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
 563    }
 564
 565    tu_cs_emit_regs(cs,
 566                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 567                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 568 }
 569
 570 void
 571 tu6_emit_window_scissor(struct tu_cs *cs,
 572                         uint32_t x1,
 573                         uint32_t y1,
 574                         uint32_t x2,
 575                         uint32_t y2)
 576 {
 577    tu_cs_emit_regs(cs,
 578                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 579                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 580
 581    tu_cs_emit_regs(cs,
 582                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 583                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 584 }
 585
 586 void
 587 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
 588 {
 589    tu_cs_emit_regs(cs,
 590                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 591
 592    tu_cs_emit_regs(cs,
 593                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 594
 595    tu_cs_emit_regs(cs,
 596                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 597
 598    tu_cs_emit_regs(cs,
 599                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 600 }
 601
 602 static bool
 603 use_hw_binning(struct tu_cmd_buffer *cmd)
 604 {
 605    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 606
 607    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 608       return false;
 609
 610    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 611       return true;
 612
 613    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 614 }
 615
 616 static bool
 617 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 618 {
 619    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 620       return true;
 621
 622    /* can't fit attachments into gmem */
 623    if (!cmd->state.pass->gmem_pixels)
 624       return true;
 625
 626    if (cmd->state.framebuffer->layers > 1)
 627       return true;
 628
 629    return cmd->state.tiling_config.force_sysmem;
 630 }
 631
 632 static void
 633 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 634                      struct tu_cs *cs,
 635                      const struct tu_tile *tile)
 636 {
 637    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 638    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 639
 640    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 641    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 642
 643    const uint32_t x1 = tile->begin.x;
 644    const uint32_t y1 = tile->begin.y;
 645    const uint32_t x2 = tile->end.x - 1;
 646    const uint32_t y2 = tile->end.y - 1;
 647    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
 648    tu6_emit_window_offset(cs, x1, y1);
 649
 650    tu_cs_emit_regs(cs,
 651                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
 652
 653    if (use_hw_binning(cmd)) {
 654       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 655
 656       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 657       tu_cs_emit(cs, 0x0);
 658
 659       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 660       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 661                      A6XX_CP_REG_TEST_0_BIT(0) |
 662                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 663
 664       tu_cs_reserve(cs, 3 + 11);
 665       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 666       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 667       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 668
 669       /* if (no overflow) */ {
 670          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 671          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 672                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 673          tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + tile->pipe * cmd->vsc_draw_strm_pitch);
 674          tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + (tile->pipe * 4) + (32 * cmd->vsc_draw_strm_pitch));
 675          tu_cs_emit_qw(cs, cmd->vsc_prim_strm.iova + (tile->pipe * cmd->vsc_prim_strm_pitch));
 676
 677          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 678          tu_cs_emit(cs, 0x0);
 679
 680          /* use a NOP packet to skip over the 'else' side: */
 681          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 682       } /* else */ {
 683          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 684          tu_cs_emit(cs, 0x1);
 685       }
 686
 687       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 688       tu_cs_emit(cs, 0x0);
 689    } else {
 690       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 691       tu_cs_emit(cs, 0x1);
 692
 693       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 694       tu_cs_emit(cs, 0x0);
 695    }
 696 }
 697
 698 static void
 699 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 700                         struct tu_cs *cs,
 701                         uint32_t a,
 702                         uint32_t gmem_a)
 703 {
 704    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 705    struct tu_image_view *dst = fb->attachments[a].attachment;
 706    struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 707
 708    tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.tiling_config.render_area);
 709 }
 710
 711 static void
 712 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 713 {
 714    const struct tu_render_pass *pass = cmd->state.pass;
 715    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 716
 717    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 718    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 719                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 720                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 721    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 722    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 723
 724    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 725    tu_cs_emit(cs, 0x0);
 726
 727    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 728    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
 729
 730    tu6_emit_blit_scissor(cmd, cs, true);
 731
 732    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
 733       if (pass->attachments[a].gmem_offset >= 0)
 734          tu_store_gmem_attachment(cmd, cs, a, a);
 735    }
 736
 737    if (subpass->resolve_attachments) {
 738       for (unsigned i = 0; i < subpass->color_count; i++) {
 739          uint32_t a = subpass->resolve_attachments[i].attachment;
 740          if (a != VK_ATTACHMENT_UNUSED)
 741             tu_store_gmem_attachment(cmd, cs, a,
 742                                      subpass->color_attachments[i].attachment);
 743       }
 744    }
 745 }
 746
 747 static void
 748 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
 749 {
 750    tu_cs_emit_regs(cs,
 751                    A6XX_PC_RESTART_INDEX(restart_index));
 752 }
 753
 754 static void
 755 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 756 {
 757    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
 758
 759    tu6_emit_cache_flush(cmd, cs);
 760
 761    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
 762
 763    tu_cs_emit_regs(cs,
 764                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
 765    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
 766    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
 767    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
 768    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
 769    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
 770    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
 771    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
 772    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 773
 774    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
 775    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
 776    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
 777    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
 778    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
 779    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
 780    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
 781    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
 782    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
 783    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
 784    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
 785    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
 786    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
 787    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
 788
 789    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
 790    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
 791    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
 792
 793    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
 794
 795    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
 796
 797    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
 798    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
 799    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
 800    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
 801    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
 802    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
 803    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
 804    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
 805    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
 806    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
 807    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
 808
 809    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
 810    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
 811
 812    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236,
 813                         A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
 814    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
 815
 816    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
 817                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 818
 819    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
 820    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
 821    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
 822
 823    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
 824    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
 825
 826    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
 827
 828    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
 829
 830    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
 831    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
 832    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
 833    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
 834    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
 835    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
 836    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
 837    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
 838    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
 839    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
 840    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
 841    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
 842    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
 843    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 844
 845    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
 846
 847    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
 848
 849    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
 850
 851    /* we don't use this yet.. probably best to disable.. */
 852    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 853    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 854                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 855                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 856    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 857    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 858
 859    /* Set not to use streamout by default, */
 860    tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
 861    tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
 862    tu_cs_emit(cs, 0);
 863    tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
 864    tu_cs_emit(cs, 0);
 865
 866    tu_cs_emit_regs(cs,
 867                    A6XX_SP_HS_CTRL_REG0(0));
 868
 869    tu_cs_emit_regs(cs,
 870                    A6XX_SP_GS_CTRL_REG0(0));
 871
 872    tu_cs_emit_regs(cs,
 873                    A6XX_GRAS_LRZ_CNTL(0));
 874
 875    tu_cs_emit_regs(cs,
 876                    A6XX_RB_LRZ_CNTL(0));
 877
 878    tu_cs_emit_regs(cs,
 879                    A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 880    tu_cs_emit_regs(cs,
 881                    A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 882
 883    tu_cs_sanity_check(cs);
 884 }
 885
 886 static void
 887 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 888 {
 889    unsigned seqno;
 890
 891    seqno = tu6_emit_event_write(cmd, cs, RB_DONE_TS, true);
 892
 893    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
 894    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
 895                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
 896    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 897    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
 898    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
 899    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
 900
 901    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
 902
 903    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
 904    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
 905    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 906    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
 907 }
 908
 909 static void
 910 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 911 {
 912    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 913
 914    tu_cs_emit_regs(cs,
 915                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
 916                                      .height = tiling->tile0.extent.height),
 917                    A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = &cmd->vsc_draw_strm,
 918                                                    .bo_offset = 32 * cmd->vsc_draw_strm_pitch));
 919
 920    tu_cs_emit_regs(cs,
 921                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
 922                                       .ny = tiling->tile_count.height));
 923
 924    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
 925    for (unsigned i = 0; i < 32; i++)
 926       tu_cs_emit(cs, tiling->pipe_config[i]);
 927
 928    tu_cs_emit_regs(cs,
 929                    A6XX_VSC_PRIM_STRM_ADDRESS(.bo = &cmd->vsc_prim_strm),
 930                    A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
 931                    A6XX_VSC_PRIM_STRM_ARRAY_PITCH(cmd->vsc_prim_strm.size));
 932
 933    tu_cs_emit_regs(cs,
 934                    A6XX_VSC_DRAW_STRM_ADDRESS(.bo = &cmd->vsc_draw_strm),
 935                    A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
 936                    A6XX_VSC_DRAW_STRM_ARRAY_PITCH(cmd->vsc_draw_strm.size));
 937 }
 938
 939 static void
 940 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 941 {
 942    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 943    const uint32_t used_pipe_count =
 944       tiling->pipe_count.width * tiling->pipe_count.height;
 945
 946    /* Clear vsc_scratch: */
 947    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
 948    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 949    tu_cs_emit(cs, 0x0);
 950
 951    /* Check for overflow, write vsc_scratch if detected: */
 952    for (int i = 0; i < used_pipe_count; i++) {
 953       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
 954       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
 955             CP_COND_WRITE5_0_WRITE_MEMORY);
 956       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
 957       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
 958       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch));
 959       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
 960       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 961       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_draw_strm_pitch));
 962
 963       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
 964       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
 965             CP_COND_WRITE5_0_WRITE_MEMORY);
 966       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
 967       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
 968       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch));
 969       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
 970       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 971       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_prim_strm_pitch));
 972    }
 973
 974    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
 975
 976    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 977
 978    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
 979    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
 980          CP_MEM_TO_REG_0_CNT(1 - 1));
 981    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 982
 983    /*
 984     * This is a bit awkward, we really want a way to invert the
 985     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
 986     * execute cmds to use hwbinning when a bit is *not* set.  This
 987     * dance is to invert OVERFLOW_FLAG_REG
 988     *
 989     * A CP_NOP packet is used to skip executing the 'else' clause
 990     * if (b0 set)..
 991     */
 992
 993    /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
 994    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 995    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 996          A6XX_CP_REG_TEST_0_BIT(0) |
 997          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 998
 999    tu_cs_reserve(cs, 3 + 7);
1000    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1001    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1002    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1003
1004    /* if (b0 set) */ {
1005       /*
1006        * On overflow, mirror the value to control->vsc_overflow
1007        * which CPU is checking to detect overflow (see
1008        * check_vsc_overflow())
1009        */
1010       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1011       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1012             CP_REG_TO_MEM_0_CNT(0));
1013       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_overflow));
1014
1015       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1016       tu_cs_emit(cs, 0x0);
1017
1018       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1019    } /* else */ {
1020       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1021       tu_cs_emit(cs, 0x1);
1022    }
1023 }
1024
1025 static void
1026 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1027 {
1028    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1029    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1030
1031    uint32_t x1 = tiling->tile0.offset.x;
1032    uint32_t y1 = tiling->tile0.offset.y;
1033    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1034    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1035
1036    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
1037
1038    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1039    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1040
1041    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1042    tu_cs_emit(cs, 0x1);
1043
1044    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1045    tu_cs_emit(cs, 0x1);
1046
1047    tu_cs_emit_wfi(cs);
1048
1049    tu_cs_emit_regs(cs,
1050                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1051
1052    update_vsc_pipe(cmd, cs);
1053
1054    tu_cs_emit_regs(cs,
1055                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1056
1057    tu_cs_emit_regs(cs,
1058                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1059
1060    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1061    tu_cs_emit(cs, UNK_2C);
1062
1063    tu_cs_emit_regs(cs,
1064                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1065
1066    tu_cs_emit_regs(cs,
1067                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1068
1069    /* emit IB to binning drawcmds: */
1070    tu_cs_emit_call(cs, &cmd->draw_cs);
1071
1072    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1073    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1074                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1075                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1076    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1077    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1078
1079    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1080    tu_cs_emit(cs, UNK_2D);
1081
1082    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1083    tu6_cache_flush(cmd, cs);
1084
1085    tu_cs_emit_wfi(cs);
1086
1087    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1088
1089    emit_vsc_overflow_test(cmd, cs);
1090
1091    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1092    tu_cs_emit(cs, 0x0);
1093
1094    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1095    tu_cs_emit(cs, 0x0);
1096
1097    cmd->wait_for_idle = false;
1098 }
1099
1100 static void
1101 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1102                    const VkRenderPassBeginInfo *info)
1103 {
1104    struct tu_cs *cs = &cmd->draw_cs;
1105
1106    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1107
1108    tu6_emit_blit_scissor(cmd, cs, true);
1109
1110    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1111       tu_load_gmem_attachment(cmd, cs, i, false);
1112
1113    tu6_emit_blit_scissor(cmd, cs, false);
1114
1115    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1116       tu_clear_gmem_attachment(cmd, cs, i, info);
1117
1118    tu_cond_exec_end(cs);
1119
1120    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1121
1122    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1123       tu_clear_sysmem_attachment(cmd, cs, i, info);
1124
1125    tu_cond_exec_end(cs);
1126 }
1127
1128 static void
1129 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1130                         const struct VkRect2D *renderArea)
1131 {
1132    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
1133    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1134
1135    assert(fb->width > 0 && fb->height > 0);
1136    tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1137    tu6_emit_window_offset(cs, 0, 0);
1138
1139    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1140
1141    tu6_emit_lrz_flush(cmd, cs);
1142
1143    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1144    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1145
1146    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1147    tu_cs_emit(cs, 0x0);
1148
1149    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1150    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1151    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1152
1153    tu6_emit_wfi(cmd, cs);
1154    tu_cs_emit_regs(cs,
1155                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
1156
1157    /* enable stream-out, with sysmem there is only one pass: */
1158    tu_cs_emit_regs(cs,
1159                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1160
1161    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1162    tu_cs_emit(cs, 0x1);
1163
1164    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1165    tu_cs_emit(cs, 0x0);
1166
1167    tu_cs_sanity_check(cs);
1168 }
1169
1170 static void
1171 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1172 {
1173    /* Do any resolves of the last subpass. These are handled in the
1174     * tile_store_ib in the gmem path.
1175     */
1176    const struct tu_subpass *subpass = cmd->state.subpass;
1177    if (subpass->resolve_attachments) {
1178       for (unsigned i = 0; i < subpass->color_count; i++) {
1179          uint32_t a = subpass->resolve_attachments[i].attachment;
1180          if (a != VK_ATTACHMENT_UNUSED)
1181             tu6_emit_sysmem_resolve(cmd, cs, a,
1182                                     subpass->color_attachments[i].attachment);
1183       }
1184    }
1185
1186    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1187
1188    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1189    tu_cs_emit(cs, 0x0);
1190
1191    tu6_emit_lrz_flush(cmd, cs);
1192
1193    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1194    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1195
1196    tu_cs_sanity_check(cs);
1197 }
1198
1199
1200 static void
1201 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1202 {
1203    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1204
1205    tu6_emit_lrz_flush(cmd, cs);
1206
1207    /* lrz clear? */
1208
1209    tu6_emit_cache_flush(cmd, cs);
1210
1211    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1212    tu_cs_emit(cs, 0x0);
1213
1214    /* TODO: flushing with barriers instead of blindly always flushing */
1215    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1216    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1217    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1218    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1219
1220    tu_cs_emit_wfi(cs);
1221    tu_cs_emit_regs(cs,
1222                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_gmem, .gmem = 1));
1223
1224    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1225    if (use_hw_binning(cmd)) {
1226       /* enable stream-out during binning pass: */
1227       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1228
1229       tu6_emit_bin_size(cs,
1230                         tiling->tile0.extent.width,
1231                         tiling->tile0.extent.height,
1232                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1233
1234       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1235
1236       tu6_emit_binning_pass(cmd, cs);
1237
1238       /* and disable stream-out for draw pass: */
1239       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=true));
1240
1241       tu6_emit_bin_size(cs,
1242                         tiling->tile0.extent.width,
1243                         tiling->tile0.extent.height,
1244                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1245
1246       tu_cs_emit_regs(cs,
1247                       A6XX_VFD_MODE_CNTL(0));
1248
1249       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1250
1251       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1252
1253       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1254       tu_cs_emit(cs, 0x1);
1255    } else {
1256       /* no binning pass, so enable stream-out for draw pass:: */
1257       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1258
1259       tu6_emit_bin_size(cs,
1260                         tiling->tile0.extent.width,
1261                         tiling->tile0.extent.height,
1262                         0x6000000);
1263    }
1264
1265    tu_cs_sanity_check(cs);
1266 }
1267
1268 static void
1269 tu6_render_tile(struct tu_cmd_buffer *cmd,
1270                 struct tu_cs *cs,
1271                 const struct tu_tile *tile)
1272 {
1273    tu6_emit_tile_select(cmd, cs, tile);
1274
1275    tu_cs_emit_call(cs, &cmd->draw_cs);
1276    cmd->wait_for_idle = true;
1277
1278    if (use_hw_binning(cmd)) {
1279       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1280       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1281                      A6XX_CP_REG_TEST_0_BIT(0) |
1282                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1283
1284       tu_cs_reserve(cs, 3 + 2);
1285       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1286       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1287       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1288
1289       /* if (no overflow) */ {
1290          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1291          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1292       }
1293    }
1294
1295    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1296
1297    tu_cs_sanity_check(cs);
1298 }
1299
1300 static void
1301 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1302 {
1303    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1304
1305    tu_cs_emit_regs(cs,
1306                    A6XX_GRAS_LRZ_CNTL(0));
1307
1308    tu6_emit_lrz_flush(cmd, cs);
1309
1310    tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS, true);
1311
1312    tu_cs_sanity_check(cs);
1313 }
1314
1315 static void
1316 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1317 {
1318    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1319
1320    tu6_tile_render_begin(cmd, &cmd->cs);
1321
1322    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1323       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1324          struct tu_tile tile;
1325          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1326          tu6_render_tile(cmd, &cmd->cs, &tile);
1327       }
1328    }
1329
1330    tu6_tile_render_end(cmd, &cmd->cs);
1331 }
1332
1333 static void
1334 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1335 {
1336    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1337
1338    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1339
1340    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1341    cmd->wait_for_idle = true;
1342
1343    tu6_sysmem_render_end(cmd, &cmd->cs);
1344 }
1345
1346 static void
1347 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1348 {
1349    const uint32_t tile_store_space = 11 + (35 * 2) * cmd->state.pass->attachment_count;
1350    struct tu_cs sub_cs;
1351
1352    VkResult result =
1353       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1354    if (result != VK_SUCCESS) {
1355       cmd->record_result = result;
1356       return;
1357    }
1358
1359    /* emit to tile-store sub_cs */
1360    tu6_emit_tile_store(cmd, &sub_cs);
1361
1362    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1363 }
1364
1365 static void
1366 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1367                             const VkRect2D *render_area)
1368 {
1369    const struct tu_device *dev = cmd->device;
1370    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1371
1372    tiling->render_area = *render_area;
1373    tiling->force_sysmem = false;
1374
1375    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass);
1376    tu_tiling_config_update_pipe_layout(tiling, dev);
1377    tu_tiling_config_update_pipes(tiling, dev);
1378 }
1379
1380 const struct tu_dynamic_state default_dynamic_state = {
1381    .viewport =
1382      {
1383        .count = 0,
1384      },
1385    .scissor =
1386      {
1387        .count = 0,
1388      },
1389    .line_width = 1.0f,
1390    .depth_bias =
1391      {
1392        .bias = 0.0f,
1393        .clamp = 0.0f,
1394        .slope = 0.0f,
1395      },
1396    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1397    .depth_bounds =
1398      {
1399        .min = 0.0f,
1400        .max = 1.0f,
1401      },
1402    .stencil_compare_mask =
1403      {
1404        .front = ~0u,
1405        .back = ~0u,
1406      },
1407    .stencil_write_mask =
1408      {
1409        .front = ~0u,
1410        .back = ~0u,
1411      },
1412    .stencil_reference =
1413      {
1414        .front = 0u,
1415        .back = 0u,
1416      },
1417 };
1418
1419 static void UNUSED /* FINISHME */
1420 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1421                       const struct tu_dynamic_state *src)
1422 {
1423    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1424    uint32_t copy_mask = src->mask;
1425    uint32_t dest_mask = 0;
1426
1427    tu_use_args(cmd_buffer); /* FINISHME */
1428
1429    /* Make sure to copy the number of viewports/scissors because they can
1430     * only be specified at pipeline creation time.
1431     */
1432    dest->viewport.count = src->viewport.count;
1433    dest->scissor.count = src->scissor.count;
1434    dest->discard_rectangle.count = src->discard_rectangle.count;
1435
1436    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1437       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1438                  src->viewport.count * sizeof(VkViewport))) {
1439          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1440                       src->viewport.count);
1441          dest_mask |= TU_DYNAMIC_VIEWPORT;
1442       }
1443    }
1444
1445    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1446       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1447                  src->scissor.count * sizeof(VkRect2D))) {
1448          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1449                       src->scissor.count);
1450          dest_mask |= TU_DYNAMIC_SCISSOR;
1451       }
1452    }
1453
1454    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1455       if (dest->line_width != src->line_width) {
1456          dest->line_width = src->line_width;
1457          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1458       }
1459    }
1460
1461    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1462       if (memcmp(&dest->depth_bias, &src->depth_bias,
1463                  sizeof(src->depth_bias))) {
1464          dest->depth_bias = src->depth_bias;
1465          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1466       }
1467    }
1468
1469    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1470       if (memcmp(&dest->blend_constants, &src->blend_constants,
1471                  sizeof(src->blend_constants))) {
1472          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1473          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1474       }
1475    }
1476
1477    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1478       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1479                  sizeof(src->depth_bounds))) {
1480          dest->depth_bounds = src->depth_bounds;
1481          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1482       }
1483    }
1484
1485    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1486       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1487                  sizeof(src->stencil_compare_mask))) {
1488          dest->stencil_compare_mask = src->stencil_compare_mask;
1489          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1490       }
1491    }
1492
1493    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1494       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1495                  sizeof(src->stencil_write_mask))) {
1496          dest->stencil_write_mask = src->stencil_write_mask;
1497          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1498       }
1499    }
1500
1501    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1502       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1503                  sizeof(src->stencil_reference))) {
1504          dest->stencil_reference = src->stencil_reference;
1505          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1506       }
1507    }
1508
1509    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1510       if (memcmp(&dest->discard_rectangle.rectangles,
1511                  &src->discard_rectangle.rectangles,
1512                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1513          typed_memcpy(dest->discard_rectangle.rectangles,
1514                       src->discard_rectangle.rectangles,
1515                       src->discard_rectangle.count);
1516          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1517       }
1518    }
1519 }
1520
1521 static VkResult
1522 tu_create_cmd_buffer(struct tu_device *device,
1523                      struct tu_cmd_pool *pool,
1524                      VkCommandBufferLevel level,
1525                      VkCommandBuffer *pCommandBuffer)
1526 {
1527    struct tu_cmd_buffer *cmd_buffer;
1528    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1529                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1530    if (cmd_buffer == NULL)
1531       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1532
1533    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1534    cmd_buffer->device = device;
1535    cmd_buffer->pool = pool;
1536    cmd_buffer->level = level;
1537
1538    if (pool) {
1539       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1540       cmd_buffer->queue_family_index = pool->queue_family_index;
1541
1542    } else {
1543       /* Init the pool_link so we can safely call list_del when we destroy
1544        * the command buffer
1545        */
1546       list_inithead(&cmd_buffer->pool_link);
1547       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1548    }
1549
1550    tu_bo_list_init(&cmd_buffer->bo_list);
1551    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1552    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1553    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1554    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1555
1556    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1557
1558    list_inithead(&cmd_buffer->upload.list);
1559
1560    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1561    if (result != VK_SUCCESS)
1562       goto fail_scratch_bo;
1563
1564    /* TODO: resize on overflow */
1565    cmd_buffer->vsc_draw_strm_pitch = device->vsc_draw_strm_pitch;
1566    cmd_buffer->vsc_prim_strm_pitch = device->vsc_prim_strm_pitch;
1567    cmd_buffer->vsc_draw_strm = device->vsc_draw_strm;
1568    cmd_buffer->vsc_prim_strm = device->vsc_prim_strm;
1569
1570    return VK_SUCCESS;
1571
1572 fail_scratch_bo:
1573    list_del(&cmd_buffer->pool_link);
1574    return result;
1575 }
1576
1577 static void
1578 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1579 {
1580    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1581
1582    list_del(&cmd_buffer->pool_link);
1583
1584    for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
1585       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1586
1587    tu_cs_finish(&cmd_buffer->cs);
1588    tu_cs_finish(&cmd_buffer->draw_cs);
1589    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1590    tu_cs_finish(&cmd_buffer->sub_cs);
1591
1592    tu_bo_list_destroy(&cmd_buffer->bo_list);
1593    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1594 }
1595
1596 static VkResult
1597 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1598 {
1599    cmd_buffer->wait_for_idle = true;
1600
1601    cmd_buffer->record_result = VK_SUCCESS;
1602
1603    tu_bo_list_reset(&cmd_buffer->bo_list);
1604    tu_cs_reset(&cmd_buffer->cs);
1605    tu_cs_reset(&cmd_buffer->draw_cs);
1606    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1607    tu_cs_reset(&cmd_buffer->sub_cs);
1608
1609    for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
1610       cmd_buffer->descriptors[i].valid = 0;
1611       cmd_buffer->descriptors[i].push_dirty = false;
1612    }
1613
1614    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1615
1616    return cmd_buffer->record_result;
1617 }
1618
1619 VkResult
1620 tu_AllocateCommandBuffers(VkDevice _device,
1621                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1622                           VkCommandBuffer *pCommandBuffers)
1623 {
1624    TU_FROM_HANDLE(tu_device, device, _device);
1625    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1626
1627    VkResult result = VK_SUCCESS;
1628    uint32_t i;
1629
1630    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1631
1632       if (!list_is_empty(&pool->free_cmd_buffers)) {
1633          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1634             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1635
1636          list_del(&cmd_buffer->pool_link);
1637          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1638
1639          result = tu_reset_cmd_buffer(cmd_buffer);
1640          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1641          cmd_buffer->level = pAllocateInfo->level;
1642
1643          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1644       } else {
1645          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1646                                        &pCommandBuffers[i]);
1647       }
1648       if (result != VK_SUCCESS)
1649          break;
1650    }
1651
1652    if (result != VK_SUCCESS) {
1653       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1654                             pCommandBuffers);
1655
1656       /* From the Vulkan 1.0.66 spec:
1657        *
1658        * "vkAllocateCommandBuffers can be used to create multiple
1659        *  command buffers. If the creation of any of those command
1660        *  buffers fails, the implementation must destroy all
1661        *  successfully created command buffer objects from this
1662        *  command, set all entries of the pCommandBuffers array to
1663        *  NULL and return the error."
1664        */
1665       memset(pCommandBuffers, 0,
1666              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1667    }
1668
1669    return result;
1670 }
1671
1672 void
1673 tu_FreeCommandBuffers(VkDevice device,
1674                       VkCommandPool commandPool,
1675                       uint32_t commandBufferCount,
1676                       const VkCommandBuffer *pCommandBuffers)
1677 {
1678    for (uint32_t i = 0; i < commandBufferCount; i++) {
1679       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1680
1681       if (cmd_buffer) {
1682          if (cmd_buffer->pool) {
1683             list_del(&cmd_buffer->pool_link);
1684             list_addtail(&cmd_buffer->pool_link,
1685                          &cmd_buffer->pool->free_cmd_buffers);
1686          } else
1687             tu_cmd_buffer_destroy(cmd_buffer);
1688       }
1689    }
1690 }
1691
1692 VkResult
1693 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1694                       VkCommandBufferResetFlags flags)
1695 {
1696    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1697    return tu_reset_cmd_buffer(cmd_buffer);
1698 }
1699
1700 VkResult
1701 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1702                       const VkCommandBufferBeginInfo *pBeginInfo)
1703 {
1704    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1705    VkResult result = VK_SUCCESS;
1706
1707    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1708       /* If the command buffer has already been resetted with
1709        * vkResetCommandBuffer, no need to do it again.
1710        */
1711       result = tu_reset_cmd_buffer(cmd_buffer);
1712       if (result != VK_SUCCESS)
1713          return result;
1714    }
1715
1716    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1717    cmd_buffer->usage_flags = pBeginInfo->flags;
1718
1719    tu_cs_begin(&cmd_buffer->cs);
1720    tu_cs_begin(&cmd_buffer->draw_cs);
1721    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
1722
1723    cmd_buffer->scratch_seqno = 0;
1724
1725    /* setup initial configuration into command buffer */
1726    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1727       switch (cmd_buffer->queue_family_index) {
1728       case TU_QUEUE_GENERAL:
1729          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1730          break;
1731       default:
1732          break;
1733       }
1734    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1735               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1736       assert(pBeginInfo->pInheritanceInfo);
1737       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1738       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1739    }
1740
1741    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1742
1743    return VK_SUCCESS;
1744 }
1745
1746 void
1747 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1748                         uint32_t firstBinding,
1749                         uint32_t bindingCount,
1750                         const VkBuffer *pBuffers,
1751                         const VkDeviceSize *pOffsets)
1752 {
1753    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1754
1755    assert(firstBinding + bindingCount <= MAX_VBS);
1756
1757    for (uint32_t i = 0; i < bindingCount; i++) {
1758       cmd->state.vb.buffers[firstBinding + i] =
1759          tu_buffer_from_handle(pBuffers[i]);
1760       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1761    }
1762
1763    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1764    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1765 }
1766
1767 void
1768 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1769                       VkBuffer buffer,
1770                       VkDeviceSize offset,
1771                       VkIndexType indexType)
1772 {
1773    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1774    TU_FROM_HANDLE(tu_buffer, buf, buffer);
1775
1776    /* initialize/update the restart index */
1777    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1778       struct tu_cs *draw_cs = &cmd->draw_cs;
1779
1780       tu6_emit_restart_index(
1781          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1782
1783       tu_cs_sanity_check(draw_cs);
1784    }
1785
1786    /* track the BO */
1787    if (cmd->state.index_buffer != buf)
1788       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1789
1790    cmd->state.index_buffer = buf;
1791    cmd->state.index_offset = offset;
1792    cmd->state.index_type = indexType;
1793 }
1794
1795 void
1796 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1797                          VkPipelineBindPoint pipelineBindPoint,
1798                          VkPipelineLayout _layout,
1799                          uint32_t firstSet,
1800                          uint32_t descriptorSetCount,
1801                          const VkDescriptorSet *pDescriptorSets,
1802                          uint32_t dynamicOffsetCount,
1803                          const uint32_t *pDynamicOffsets)
1804 {
1805    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1806    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1807    unsigned dyn_idx = 0;
1808
1809    struct tu_descriptor_state *descriptors_state =
1810       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1811
1812    for (unsigned i = 0; i < descriptorSetCount; ++i) {
1813       unsigned idx = i + firstSet;
1814       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1815
1816       descriptors_state->sets[idx] = set;
1817       descriptors_state->valid |= (1u << idx);
1818
1819       /* Note: the actual input attachment indices come from the shader
1820        * itself, so we can't generate the patched versions of these until
1821        * draw time when both the pipeline and descriptors are bound and
1822        * we're inside the render pass.
1823        */
1824       unsigned dst_idx = layout->set[idx].input_attachment_start;
1825       memcpy(&descriptors_state->input_attachments[dst_idx * A6XX_TEX_CONST_DWORDS],
1826              set->dynamic_descriptors,
1827              set->layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
1828
1829       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1830          /* Dynamic buffers come after input attachments in the descriptor set
1831           * itself, but due to how the Vulkan descriptor set binding works, we
1832           * have to put input attachments and dynamic buffers in separate
1833           * buffers in the descriptor_state and then combine them at draw
1834           * time. Binding a descriptor set only invalidates the descriptor
1835           * sets after it, but if we try to tightly pack the descriptors after
1836           * the input attachments then we could corrupt dynamic buffers in the
1837           * descriptor set before it, or we'd have to move all the dynamic
1838           * buffers over. We just put them into separate buffers to make
1839           * binding as well as the later patching of input attachments easy.
1840           */
1841          unsigned src_idx = j + set->layout->input_attachment_count;
1842          unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
1843          assert(dyn_idx < dynamicOffsetCount);
1844
1845          uint32_t *dst =
1846             &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
1847          uint32_t *src =
1848             &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
1849          uint32_t offset = pDynamicOffsets[dyn_idx];
1850
1851          /* Patch the storage/uniform descriptors right away. */
1852          if (layout->set[idx].layout->dynamic_ubo & (1 << j)) {
1853             /* Note: we can assume here that the addition won't roll over and
1854              * change the SIZE field.
1855              */
1856             uint64_t va = src[0] | ((uint64_t)src[1] << 32);
1857             va += offset;
1858             dst[0] = va;
1859             dst[1] = va >> 32;
1860          } else {
1861             memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
1862             /* Note: A6XX_IBO_5_DEPTH is always 0 */
1863             uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
1864             va += offset;
1865             dst[4] = va;
1866             dst[5] = va >> 32;
1867          }
1868       }
1869    }
1870
1871    if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE)
1872       cmd_buffer->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
1873    else
1874       cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1875 }
1876
1877 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
1878                                            uint32_t firstBinding,
1879                                            uint32_t bindingCount,
1880                                            const VkBuffer *pBuffers,
1881                                            const VkDeviceSize *pOffsets,
1882                                            const VkDeviceSize *pSizes)
1883 {
1884    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1885    assert(firstBinding + bindingCount <= IR3_MAX_SO_BUFFERS);
1886
1887    for (uint32_t i = 0; i < bindingCount; i++) {
1888       uint32_t idx = firstBinding + i;
1889       TU_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
1890
1891       if (pOffsets[i] != 0)
1892          cmd->state.streamout_reset |= 1 << idx;
1893
1894       cmd->state.streamout_buf.buffers[idx] = buf;
1895       cmd->state.streamout_buf.offsets[idx] = pOffsets[i];
1896       cmd->state.streamout_buf.sizes[idx] = pSizes[i];
1897
1898       cmd->state.streamout_enabled |= 1 << idx;
1899    }
1900
1901    cmd->state.dirty |= TU_CMD_DIRTY_STREAMOUT_BUFFERS;
1902 }
1903
1904 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1905                                        uint32_t firstCounterBuffer,
1906                                        uint32_t counterBufferCount,
1907                                        const VkBuffer *pCounterBuffers,
1908                                        const VkDeviceSize *pCounterBufferOffsets)
1909 {
1910    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1911    /* TODO do something with counter buffer? */
1912 }
1913
1914 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1915                                        uint32_t firstCounterBuffer,
1916                                        uint32_t counterBufferCount,
1917                                        const VkBuffer *pCounterBuffers,
1918                                        const VkDeviceSize *pCounterBufferOffsets)
1919 {
1920    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1921    /* TODO do something with counter buffer? */
1922
1923    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1924    cmd->state.streamout_enabled = 0;
1925 }
1926
1927 void
1928 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1929                     VkPipelineLayout layout,
1930                     VkShaderStageFlags stageFlags,
1931                     uint32_t offset,
1932                     uint32_t size,
1933                     const void *pValues)
1934 {
1935    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1936    memcpy((void*) cmd->push_constants + offset, pValues, size);
1937    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1938 }
1939
1940 VkResult
1941 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1942 {
1943    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1944
1945    if (cmd_buffer->scratch_seqno) {
1946       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1947                      MSM_SUBMIT_BO_WRITE);
1948    }
1949
1950    if (cmd_buffer->use_vsc_data) {
1951       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_draw_strm,
1952                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1953       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_prim_strm,
1954                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1955    }
1956
1957    tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->device->border_color,
1958                   MSM_SUBMIT_BO_READ);
1959
1960    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1961       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1962                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1963    }
1964
1965    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
1966       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
1967                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1968    }
1969
1970    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
1971       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
1972                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1973    }
1974
1975    tu_cs_end(&cmd_buffer->cs);
1976    tu_cs_end(&cmd_buffer->draw_cs);
1977    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
1978
1979    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1980
1981    return cmd_buffer->record_result;
1982 }
1983
1984 void
1985 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1986                    VkPipelineBindPoint pipelineBindPoint,
1987                    VkPipeline _pipeline)
1988 {
1989    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1990    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1991
1992    switch (pipelineBindPoint) {
1993    case VK_PIPELINE_BIND_POINT_GRAPHICS:
1994       cmd->state.pipeline = pipeline;
1995       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1996       break;
1997    case VK_PIPELINE_BIND_POINT_COMPUTE:
1998       cmd->state.compute_pipeline = pipeline;
1999       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2000       break;
2001    default:
2002       unreachable("unrecognized pipeline bind point");
2003       break;
2004    }
2005
2006    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2007                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2008    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2009       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2010                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2011    }
2012 }
2013
2014 void
2015 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2016                   uint32_t firstViewport,
2017                   uint32_t viewportCount,
2018                   const VkViewport *pViewports)
2019 {
2020    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2021
2022    assert(firstViewport == 0 && viewportCount == 1);
2023    cmd->state.dynamic.viewport.viewports[0] = pViewports[0];
2024    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_VIEWPORT;
2025 }
2026
2027 void
2028 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2029                  uint32_t firstScissor,
2030                  uint32_t scissorCount,
2031                  const VkRect2D *pScissors)
2032 {
2033    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2034
2035    assert(firstScissor == 0 && scissorCount == 1);
2036    cmd->state.dynamic.scissor.scissors[0] = pScissors[0];
2037    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_SCISSOR;
2038 }
2039
2040 void
2041 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2042 {
2043    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2044
2045    cmd->state.dynamic.line_width = lineWidth;
2046
2047    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2048    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2049 }
2050
2051 void
2052 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2053                    float depthBiasConstantFactor,
2054                    float depthBiasClamp,
2055                    float depthBiasSlopeFactor)
2056 {
2057    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2058    struct tu_cs *draw_cs = &cmd->draw_cs;
2059
2060    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2061                        depthBiasSlopeFactor);
2062
2063    tu_cs_sanity_check(draw_cs);
2064 }
2065
2066 void
2067 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2068                         const float blendConstants[4])
2069 {
2070    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2071    struct tu_cs *draw_cs = &cmd->draw_cs;
2072
2073    tu6_emit_blend_constants(draw_cs, blendConstants);
2074
2075    tu_cs_sanity_check(draw_cs);
2076 }
2077
2078 void
2079 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2080                      float minDepthBounds,
2081                      float maxDepthBounds)
2082 {
2083 }
2084
2085 void
2086 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2087                             VkStencilFaceFlags faceMask,
2088                             uint32_t compareMask)
2089 {
2090    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2091
2092    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2093       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2094    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2095       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2096
2097    /* the front/back compare masks must be updated together */
2098    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2099 }
2100
2101 void
2102 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2103                           VkStencilFaceFlags faceMask,
2104                           uint32_t writeMask)
2105 {
2106    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2107
2108    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2109       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2110    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2111       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2112
2113    /* the front/back write masks must be updated together */
2114    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2115 }
2116
2117 void
2118 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2119                           VkStencilFaceFlags faceMask,
2120                           uint32_t reference)
2121 {
2122    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2123
2124    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2125       cmd->state.dynamic.stencil_reference.front = reference;
2126    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2127       cmd->state.dynamic.stencil_reference.back = reference;
2128
2129    /* the front/back references must be updated together */
2130    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2131 }
2132
2133 void
2134 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer,
2135                             const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
2136 {
2137    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2138
2139    tu6_emit_sample_locations(&cmd->draw_cs, pSampleLocationsInfo);
2140 }
2141
2142 void
2143 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2144                       uint32_t commandBufferCount,
2145                       const VkCommandBuffer *pCmdBuffers)
2146 {
2147    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2148    VkResult result;
2149
2150    assert(commandBufferCount > 0);
2151
2152    for (uint32_t i = 0; i < commandBufferCount; i++) {
2153       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2154
2155       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2156       if (result != VK_SUCCESS) {
2157          cmd->record_result = result;
2158          break;
2159       }
2160
2161       if (secondary->usage_flags &
2162           VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2163          assert(tu_cs_is_empty(&secondary->cs));
2164
2165          result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2166          if (result != VK_SUCCESS) {
2167             cmd->record_result = result;
2168             break;
2169          }
2170
2171          result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2172                &secondary->draw_epilogue_cs);
2173          if (result != VK_SUCCESS) {
2174             cmd->record_result = result;
2175             break;
2176          }
2177       } else {
2178          assert(tu_cs_is_empty(&secondary->draw_cs));
2179          assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
2180
2181          for (uint32_t j = 0; j < secondary->cs.bo_count; j++) {
2182             tu_bo_list_add(&cmd->bo_list, secondary->cs.bos[j],
2183                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2184          }
2185
2186          tu_cs_add_entries(&cmd->cs, &secondary->cs);
2187       }
2188    }
2189    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2190 }
2191
2192 VkResult
2193 tu_CreateCommandPool(VkDevice _device,
2194                      const VkCommandPoolCreateInfo *pCreateInfo,
2195                      const VkAllocationCallbacks *pAllocator,
2196                      VkCommandPool *pCmdPool)
2197 {
2198    TU_FROM_HANDLE(tu_device, device, _device);
2199    struct tu_cmd_pool *pool;
2200
2201    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2202                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2203    if (pool == NULL)
2204       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2205
2206    if (pAllocator)
2207       pool->alloc = *pAllocator;
2208    else
2209       pool->alloc = device->alloc;
2210
2211    list_inithead(&pool->cmd_buffers);
2212    list_inithead(&pool->free_cmd_buffers);
2213
2214    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2215
2216    *pCmdPool = tu_cmd_pool_to_handle(pool);
2217
2218    return VK_SUCCESS;
2219 }
2220
2221 void
2222 tu_DestroyCommandPool(VkDevice _device,
2223                       VkCommandPool commandPool,
2224                       const VkAllocationCallbacks *pAllocator)
2225 {
2226    TU_FROM_HANDLE(tu_device, device, _device);
2227    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2228
2229    if (!pool)
2230       return;
2231
2232    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2233                             &pool->cmd_buffers, pool_link)
2234    {
2235       tu_cmd_buffer_destroy(cmd_buffer);
2236    }
2237
2238    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2239                             &pool->free_cmd_buffers, pool_link)
2240    {
2241       tu_cmd_buffer_destroy(cmd_buffer);
2242    }
2243
2244    vk_free2(&device->alloc, pAllocator, pool);
2245 }
2246
2247 VkResult
2248 tu_ResetCommandPool(VkDevice device,
2249                     VkCommandPool commandPool,
2250                     VkCommandPoolResetFlags flags)
2251 {
2252    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2253    VkResult result;
2254
2255    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2256                        pool_link)
2257    {
2258       result = tu_reset_cmd_buffer(cmd_buffer);
2259       if (result != VK_SUCCESS)
2260          return result;
2261    }
2262
2263    return VK_SUCCESS;
2264 }
2265
2266 void
2267 tu_TrimCommandPool(VkDevice device,
2268                    VkCommandPool commandPool,
2269                    VkCommandPoolTrimFlags flags)
2270 {
2271    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2272
2273    if (!pool)
2274       return;
2275
2276    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2277                             &pool->free_cmd_buffers, pool_link)
2278    {
2279       tu_cmd_buffer_destroy(cmd_buffer);
2280    }
2281 }
2282
2283 void
2284 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2285                       const VkRenderPassBeginInfo *pRenderPassBegin,
2286                       VkSubpassContents contents)
2287 {
2288    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2289    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2290    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2291
2292    cmd->state.pass = pass;
2293    cmd->state.subpass = pass->subpasses;
2294    cmd->state.framebuffer = fb;
2295
2296    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2297    tu_cmd_prepare_tile_store_ib(cmd);
2298
2299    tu_emit_load_clear(cmd, pRenderPassBegin);
2300
2301    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2302    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2303    tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples);
2304    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2305
2306    /* note: use_hw_binning only checks tiling config */
2307    if (use_hw_binning(cmd))
2308       cmd->use_vsc_data = true;
2309
2310    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2311       const struct tu_image_view *iview = fb->attachments[i].attachment;
2312       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2313                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2314    }
2315
2316    /* Flag input attachment descriptors for re-emission if necessary */
2317    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2318 }
2319
2320 void
2321 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2322                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2323                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2324 {
2325    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2326                          pSubpassBeginInfo->contents);
2327 }
2328
2329 void
2330 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2331 {
2332    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2333    const struct tu_render_pass *pass = cmd->state.pass;
2334    struct tu_cs *cs = &cmd->draw_cs;
2335
2336    const struct tu_subpass *subpass = cmd->state.subpass++;
2337
2338    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
2339
2340    if (subpass->resolve_attachments) {
2341       tu6_emit_blit_scissor(cmd, cs, true);
2342
2343       for (unsigned i = 0; i < subpass->color_count; i++) {
2344          uint32_t a = subpass->resolve_attachments[i].attachment;
2345          if (a == VK_ATTACHMENT_UNUSED)
2346             continue;
2347
2348          tu_store_gmem_attachment(cmd, cs, a,
2349                                   subpass->color_attachments[i].attachment);
2350
2351          if (pass->attachments[a].gmem_offset < 0)
2352             continue;
2353
2354          /* TODO:
2355           * check if the resolved attachment is needed by later subpasses,
2356           * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2357           */
2358          tu_finishme("missing GMEM->GMEM resolve path\n");
2359          tu_load_gmem_attachment(cmd, cs, a, true);
2360       }
2361    }
2362
2363    tu_cond_exec_end(cs);
2364
2365    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
2366
2367    /* Emit flushes so that input attachments will read the correct value.
2368     * TODO: use subpass dependencies to flush or not
2369     */
2370    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2371    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2372
2373    if (subpass->resolve_attachments) {
2374       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2375
2376       for (unsigned i = 0; i < subpass->color_count; i++) {
2377          uint32_t a = subpass->resolve_attachments[i].attachment;
2378          if (a == VK_ATTACHMENT_UNUSED)
2379             continue;
2380
2381          tu6_emit_sysmem_resolve(cmd, cs, a,
2382                                  subpass->color_attachments[i].attachment);
2383       }
2384
2385       tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2386    }
2387
2388    tu_cond_exec_end(cs);
2389
2390    /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2391    if (cmd->state.subpass->input_count)
2392       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2393
2394    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2395    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2396    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2397    tu6_emit_msaa(cs, cmd->state.subpass->samples);
2398    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2399
2400    /* Flag input attachment descriptors for re-emission if necessary */
2401    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2402 }
2403
2404 void
2405 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2406                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2407                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2408 {
2409    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2410 }
2411
2412 struct tu_draw_info
2413 {
2414    /**
2415     * Number of vertices.
2416     */
2417    uint32_t count;
2418
2419    /**
2420     * Index of the first vertex.
2421     */
2422    int32_t vertex_offset;
2423
2424    /**
2425     * First instance id.
2426     */
2427    uint32_t first_instance;
2428
2429    /**
2430     * Number of instances.
2431     */
2432    uint32_t instance_count;
2433
2434    /**
2435     * First index (indexed draws only).
2436     */
2437    uint32_t first_index;
2438
2439    /**
2440     * Whether it's an indexed draw.
2441     */
2442    bool indexed;
2443
2444    /**
2445     * Indirect draw parameters resource.
2446     */
2447    struct tu_buffer *indirect;
2448    uint64_t indirect_offset;
2449    uint32_t stride;
2450
2451    /**
2452     * Draw count parameters resource.
2453     */
2454    struct tu_buffer *count_buffer;
2455    uint64_t count_buffer_offset;
2456
2457    /**
2458     * Stream output parameters resource.
2459     */
2460    struct tu_buffer *streamout_buffer;
2461    uint64_t streamout_buffer_offset;
2462 };
2463
2464 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2465 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2466 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2467
2468 enum tu_draw_state_group_id
2469 {
2470    TU_DRAW_STATE_PROGRAM,
2471    TU_DRAW_STATE_PROGRAM_BINNING,
2472    TU_DRAW_STATE_VI,
2473    TU_DRAW_STATE_VI_BINNING,
2474    TU_DRAW_STATE_VP,
2475    TU_DRAW_STATE_RAST,
2476    TU_DRAW_STATE_DS,
2477    TU_DRAW_STATE_BLEND,
2478    TU_DRAW_STATE_VS_CONST,
2479    TU_DRAW_STATE_GS_CONST,
2480    TU_DRAW_STATE_FS_CONST,
2481    TU_DRAW_STATE_DESC_SETS,
2482    TU_DRAW_STATE_DESC_SETS_GMEM,
2483    TU_DRAW_STATE_DESC_SETS_LOAD,
2484    TU_DRAW_STATE_VS_PARAMS,
2485
2486    TU_DRAW_STATE_COUNT,
2487 };
2488
2489 struct tu_draw_state_group
2490 {
2491    enum tu_draw_state_group_id id;
2492    uint32_t enable_mask;
2493    struct tu_cs_entry ib;
2494 };
2495
2496 static inline uint32_t
2497 tu6_stage2opcode(gl_shader_stage type)
2498 {
2499    switch (type) {
2500    case MESA_SHADER_VERTEX:
2501    case MESA_SHADER_TESS_CTRL:
2502    case MESA_SHADER_TESS_EVAL:
2503    case MESA_SHADER_GEOMETRY:
2504       return CP_LOAD_STATE6_GEOM;
2505    case MESA_SHADER_FRAGMENT:
2506    case MESA_SHADER_COMPUTE:
2507    case MESA_SHADER_KERNEL:
2508       return CP_LOAD_STATE6_FRAG;
2509    default:
2510       unreachable("bad shader type");
2511    }
2512 }
2513
2514 static inline enum a6xx_state_block
2515 tu6_stage2shadersb(gl_shader_stage type)
2516 {
2517    switch (type) {
2518    case MESA_SHADER_VERTEX:
2519       return SB6_VS_SHADER;
2520    case MESA_SHADER_GEOMETRY:
2521       return SB6_GS_SHADER;
2522    case MESA_SHADER_FRAGMENT:
2523       return SB6_FS_SHADER;
2524    case MESA_SHADER_COMPUTE:
2525    case MESA_SHADER_KERNEL:
2526       return SB6_CS_SHADER;
2527    default:
2528       unreachable("bad shader type");
2529       return ~0;
2530    }
2531 }
2532
2533 static void
2534 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2535                      struct tu_descriptor_state *descriptors_state,
2536                      gl_shader_stage type,
2537                      uint32_t *push_constants)
2538 {
2539    const struct tu_program_descriptor_linkage *link =
2540       &pipeline->program.link[type];
2541    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2542
2543    if (link->push_consts.count > 0) {
2544       unsigned num_units = link->push_consts.count;
2545       unsigned offset = link->push_consts.lo;
2546       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4);
2547       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
2548             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2549             CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2550             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2551             CP_LOAD_STATE6_0_NUM_UNIT(num_units));
2552       tu_cs_emit(cs, 0);
2553       tu_cs_emit(cs, 0);
2554       for (unsigned i = 0; i < num_units * 4; i++)
2555          tu_cs_emit(cs, push_constants[i + offset * 4]);
2556    }
2557
2558    for (uint32_t i = 0; i < state->num_enabled; i++) {
2559       uint32_t size = state->range[i].end - state->range[i].start;
2560       uint32_t offset = state->range[i].start;
2561
2562       /* and even if the start of the const buffer is before
2563        * first_immediate, the end may not be:
2564        */
2565       size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2566
2567       if (size == 0)
2568          continue;
2569
2570       /* things should be aligned to vec4: */
2571       debug_assert((state->range[i].offset % 16) == 0);
2572       debug_assert((size % 16) == 0);
2573       debug_assert((offset % 16) == 0);
2574
2575       /* Dig out the descriptor from the descriptor state and read the VA from
2576        * it.
2577        */
2578       assert(state->range[i].bindless);
2579       uint32_t *base = state->range[i].bindless_base == MAX_SETS ?
2580          descriptors_state->dynamic_descriptors :
2581          descriptors_state->sets[state->range[i].bindless_base]->mapped_ptr;
2582       unsigned block = state->range[i].block;
2583       /* If the block in the shader here is in the dynamic descriptor set, it
2584        * is an index into the dynamic descriptor set which is combined from
2585        * dynamic descriptors and input attachments on-the-fly, and we don't
2586        * have access to it here. Instead we work backwards to get the index
2587        * into dynamic_descriptors.
2588        */
2589       if (state->range[i].bindless_base == MAX_SETS)
2590          block -= pipeline->layout->input_attachment_count;
2591       uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
2592       uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
2593       assert(va);
2594
2595       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2596       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2597             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2598             CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2599             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2600             CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2601       tu_cs_emit_qw(cs, va + offset);
2602    }
2603 }
2604
2605 static struct tu_cs_entry
2606 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2607                 const struct tu_pipeline *pipeline,
2608                 struct tu_descriptor_state *descriptors_state,
2609                 gl_shader_stage type)
2610 {
2611    struct tu_cs cs;
2612    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2613
2614    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2615
2616    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2617 }
2618
2619 static VkResult
2620 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2621                    const struct tu_draw_info *draw,
2622                    struct tu_cs_entry *entry)
2623 {
2624    /* TODO: fill out more than just base instance */
2625    const struct tu_program_descriptor_linkage *link =
2626       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2627    const struct ir3_const_state *const_state = &link->const_state;
2628    struct tu_cs cs;
2629
2630    if (const_state->offsets.driver_param >= link->constlen) {
2631       *entry = (struct tu_cs_entry) {};
2632       return VK_SUCCESS;
2633    }
2634
2635    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
2636    if (result != VK_SUCCESS)
2637       return result;
2638
2639    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2640    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2641          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2642          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2643          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2644          CP_LOAD_STATE6_0_NUM_UNIT(1));
2645    tu_cs_emit(&cs, 0);
2646    tu_cs_emit(&cs, 0);
2647
2648    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2649
2650    tu_cs_emit(&cs, 0);
2651    tu_cs_emit(&cs, 0);
2652    tu_cs_emit(&cs, draw->first_instance);
2653    tu_cs_emit(&cs, 0);
2654
2655    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2656    return VK_SUCCESS;
2657 }
2658
2659 static VkResult
2660 tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
2661                          const struct tu_pipeline *pipeline,
2662                          VkPipelineBindPoint bind_point,
2663                          struct tu_cs_entry *entry,
2664                          bool gmem)
2665 {
2666    struct tu_cs *draw_state = &cmd->sub_cs;
2667    struct tu_pipeline_layout *layout = pipeline->layout;
2668    struct tu_descriptor_state *descriptors_state =
2669       tu_get_descriptors_state(cmd, bind_point);
2670    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2671    const uint32_t *input_attachment_idx =
2672       pipeline->program.input_attachment_idx;
2673    uint32_t num_dynamic_descs = layout->dynamic_offset_count +
2674       layout->input_attachment_count;
2675    struct ts_cs_memory dynamic_desc_set;
2676    VkResult result;
2677
2678    if (num_dynamic_descs > 0) {
2679       /* allocate and fill out dynamic descriptor set */
2680       result = tu_cs_alloc(draw_state, num_dynamic_descs,
2681                            A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
2682       if (result != VK_SUCCESS)
2683          return result;
2684
2685       memcpy(dynamic_desc_set.map, descriptors_state->input_attachments,
2686              layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
2687
2688       if (gmem) {
2689          /* Patch input attachments to refer to GMEM instead */
2690          for (unsigned i = 0; i < layout->input_attachment_count; i++) {
2691             uint32_t *dst =
2692                &dynamic_desc_set.map[A6XX_TEX_CONST_DWORDS * i];
2693
2694             /* The compiler has already laid out input_attachment_idx in the
2695              * final order of input attachments, so there's no need to go
2696              * through the pipeline layout finding input attachments.
2697              */
2698             unsigned attachment_idx = input_attachment_idx[i];
2699
2700             /* It's possible for the pipeline layout to include an input
2701              * attachment which doesn't actually exist for the current
2702              * subpass. Of course, this is only valid so long as the pipeline
2703              * doesn't try to actually load that attachment. Just skip
2704              * patching in that scenario to avoid out-of-bounds accesses.
2705              */
2706             if (attachment_idx >= cmd->state.subpass->input_count)
2707                continue;
2708
2709             uint32_t a = cmd->state.subpass->input_attachments[attachment_idx].attachment;
2710             const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2711
2712             assert(att->gmem_offset >= 0);
2713
2714             dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2715             dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2716             dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2717             dst[2] |=
2718                A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2719                A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2720             dst[3] = 0;
2721             dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
2722             dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2723             for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2724                dst[i] = 0;
2725
2726             if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2727                tu_finishme("patch input attachment pitch for secondary cmd buffer");
2728          }
2729       }
2730
2731       memcpy(dynamic_desc_set.map + layout->input_attachment_count * A6XX_TEX_CONST_DWORDS,
2732              descriptors_state->dynamic_descriptors,
2733              layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
2734    }
2735
2736    uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
2737    uint32_t hlsq_update_value;
2738    switch (bind_point) {
2739    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2740       sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
2741       hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
2742       hlsq_update_value = 0x7c000;
2743       break;
2744    case VK_PIPELINE_BIND_POINT_COMPUTE:
2745       sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
2746       hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2747       hlsq_update_value = 0x3e00;
2748       break;
2749    default:
2750       unreachable("bad bind point");
2751    }
2752
2753    /* Be careful here to *not* refer to the pipeline, so that if only the
2754     * pipeline changes we don't have to emit this again (except if there are
2755     * dynamic descriptors in the pipeline layout). This means always emitting
2756     * all the valid descriptors, which means that we always have to put the
2757     * dynamic descriptor in the driver-only slot at the end
2758     */
2759    uint32_t num_user_sets = util_last_bit(descriptors_state->valid);
2760    uint32_t num_sets = num_user_sets;
2761    if (num_dynamic_descs > 0) {
2762       num_user_sets = MAX_SETS;
2763       num_sets = num_user_sets + 1;
2764    }
2765
2766    unsigned regs[2] = { sp_bindless_base_reg, hlsq_bindless_base_reg };
2767
2768    struct tu_cs cs;
2769    result = tu_cs_begin_sub_stream(draw_state, ARRAY_SIZE(regs) * (1 + num_sets * 2) + 2, &cs);
2770    if (result != VK_SUCCESS)
2771       return result;
2772
2773    if (num_sets > 0) {
2774       for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) {
2775          tu_cs_emit_pkt4(&cs, regs[i], num_sets * 2);
2776          for (unsigned j = 0; j < num_user_sets; j++) {
2777             if (descriptors_state->valid & (1 << j)) {
2778                /* magic | 3 copied from the blob */
2779                tu_cs_emit_qw(&cs, descriptors_state->sets[j]->va | 3);
2780             } else {
2781                tu_cs_emit_qw(&cs, 0 | 3);
2782             }
2783          }
2784          if (num_dynamic_descs > 0) {
2785             tu_cs_emit_qw(&cs, dynamic_desc_set.iova | 3);
2786          }
2787       }
2788
2789       tu_cs_emit_regs(&cs, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value));
2790    }
2791
2792    *entry = tu_cs_end_sub_stream(draw_state, &cs);
2793    return VK_SUCCESS;
2794 }
2795
2796 static void
2797 tu6_emit_streamout(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
2798 {
2799    struct tu_streamout_state *tf = &cmd->state.pipeline->streamout;
2800
2801    for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2802       struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
2803       if (!buf)
2804          continue;
2805
2806       uint32_t offset;
2807       offset = cmd->state.streamout_buf.offsets[i];
2808
2809       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_BASE(i, .bo = buf->bo,
2810                                                      .bo_offset = buf->bo_offset));
2811       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_SIZE(i, buf->size));
2812
2813       if (cmd->state.streamout_reset & (1 << i)) {
2814          tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, offset));
2815          cmd->state.streamout_reset &= ~(1  << i);
2816       } else {
2817          tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2818          tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
2819                         CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
2820                         CP_MEM_TO_REG_0_CNT(0));
2821          tu_cs_emit_qw(cs, cmd->scratch_bo.iova +
2822                            ctrl_offset(flush_base[i].offset));
2823       }
2824
2825       tu_cs_emit_regs(cs, A6XX_VPC_SO_FLUSH_BASE(i, .bo = &cmd->scratch_bo,
2826                                                     .bo_offset =
2827                                                        ctrl_offset(flush_base[i])));
2828    }
2829
2830    if (cmd->state.streamout_enabled) {
2831       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
2832       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2833       tu_cs_emit(cs, tf->vpc_so_buf_cntl);
2834       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(0));
2835       tu_cs_emit(cs, tf->ncomp[0]);
2836       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(1));
2837       tu_cs_emit(cs, tf->ncomp[1]);
2838       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(2));
2839       tu_cs_emit(cs, tf->ncomp[2]);
2840       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(3));
2841       tu_cs_emit(cs, tf->ncomp[3]);
2842       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2843       tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
2844       for (unsigned i = 0; i < tf->prog_count; i++) {
2845          tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
2846          tu_cs_emit(cs, tf->prog[i]);
2847       }
2848    } else {
2849       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
2850       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2851       tu_cs_emit(cs, 0);
2852       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2853       tu_cs_emit(cs, 0);
2854    }
2855 }
2856
2857 static VkResult
2858 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2859                      struct tu_cs *cs,
2860                      const struct tu_draw_info *draw)
2861 {
2862    const struct tu_pipeline *pipeline = cmd->state.pipeline;
2863    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2864    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2865    uint32_t draw_state_group_count = 0;
2866    VkResult result;
2867
2868    struct tu_descriptor_state *descriptors_state =
2869       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2870
2871    /* TODO lrz */
2872
2873    tu_cs_emit_regs(cs,
2874                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
2875                                             pipeline->ia.primitive_restart && draw->indexed));
2876
2877    if (cmd->state.dirty &
2878           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2879        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2880       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2881                             dynamic->line_width);
2882    }
2883
2884    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2885        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2886       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2887                                     dynamic->stencil_compare_mask.back);
2888    }
2889
2890    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2891        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2892       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2893                                   dynamic->stencil_write_mask.back);
2894    }
2895
2896    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2897        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2898       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2899                                  dynamic->stencil_reference.back);
2900    }
2901
2902    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2903        (pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2904       tu6_emit_viewport(cs, &cmd->state.dynamic.viewport.viewports[0]);
2905    }
2906
2907    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_SCISSOR) &&
2908        (pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2909       tu6_emit_scissor(cs, &cmd->state.dynamic.scissor.scissors[0]);
2910    }
2911
2912    if (cmd->state.dirty &
2913        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2914       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2915          const uint32_t binding = pipeline->vi.bindings[i];
2916          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2917          const VkDeviceSize offset = buf->bo_offset +
2918                                      cmd->state.vb.offsets[binding];
2919          const VkDeviceSize size =
2920             offset < buf->size ? buf->size - offset : 0;
2921
2922          tu_cs_emit_regs(cs,
2923                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
2924                          A6XX_VFD_FETCH_SIZE(i, size));
2925       }
2926    }
2927
2928    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2929       draw_state_groups[draw_state_group_count++] =
2930          (struct tu_draw_state_group) {
2931             .id = TU_DRAW_STATE_PROGRAM,
2932             .enable_mask = ENABLE_DRAW,
2933             .ib = pipeline->program.state_ib,
2934          };
2935       draw_state_groups[draw_state_group_count++] =
2936          (struct tu_draw_state_group) {
2937             .id = TU_DRAW_STATE_PROGRAM_BINNING,
2938             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2939             .ib = pipeline->program.binning_state_ib,
2940          };
2941       draw_state_groups[draw_state_group_count++] =
2942          (struct tu_draw_state_group) {
2943             .id = TU_DRAW_STATE_VI,
2944             .enable_mask = ENABLE_DRAW,
2945             .ib = pipeline->vi.state_ib,
2946          };
2947       draw_state_groups[draw_state_group_count++] =
2948          (struct tu_draw_state_group) {
2949             .id = TU_DRAW_STATE_VI_BINNING,
2950             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2951             .ib = pipeline->vi.binning_state_ib,
2952          };
2953       draw_state_groups[draw_state_group_count++] =
2954          (struct tu_draw_state_group) {
2955             .id = TU_DRAW_STATE_VP,
2956             .enable_mask = ENABLE_ALL,
2957             .ib = pipeline->vp.state_ib,
2958          };
2959       draw_state_groups[draw_state_group_count++] =
2960          (struct tu_draw_state_group) {
2961             .id = TU_DRAW_STATE_RAST,
2962             .enable_mask = ENABLE_ALL,
2963             .ib = pipeline->rast.state_ib,
2964          };
2965       draw_state_groups[draw_state_group_count++] =
2966          (struct tu_draw_state_group) {
2967             .id = TU_DRAW_STATE_DS,
2968             .enable_mask = ENABLE_ALL,
2969             .ib = pipeline->ds.state_ib,
2970          };
2971       draw_state_groups[draw_state_group_count++] =
2972          (struct tu_draw_state_group) {
2973             .id = TU_DRAW_STATE_BLEND,
2974             .enable_mask = ENABLE_ALL,
2975             .ib = pipeline->blend.state_ib,
2976          };
2977    }
2978
2979    if (cmd->state.dirty &
2980          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
2981       draw_state_groups[draw_state_group_count++] =
2982          (struct tu_draw_state_group) {
2983             .id = TU_DRAW_STATE_VS_CONST,
2984             .enable_mask = ENABLE_ALL,
2985             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2986          };
2987       draw_state_groups[draw_state_group_count++] =
2988          (struct tu_draw_state_group) {
2989             .id = TU_DRAW_STATE_GS_CONST,
2990             .enable_mask = ENABLE_ALL,
2991             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_GEOMETRY)
2992          };
2993       draw_state_groups[draw_state_group_count++] =
2994          (struct tu_draw_state_group) {
2995             .id = TU_DRAW_STATE_FS_CONST,
2996             .enable_mask = ENABLE_DRAW,
2997             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2998          };
2999    }
3000
3001    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS)
3002       tu6_emit_streamout(cmd, cs);
3003
3004    /* If there are any any dynamic descriptors, then we may need to re-emit
3005     * them after every pipeline change in case the number of input attachments
3006     * changes. We also always need to re-emit after a pipeline change if there
3007     * are any input attachments, because the input attachment index comes from
3008     * the pipeline. Finally, it can also happen that the subpass changes
3009     * without the pipeline changing, in which case the GMEM descriptors need
3010     * to be patched differently.
3011     *
3012     * TODO: We could probably be clever and avoid re-emitting state on
3013     * pipeline changes if the number of input attachments is always 0. We
3014     * could also only re-emit dynamic state.
3015     */
3016    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS ||
3017        ((pipeline->layout->dynamic_offset_count +
3018          pipeline->layout->input_attachment_count > 0) &&
3019         cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) ||
3020        (pipeline->layout->input_attachment_count > 0 &&
3021         cmd->state.dirty & TU_CMD_DIRTY_INPUT_ATTACHMENTS)) {
3022       struct tu_cs_entry desc_sets, desc_sets_gmem;
3023       bool need_gmem_desc_set = pipeline->layout->input_attachment_count > 0;
3024
3025       result = tu6_emit_descriptor_sets(cmd, pipeline,
3026                                         VK_PIPELINE_BIND_POINT_GRAPHICS,
3027                                         &desc_sets, false);
3028       if (result != VK_SUCCESS)
3029          return result;
3030
3031       draw_state_groups[draw_state_group_count++] =
3032          (struct tu_draw_state_group) {
3033             .id = TU_DRAW_STATE_DESC_SETS,
3034             .enable_mask = need_gmem_desc_set ? ENABLE_NON_GMEM : ENABLE_ALL,
3035             .ib = desc_sets,
3036          };
3037
3038       if (need_gmem_desc_set) {
3039          result = tu6_emit_descriptor_sets(cmd, pipeline,
3040                                            VK_PIPELINE_BIND_POINT_GRAPHICS,
3041                                            &desc_sets_gmem, true);
3042          if (result != VK_SUCCESS)
3043             return result;
3044
3045          draw_state_groups[draw_state_group_count++] =
3046             (struct tu_draw_state_group) {
3047                .id = TU_DRAW_STATE_DESC_SETS_GMEM,
3048                .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3049                .ib = desc_sets_gmem,
3050             };
3051       }
3052
3053       /* We need to reload the descriptors every time the descriptor sets
3054        * change. However, the commands we send only depend on the pipeline
3055        * because the whole point is to cache descriptors which are used by the
3056        * pipeline. There's a problem here, in that the firmware has an
3057        * "optimization" which skips executing groups that are set to the same
3058        * value as the last draw. This means that if the descriptor sets change
3059        * but not the pipeline, we'd try to re-execute the same buffer which
3060        * the firmware would ignore and we wouldn't pre-load the new
3061        * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3062        * the descriptor sets change, which we emulate here by copying the
3063        * pre-prepared buffer.
3064        */
3065       const struct tu_cs_entry *load_entry = &pipeline->load_state.state_ib;
3066       if (load_entry->size > 0) {
3067          struct tu_cs load_cs;
3068          result = tu_cs_begin_sub_stream(&cmd->sub_cs, load_entry->size, &load_cs);
3069          if (result != VK_SUCCESS)
3070             return result;
3071          tu_cs_emit_array(&load_cs,
3072                           (uint32_t *)((char  *)load_entry->bo->map + load_entry->offset),
3073                           load_entry->size / 4);
3074          struct tu_cs_entry load_copy = tu_cs_end_sub_stream(&cmd->sub_cs, &load_cs);
3075
3076          draw_state_groups[draw_state_group_count++] =
3077             (struct tu_draw_state_group) {
3078                .id = TU_DRAW_STATE_DESC_SETS_LOAD,
3079                /* The blob seems to not enable this for binning, even when
3080                 * resources would actually be used in the binning shader.
3081                 * Presumably the overhead of prefetching the resources isn't
3082                 * worth it.
3083                 */
3084                .enable_mask = ENABLE_DRAW,
3085                .ib = load_copy,
3086             };
3087       }
3088    }
3089
3090    struct tu_cs_entry vs_params;
3091    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3092    if (result != VK_SUCCESS)
3093       return result;
3094
3095    draw_state_groups[draw_state_group_count++] =
3096       (struct tu_draw_state_group) {
3097          .id = TU_DRAW_STATE_VS_PARAMS,
3098          .enable_mask = ENABLE_ALL,
3099          .ib = vs_params,
3100       };
3101
3102    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3103    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3104       const struct tu_draw_state_group *group = &draw_state_groups[i];
3105       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3106       uint32_t cp_set_draw_state =
3107          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3108          group->enable_mask |
3109          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3110       uint64_t iova;
3111       if (group->ib.size) {
3112          iova = group->ib.bo->iova + group->ib.offset;
3113       } else {
3114          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3115          iova = 0;
3116       }
3117
3118       tu_cs_emit(cs, cp_set_draw_state);
3119       tu_cs_emit_qw(cs, iova);
3120    }
3121
3122    tu_cs_sanity_check(cs);
3123
3124    /* track BOs */
3125    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3126       for (uint32_t i = 0; i < MAX_VBS; i++) {
3127          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3128          if (buf)
3129             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3130       }
3131    }
3132    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3133       unsigned i;
3134       for_each_bit(i, descriptors_state->valid) {
3135          struct tu_descriptor_set *set = descriptors_state->sets[i];
3136          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3137             if (set->buffers[j]) {
3138                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3139                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3140             }
3141          }
3142          if (set->size > 0) {
3143             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3144                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3145          }
3146       }
3147    }
3148    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS) {
3149       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3150          const struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
3151          if (buf) {
3152             tu_bo_list_add(&cmd->bo_list, buf->bo,
3153                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3154          }
3155       }
3156    }
3157
3158    /* There are too many graphics dirty bits to list here, so just list the
3159     * bits to preserve instead. The only things not emitted here are
3160     * compute-related state.
3161     */
3162    cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
3163
3164    /* Fragment shader state overwrites compute shader state, so flag the
3165     * compute pipeline for re-emit.
3166     */
3167    cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
3168    return VK_SUCCESS;
3169 }
3170
3171 static void
3172 tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
3173                      struct tu_cs *cs,
3174                      const struct tu_draw_info *draw)
3175 {
3176    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3177    bool has_gs = cmd->state.pipeline->active_stages &
3178                  VK_SHADER_STAGE_GEOMETRY_BIT;
3179
3180    tu_cs_emit_regs(cs,
3181                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3182                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3183
3184    if (draw->indexed) {
3185       const enum a4xx_index_size index_size =
3186          tu6_index_size(cmd->state.index_type);
3187       const uint32_t index_bytes =
3188          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3189       const struct tu_buffer *index_buf = cmd->state.index_buffer;
3190       unsigned max_indicies =
3191          (index_buf->size - cmd->state.index_offset) / index_bytes;
3192
3193       const uint32_t cp_draw_indx =
3194          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3195          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3196          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3197          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3198          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3199
3200       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
3201       tu_cs_emit(cs, cp_draw_indx);
3202       tu_cs_emit_qw(cs, index_buf->bo->iova + cmd->state.index_offset);
3203       tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
3204       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3205    } else {
3206       const uint32_t cp_draw_indx =
3207          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3208          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3209          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3210          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3211
3212       tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
3213       tu_cs_emit(cs, cp_draw_indx);
3214       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3215    }
3216
3217    tu_bo_list_add(&cmd->bo_list, draw->indirect->bo, MSM_SUBMIT_BO_READ);
3218 }
3219
3220 static void
3221 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3222                      struct tu_cs *cs,
3223                      const struct tu_draw_info *draw)
3224 {
3225
3226    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3227    bool has_gs = cmd->state.pipeline->active_stages &
3228                  VK_SHADER_STAGE_GEOMETRY_BIT;
3229
3230    tu_cs_emit_regs(cs,
3231                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3232                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3233
3234    /* TODO hw binning */
3235    if (draw->indexed) {
3236       const enum a4xx_index_size index_size =
3237          tu6_index_size(cmd->state.index_type);
3238       const uint32_t index_bytes =
3239          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3240       const struct tu_buffer *buf = cmd->state.index_buffer;
3241       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3242                                   index_bytes * draw->first_index;
3243       const uint32_t size = index_bytes * draw->count;
3244
3245       const uint32_t cp_draw_indx =
3246          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3247          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3248          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3249          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3250          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3251
3252       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3253       tu_cs_emit(cs, cp_draw_indx);
3254       tu_cs_emit(cs, draw->instance_count);
3255       tu_cs_emit(cs, draw->count);
3256       tu_cs_emit(cs, 0x0); /* XXX */
3257       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3258       tu_cs_emit(cs, size);
3259    } else {
3260       const uint32_t cp_draw_indx =
3261          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3262          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3263          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3264          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3265
3266       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3267       tu_cs_emit(cs, cp_draw_indx);
3268       tu_cs_emit(cs, draw->instance_count);
3269       tu_cs_emit(cs, draw->count);
3270    }
3271 }
3272
3273 static void
3274 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3275 {
3276    struct tu_cs *cs = &cmd->draw_cs;
3277    VkResult result;
3278
3279    result = tu6_bind_draw_states(cmd, cs, draw);
3280    if (result != VK_SUCCESS) {
3281       cmd->record_result = result;
3282       return;
3283    }
3284
3285    if (draw->indirect)
3286       tu6_emit_draw_indirect(cmd, cs, draw);
3287    else
3288       tu6_emit_draw_direct(cmd, cs, draw);
3289
3290    if (cmd->state.streamout_enabled) {
3291       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3292          if (cmd->state.streamout_enabled & (1 << i))
3293             tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i, false);
3294       }
3295    }
3296
3297    cmd->wait_for_idle = true;
3298
3299    tu_cs_sanity_check(cs);
3300 }
3301
3302 void
3303 tu_CmdDraw(VkCommandBuffer commandBuffer,
3304            uint32_t vertexCount,
3305            uint32_t instanceCount,
3306            uint32_t firstVertex,
3307            uint32_t firstInstance)
3308 {
3309    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3310    struct tu_draw_info info = {};
3311
3312    info.count = vertexCount;
3313    info.instance_count = instanceCount;
3314    info.first_instance = firstInstance;
3315    info.vertex_offset = firstVertex;
3316
3317    tu_draw(cmd_buffer, &info);
3318 }
3319
3320 void
3321 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3322                   uint32_t indexCount,
3323                   uint32_t instanceCount,
3324                   uint32_t firstIndex,
3325                   int32_t vertexOffset,
3326                   uint32_t firstInstance)
3327 {
3328    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3329    struct tu_draw_info info = {};
3330
3331    info.indexed = true;
3332    info.count = indexCount;
3333    info.instance_count = instanceCount;
3334    info.first_index = firstIndex;
3335    info.vertex_offset = vertexOffset;
3336    info.first_instance = firstInstance;
3337
3338    tu_draw(cmd_buffer, &info);
3339 }
3340
3341 void
3342 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3343                    VkBuffer _buffer,
3344                    VkDeviceSize offset,
3345                    uint32_t drawCount,
3346                    uint32_t stride)
3347 {
3348    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3349    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3350    struct tu_draw_info info = {};
3351
3352    info.count = drawCount;
3353    info.indirect = buffer;
3354    info.indirect_offset = offset;
3355    info.stride = stride;
3356
3357    tu_draw(cmd_buffer, &info);
3358 }
3359
3360 void
3361 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3362                           VkBuffer _buffer,
3363                           VkDeviceSize offset,
3364                           uint32_t drawCount,
3365                           uint32_t stride)
3366 {
3367    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3368    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3369    struct tu_draw_info info = {};
3370
3371    info.indexed = true;
3372    info.count = drawCount;
3373    info.indirect = buffer;
3374    info.indirect_offset = offset;
3375    info.stride = stride;
3376
3377    tu_draw(cmd_buffer, &info);
3378 }
3379
3380 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
3381                                     uint32_t instanceCount,
3382                                     uint32_t firstInstance,
3383                                     VkBuffer _counterBuffer,
3384                                     VkDeviceSize counterBufferOffset,
3385                                     uint32_t counterOffset,
3386                                     uint32_t vertexStride)
3387 {
3388    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3389    TU_FROM_HANDLE(tu_buffer, buffer, _counterBuffer);
3390
3391    struct tu_draw_info info = {};
3392
3393    info.instance_count = instanceCount;
3394    info.first_instance = firstInstance;
3395    info.streamout_buffer = buffer;
3396    info.streamout_buffer_offset = counterBufferOffset;
3397    info.stride = vertexStride;
3398
3399    tu_draw(cmd_buffer, &info);
3400 }
3401
3402 struct tu_dispatch_info
3403 {
3404    /**
3405     * Determine the layout of the grid (in block units) to be used.
3406     */
3407    uint32_t blocks[3];
3408
3409    /**
3410     * A starting offset for the grid. If unaligned is set, the offset
3411     * must still be aligned.
3412     */
3413    uint32_t offsets[3];
3414    /**
3415     * Whether it's an unaligned compute dispatch.
3416     */
3417    bool unaligned;
3418
3419    /**
3420     * Indirect compute parameters resource.
3421     */
3422    struct tu_buffer *indirect;
3423    uint64_t indirect_offset;
3424 };
3425
3426 static void
3427 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3428                               const struct tu_dispatch_info *info)
3429 {
3430    gl_shader_stage type = MESA_SHADER_COMPUTE;
3431    const struct tu_program_descriptor_linkage *link =
3432       &pipeline->program.link[type];
3433    const struct ir3_const_state *const_state = &link->const_state;
3434    uint32_t offset = const_state->offsets.driver_param;
3435
3436    if (link->constlen <= offset)
3437       return;
3438
3439    if (!info->indirect) {
3440       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3441          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3442          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3443          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3444          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3445          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3446          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3447       };
3448
3449       uint32_t num_consts = MIN2(const_state->num_driver_params,
3450                                  (link->constlen - offset) * 4);
3451       /* push constants */
3452       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3453       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3454                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3455                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3456                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3457                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3458       tu_cs_emit(cs, 0);
3459       tu_cs_emit(cs, 0);
3460       uint32_t i;
3461       for (i = 0; i < num_consts; i++)
3462          tu_cs_emit(cs, driver_params[i]);
3463    } else {
3464       tu_finishme("Indirect driver params");
3465    }
3466 }
3467
3468 static void
3469 tu_dispatch(struct tu_cmd_buffer *cmd,
3470             const struct tu_dispatch_info *info)
3471 {
3472    struct tu_cs *cs = &cmd->cs;
3473    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3474    struct tu_descriptor_state *descriptors_state =
3475       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3476    VkResult result;
3477
3478    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3479       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3480
3481    struct tu_cs_entry ib;
3482
3483    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3484    if (ib.size)
3485       tu_cs_emit_ib(cs, &ib);
3486
3487    tu_emit_compute_driver_params(cs, pipeline, info);
3488
3489    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) {
3490       result = tu6_emit_descriptor_sets(cmd, pipeline,
3491                                         VK_PIPELINE_BIND_POINT_COMPUTE, &ib,
3492                                         false);
3493       if (result != VK_SUCCESS) {
3494          cmd->record_result = result;
3495          return;
3496       }
3497
3498       /* track BOs */
3499       unsigned i;
3500       for_each_bit(i, descriptors_state->valid) {
3501          struct tu_descriptor_set *set = descriptors_state->sets[i];
3502          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3503             if (set->buffers[j]) {
3504                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3505                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3506             }
3507          }
3508
3509          if (set->size > 0) {
3510             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3511                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3512          }
3513       }
3514    }
3515
3516    if (ib.size)
3517       tu_cs_emit_ib(cs, &ib);
3518
3519    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS)
3520       tu_cs_emit_ib(cs, &pipeline->load_state.state_ib);
3521
3522    cmd->state.dirty &=
3523       ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
3524
3525    /* Compute shader state overwrites fragment shader state, so we flag the
3526     * graphics pipeline for re-emit.
3527     */
3528    cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
3529
3530    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3531    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3532
3533    const uint32_t *local_size = pipeline->compute.local_size;
3534    const uint32_t *num_groups = info->blocks;
3535    tu_cs_emit_regs(cs,
3536                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3537                                           .localsizex = local_size[0] - 1,
3538                                           .localsizey = local_size[1] - 1,
3539                                           .localsizez = local_size[2] - 1),
3540                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3541                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3542                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3543                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3544                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3545                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3546
3547    tu_cs_emit_regs(cs,
3548                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3549                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3550                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3551
3552    if (info->indirect) {
3553       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3554
3555       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3556                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3557
3558       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3559       tu_cs_emit(cs, 0x00000000);
3560       tu_cs_emit_qw(cs, iova);
3561       tu_cs_emit(cs,
3562                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3563                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3564                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3565    } else {
3566       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3567       tu_cs_emit(cs, 0x00000000);
3568       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3569       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3570       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3571    }
3572
3573    tu_cs_emit_wfi(cs);
3574
3575    tu6_emit_cache_flush(cmd, cs);
3576 }
3577
3578 void
3579 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3580                    uint32_t base_x,
3581                    uint32_t base_y,
3582                    uint32_t base_z,
3583                    uint32_t x,
3584                    uint32_t y,
3585                    uint32_t z)
3586 {
3587    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3588    struct tu_dispatch_info info = {};
3589
3590    info.blocks[0] = x;
3591    info.blocks[1] = y;
3592    info.blocks[2] = z;
3593
3594    info.offsets[0] = base_x;
3595    info.offsets[1] = base_y;
3596    info.offsets[2] = base_z;
3597    tu_dispatch(cmd_buffer, &info);
3598 }
3599
3600 void
3601 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3602                uint32_t x,
3603                uint32_t y,
3604                uint32_t z)
3605 {
3606    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3607 }
3608
3609 void
3610 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3611                        VkBuffer _buffer,
3612                        VkDeviceSize offset)
3613 {
3614    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3615    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3616    struct tu_dispatch_info info = {};
3617
3618    info.indirect = buffer;
3619    info.indirect_offset = offset;
3620
3621    tu_dispatch(cmd_buffer, &info);
3622 }
3623
3624 void
3625 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3626 {
3627    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3628
3629    tu_cs_end(&cmd_buffer->draw_cs);
3630    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3631
3632    if (use_sysmem_rendering(cmd_buffer))
3633       tu_cmd_render_sysmem(cmd_buffer);
3634    else
3635       tu_cmd_render_tiles(cmd_buffer);
3636
3637    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3638       rendered */
3639    tu_cs_discard_entries(&cmd_buffer->draw_cs);
3640    tu_cs_begin(&cmd_buffer->draw_cs);
3641    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
3642    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
3643
3644    cmd_buffer->state.pass = NULL;
3645    cmd_buffer->state.subpass = NULL;
3646    cmd_buffer->state.framebuffer = NULL;
3647 }
3648
3649 void
3650 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3651                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
3652 {
3653    tu_CmdEndRenderPass(commandBuffer);
3654 }
3655
3656 struct tu_barrier_info
3657 {
3658    uint32_t eventCount;
3659    const VkEvent *pEvents;
3660    VkPipelineStageFlags srcStageMask;
3661 };
3662
3663 static void
3664 tu_barrier(struct tu_cmd_buffer *cmd,
3665            uint32_t memoryBarrierCount,
3666            const VkMemoryBarrier *pMemoryBarriers,
3667            uint32_t bufferMemoryBarrierCount,
3668            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3669            uint32_t imageMemoryBarrierCount,
3670            const VkImageMemoryBarrier *pImageMemoryBarriers,
3671            const struct tu_barrier_info *info)
3672 {
3673    /* renderpass case is only for subpass self-dependencies
3674     * which means syncing the render output with texture cache
3675     * note: only the CACHE_INVALIDATE is needed in GMEM mode
3676     * and in sysmem mode we might not need either color/depth flush
3677     */
3678    if (cmd->state.pass) {
3679       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_COLOR_TS, true);
3680       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_DEPTH_TS, true);
3681       tu6_emit_event_write(cmd, &cmd->draw_cs, CACHE_INVALIDATE, false);
3682       return;
3683    }
3684 }
3685
3686 void
3687 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3688                       VkPipelineStageFlags srcStageMask,
3689                       VkPipelineStageFlags dstStageMask,
3690                       VkDependencyFlags dependencyFlags,
3691                       uint32_t memoryBarrierCount,
3692                       const VkMemoryBarrier *pMemoryBarriers,
3693                       uint32_t bufferMemoryBarrierCount,
3694                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3695                       uint32_t imageMemoryBarrierCount,
3696                       const VkImageMemoryBarrier *pImageMemoryBarriers)
3697 {
3698    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3699    struct tu_barrier_info info;
3700
3701    info.eventCount = 0;
3702    info.pEvents = NULL;
3703    info.srcStageMask = srcStageMask;
3704
3705    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3706               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3707               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3708 }
3709
3710 static void
3711 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
3712 {
3713    struct tu_cs *cs = &cmd->cs;
3714
3715    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
3716
3717    /* TODO: any flush required before/after ? */
3718
3719    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
3720    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
3721    tu_cs_emit(cs, value);
3722 }
3723
3724 void
3725 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3726                VkEvent _event,
3727                VkPipelineStageFlags stageMask)
3728 {
3729    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3730    TU_FROM_HANDLE(tu_event, event, _event);
3731
3732    write_event(cmd, event, 1);
3733 }
3734
3735 void
3736 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3737                  VkEvent _event,
3738                  VkPipelineStageFlags stageMask)
3739 {
3740    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3741    TU_FROM_HANDLE(tu_event, event, _event);
3742
3743    write_event(cmd, event, 0);
3744 }
3745
3746 void
3747 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3748                  uint32_t eventCount,
3749                  const VkEvent *pEvents,
3750                  VkPipelineStageFlags srcStageMask,
3751                  VkPipelineStageFlags dstStageMask,
3752                  uint32_t memoryBarrierCount,
3753                  const VkMemoryBarrier *pMemoryBarriers,
3754                  uint32_t bufferMemoryBarrierCount,
3755                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3756                  uint32_t imageMemoryBarrierCount,
3757                  const VkImageMemoryBarrier *pImageMemoryBarriers)
3758 {
3759    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3760    struct tu_cs *cs = &cmd->cs;
3761
3762    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3763
3764    for (uint32_t i = 0; i < eventCount; i++) {
3765       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
3766
3767       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
3768
3769       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
3770       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
3771                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
3772       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
3773       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
3774       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
3775       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3776    }
3777 }
3778
3779 void
3780 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3781 {
3782    /* No-op */
3783 }