2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
41 tu_bo_list_init(struct tu_bo_list
*list
)
43 list
->count
= list
->capacity
= 0;
44 list
->bo_infos
= NULL
;
48 tu_bo_list_destroy(struct tu_bo_list
*list
)
54 tu_bo_list_reset(struct tu_bo_list
*list
)
60 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
63 tu_bo_list_add_info(struct tu_bo_list
*list
,
64 const struct drm_msm_gem_submit_bo
*bo_info
)
66 assert(bo_info
->handle
!= 0);
68 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
69 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
70 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
71 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
76 /* grow list->bo_infos if needed */
77 if (list
->count
== list
->capacity
) {
78 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
79 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
80 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
82 return TU_BO_LIST_FAILED
;
83 list
->bo_infos
= new_bo_infos
;
84 list
->capacity
= new_capacity
;
87 list
->bo_infos
[list
->count
] = *bo_info
;
92 tu_bo_list_add(struct tu_bo_list
*list
,
93 const struct tu_bo
*bo
,
96 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
98 .handle
= bo
->gem_handle
,
104 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
106 for (uint32_t i
= 0; i
< other
->count
; i
++) {
107 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
108 return VK_ERROR_OUT_OF_HOST_MEMORY
;
115 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
116 const struct tu_device
*dev
,
119 const uint32_t tile_align_w
= dev
->physical_device
->tile_align_w
;
120 const uint32_t tile_align_h
= dev
->physical_device
->tile_align_h
;
121 const uint32_t max_tile_width
= 1024; /* A6xx */
123 tiling
->tile0
.offset
= (VkOffset2D
) {
124 .x
= tiling
->render_area
.offset
.x
& ~(tile_align_w
- 1),
125 .y
= tiling
->render_area
.offset
.y
& ~(tile_align_h
- 1),
128 const uint32_t ra_width
=
129 tiling
->render_area
.extent
.width
+
130 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
131 const uint32_t ra_height
=
132 tiling
->render_area
.extent
.height
+
133 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
135 /* start from 1 tile */
136 tiling
->tile_count
= (VkExtent2D
) {
140 tiling
->tile0
.extent
= (VkExtent2D
) {
141 .width
= align(ra_width
, tile_align_w
),
142 .height
= align(ra_height
, tile_align_h
),
145 /* do not exceed max tile width */
146 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
147 tiling
->tile_count
.width
++;
148 tiling
->tile0
.extent
.width
=
149 align(ra_width
/ tiling
->tile_count
.width
, tile_align_w
);
152 /* do not exceed gmem size */
153 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pixels
) {
154 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
155 tiling
->tile_count
.width
++;
156 tiling
->tile0
.extent
.width
=
157 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
159 /* if this assert fails then layout is impossible.. */
160 assert(tiling
->tile0
.extent
.height
> tile_align_h
);
161 tiling
->tile_count
.height
++;
162 tiling
->tile0
.extent
.height
=
163 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), tile_align_h
);
169 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
170 const struct tu_device
*dev
)
172 const uint32_t max_pipe_count
= 32; /* A6xx */
174 /* start from 1 tile per pipe */
175 tiling
->pipe0
= (VkExtent2D
) {
179 tiling
->pipe_count
= tiling
->tile_count
;
181 /* do not exceed max pipe count vertically */
182 while (tiling
->pipe_count
.height
> max_pipe_count
) {
183 tiling
->pipe0
.height
+= 2;
184 tiling
->pipe_count
.height
=
185 (tiling
->tile_count
.height
+ tiling
->pipe0
.height
- 1) /
186 tiling
->pipe0
.height
;
189 /* do not exceed max pipe count */
190 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
>
192 tiling
->pipe0
.width
+= 1;
193 tiling
->pipe_count
.width
=
194 (tiling
->tile_count
.width
+ tiling
->pipe0
.width
- 1) /
200 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
201 const struct tu_device
*dev
)
203 const uint32_t max_pipe_count
= 32; /* A6xx */
204 const uint32_t used_pipe_count
=
205 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
206 const VkExtent2D last_pipe
= {
207 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
208 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
211 assert(used_pipe_count
<= max_pipe_count
);
212 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
214 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
215 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
216 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
217 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
218 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
220 : tiling
->pipe0
.width
;
221 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
223 : tiling
->pipe0
.height
;
224 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
226 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
227 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
228 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
229 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
230 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
234 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
235 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
239 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
240 const struct tu_device
*dev
,
243 struct tu_tile
*tile
)
245 /* find the pipe and the slot for tile (tx, ty) */
246 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
247 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
248 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
249 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
251 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
252 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
253 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
255 /* convert to 1D indices */
256 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
257 tile
->slot
= tiling
->pipe0
.width
* sy
+ sx
;
259 /* get the blit area for the tile */
260 tile
->begin
= (VkOffset2D
) {
261 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
262 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
265 (tx
== tiling
->tile_count
.width
- 1)
266 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
267 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
269 (ty
== tiling
->tile_count
.height
- 1)
270 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
271 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
274 enum a3xx_msaa_samples
275 tu_msaa_samples(uint32_t samples
)
287 assert(!"invalid sample count");
292 static enum a4xx_index_size
293 tu6_index_size(VkIndexType type
)
296 case VK_INDEX_TYPE_UINT16
:
297 return INDEX4_SIZE_16_BIT
;
298 case VK_INDEX_TYPE_UINT32
:
299 return INDEX4_SIZE_32_BIT
;
301 unreachable("invalid VkIndexType");
302 return INDEX4_SIZE_8_BIT
;
307 tu6_emit_marker(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
309 tu_cs_emit_write_reg(cs
, cmd
->marker_reg
, ++cmd
->marker_seqno
);
313 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
315 enum vgt_event_type event
,
320 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
321 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
323 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
324 seqno
= ++cmd
->scratch_seqno
;
325 tu_cs_emit(cs
, seqno
);
332 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
334 tu6_emit_event_write(cmd
, cs
, 0x31, false);
338 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
340 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
344 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
346 if (cmd
->wait_for_idle
) {
348 cmd
->wait_for_idle
= false;
352 #define tu_image_view_ubwc_pitches(iview) \
353 .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
354 .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
357 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
358 const struct tu_subpass
*subpass
,
361 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
363 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
364 if (a
== VK_ATTACHMENT_UNUSED
) {
366 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
367 A6XX_RB_DEPTH_BUFFER_PITCH(0),
368 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
369 A6XX_RB_DEPTH_BUFFER_BASE(0),
370 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
373 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
376 A6XX_GRAS_LRZ_BUFFER_BASE(0),
377 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
378 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
380 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
385 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
386 enum a6xx_depth_format fmt
= tu6_pipe2depth(iview
->vk_format
);
389 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
),
390 A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)),
391 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview
->image
->layout
.layer_size
),
392 A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview
)),
393 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd
->state
.pass
->attachments
[a
].gmem_offset
));
396 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
399 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview
)),
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview
)));
403 A6XX_GRAS_LRZ_BUFFER_BASE(0),
404 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
405 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
408 A6XX_RB_STENCIL_INFO(0));
414 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
415 const struct tu_subpass
*subpass
,
418 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
419 unsigned char mrt_comp
[MAX_RTS
] = { 0 };
420 unsigned srgb_cntl
= 0;
422 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
423 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
424 if (a
== VK_ATTACHMENT_UNUSED
)
427 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
428 const enum a6xx_tile_mode tile_mode
=
429 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
433 if (vk_format_is_srgb(iview
->vk_format
))
434 srgb_cntl
|= (1 << i
);
436 const struct tu_native_format
*format
=
437 tu6_get_native_format(iview
->vk_format
);
438 assert(format
&& format
->rb
>= 0);
441 A6XX_RB_MRT_BUF_INFO(i
,
442 .color_tile_mode
= tile_mode
,
443 .color_format
= format
->rb
,
444 .color_swap
= format
->swap
),
445 A6XX_RB_MRT_PITCH(i
, tu_image_stride(iview
->image
, iview
->base_mip
)),
446 A6XX_RB_MRT_ARRAY_PITCH(i
, iview
->image
->layout
.layer_size
),
447 A6XX_RB_MRT_BASE(i
, tu_image_view_base_ref(iview
)),
448 A6XX_RB_MRT_BASE_GMEM(i
, cmd
->state
.pass
->attachments
[a
].gmem_offset
));
451 A6XX_SP_FS_MRT_REG(i
,
452 .color_format
= format
->rb
,
453 .color_sint
= vk_format_is_sint(iview
->vk_format
),
454 .color_uint
= vk_format_is_uint(iview
->vk_format
)));
457 A6XX_RB_MRT_FLAG_BUFFER_ADDR(i
, tu_image_view_ubwc_base_ref(iview
)),
458 A6XX_RB_MRT_FLAG_BUFFER_PITCH(i
, tu_image_view_ubwc_pitches(iview
)));
462 A6XX_RB_SRGB_CNTL(srgb_cntl
));
465 A6XX_SP_SRGB_CNTL(srgb_cntl
));
468 A6XX_RB_RENDER_COMPONENTS(
476 .rt7
= mrt_comp
[7]));
479 A6XX_SP_FS_RENDER_COMPONENTS(
487 .rt7
= mrt_comp
[7]));
491 tu6_emit_msaa(struct tu_cmd_buffer
*cmd
,
492 const struct tu_subpass
*subpass
,
495 const enum a3xx_msaa_samples samples
= tu_msaa_samples(subpass
->samples
);
496 bool msaa_disable
= samples
== MSAA_ONE
;
499 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
500 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
501 .msaa_disable
= msaa_disable
));
504 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
505 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
506 .msaa_disable
= msaa_disable
));
509 A6XX_RB_RAS_MSAA_CNTL(samples
),
510 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
511 .msaa_disable
= msaa_disable
));
514 A6XX_RB_MSAA_CNTL(samples
));
518 tu6_emit_bin_size(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t flags
)
520 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
521 const uint32_t bin_w
= tiling
->tile0
.extent
.width
;
522 const uint32_t bin_h
= tiling
->tile0
.extent
.height
;
525 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
530 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
534 /* no flag for RB_BIN_CONTROL2... */
536 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
541 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
546 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
548 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
550 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
552 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
553 tu_cs_emit(cs
, cntl
);
557 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
559 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
560 uint32_t x1
= render_area
->offset
.x
;
561 uint32_t y1
= render_area
->offset
.y
;
562 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
563 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
565 /* TODO: alignment requirement seems to be less than tile_align_w/h */
567 x1
= x1
& ~cmd
->device
->physical_device
->tile_align_w
;
568 y1
= y1
& ~cmd
->device
->physical_device
->tile_align_h
;
569 x2
= ALIGN_POT(x2
+ 1, cmd
->device
->physical_device
->tile_align_w
) - 1;
570 y2
= ALIGN_POT(y2
+ 1, cmd
->device
->physical_device
->tile_align_h
) - 1;
574 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
575 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
579 tu6_emit_blit_info(struct tu_cmd_buffer
*cmd
,
581 const struct tu_image_view
*iview
,
582 uint32_t gmem_offset
,
586 A6XX_RB_BLIT_INFO(.unk0
= !resolve
, .gmem
= !resolve
));
588 const struct tu_native_format
*format
=
589 tu6_get_native_format(iview
->vk_format
);
590 assert(format
&& format
->rb
>= 0);
592 enum a6xx_tile_mode tile_mode
=
593 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
595 A6XX_RB_BLIT_DST_INFO(
596 .tile_mode
= tile_mode
,
597 .samples
= tu_msaa_samples(iview
->image
->samples
),
598 .color_format
= format
->rb
,
599 .color_swap
= format
->swap
,
600 .flags
= iview
->image
->layout
.ubwc_size
!= 0),
601 A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview
)),
602 A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)),
603 A6XX_RB_BLIT_DST_ARRAY_PITCH(iview
->image
->layout
.layer_size
));
605 if (iview
->image
->layout
.ubwc_size
) {
607 A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview
)),
608 A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview
)));
612 A6XX_RB_BLIT_BASE_GMEM(gmem_offset
));
616 tu6_emit_blit(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
618 tu6_emit_marker(cmd
, cs
);
619 tu6_emit_event_write(cmd
, cs
, BLIT
, false);
620 tu6_emit_marker(cmd
, cs
);
624 tu6_emit_window_scissor(struct tu_cmd_buffer
*cmd
,
632 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
633 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
636 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
637 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
641 tu6_emit_window_offset(struct tu_cmd_buffer
*cmd
,
647 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
650 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
653 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
656 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
660 use_hw_binning(struct tu_cmd_buffer
*cmd
)
662 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
664 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
667 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
671 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
673 const struct tu_tile
*tile
)
675 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
676 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x7));
678 tu6_emit_marker(cmd
, cs
);
679 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
680 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
681 tu6_emit_marker(cmd
, cs
);
683 const uint32_t x1
= tile
->begin
.x
;
684 const uint32_t y1
= tile
->begin
.y
;
685 const uint32_t x2
= tile
->end
.x
- 1;
686 const uint32_t y2
= tile
->end
.y
- 1;
687 tu6_emit_window_scissor(cmd
, cs
, x1
, y1
, x2
, y2
);
688 tu6_emit_window_offset(cmd
, cs
, x1
, y1
);
691 A6XX_VPC_SO_OVERRIDE(.so_disable
= true));
693 if (use_hw_binning(cmd
)) {
694 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
696 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
699 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
700 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
701 A6XX_CP_REG_TEST_0_BIT(0) |
702 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
704 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
705 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
706 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
708 /* if (no overflow) */ {
709 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
710 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
711 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
712 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
713 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
714 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
716 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
719 /* use a NOP packet to skip over the 'else' side: */
720 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
722 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
726 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
730 A6XX_RB_UNKNOWN_8804(0));
733 A6XX_SP_TP_UNKNOWN_B304(0));
736 A6XX_GRAS_UNKNOWN_80A4(0));
738 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
741 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
747 tu6_emit_load_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
)
749 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
750 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
751 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
752 const struct tu_render_pass_attachment
*attachment
=
753 &cmd
->state
.pass
->attachments
[a
];
755 if (attachment
->gmem_offset
< 0)
758 const uint32_t x1
= tiling
->render_area
.offset
.x
;
759 const uint32_t y1
= tiling
->render_area
.offset
.y
;
760 const uint32_t x2
= x1
+ tiling
->render_area
.extent
.width
;
761 const uint32_t y2
= y1
+ tiling
->render_area
.extent
.height
;
762 const uint32_t tile_x2
=
763 tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tiling
->tile_count
.width
;
764 const uint32_t tile_y2
=
765 tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* tiling
->tile_count
.height
;
767 x1
!= tiling
->tile0
.offset
.x
|| x2
!= MIN2(fb
->width
, tile_x2
) ||
768 y1
!= tiling
->tile0
.offset
.y
|| y2
!= MIN2(fb
->height
, tile_y2
);
771 tu_finishme("improve handling of unaligned render area");
773 if (attachment
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
)
776 if (vk_format_has_stencil(iview
->vk_format
) &&
777 attachment
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
)
781 tu6_emit_blit_info(cmd
, cs
, iview
, attachment
->gmem_offset
, false);
782 tu6_emit_blit(cmd
, cs
);
787 tu6_emit_clear_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
789 const VkRenderPassBeginInfo
*info
)
791 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
792 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
793 const struct tu_render_pass_attachment
*attachment
=
794 &cmd
->state
.pass
->attachments
[a
];
795 unsigned clear_mask
= 0;
797 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
798 if (attachment
->gmem_offset
< 0)
801 if (attachment
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
)
804 if (vk_format_has_stencil(iview
->vk_format
)) {
806 if (attachment
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
)
812 const struct tu_native_format
*format
=
813 tu6_get_native_format(iview
->vk_format
);
814 assert(format
&& format
->rb
>= 0);
817 A6XX_RB_BLIT_DST_INFO(.color_format
= format
->rb
));
820 A6XX_RB_BLIT_INFO(.gmem
= true,
821 .clear_mask
= clear_mask
));
824 A6XX_RB_BLIT_BASE_GMEM(attachment
->gmem_offset
));
827 A6XX_RB_UNKNOWN_88D0(0));
829 uint32_t clear_vals
[4] = { 0 };
830 tu_pack_clear_value(&info
->pClearValues
[a
], iview
->vk_format
, clear_vals
);
833 A6XX_RB_BLIT_CLEAR_COLOR_DW0(clear_vals
[0]),
834 A6XX_RB_BLIT_CLEAR_COLOR_DW1(clear_vals
[1]),
835 A6XX_RB_BLIT_CLEAR_COLOR_DW2(clear_vals
[2]),
836 A6XX_RB_BLIT_CLEAR_COLOR_DW3(clear_vals
[3]));
838 tu6_emit_blit(cmd
, cs
);
842 tu6_emit_store_attachment(struct tu_cmd_buffer
*cmd
,
847 if (cmd
->state
.pass
->attachments
[a
].store_op
== VK_ATTACHMENT_STORE_OP_DONT_CARE
)
850 tu6_emit_blit_info(cmd
, cs
,
851 cmd
->state
.framebuffer
->attachments
[a
].attachment
,
852 cmd
->state
.pass
->attachments
[gmem_a
].gmem_offset
, true);
853 tu6_emit_blit(cmd
, cs
);
857 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
859 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
860 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
862 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
863 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
864 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
865 CP_SET_DRAW_STATE__0_GROUP_ID(0));
866 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
867 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
869 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
872 tu6_emit_marker(cmd
, cs
);
873 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
874 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
875 tu6_emit_marker(cmd
, cs
);
877 tu6_emit_blit_scissor(cmd
, cs
, true);
879 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
880 if (pass
->attachments
[a
].gmem_offset
>= 0)
881 tu6_emit_store_attachment(cmd
, cs
, a
, a
);
884 if (subpass
->resolve_attachments
) {
885 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
886 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
887 if (a
!= VK_ATTACHMENT_UNUSED
)
888 tu6_emit_store_attachment(cmd
, cs
, a
,
889 subpass
->color_attachments
[i
].attachment
);
895 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
898 A6XX_PC_RESTART_INDEX(restart_index
));
902 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
904 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
905 if (result
!= VK_SUCCESS
) {
906 cmd
->record_result
= result
;
910 tu6_emit_cache_flush(cmd
, cs
);
912 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
914 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_CCU_CNTL
, 0x7c400004);
915 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
916 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
917 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
918 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
919 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
920 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
921 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
922 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
924 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
925 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
926 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
927 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
928 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
929 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
930 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
931 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
932 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
933 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
934 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
935 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
936 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
937 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
939 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
941 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 0);
942 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 0);
943 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
945 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
946 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
947 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
948 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 0);
949 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
950 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
951 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
952 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
954 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
955 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
958 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
959 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
961 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
962 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
965 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
974 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
976 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
978 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
979 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
980 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
981 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
982 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
983 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
984 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
985 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
986 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
987 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
988 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
989 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
990 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8804
, 0);
991 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
992 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
993 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
994 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8805
, 0);
995 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8806
, 0);
996 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
997 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
998 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
1000 tu6_emit_marker(cmd
, cs
);
1002 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
1004 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
1006 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
1008 /* we don't use this yet.. probably best to disable.. */
1009 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1010 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1011 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1012 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1013 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1014 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1017 A6XX_VPC_SO_BUFFER_BASE(0),
1018 A6XX_VPC_SO_BUFFER_SIZE(0));
1021 A6XX_VPC_SO_FLUSH_BASE(0));
1024 A6XX_VPC_SO_BUF_CNTL(0));
1027 A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1030 A6XX_VPC_SO_BUFFER_BASE(1, 0),
1031 A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1034 A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1035 A6XX_VPC_SO_FLUSH_BASE(1, 0),
1036 A6XX_VPC_SO_BUFFER_BASE(2, 0),
1037 A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1040 A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1041 A6XX_VPC_SO_FLUSH_BASE(2, 0),
1042 A6XX_VPC_SO_BUFFER_BASE(3, 0),
1043 A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1046 A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1047 A6XX_VPC_SO_FLUSH_BASE(3, 0));
1050 A6XX_SP_HS_CTRL_REG0(0));
1053 A6XX_SP_GS_CTRL_REG0(0));
1056 A6XX_GRAS_LRZ_CNTL(0));
1059 A6XX_RB_LRZ_CNTL(0));
1061 tu_cs_sanity_check(cs
);
1065 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1069 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_AND_INV_EVENT
, true);
1071 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
1072 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
1073 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
1074 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
1075 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
1076 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
1077 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1079 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1081 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
1082 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
1083 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
1084 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
1088 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1090 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1093 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
1094 .height
= tiling
->tile0
.extent
.height
),
1095 A6XX_VSC_SIZE_ADDRESS(.bo
= &cmd
->vsc_data
, .bo_offset
= cmd
->vsc_data_pitch
));
1098 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
1099 .ny
= tiling
->tile_count
.height
));
1101 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1102 for (unsigned i
= 0; i
< 32; i
++)
1103 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
1106 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo
= &cmd
->vsc_data2
),
1107 A6XX_VSC_PIPE_DATA2_PITCH(cmd
->vsc_data2_pitch
),
1108 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd
->vsc_data2
.size
));
1111 A6XX_VSC_PIPE_DATA_ADDRESS(.bo
= &cmd
->vsc_data
),
1112 A6XX_VSC_PIPE_DATA_PITCH(cmd
->vsc_data_pitch
),
1113 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd
->vsc_data
.size
));
1117 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1119 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1120 const uint32_t used_pipe_count
=
1121 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1123 /* Clear vsc_scratch: */
1124 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1125 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1126 tu_cs_emit(cs
, 0x0);
1128 /* Check for overflow, write vsc_scratch if detected: */
1129 for (int i
= 0; i
< used_pipe_count
; i
++) {
1130 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1131 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1132 CP_COND_WRITE5_0_WRITE_MEMORY
);
1133 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
1134 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1135 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
1136 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1137 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1138 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
1140 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1141 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1142 CP_COND_WRITE5_0_WRITE_MEMORY
);
1143 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
1144 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1145 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
1146 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1147 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1148 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
1151 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1153 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1155 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1156 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
1157 CP_MEM_TO_REG_0_CNT(1 - 1));
1158 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1161 * This is a bit awkward, we really want a way to invert the
1162 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1163 * execute cmds to use hwbinning when a bit is *not* set. This
1164 * dance is to invert OVERFLOW_FLAG_REG
1166 * A CP_NOP packet is used to skip executing the 'else' clause
1170 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1171 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1172 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1173 A6XX_CP_REG_TEST_0_BIT(0) |
1174 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1176 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1177 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1178 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1182 * On overflow, mirror the value to control->vsc_overflow
1183 * which CPU is checking to detect overflow (see
1184 * check_vsc_overflow())
1186 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1187 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1188 CP_REG_TO_MEM_0_CNT(0));
1189 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_OVERFLOW
);
1191 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1192 tu_cs_emit(cs
, 0x0);
1194 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1196 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1197 tu_cs_emit(cs
, 0x1);
1202 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1204 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1206 uint32_t x1
= tiling
->tile0
.offset
.x
;
1207 uint32_t y1
= tiling
->tile0
.offset
.y
;
1208 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1209 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1211 tu6_emit_window_scissor(cmd
, cs
, x1
, y1
, x2
, y2
);
1213 tu6_emit_marker(cmd
, cs
);
1214 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1215 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1216 tu6_emit_marker(cmd
, cs
);
1218 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1219 tu_cs_emit(cs
, 0x1);
1221 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1222 tu_cs_emit(cs
, 0x1);
1227 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1229 update_vsc_pipe(cmd
, cs
);
1232 A6XX_PC_UNKNOWN_9805(.unknown
= 0x1));
1235 A6XX_SP_UNKNOWN_A0F8(.unknown
= 0x1));
1237 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1238 tu_cs_emit(cs
, UNK_2C
);
1241 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1244 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1246 /* emit IB to binning drawcmds: */
1247 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1249 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1250 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1251 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1252 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1253 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1254 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1256 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1257 tu_cs_emit(cs
, UNK_2D
);
1259 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1260 tu6_cache_flush(cmd
, cs
);
1264 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1266 emit_vsc_overflow_test(cmd
, cs
);
1268 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1269 tu_cs_emit(cs
, 0x0);
1271 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1272 tu_cs_emit(cs
, 0x0);
1277 A6XX_RB_CCU_CNTL(.unknown
= 0x7c400004));
1279 cmd
->wait_for_idle
= false;
1283 tu6_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1285 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 1024);
1286 if (result
!= VK_SUCCESS
) {
1287 cmd
->record_result
= result
;
1291 tu6_emit_lrz_flush(cmd
, cs
);
1295 tu6_emit_cache_flush(cmd
, cs
);
1297 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1298 tu_cs_emit(cs
, 0x0);
1300 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1301 tu6_emit_wfi(cmd
, cs
);
1303 A6XX_RB_CCU_CNTL(0x7c400004));
1305 if (use_hw_binning(cmd
)) {
1306 tu6_emit_bin_size(cmd
, cs
, A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1308 tu6_emit_render_cntl(cmd
, cs
, true);
1310 tu6_emit_binning_pass(cmd
, cs
);
1312 tu6_emit_bin_size(cmd
, cs
, A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1315 A6XX_VFD_MODE_CNTL(0));
1317 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= 0x1));
1319 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= 0x1));
1321 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1322 tu_cs_emit(cs
, 0x1);
1324 tu6_emit_bin_size(cmd
, cs
, 0x6000000);
1327 tu6_emit_render_cntl(cmd
, cs
, false);
1329 tu_cs_sanity_check(cs
);
1333 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1335 const struct tu_tile
*tile
)
1337 const uint32_t render_tile_space
= 256 + tu_cs_get_call_size(&cmd
->draw_cs
);
1338 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, render_tile_space
);
1339 if (result
!= VK_SUCCESS
) {
1340 cmd
->record_result
= result
;
1344 tu6_emit_tile_select(cmd
, cs
, tile
);
1345 tu_cs_emit_ib(cs
, &cmd
->state
.tile_load_ib
);
1347 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1348 cmd
->wait_for_idle
= true;
1350 if (use_hw_binning(cmd
)) {
1351 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1352 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1353 A6XX_CP_REG_TEST_0_BIT(0) |
1354 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1356 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1357 tu_cs_emit(cs
, 0x10000000);
1358 tu_cs_emit(cs
, 2); /* conditionally execute next 2 dwords */
1360 /* if (no overflow) */ {
1361 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1362 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1366 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1368 tu_cs_sanity_check(cs
);
1372 tu6_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1374 const uint32_t space
= 16 + tu_cs_get_call_size(&cmd
->draw_epilogue_cs
);
1375 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, space
);
1376 if (result
!= VK_SUCCESS
) {
1377 cmd
->record_result
= result
;
1381 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1384 A6XX_GRAS_LRZ_CNTL(0));
1386 tu6_emit_lrz_flush(cmd
, cs
);
1388 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1390 tu_cs_sanity_check(cs
);
1394 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1396 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1398 tu6_render_begin(cmd
, &cmd
->cs
);
1400 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1401 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1402 struct tu_tile tile
;
1403 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1404 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1408 tu6_render_end(cmd
, &cmd
->cs
);
1412 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer
*cmd
,
1413 const VkRenderPassBeginInfo
*info
)
1415 const uint32_t tile_load_space
=
1416 8 + (23+19) * cmd
->state
.pass
->attachment_count
+
1417 21 + (13 * cmd
->state
.subpass
->color_count
+ 8) + 11;
1419 struct tu_cs sub_cs
;
1421 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
,
1422 tile_load_space
, &sub_cs
);
1423 if (result
!= VK_SUCCESS
) {
1424 cmd
->record_result
= result
;
1428 tu6_emit_blit_scissor(cmd
, &sub_cs
, true);
1430 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1431 tu6_emit_load_attachment(cmd
, &sub_cs
, i
);
1433 tu6_emit_blit_scissor(cmd
, &sub_cs
, false);
1435 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1436 tu6_emit_clear_attachment(cmd
, &sub_cs
, i
, info
);
1438 /* invalidate because reading input attachments will cache GMEM and
1439 * the cache isn''t updated when GMEM is written
1440 * TODO: is there a no-cache bit for textures?
1442 if (cmd
->state
.subpass
->input_count
)
1443 tu6_emit_event_write(cmd
, &sub_cs
, CACHE_INVALIDATE
, false);
1445 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &sub_cs
);
1446 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &sub_cs
);
1447 tu6_emit_msaa(cmd
, cmd
->state
.subpass
, &sub_cs
);
1449 cmd
->state
.tile_load_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1453 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1455 const uint32_t tile_store_space
= 32 + 23 * cmd
->state
.pass
->attachment_count
;
1456 struct tu_cs sub_cs
;
1458 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
,
1459 tile_store_space
, &sub_cs
);
1460 if (result
!= VK_SUCCESS
) {
1461 cmd
->record_result
= result
;
1465 /* emit to tile-store sub_cs */
1466 tu6_emit_tile_store(cmd
, &sub_cs
);
1468 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1472 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1473 const VkRect2D
*render_area
)
1475 const struct tu_device
*dev
= cmd
->device
;
1476 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1478 tiling
->render_area
= *render_area
;
1480 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
->gmem_pixels
);
1481 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1482 tu_tiling_config_update_pipes(tiling
, dev
);
1485 const struct tu_dynamic_state default_dynamic_state
= {
1501 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1507 .stencil_compare_mask
=
1512 .stencil_write_mask
=
1517 .stencil_reference
=
1524 static void UNUSED
/* FINISHME */
1525 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1526 const struct tu_dynamic_state
*src
)
1528 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1529 uint32_t copy_mask
= src
->mask
;
1530 uint32_t dest_mask
= 0;
1532 tu_use_args(cmd_buffer
); /* FINISHME */
1534 /* Make sure to copy the number of viewports/scissors because they can
1535 * only be specified at pipeline creation time.
1537 dest
->viewport
.count
= src
->viewport
.count
;
1538 dest
->scissor
.count
= src
->scissor
.count
;
1539 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1541 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1542 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1543 src
->viewport
.count
* sizeof(VkViewport
))) {
1544 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1545 src
->viewport
.count
);
1546 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1550 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1551 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1552 src
->scissor
.count
* sizeof(VkRect2D
))) {
1553 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1554 src
->scissor
.count
);
1555 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1559 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1560 if (dest
->line_width
!= src
->line_width
) {
1561 dest
->line_width
= src
->line_width
;
1562 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1566 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1567 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1568 sizeof(src
->depth_bias
))) {
1569 dest
->depth_bias
= src
->depth_bias
;
1570 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1574 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1575 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1576 sizeof(src
->blend_constants
))) {
1577 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1578 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1582 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1583 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1584 sizeof(src
->depth_bounds
))) {
1585 dest
->depth_bounds
= src
->depth_bounds
;
1586 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1590 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1591 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1592 sizeof(src
->stencil_compare_mask
))) {
1593 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1594 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1598 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1599 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1600 sizeof(src
->stencil_write_mask
))) {
1601 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1602 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1606 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1607 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1608 sizeof(src
->stencil_reference
))) {
1609 dest
->stencil_reference
= src
->stencil_reference
;
1610 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1614 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1615 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1616 &src
->discard_rectangle
.rectangles
,
1617 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1618 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1619 src
->discard_rectangle
.rectangles
,
1620 src
->discard_rectangle
.count
);
1621 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1627 tu_create_cmd_buffer(struct tu_device
*device
,
1628 struct tu_cmd_pool
*pool
,
1629 VkCommandBufferLevel level
,
1630 VkCommandBuffer
*pCommandBuffer
)
1632 struct tu_cmd_buffer
*cmd_buffer
;
1633 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1634 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1635 if (cmd_buffer
== NULL
)
1636 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1638 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1639 cmd_buffer
->device
= device
;
1640 cmd_buffer
->pool
= pool
;
1641 cmd_buffer
->level
= level
;
1644 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1645 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1648 /* Init the pool_link so we can safely call list_del when we destroy
1649 * the command buffer
1651 list_inithead(&cmd_buffer
->pool_link
);
1652 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1655 tu_bo_list_init(&cmd_buffer
->bo_list
);
1656 tu_cs_init(&cmd_buffer
->cs
, TU_CS_MODE_GROW
, 4096);
1657 tu_cs_init(&cmd_buffer
->draw_cs
, TU_CS_MODE_GROW
, 4096);
1658 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, TU_CS_MODE_GROW
, 4096);
1659 tu_cs_init(&cmd_buffer
->sub_cs
, TU_CS_MODE_SUB_STREAM
, 2048);
1661 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1663 list_inithead(&cmd_buffer
->upload
.list
);
1665 cmd_buffer
->marker_reg
= REG_A6XX_CP_SCRATCH_REG(
1666 cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
? 7 : 6);
1668 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1669 if (result
!= VK_SUCCESS
)
1670 goto fail_scratch_bo
;
1672 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1673 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1675 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1676 cmd_buffer
->vsc_data_pitch
= 0x440 * 4;
1677 cmd_buffer
->vsc_data2_pitch
= 0x1040 * 4;
1679 result
= tu_bo_init_new(device
, &cmd_buffer
->vsc_data
, VSC_DATA_SIZE(cmd_buffer
->vsc_data_pitch
));
1680 if (result
!= VK_SUCCESS
)
1683 result
= tu_bo_init_new(device
, &cmd_buffer
->vsc_data2
, VSC_DATA2_SIZE(cmd_buffer
->vsc_data2_pitch
));
1684 if (result
!= VK_SUCCESS
)
1685 goto fail_vsc_data2
;
1690 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data
);
1692 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1694 list_del(&cmd_buffer
->pool_link
);
1699 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1701 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1702 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data
);
1703 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data2
);
1705 list_del(&cmd_buffer
->pool_link
);
1707 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1708 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1710 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->cs
);
1711 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1712 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->draw_epilogue_cs
);
1713 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->sub_cs
);
1715 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1716 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1720 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1722 cmd_buffer
->wait_for_idle
= true;
1724 cmd_buffer
->record_result
= VK_SUCCESS
;
1726 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1727 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->cs
);
1728 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1729 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->draw_epilogue_cs
);
1730 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->sub_cs
);
1732 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1733 cmd_buffer
->descriptors
[i
].dirty
= 0;
1734 cmd_buffer
->descriptors
[i
].valid
= 0;
1735 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1738 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1740 return cmd_buffer
->record_result
;
1744 tu_AllocateCommandBuffers(VkDevice _device
,
1745 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1746 VkCommandBuffer
*pCommandBuffers
)
1748 TU_FROM_HANDLE(tu_device
, device
, _device
);
1749 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1751 VkResult result
= VK_SUCCESS
;
1754 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1756 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1757 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1758 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1760 list_del(&cmd_buffer
->pool_link
);
1761 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1763 result
= tu_reset_cmd_buffer(cmd_buffer
);
1764 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1765 cmd_buffer
->level
= pAllocateInfo
->level
;
1767 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1769 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1770 &pCommandBuffers
[i
]);
1772 if (result
!= VK_SUCCESS
)
1776 if (result
!= VK_SUCCESS
) {
1777 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1780 /* From the Vulkan 1.0.66 spec:
1782 * "vkAllocateCommandBuffers can be used to create multiple
1783 * command buffers. If the creation of any of those command
1784 * buffers fails, the implementation must destroy all
1785 * successfully created command buffer objects from this
1786 * command, set all entries of the pCommandBuffers array to
1787 * NULL and return the error."
1789 memset(pCommandBuffers
, 0,
1790 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1797 tu_FreeCommandBuffers(VkDevice device
,
1798 VkCommandPool commandPool
,
1799 uint32_t commandBufferCount
,
1800 const VkCommandBuffer
*pCommandBuffers
)
1802 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1803 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1806 if (cmd_buffer
->pool
) {
1807 list_del(&cmd_buffer
->pool_link
);
1808 list_addtail(&cmd_buffer
->pool_link
,
1809 &cmd_buffer
->pool
->free_cmd_buffers
);
1811 tu_cmd_buffer_destroy(cmd_buffer
);
1817 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1818 VkCommandBufferResetFlags flags
)
1820 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1821 return tu_reset_cmd_buffer(cmd_buffer
);
1825 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1826 const VkCommandBufferBeginInfo
*pBeginInfo
)
1828 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1829 VkResult result
= VK_SUCCESS
;
1831 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1832 /* If the command buffer has already been resetted with
1833 * vkResetCommandBuffer, no need to do it again.
1835 result
= tu_reset_cmd_buffer(cmd_buffer
);
1836 if (result
!= VK_SUCCESS
)
1840 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1841 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1843 tu_cs_begin(&cmd_buffer
->cs
);
1844 tu_cs_begin(&cmd_buffer
->draw_cs
);
1845 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1847 cmd_buffer
->marker_seqno
= 0;
1848 cmd_buffer
->scratch_seqno
= 0;
1850 /* setup initial configuration into command buffer */
1851 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1852 switch (cmd_buffer
->queue_family_index
) {
1853 case TU_QUEUE_GENERAL
:
1854 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1859 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1860 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1861 assert(pBeginInfo
->pInheritanceInfo
);
1862 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1863 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1866 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1872 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1873 uint32_t firstBinding
,
1874 uint32_t bindingCount
,
1875 const VkBuffer
*pBuffers
,
1876 const VkDeviceSize
*pOffsets
)
1878 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1880 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1882 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1883 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1884 tu_buffer_from_handle(pBuffers
[i
]);
1885 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1888 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1889 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1893 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1895 VkDeviceSize offset
,
1896 VkIndexType indexType
)
1898 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1899 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1901 /* initialize/update the restart index */
1902 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1903 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1904 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 2);
1905 if (result
!= VK_SUCCESS
) {
1906 cmd
->record_result
= result
;
1910 tu6_emit_restart_index(
1911 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1913 tu_cs_sanity_check(draw_cs
);
1917 if (cmd
->state
.index_buffer
!= buf
)
1918 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1920 cmd
->state
.index_buffer
= buf
;
1921 cmd
->state
.index_offset
= offset
;
1922 cmd
->state
.index_type
= indexType
;
1926 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1927 VkPipelineBindPoint pipelineBindPoint
,
1928 VkPipelineLayout _layout
,
1930 uint32_t descriptorSetCount
,
1931 const VkDescriptorSet
*pDescriptorSets
,
1932 uint32_t dynamicOffsetCount
,
1933 const uint32_t *pDynamicOffsets
)
1935 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1936 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1937 unsigned dyn_idx
= 0;
1939 struct tu_descriptor_state
*descriptors_state
=
1940 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1942 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1943 unsigned idx
= i
+ firstSet
;
1944 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1946 descriptors_state
->sets
[idx
] = set
;
1947 descriptors_state
->valid
|= (1u << idx
);
1949 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1950 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
1951 assert(dyn_idx
< dynamicOffsetCount
);
1953 descriptors_state
->dynamic_buffers
[idx
] =
1954 set
->dynamic_descriptors
[j
].va
+ pDynamicOffsets
[dyn_idx
];
1958 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1962 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1963 VkPipelineLayout layout
,
1964 VkShaderStageFlags stageFlags
,
1967 const void *pValues
)
1969 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1970 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1971 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
1975 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1977 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1979 if (cmd_buffer
->scratch_seqno
) {
1980 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
1981 MSM_SUBMIT_BO_WRITE
);
1984 if (cmd_buffer
->use_vsc_data
) {
1985 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
1986 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1987 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
1988 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1991 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1992 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1993 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1996 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1997 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1998 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2001 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2002 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2003 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2006 tu_cs_end(&cmd_buffer
->cs
);
2007 tu_cs_end(&cmd_buffer
->draw_cs
);
2008 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2010 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2012 return cmd_buffer
->record_result
;
2016 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2017 VkPipelineBindPoint pipelineBindPoint
,
2018 VkPipeline _pipeline
)
2020 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2021 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2023 switch (pipelineBindPoint
) {
2024 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2025 cmd
->state
.pipeline
= pipeline
;
2026 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2028 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2029 cmd
->state
.compute_pipeline
= pipeline
;
2030 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2033 unreachable("unrecognized pipeline bind point");
2037 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2038 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2039 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2040 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2041 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2046 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2047 uint32_t firstViewport
,
2048 uint32_t viewportCount
,
2049 const VkViewport
*pViewports
)
2051 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2052 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2054 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 12);
2055 if (result
!= VK_SUCCESS
) {
2056 cmd
->record_result
= result
;
2060 assert(firstViewport
== 0 && viewportCount
== 1);
2061 tu6_emit_viewport(draw_cs
, pViewports
);
2063 tu_cs_sanity_check(draw_cs
);
2067 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2068 uint32_t firstScissor
,
2069 uint32_t scissorCount
,
2070 const VkRect2D
*pScissors
)
2072 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2073 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2075 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 3);
2076 if (result
!= VK_SUCCESS
) {
2077 cmd
->record_result
= result
;
2081 assert(firstScissor
== 0 && scissorCount
== 1);
2082 tu6_emit_scissor(draw_cs
, pScissors
);
2084 tu_cs_sanity_check(draw_cs
);
2088 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2090 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2092 cmd
->state
.dynamic
.line_width
= lineWidth
;
2094 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2095 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2099 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2100 float depthBiasConstantFactor
,
2101 float depthBiasClamp
,
2102 float depthBiasSlopeFactor
)
2104 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2105 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2107 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 4);
2108 if (result
!= VK_SUCCESS
) {
2109 cmd
->record_result
= result
;
2113 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2114 depthBiasSlopeFactor
);
2116 tu_cs_sanity_check(draw_cs
);
2120 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2121 const float blendConstants
[4])
2123 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2124 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2126 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 5);
2127 if (result
!= VK_SUCCESS
) {
2128 cmd
->record_result
= result
;
2132 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2134 tu_cs_sanity_check(draw_cs
);
2138 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2139 float minDepthBounds
,
2140 float maxDepthBounds
)
2145 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2146 VkStencilFaceFlags faceMask
,
2147 uint32_t compareMask
)
2149 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2151 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2152 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2153 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2154 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2156 /* the front/back compare masks must be updated together */
2157 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2161 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2162 VkStencilFaceFlags faceMask
,
2165 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2167 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2168 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2169 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2170 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2172 /* the front/back write masks must be updated together */
2173 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2177 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2178 VkStencilFaceFlags faceMask
,
2181 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2183 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2184 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2185 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2186 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2188 /* the front/back references must be updated together */
2189 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2193 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2194 uint32_t commandBufferCount
,
2195 const VkCommandBuffer
*pCmdBuffers
)
2197 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2200 assert(commandBufferCount
> 0);
2202 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2203 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2205 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2206 if (result
!= VK_SUCCESS
) {
2207 cmd
->record_result
= result
;
2211 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2212 if (result
!= VK_SUCCESS
) {
2213 cmd
->record_result
= result
;
2217 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2218 &secondary
->draw_epilogue_cs
);
2219 if (result
!= VK_SUCCESS
) {
2220 cmd
->record_result
= result
;
2224 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2228 tu_CreateCommandPool(VkDevice _device
,
2229 const VkCommandPoolCreateInfo
*pCreateInfo
,
2230 const VkAllocationCallbacks
*pAllocator
,
2231 VkCommandPool
*pCmdPool
)
2233 TU_FROM_HANDLE(tu_device
, device
, _device
);
2234 struct tu_cmd_pool
*pool
;
2236 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2237 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2239 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2242 pool
->alloc
= *pAllocator
;
2244 pool
->alloc
= device
->alloc
;
2246 list_inithead(&pool
->cmd_buffers
);
2247 list_inithead(&pool
->free_cmd_buffers
);
2249 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2251 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2257 tu_DestroyCommandPool(VkDevice _device
,
2258 VkCommandPool commandPool
,
2259 const VkAllocationCallbacks
*pAllocator
)
2261 TU_FROM_HANDLE(tu_device
, device
, _device
);
2262 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2267 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2268 &pool
->cmd_buffers
, pool_link
)
2270 tu_cmd_buffer_destroy(cmd_buffer
);
2273 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2274 &pool
->free_cmd_buffers
, pool_link
)
2276 tu_cmd_buffer_destroy(cmd_buffer
);
2279 vk_free2(&device
->alloc
, pAllocator
, pool
);
2283 tu_ResetCommandPool(VkDevice device
,
2284 VkCommandPool commandPool
,
2285 VkCommandPoolResetFlags flags
)
2287 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2290 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2293 result
= tu_reset_cmd_buffer(cmd_buffer
);
2294 if (result
!= VK_SUCCESS
)
2302 tu_TrimCommandPool(VkDevice device
,
2303 VkCommandPool commandPool
,
2304 VkCommandPoolTrimFlags flags
)
2306 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2311 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2312 &pool
->free_cmd_buffers
, pool_link
)
2314 tu_cmd_buffer_destroy(cmd_buffer
);
2319 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2320 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2321 VkSubpassContents contents
)
2323 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2324 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2325 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2327 cmd
->state
.pass
= pass
;
2328 cmd
->state
.subpass
= pass
->subpasses
;
2329 cmd
->state
.framebuffer
= fb
;
2331 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2332 tu_cmd_prepare_tile_load_ib(cmd
, pRenderPassBegin
);
2333 tu_cmd_prepare_tile_store_ib(cmd
);
2335 /* note: use_hw_binning only checks tiling config */
2336 if (use_hw_binning(cmd
))
2337 cmd
->use_vsc_data
= true;
2339 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2340 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2341 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2342 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2347 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2348 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2349 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2351 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2352 pSubpassBeginInfo
->contents
);
2356 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2358 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2359 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2360 struct tu_cs
*cs
= &cmd
->draw_cs
;
2362 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 1024);
2363 if (result
!= VK_SUCCESS
) {
2364 cmd
->record_result
= result
;
2368 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2370 * if msaa samples change between subpasses,
2371 * attachment store is broken for some attachments
2373 if (subpass
->resolve_attachments
) {
2374 tu6_emit_blit_scissor(cmd
, cs
, true);
2375 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2376 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2377 if (a
!= VK_ATTACHMENT_UNUSED
) {
2378 tu6_emit_store_attachment(cmd
, cs
, a
,
2379 subpass
->color_attachments
[i
].attachment
);
2384 /* invalidate because reading input attachments will cache GMEM and
2385 * the cache isn''t updated when GMEM is written
2386 * TODO: is there a no-cache bit for textures?
2388 if (cmd
->state
.subpass
->input_count
)
2389 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2391 /* emit mrt/zs/msaa state for the subpass that is starting */
2392 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2393 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2394 tu6_emit_msaa(cmd
, cmd
->state
.subpass
, cs
);
2397 * since we don't know how to do GMEM->GMEM resolve,
2398 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2400 if (subpass
->resolve_attachments
) {
2401 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2402 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2403 const struct tu_image_view
*iview
=
2404 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
2405 if (a
!= VK_ATTACHMENT_UNUSED
&& pass
->attachments
[a
].gmem_offset
>= 0) {
2406 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2407 tu6_emit_blit_info(cmd
, cs
, iview
, pass
->attachments
[a
].gmem_offset
, false);
2408 tu6_emit_blit(cmd
, cs
);
2415 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2416 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2417 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2419 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2425 * Number of vertices.
2430 * Index of the first vertex.
2432 int32_t vertex_offset
;
2435 * First instance id.
2437 uint32_t first_instance
;
2440 * Number of instances.
2442 uint32_t instance_count
;
2445 * First index (indexed draws only).
2447 uint32_t first_index
;
2450 * Whether it's an indexed draw.
2455 * Indirect draw parameters resource.
2457 struct tu_buffer
*indirect
;
2458 uint64_t indirect_offset
;
2462 * Draw count parameters resource.
2464 struct tu_buffer
*count_buffer
;
2465 uint64_t count_buffer_offset
;
2468 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2469 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2471 enum tu_draw_state_group_id
2473 TU_DRAW_STATE_PROGRAM
,
2474 TU_DRAW_STATE_PROGRAM_BINNING
,
2476 TU_DRAW_STATE_VI_BINNING
,
2480 TU_DRAW_STATE_BLEND
,
2481 TU_DRAW_STATE_VS_CONST
,
2482 TU_DRAW_STATE_FS_CONST
,
2483 TU_DRAW_STATE_VS_TEX
,
2484 TU_DRAW_STATE_FS_TEX
,
2485 TU_DRAW_STATE_FS_IBO
,
2486 TU_DRAW_STATE_VS_PARAMS
,
2488 TU_DRAW_STATE_COUNT
,
2491 struct tu_draw_state_group
2493 enum tu_draw_state_group_id id
;
2494 uint32_t enable_mask
;
2495 struct tu_cs_entry ib
;
2498 const static struct tu_sampler
*
2499 sampler_ptr(struct tu_descriptor_state
*descriptors_state
,
2500 const struct tu_descriptor_map
*map
, unsigned i
,
2501 unsigned array_index
)
2503 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2505 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2506 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2508 const struct tu_descriptor_set_binding_layout
*layout
=
2509 &set
->layout
->binding
[map
->binding
[i
]];
2511 if (layout
->immutable_samplers_offset
) {
2512 const struct tu_sampler
*immutable_samplers
=
2513 tu_immutable_samplers(set
->layout
, layout
);
2515 return &immutable_samplers
[array_index
];
2518 switch (layout
->type
) {
2519 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2520 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4];
2521 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2522 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4 + A6XX_TEX_CONST_DWORDS
+
2524 (A6XX_TEX_CONST_DWORDS
+
2525 sizeof(struct tu_sampler
) / 4)];
2527 unreachable("unimplemented descriptor type");
2533 write_tex_const(struct tu_cmd_buffer
*cmd
,
2535 struct tu_descriptor_state
*descriptors_state
,
2536 const struct tu_descriptor_map
*map
,
2537 unsigned i
, unsigned array_index
)
2539 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2541 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2542 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2544 const struct tu_descriptor_set_binding_layout
*layout
=
2545 &set
->layout
->binding
[map
->binding
[i
]];
2547 switch (layout
->type
) {
2548 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
2549 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2550 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2551 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2552 memcpy(dst
, &set
->mapped_ptr
[layout
->offset
/ 4 +
2553 array_index
* A6XX_TEX_CONST_DWORDS
],
2554 A6XX_TEX_CONST_DWORDS
* 4);
2556 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2557 memcpy(dst
, &set
->mapped_ptr
[layout
->offset
/ 4 +
2559 (A6XX_TEX_CONST_DWORDS
+
2560 sizeof(struct tu_sampler
) / 4)],
2561 A6XX_TEX_CONST_DWORDS
* 4);
2564 unreachable("unimplemented descriptor type");
2568 if (layout
->type
== VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
) {
2569 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2570 uint32_t a
= cmd
->state
.subpass
->input_attachments
[map
->value
[i
] +
2571 array_index
].attachment
;
2572 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2574 assert(att
->gmem_offset
>= 0);
2576 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2577 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2578 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2580 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2581 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2583 dst
[4] = 0x100000 + att
->gmem_offset
;
2584 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2585 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2588 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2589 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2594 write_image_ibo(struct tu_cmd_buffer
*cmd
,
2596 struct tu_descriptor_state
*descriptors_state
,
2597 const struct tu_descriptor_map
*map
,
2598 unsigned i
, unsigned array_index
)
2600 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2602 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2603 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2605 const struct tu_descriptor_set_binding_layout
*layout
=
2606 &set
->layout
->binding
[map
->binding
[i
]];
2608 assert(layout
->type
== VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
);
2610 memcpy(dst
, &set
->mapped_ptr
[layout
->offset
/ 4 +
2611 (array_index
* 2 + 1) * A6XX_TEX_CONST_DWORDS
],
2612 A6XX_TEX_CONST_DWORDS
* 4);
2616 buffer_ptr(struct tu_descriptor_state
*descriptors_state
,
2617 const struct tu_descriptor_map
*map
,
2618 unsigned i
, unsigned array_index
)
2620 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2622 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2623 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2625 const struct tu_descriptor_set_binding_layout
*layout
=
2626 &set
->layout
->binding
[map
->binding
[i
]];
2628 switch (layout
->type
) {
2629 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2630 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
2631 return descriptors_state
->dynamic_buffers
[layout
->dynamic_offset_offset
+
2633 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2634 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2635 return (uint64_t) set
->mapped_ptr
[layout
->offset
/ 4 + array_index
* 2 + 1] << 32 |
2636 set
->mapped_ptr
[layout
->offset
/ 4 + array_index
* 2];
2638 unreachable("unimplemented descriptor type");
2643 static inline uint32_t
2644 tu6_stage2opcode(gl_shader_stage type
)
2647 case MESA_SHADER_VERTEX
:
2648 case MESA_SHADER_TESS_CTRL
:
2649 case MESA_SHADER_TESS_EVAL
:
2650 case MESA_SHADER_GEOMETRY
:
2651 return CP_LOAD_STATE6_GEOM
;
2652 case MESA_SHADER_FRAGMENT
:
2653 case MESA_SHADER_COMPUTE
:
2654 case MESA_SHADER_KERNEL
:
2655 return CP_LOAD_STATE6_FRAG
;
2657 unreachable("bad shader type");
2661 static inline enum a6xx_state_block
2662 tu6_stage2shadersb(gl_shader_stage type
)
2665 case MESA_SHADER_VERTEX
:
2666 return SB6_VS_SHADER
;
2667 case MESA_SHADER_FRAGMENT
:
2668 return SB6_FS_SHADER
;
2669 case MESA_SHADER_COMPUTE
:
2670 case MESA_SHADER_KERNEL
:
2671 return SB6_CS_SHADER
;
2673 unreachable("bad shader type");
2679 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2680 struct tu_descriptor_state
*descriptors_state
,
2681 gl_shader_stage type
,
2682 uint32_t *push_constants
)
2684 const struct tu_program_descriptor_linkage
*link
=
2685 &pipeline
->program
.link
[type
];
2686 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2688 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
2689 if (state
->range
[i
].start
< state
->range
[i
].end
) {
2690 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2691 uint32_t offset
= state
->range
[i
].start
;
2693 /* and even if the start of the const buffer is before
2694 * first_immediate, the end may not be:
2696 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2701 /* things should be aligned to vec4: */
2702 debug_assert((state
->range
[i
].offset
% 16) == 0);
2703 debug_assert((size
% 16) == 0);
2704 debug_assert((offset
% 16) == 0);
2707 /* push constants */
2708 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (size
/ 4));
2709 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2710 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2711 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2712 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2713 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2716 for (unsigned i
= 0; i
< size
/ 4; i
++)
2717 tu_cs_emit(cs
, push_constants
[i
+ offset
/ 4]);
2721 /* Look through the UBO map to find our UBO index, and get the VA for
2725 uint32_t ubo_idx
= i
- 1;
2726 uint32_t ubo_map_base
= 0;
2727 for (int j
= 0; j
< link
->ubo_map
.num
; j
++) {
2728 if (ubo_idx
>= ubo_map_base
&&
2729 ubo_idx
< ubo_map_base
+ link
->ubo_map
.array_size
[j
]) {
2730 va
= buffer_ptr(descriptors_state
, &link
->ubo_map
, j
,
2731 ubo_idx
- ubo_map_base
);
2734 ubo_map_base
+= link
->ubo_map
.array_size
[j
];
2738 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2739 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2740 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2741 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2742 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2743 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2744 tu_cs_emit_qw(cs
, va
+ offset
);
2750 tu6_emit_ubos(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2751 struct tu_descriptor_state
*descriptors_state
,
2752 gl_shader_stage type
)
2754 const struct tu_program_descriptor_linkage
*link
=
2755 &pipeline
->program
.link
[type
];
2757 uint32_t num
= MIN2(link
->ubo_map
.num_desc
, link
->const_state
.num_ubos
);
2758 uint32_t anum
= align(num
, 2);
2763 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (2 * anum
));
2764 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(link
->const_state
.offsets
.ubo
) |
2765 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2766 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2767 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2768 CP_LOAD_STATE6_0_NUM_UNIT(anum
/2));
2769 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2770 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2772 unsigned emitted
= 0;
2773 for (unsigned i
= 0; emitted
< num
&& i
< link
->ubo_map
.num
; i
++) {
2774 for (unsigned j
= 0; emitted
< num
&& j
< link
->ubo_map
.array_size
[i
]; j
++) {
2775 tu_cs_emit_qw(cs
, buffer_ptr(descriptors_state
, &link
->ubo_map
, i
, j
));
2780 for (; emitted
< anum
; emitted
++) {
2781 tu_cs_emit(cs
, 0xffffffff);
2782 tu_cs_emit(cs
, 0xffffffff);
2786 static struct tu_cs_entry
2787 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2788 const struct tu_pipeline
*pipeline
,
2789 struct tu_descriptor_state
*descriptors_state
,
2790 gl_shader_stage type
)
2793 tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2795 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2796 tu6_emit_ubos(&cs
, pipeline
, descriptors_state
, type
);
2798 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2802 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2803 const struct tu_draw_info
*draw
,
2804 struct tu_cs_entry
*entry
)
2806 /* TODO: fill out more than just base instance */
2807 const struct tu_program_descriptor_linkage
*link
=
2808 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2809 const struct ir3_const_state
*const_state
= &link
->const_state
;
2812 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2813 *entry
= (struct tu_cs_entry
) {};
2817 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
, 8, &cs
);
2818 if (result
!= VK_SUCCESS
)
2821 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2822 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2823 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2824 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2825 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2826 CP_LOAD_STATE6_0_NUM_UNIT(1));
2830 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2834 tu_cs_emit(&cs
, draw
->first_instance
);
2837 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2842 tu6_emit_textures(struct tu_cmd_buffer
*cmd
,
2843 const struct tu_pipeline
*pipeline
,
2844 struct tu_descriptor_state
*descriptors_state
,
2845 gl_shader_stage type
,
2846 struct tu_cs_entry
*entry
,
2849 struct tu_device
*device
= cmd
->device
;
2850 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2851 const struct tu_program_descriptor_linkage
*link
=
2852 &pipeline
->program
.link
[type
];
2855 if (link
->texture_map
.num_desc
== 0 && link
->sampler_map
.num_desc
== 0) {
2856 *entry
= (struct tu_cs_entry
) {};
2860 /* allocate and fill texture state */
2861 struct ts_cs_memory tex_const
;
2862 result
= tu_cs_alloc(device
, draw_state
, link
->texture_map
.num_desc
,
2863 A6XX_TEX_CONST_DWORDS
, &tex_const
);
2864 if (result
!= VK_SUCCESS
)
2868 for (unsigned i
= 0; i
< link
->texture_map
.num
; i
++) {
2869 for (int j
= 0; j
< link
->texture_map
.array_size
[i
]; j
++) {
2870 write_tex_const(cmd
,
2871 &tex_const
.map
[A6XX_TEX_CONST_DWORDS
* tex_index
++],
2872 descriptors_state
, &link
->texture_map
, i
, j
);
2876 /* allocate and fill sampler state */
2877 struct ts_cs_memory tex_samp
= { 0 };
2878 if (link
->sampler_map
.num_desc
) {
2879 result
= tu_cs_alloc(device
, draw_state
, link
->sampler_map
.num_desc
,
2880 A6XX_TEX_SAMP_DWORDS
, &tex_samp
);
2881 if (result
!= VK_SUCCESS
)
2884 int sampler_index
= 0;
2885 for (unsigned i
= 0; i
< link
->sampler_map
.num
; i
++) {
2886 for (int j
= 0; j
< link
->sampler_map
.array_size
[i
]; j
++) {
2887 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
2890 memcpy(&tex_samp
.map
[A6XX_TEX_SAMP_DWORDS
* sampler_index
++],
2891 sampler
->state
, sizeof(sampler
->state
));
2892 *needs_border
|= sampler
->needs_border
;
2897 unsigned tex_samp_reg
, tex_const_reg
, tex_count_reg
;
2898 enum a6xx_state_block sb
;
2901 case MESA_SHADER_VERTEX
:
2903 tex_samp_reg
= REG_A6XX_SP_VS_TEX_SAMP_LO
;
2904 tex_const_reg
= REG_A6XX_SP_VS_TEX_CONST_LO
;
2905 tex_count_reg
= REG_A6XX_SP_VS_TEX_COUNT
;
2907 case MESA_SHADER_FRAGMENT
:
2909 tex_samp_reg
= REG_A6XX_SP_FS_TEX_SAMP_LO
;
2910 tex_const_reg
= REG_A6XX_SP_FS_TEX_CONST_LO
;
2911 tex_count_reg
= REG_A6XX_SP_FS_TEX_COUNT
;
2913 case MESA_SHADER_COMPUTE
:
2915 tex_samp_reg
= REG_A6XX_SP_CS_TEX_SAMP_LO
;
2916 tex_const_reg
= REG_A6XX_SP_CS_TEX_CONST_LO
;
2917 tex_count_reg
= REG_A6XX_SP_CS_TEX_COUNT
;
2920 unreachable("bad state block");
2924 result
= tu_cs_begin_sub_stream(device
, draw_state
, 16, &cs
);
2925 if (result
!= VK_SUCCESS
)
2928 if (link
->sampler_map
.num_desc
) {
2929 /* output sampler state: */
2930 tu_cs_emit_pkt7(&cs
, tu6_stage2opcode(type
), 3);
2931 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2932 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
2933 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2934 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2935 CP_LOAD_STATE6_0_NUM_UNIT(link
->sampler_map
.num_desc
));
2936 tu_cs_emit_qw(&cs
, tex_samp
.iova
); /* SRC_ADDR_LO/HI */
2938 tu_cs_emit_pkt4(&cs
, tex_samp_reg
, 2);
2939 tu_cs_emit_qw(&cs
, tex_samp
.iova
); /* SRC_ADDR_LO/HI */
2942 /* emit texture state: */
2943 tu_cs_emit_pkt7(&cs
, tu6_stage2opcode(type
), 3);
2944 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2945 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2946 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2947 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2948 CP_LOAD_STATE6_0_NUM_UNIT(link
->texture_map
.num_desc
));
2949 tu_cs_emit_qw(&cs
, tex_const
.iova
); /* SRC_ADDR_LO/HI */
2951 tu_cs_emit_pkt4(&cs
, tex_const_reg
, 2);
2952 tu_cs_emit_qw(&cs
, tex_const
.iova
); /* SRC_ADDR_LO/HI */
2954 tu_cs_emit_pkt4(&cs
, tex_count_reg
, 1);
2955 tu_cs_emit(&cs
, link
->texture_map
.num_desc
);
2957 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2962 tu6_emit_ibo(struct tu_cmd_buffer
*cmd
,
2963 const struct tu_pipeline
*pipeline
,
2964 struct tu_descriptor_state
*descriptors_state
,
2965 gl_shader_stage type
,
2966 struct tu_cs_entry
*entry
)
2968 struct tu_device
*device
= cmd
->device
;
2969 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2970 const struct tu_program_descriptor_linkage
*link
=
2971 &pipeline
->program
.link
[type
];
2974 unsigned num_desc
= link
->ssbo_map
.num_desc
+ link
->image_map
.num_desc
;
2976 if (num_desc
== 0) {
2977 *entry
= (struct tu_cs_entry
) {};
2981 struct ts_cs_memory ibo_const
;
2982 result
= tu_cs_alloc(device
, draw_state
, num_desc
,
2983 A6XX_TEX_CONST_DWORDS
, &ibo_const
);
2984 if (result
!= VK_SUCCESS
)
2988 for (unsigned i
= 0; i
< link
->ssbo_map
.num
; i
++) {
2989 for (int j
= 0; j
< link
->ssbo_map
.array_size
[i
]; j
++) {
2990 uint32_t *dst
= &ibo_const
.map
[A6XX_TEX_CONST_DWORDS
* ssbo_index
];
2992 uint64_t va
= buffer_ptr(descriptors_state
, &link
->ssbo_map
, i
, j
);
2993 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2994 uint32_t sz
= MAX_STORAGE_BUFFER_RANGE
/ 4;
2996 dst
[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT
);
2997 dst
[1] = A6XX_IBO_1_WIDTH(sz
& MASK(15)) |
2998 A6XX_IBO_1_HEIGHT(sz
>> 15);
2999 dst
[2] = A6XX_IBO_2_UNK4
|
3001 A6XX_IBO_2_TYPE(A6XX_TEX_1D
);
3005 for (int i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
3012 for (unsigned i
= 0; i
< link
->image_map
.num
; i
++) {
3013 for (int j
= 0; j
< link
->image_map
.array_size
[i
]; j
++) {
3014 uint32_t *dst
= &ibo_const
.map
[A6XX_TEX_CONST_DWORDS
* ssbo_index
];
3016 write_image_ibo(cmd
, dst
,
3017 descriptors_state
, &link
->image_map
, i
, j
);
3023 assert(ssbo_index
== num_desc
);
3026 result
= tu_cs_begin_sub_stream(device
, draw_state
, 7, &cs
);
3027 if (result
!= VK_SUCCESS
)
3030 uint32_t opcode
, ibo_addr_reg
;
3031 enum a6xx_state_block sb
;
3032 enum a6xx_state_type st
;
3035 case MESA_SHADER_FRAGMENT
:
3036 opcode
= CP_LOAD_STATE6
;
3039 ibo_addr_reg
= REG_A6XX_SP_IBO_LO
;
3041 case MESA_SHADER_COMPUTE
:
3042 opcode
= CP_LOAD_STATE6_FRAG
;
3045 ibo_addr_reg
= REG_A6XX_SP_CS_IBO_LO
;
3048 unreachable("unsupported stage for ibos");
3051 /* emit texture state: */
3052 tu_cs_emit_pkt7(&cs
, opcode
, 3);
3053 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
3054 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
3055 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
3056 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
3057 CP_LOAD_STATE6_0_NUM_UNIT(num_desc
));
3058 tu_cs_emit_qw(&cs
, ibo_const
.iova
); /* SRC_ADDR_LO/HI */
3060 tu_cs_emit_pkt4(&cs
, ibo_addr_reg
, 2);
3061 tu_cs_emit_qw(&cs
, ibo_const
.iova
); /* SRC_ADDR_LO/HI */
3063 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
3067 struct PACKED bcolor_entry
{
3079 uint32_t z24
; /* also s8? */
3080 uint16_t srgb
[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
3082 } border_color
[] = {
3083 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
] = {},
3084 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
] = {},
3085 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
] = {
3086 .fp32
[3] = 0x3f800000,
3094 .rgb10a2
= 0xc0000000,
3097 [VK_BORDER_COLOR_INT_OPAQUE_BLACK
] = {
3101 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
] = {
3102 .fp32
[0 ... 3] = 0x3f800000,
3103 .ui16
[0 ... 3] = 0xffff,
3104 .si16
[0 ... 3] = 0x7fff,
3105 .fp16
[0 ... 3] = 0x3c00,
3109 .ui8
[0 ... 3] = 0xff,
3110 .si8
[0 ... 3] = 0x7f,
3111 .rgb10a2
= 0xffffffff,
3113 .srgb
[0 ... 3] = 0x3c00,
3115 [VK_BORDER_COLOR_INT_OPAQUE_WHITE
] = {
3122 tu6_emit_border_color(struct tu_cmd_buffer
*cmd
,
3125 STATIC_ASSERT(sizeof(struct bcolor_entry
) == 128);
3127 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3128 struct tu_descriptor_state
*descriptors_state
=
3129 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3130 const struct tu_descriptor_map
*vs_sampler
=
3131 &pipeline
->program
.link
[MESA_SHADER_VERTEX
].sampler_map
;
3132 const struct tu_descriptor_map
*fs_sampler
=
3133 &pipeline
->program
.link
[MESA_SHADER_FRAGMENT
].sampler_map
;
3134 struct ts_cs_memory ptr
;
3136 VkResult result
= tu_cs_alloc(cmd
->device
, &cmd
->sub_cs
,
3137 vs_sampler
->num_desc
+ fs_sampler
->num_desc
,
3140 if (result
!= VK_SUCCESS
)
3143 for (unsigned i
= 0; i
< vs_sampler
->num
; i
++) {
3144 for (unsigned j
= 0; j
< vs_sampler
->array_size
[i
]; j
++) {
3145 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
3147 memcpy(ptr
.map
, &border_color
[sampler
->border
], 128);
3152 for (unsigned i
= 0; i
< fs_sampler
->num
; i
++) {
3153 for (unsigned j
= 0; j
< fs_sampler
->array_size
[i
]; j
++) {
3154 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
3156 memcpy(ptr
.map
, &border_color
[sampler
->border
], 128);
3161 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
3162 tu_cs_emit_qw(cs
, ptr
.iova
);
3167 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
3169 const struct tu_draw_info
*draw
)
3171 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3172 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
3173 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
3174 uint32_t draw_state_group_count
= 0;
3176 struct tu_descriptor_state
*descriptors_state
=
3177 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3179 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
3180 if (result
!= VK_SUCCESS
)
3185 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
3186 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
3187 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
3190 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
3191 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
3193 if (cmd
->state
.dirty
&
3194 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
3195 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
3196 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
3197 dynamic
->line_width
);
3200 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
3201 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
3202 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
3203 dynamic
->stencil_compare_mask
.back
);
3206 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
3207 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
3208 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
3209 dynamic
->stencil_write_mask
.back
);
3212 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
3213 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
3214 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
3215 dynamic
->stencil_reference
.back
);
3218 if (cmd
->state
.dirty
&
3219 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
3220 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
3221 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
3222 const uint32_t stride
= pipeline
->vi
.strides
[i
];
3223 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
3224 const VkDeviceSize offset
= buf
->bo_offset
+
3225 cmd
->state
.vb
.offsets
[binding
] +
3226 pipeline
->vi
.offsets
[i
];
3227 const VkDeviceSize size
=
3228 offset
< buf
->bo
->size
? buf
->bo
->size
- offset
: 0;
3231 A6XX_VFD_FETCH_BASE(i
, .bo
= buf
->bo
, .bo_offset
= offset
),
3232 A6XX_VFD_FETCH_SIZE(i
, size
),
3233 A6XX_VFD_FETCH_STRIDE(i
, stride
));
3237 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
3238 draw_state_groups
[draw_state_group_count
++] =
3239 (struct tu_draw_state_group
) {
3240 .id
= TU_DRAW_STATE_PROGRAM
,
3241 .enable_mask
= ENABLE_DRAW
,
3242 .ib
= pipeline
->program
.state_ib
,
3244 draw_state_groups
[draw_state_group_count
++] =
3245 (struct tu_draw_state_group
) {
3246 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
3247 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
3248 .ib
= pipeline
->program
.binning_state_ib
,
3250 draw_state_groups
[draw_state_group_count
++] =
3251 (struct tu_draw_state_group
) {
3252 .id
= TU_DRAW_STATE_VI
,
3253 .enable_mask
= ENABLE_DRAW
,
3254 .ib
= pipeline
->vi
.state_ib
,
3256 draw_state_groups
[draw_state_group_count
++] =
3257 (struct tu_draw_state_group
) {
3258 .id
= TU_DRAW_STATE_VI_BINNING
,
3259 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
3260 .ib
= pipeline
->vi
.binning_state_ib
,
3262 draw_state_groups
[draw_state_group_count
++] =
3263 (struct tu_draw_state_group
) {
3264 .id
= TU_DRAW_STATE_VP
,
3265 .enable_mask
= ENABLE_ALL
,
3266 .ib
= pipeline
->vp
.state_ib
,
3268 draw_state_groups
[draw_state_group_count
++] =
3269 (struct tu_draw_state_group
) {
3270 .id
= TU_DRAW_STATE_RAST
,
3271 .enable_mask
= ENABLE_ALL
,
3272 .ib
= pipeline
->rast
.state_ib
,
3274 draw_state_groups
[draw_state_group_count
++] =
3275 (struct tu_draw_state_group
) {
3276 .id
= TU_DRAW_STATE_DS
,
3277 .enable_mask
= ENABLE_ALL
,
3278 .ib
= pipeline
->ds
.state_ib
,
3280 draw_state_groups
[draw_state_group_count
++] =
3281 (struct tu_draw_state_group
) {
3282 .id
= TU_DRAW_STATE_BLEND
,
3283 .enable_mask
= ENABLE_ALL
,
3284 .ib
= pipeline
->blend
.state_ib
,
3288 if (cmd
->state
.dirty
&
3289 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
3290 draw_state_groups
[draw_state_group_count
++] =
3291 (struct tu_draw_state_group
) {
3292 .id
= TU_DRAW_STATE_VS_CONST
,
3293 .enable_mask
= ENABLE_ALL
,
3294 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
3296 draw_state_groups
[draw_state_group_count
++] =
3297 (struct tu_draw_state_group
) {
3298 .id
= TU_DRAW_STATE_FS_CONST
,
3299 .enable_mask
= ENABLE_DRAW
,
3300 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3304 if (cmd
->state
.dirty
&
3305 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
)) {
3306 bool needs_border
= false;
3307 struct tu_cs_entry vs_tex
, fs_tex
, fs_ibo
;
3309 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3310 MESA_SHADER_VERTEX
, &vs_tex
, &needs_border
);
3311 if (result
!= VK_SUCCESS
)
3314 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3315 MESA_SHADER_FRAGMENT
, &fs_tex
, &needs_border
);
3316 if (result
!= VK_SUCCESS
)
3319 result
= tu6_emit_ibo(cmd
, pipeline
, descriptors_state
,
3320 MESA_SHADER_FRAGMENT
, &fs_ibo
);
3321 if (result
!= VK_SUCCESS
)
3324 draw_state_groups
[draw_state_group_count
++] =
3325 (struct tu_draw_state_group
) {
3326 .id
= TU_DRAW_STATE_VS_TEX
,
3327 .enable_mask
= ENABLE_ALL
,
3330 draw_state_groups
[draw_state_group_count
++] =
3331 (struct tu_draw_state_group
) {
3332 .id
= TU_DRAW_STATE_FS_TEX
,
3333 .enable_mask
= ENABLE_DRAW
,
3336 draw_state_groups
[draw_state_group_count
++] =
3337 (struct tu_draw_state_group
) {
3338 .id
= TU_DRAW_STATE_FS_IBO
,
3339 .enable_mask
= ENABLE_DRAW
,
3344 result
= tu6_emit_border_color(cmd
, cs
);
3345 if (result
!= VK_SUCCESS
)
3350 struct tu_cs_entry vs_params
;
3351 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3352 if (result
!= VK_SUCCESS
)
3355 draw_state_groups
[draw_state_group_count
++] =
3356 (struct tu_draw_state_group
) {
3357 .id
= TU_DRAW_STATE_VS_PARAMS
,
3358 .enable_mask
= ENABLE_ALL
,
3362 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3363 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3364 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3365 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3366 uint32_t cp_set_draw_state
=
3367 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3368 group
->enable_mask
|
3369 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3371 if (group
->ib
.size
) {
3372 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3374 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3378 tu_cs_emit(cs
, cp_set_draw_state
);
3379 tu_cs_emit_qw(cs
, iova
);
3382 tu_cs_sanity_check(cs
);
3385 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3386 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3387 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3389 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3392 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3394 for_each_bit(i
, descriptors_state
->valid
) {
3395 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3396 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3397 if (set
->descriptors
[j
]) {
3398 tu_bo_list_add(&cmd
->bo_list
, set
->descriptors
[j
],
3399 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3404 /* Fragment shader state overwrites compute shader state, so flag the
3405 * compute pipeline for re-emit.
3407 cmd
->state
.dirty
= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3412 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3414 const struct tu_draw_info
*draw
)
3417 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3420 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3421 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3423 /* TODO hw binning */
3424 if (draw
->indexed
) {
3425 const enum a4xx_index_size index_size
=
3426 tu6_index_size(cmd
->state
.index_type
);
3427 const uint32_t index_bytes
=
3428 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3429 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3430 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3431 index_bytes
* draw
->first_index
;
3432 const uint32_t size
= index_bytes
* draw
->count
;
3434 const uint32_t cp_draw_indx
=
3435 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3436 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3437 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3438 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) | 0x2000;
3440 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3441 tu_cs_emit(cs
, cp_draw_indx
);
3442 tu_cs_emit(cs
, draw
->instance_count
);
3443 tu_cs_emit(cs
, draw
->count
);
3444 tu_cs_emit(cs
, 0x0); /* XXX */
3445 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3446 tu_cs_emit(cs
, size
);
3448 const uint32_t cp_draw_indx
=
3449 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3450 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3451 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) | 0x2000;
3453 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3454 tu_cs_emit(cs
, cp_draw_indx
);
3455 tu_cs_emit(cs
, draw
->instance_count
);
3456 tu_cs_emit(cs
, draw
->count
);
3461 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3463 struct tu_cs
*cs
= &cmd
->draw_cs
;
3466 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3467 if (result
!= VK_SUCCESS
) {
3468 cmd
->record_result
= result
;
3472 result
= tu_cs_reserve_space(cmd
->device
, cs
, 32);
3473 if (result
!= VK_SUCCESS
) {
3474 cmd
->record_result
= result
;
3478 if (draw
->indirect
) {
3479 tu_finishme("indirect draw");
3483 /* TODO tu6_emit_marker should pick different regs depending on cs */
3485 tu6_emit_marker(cmd
, cs
);
3486 tu6_emit_draw_direct(cmd
, cs
, draw
);
3487 tu6_emit_marker(cmd
, cs
);
3489 cmd
->wait_for_idle
= true;
3491 tu_cs_sanity_check(cs
);
3495 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3496 uint32_t vertexCount
,
3497 uint32_t instanceCount
,
3498 uint32_t firstVertex
,
3499 uint32_t firstInstance
)
3501 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3502 struct tu_draw_info info
= {};
3504 info
.count
= vertexCount
;
3505 info
.instance_count
= instanceCount
;
3506 info
.first_instance
= firstInstance
;
3507 info
.vertex_offset
= firstVertex
;
3509 tu_draw(cmd_buffer
, &info
);
3513 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3514 uint32_t indexCount
,
3515 uint32_t instanceCount
,
3516 uint32_t firstIndex
,
3517 int32_t vertexOffset
,
3518 uint32_t firstInstance
)
3520 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3521 struct tu_draw_info info
= {};
3523 info
.indexed
= true;
3524 info
.count
= indexCount
;
3525 info
.instance_count
= instanceCount
;
3526 info
.first_index
= firstIndex
;
3527 info
.vertex_offset
= vertexOffset
;
3528 info
.first_instance
= firstInstance
;
3530 tu_draw(cmd_buffer
, &info
);
3534 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3536 VkDeviceSize offset
,
3540 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3541 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3542 struct tu_draw_info info
= {};
3544 info
.count
= drawCount
;
3545 info
.indirect
= buffer
;
3546 info
.indirect_offset
= offset
;
3547 info
.stride
= stride
;
3549 tu_draw(cmd_buffer
, &info
);
3553 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3555 VkDeviceSize offset
,
3559 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3560 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3561 struct tu_draw_info info
= {};
3563 info
.indexed
= true;
3564 info
.count
= drawCount
;
3565 info
.indirect
= buffer
;
3566 info
.indirect_offset
= offset
;
3567 info
.stride
= stride
;
3569 tu_draw(cmd_buffer
, &info
);
3572 struct tu_dispatch_info
3575 * Determine the layout of the grid (in block units) to be used.
3580 * A starting offset for the grid. If unaligned is set, the offset
3581 * must still be aligned.
3583 uint32_t offsets
[3];
3585 * Whether it's an unaligned compute dispatch.
3590 * Indirect compute parameters resource.
3592 struct tu_buffer
*indirect
;
3593 uint64_t indirect_offset
;
3597 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3598 const struct tu_dispatch_info
*info
)
3600 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3601 const struct tu_program_descriptor_linkage
*link
=
3602 &pipeline
->program
.link
[type
];
3603 const struct ir3_const_state
*const_state
= &link
->const_state
;
3604 uint32_t offset
= const_state
->offsets
.driver_param
;
3606 if (link
->constlen
<= offset
)
3609 if (!info
->indirect
) {
3610 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3611 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3612 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3613 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3614 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3615 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3616 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3619 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3620 (link
->constlen
- offset
) * 4);
3621 /* push constants */
3622 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3623 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3624 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3625 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3626 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3627 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3631 for (i
= 0; i
< num_consts
; i
++)
3632 tu_cs_emit(cs
, driver_params
[i
]);
3634 tu_finishme("Indirect driver params");
3639 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3640 const struct tu_dispatch_info
*info
)
3642 struct tu_cs
*cs
= &cmd
->cs
;
3643 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3644 struct tu_descriptor_state
*descriptors_state
=
3645 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3647 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
3648 if (result
!= VK_SUCCESS
) {
3649 cmd
->record_result
= result
;
3653 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3654 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3656 struct tu_cs_entry ib
;
3658 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3660 tu_cs_emit_ib(cs
, &ib
);
3662 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3665 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3666 MESA_SHADER_COMPUTE
, &ib
, &needs_border
);
3667 if (result
!= VK_SUCCESS
) {
3668 cmd
->record_result
= result
;
3673 tu_cs_emit_ib(cs
, &ib
);
3676 tu_finishme("compute border color");
3678 result
= tu6_emit_ibo(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
, &ib
);
3679 if (result
!= VK_SUCCESS
) {
3680 cmd
->record_result
= result
;
3685 tu_cs_emit_ib(cs
, &ib
);
3688 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3690 for_each_bit(i
, descriptors_state
->valid
) {
3691 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3692 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3693 if (set
->descriptors
[j
]) {
3694 tu_bo_list_add(&cmd
->bo_list
, set
->descriptors
[j
],
3695 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3700 /* Compute shader state overwrites fragment shader state, so we flag the
3701 * graphics pipeline for re-emit.
3703 cmd
->state
.dirty
= TU_CMD_DIRTY_PIPELINE
;
3705 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3706 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x8));
3708 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3709 const uint32_t *num_groups
= info
->blocks
;
3711 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3712 .localsizex
= local_size
[0] - 1,
3713 .localsizey
= local_size
[1] - 1,
3714 .localsizez
= local_size
[2] - 1),
3715 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3716 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3717 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3718 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3719 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3720 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3723 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3724 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3725 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3727 if (info
->indirect
) {
3728 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3730 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3731 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3733 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3734 tu_cs_emit(cs
, 0x00000000);
3735 tu_cs_emit_qw(cs
, iova
);
3737 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3738 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3739 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3741 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3742 tu_cs_emit(cs
, 0x00000000);
3743 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3744 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3745 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3750 tu6_emit_cache_flush(cmd
, cs
);
3754 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3762 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3763 struct tu_dispatch_info info
= {};
3769 info
.offsets
[0] = base_x
;
3770 info
.offsets
[1] = base_y
;
3771 info
.offsets
[2] = base_z
;
3772 tu_dispatch(cmd_buffer
, &info
);
3776 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3781 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3785 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3787 VkDeviceSize offset
)
3789 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3790 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3791 struct tu_dispatch_info info
= {};
3793 info
.indirect
= buffer
;
3794 info
.indirect_offset
= offset
;
3796 tu_dispatch(cmd_buffer
, &info
);
3800 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3802 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3804 tu_cs_end(&cmd_buffer
->draw_cs
);
3805 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3807 tu_cmd_render_tiles(cmd_buffer
);
3809 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3811 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3812 tu_cs_begin(&cmd_buffer
->draw_cs
);
3813 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3814 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3816 cmd_buffer
->state
.pass
= NULL
;
3817 cmd_buffer
->state
.subpass
= NULL
;
3818 cmd_buffer
->state
.framebuffer
= NULL
;
3822 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3823 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3825 tu_CmdEndRenderPass(commandBuffer
);
3828 struct tu_barrier_info
3830 uint32_t eventCount
;
3831 const VkEvent
*pEvents
;
3832 VkPipelineStageFlags srcStageMask
;
3836 tu_barrier(struct tu_cmd_buffer
*cmd_buffer
,
3837 uint32_t memoryBarrierCount
,
3838 const VkMemoryBarrier
*pMemoryBarriers
,
3839 uint32_t bufferMemoryBarrierCount
,
3840 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3841 uint32_t imageMemoryBarrierCount
,
3842 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3843 const struct tu_barrier_info
*info
)
3848 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3849 VkPipelineStageFlags srcStageMask
,
3850 VkPipelineStageFlags destStageMask
,
3852 uint32_t memoryBarrierCount
,
3853 const VkMemoryBarrier
*pMemoryBarriers
,
3854 uint32_t bufferMemoryBarrierCount
,
3855 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3856 uint32_t imageMemoryBarrierCount
,
3857 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3859 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3860 struct tu_barrier_info info
;
3862 info
.eventCount
= 0;
3863 info
.pEvents
= NULL
;
3864 info
.srcStageMask
= srcStageMask
;
3866 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3867 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3868 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3872 write_event(struct tu_cmd_buffer
*cmd_buffer
,
3873 struct tu_event
*event
,
3874 VkPipelineStageFlags stageMask
,
3880 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3882 VkPipelineStageFlags stageMask
)
3884 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3885 TU_FROM_HANDLE(tu_event
, event
, _event
);
3887 write_event(cmd_buffer
, event
, stageMask
, 1);
3891 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3893 VkPipelineStageFlags stageMask
)
3895 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3896 TU_FROM_HANDLE(tu_event
, event
, _event
);
3898 write_event(cmd_buffer
, event
, stageMask
, 0);
3902 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3903 uint32_t eventCount
,
3904 const VkEvent
*pEvents
,
3905 VkPipelineStageFlags srcStageMask
,
3906 VkPipelineStageFlags dstStageMask
,
3907 uint32_t memoryBarrierCount
,
3908 const VkMemoryBarrier
*pMemoryBarriers
,
3909 uint32_t bufferMemoryBarrierCount
,
3910 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3911 uint32_t imageMemoryBarrierCount
,
3912 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3914 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3915 struct tu_barrier_info info
;
3917 info
.eventCount
= eventCount
;
3918 info
.pEvents
= pEvents
;
3919 info
.srcStageMask
= 0;
3921 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3922 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3923 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3927 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)