projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
turnip: MSAA resolve directly from GMEM
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 for (uint32_t i = 0; i < list->count; ++i) {
66 if (list->bo_infos[i].handle == bo_info->handle) {
67 assert(list->bo_infos[i].presumed == bo_info->presumed);
68 list->bo_infos[i].flags |= bo_info->flags;
69 return i;
70 }
71 }
72
73 /* grow list->bo_infos if needed */
74 if (list->count == list->capacity) {
75 uint32_t new_capacity = MAX2(2 * list->count, 16);
76 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
77 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
78 if (!new_bo_infos)
79 return TU_BO_LIST_FAILED;
80 list->bo_infos = new_bo_infos;
81 list->capacity = new_capacity;
82 }
83
84 list->bo_infos[list->count] = *bo_info;
85 return list->count++;
86 }
87
88 uint32_t
89 tu_bo_list_add(struct tu_bo_list *list,
90 const struct tu_bo *bo,
91 uint32_t flags)
92 {
93 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
94 .flags = flags,
95 .handle = bo->gem_handle,
96 .presumed = bo->iova,
97 });
98 }
99
100 VkResult
101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
102 {
103 for (uint32_t i = 0; i < other->count; i++) {
104 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
105 return VK_ERROR_OUT_OF_HOST_MEMORY;
106 }
107
108 return VK_SUCCESS;
109 }
110
111 static VkResult
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
113 const struct tu_device *dev)
114 {
115 const uint32_t gmem_size = dev->physical_device->gmem_size;
116 uint32_t offset = 0;
117
118 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
119 /* 16KB-aligned */
120 offset = align(offset, 0x4000);
121
122 tiling->gmem_offsets[i] = offset;
123 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
124 tiling->buffer_cpp[i];
125 }
126
127 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
128 }
129
130 static void
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
132 const struct tu_device *dev)
133 {
134 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
135 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
136 const uint32_t max_tile_width = 1024; /* A6xx */
137
138 tiling->tile0.offset = (VkOffset2D) {
139 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
140 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
141 };
142
143 const uint32_t ra_width =
144 tiling->render_area.extent.width +
145 (tiling->render_area.offset.x - tiling->tile0.offset.x);
146 const uint32_t ra_height =
147 tiling->render_area.extent.height +
148 (tiling->render_area.offset.y - tiling->tile0.offset.y);
149
150 /* start from 1 tile */
151 tiling->tile_count = (VkExtent2D) {
152 .width = 1,
153 .height = 1,
154 };
155 tiling->tile0.extent = (VkExtent2D) {
156 .width = align(ra_width, tile_align_w),
157 .height = align(ra_height, tile_align_h),
158 };
159
160 /* do not exceed max tile width */
161 while (tiling->tile0.extent.width > max_tile_width) {
162 tiling->tile_count.width++;
163 tiling->tile0.extent.width =
164 align(ra_width / tiling->tile_count.width, tile_align_w);
165 }
166
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
169 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
170 tiling->tile_count.width++;
171 tiling->tile0.extent.width =
172 align(ra_width / tiling->tile_count.width, tile_align_w);
173 } else {
174 tiling->tile_count.height++;
175 tiling->tile0.extent.height =
176 align(ra_height / tiling->tile_count.height, tile_align_h);
177 }
178 }
179 }
180
181 static void
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
183 const struct tu_device *dev)
184 {
185 const uint32_t max_pipe_count = 32; /* A6xx */
186
187 /* start from 1 tile per pipe */
188 tiling->pipe0 = (VkExtent2D) {
189 .width = 1,
190 .height = 1,
191 };
192 tiling->pipe_count = tiling->tile_count;
193
194 /* do not exceed max pipe count vertically */
195 while (tiling->pipe_count.height > max_pipe_count) {
196 tiling->pipe0.height += 2;
197 tiling->pipe_count.height =
198 (tiling->tile_count.height + tiling->pipe0.height - 1) /
199 tiling->pipe0.height;
200 }
201
202 /* do not exceed max pipe count */
203 while (tiling->pipe_count.width * tiling->pipe_count.height >
204 max_pipe_count) {
205 tiling->pipe0.width += 1;
206 tiling->pipe_count.width =
207 (tiling->tile_count.width + tiling->pipe0.width - 1) /
208 tiling->pipe0.width;
209 }
210 }
211
212 static void
213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
214 const struct tu_device *dev)
215 {
216 const uint32_t max_pipe_count = 32; /* A6xx */
217 const uint32_t used_pipe_count =
218 tiling->pipe_count.width * tiling->pipe_count.height;
219 const VkExtent2D last_pipe = {
220 .width = tiling->tile_count.width % tiling->pipe0.width,
221 .height = tiling->tile_count.height % tiling->pipe0.height,
222 };
223
224 assert(used_pipe_count <= max_pipe_count);
225 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
226
227 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
228 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
229 const uint32_t pipe_x = tiling->pipe0.width * x;
230 const uint32_t pipe_y = tiling->pipe0.height * y;
231 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
232 ? last_pipe.width
233 : tiling->pipe0.width;
234 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
235 ? last_pipe.height
236 : tiling->pipe0.height;
237 const uint32_t n = tiling->pipe_count.width * y + x;
238
239 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
243 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
244 }
245 }
246
247 memset(tiling->pipe_config + used_pipe_count, 0,
248 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
249 }
250
251 static void
252 tu_tiling_config_update(struct tu_tiling_config *tiling,
253 const struct tu_device *dev,
254 const uint32_t *buffer_cpp,
255 uint32_t buffer_count,
256 const VkRect2D *render_area)
257 {
258 /* see if there is any real change */
259 const bool ra_changed =
260 render_area &&
261 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
262 const bool buf_changed = tiling->buffer_count != buffer_count ||
263 memcmp(tiling->buffer_cpp, buffer_cpp,
264 sizeof(*buffer_cpp) * buffer_count);
265 if (!ra_changed && !buf_changed)
266 return;
267
268 if (ra_changed)
269 tiling->render_area = *render_area;
270
271 if (buf_changed) {
272 memcpy(tiling->buffer_cpp, buffer_cpp,
273 sizeof(*buffer_cpp) * buffer_count);
274 tiling->buffer_count = buffer_count;
275 }
276
277 tu_tiling_config_update_tile_layout(tiling, dev);
278 tu_tiling_config_update_pipe_layout(tiling, dev);
279 tu_tiling_config_update_pipes(tiling, dev);
280 }
281
282 static void
283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
284 const struct tu_device *dev,
285 uint32_t tx,
286 uint32_t ty,
287 struct tu_tile *tile)
288 {
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px = tx / tiling->pipe0.width;
291 const uint32_t py = ty / tiling->pipe0.height;
292 const uint32_t sx = tx - tiling->pipe0.width * px;
293 const uint32_t sy = ty - tiling->pipe0.height * py;
294
295 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
296 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
297 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
298
299 /* convert to 1D indices */
300 tile->pipe = tiling->pipe_count.width * py + px;
301 tile->slot = tiling->pipe0.width * sy + sx;
302
303 /* get the blit area for the tile */
304 tile->begin = (VkOffset2D) {
305 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
306 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
307 };
308 tile->end.x =
309 (tx == tiling->tile_count.width - 1)
310 ? tiling->render_area.offset.x + tiling->render_area.extent.width
311 : tile->begin.x + tiling->tile0.extent.width;
312 tile->end.y =
313 (ty == tiling->tile_count.height - 1)
314 ? tiling->render_area.offset.y + tiling->render_area.extent.height
315 : tile->begin.y + tiling->tile0.extent.height;
316 }
317
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples)
320 {
321 switch (samples) {
322 case 1:
323 return MSAA_ONE;
324 case 2:
325 return MSAA_TWO;
326 case 4:
327 return MSAA_FOUR;
328 case 8:
329 return MSAA_EIGHT;
330 default:
331 assert(!"invalid sample count");
332 return MSAA_ONE;
333 }
334 }
335
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type)
338 {
339 switch (type) {
340 case VK_INDEX_TYPE_UINT16:
341 return INDEX4_SIZE_16_BIT;
342 case VK_INDEX_TYPE_UINT32:
343 return INDEX4_SIZE_32_BIT;
344 default:
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT;
347 }
348 }
349
350 static void
351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
354 }
355
356 void
357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
358 struct tu_cs *cs,
359 enum vgt_event_type event,
360 bool need_seqno)
361 {
362 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
363 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
364 if (need_seqno) {
365 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
366 tu_cs_emit(cs, ++cmd->scratch_seqno);
367 }
368 }
369
370 static void
371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
372 {
373 tu6_emit_event_write(cmd, cs, 0x31, false);
374 }
375
376 static void
377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
378 {
379 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
380 }
381
382 static void
383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
384 {
385 if (cmd->wait_for_idle) {
386 tu_cs_emit_wfi(cs);
387 cmd->wait_for_idle = false;
388 }
389 }
390
391 static void
392 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
393 {
394 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
395 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
396 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
397 if (iview->image->ubwc_size) {
398 tu_cs_emit_qw(cs, va);
399 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
401 } else {
402 tu_cs_emit_qw(cs, 0);
403 tu_cs_emit(cs, 0);
404 }
405 }
406
407 static void
408 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
409 {
410 const struct tu_framebuffer *fb = cmd->state.framebuffer;
411 const struct tu_subpass *subpass = cmd->state.subpass;
412 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
413
414 const uint32_t a = subpass->depth_stencil_attachment.attachment;
415 if (a == VK_ATTACHMENT_UNUSED) {
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
417 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
418 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
419 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
422 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
423
424 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
425 tu_cs_emit(cs,
426 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
429 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
430 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
431 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
432 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
433 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
436 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
437
438 return;
439 }
440
441 const struct tu_image_view *iview = fb->attachments[a].attachment;
442 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
443
444 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
445 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
446 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
447 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layer_size));
448 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
449 tu_cs_emit(cs, tiling->gmem_offsets[subpass->color_count]);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
452 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
453
454 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
455 tu6_emit_flag_buffer(cs, iview);
456
457 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
458 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
459 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
460 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
461 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
462 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
465 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
466
467 /* enable zs? */
468 }
469
470 static void
471 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
472 {
473 const struct tu_framebuffer *fb = cmd->state.framebuffer;
474 const struct tu_subpass *subpass = cmd->state.subpass;
475 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
476 unsigned char mrt_comp[MAX_RTS] = { 0 };
477 unsigned srgb_cntl = 0;
478
479 for (uint32_t i = 0; i < subpass->color_count; ++i) {
480 uint32_t a = subpass->color_attachments[i].attachment;
481 if (a == VK_ATTACHMENT_UNUSED)
482 continue;
483
484 const struct tu_image_view *iview = fb->attachments[a].attachment;
485 const enum a6xx_tile_mode tile_mode =
486 tu6_get_image_tile_mode(iview->image, iview->base_mip);
487
488 mrt_comp[i] = 0xf;
489
490 if (vk_format_is_srgb(iview->vk_format))
491 srgb_cntl |= (1 << i);
492
493 const struct tu_native_format *format =
494 tu6_get_native_format(iview->vk_format);
495 assert(format && format->rb >= 0);
496
497 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
498 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
499 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
500 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
501 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
502 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layer_size));
503 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
504 tu_cs_emit(
505 cs, tiling->gmem_offsets[i]); /* RB_MRT[i].BASE_GMEM */
506
507 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
508 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
509 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
510 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
511
512 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
513 tu6_emit_flag_buffer(cs, iview);
514 }
515
516 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
517 tu_cs_emit(cs, srgb_cntl);
518
519 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
520 tu_cs_emit(cs, srgb_cntl);
521
522 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
523 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
524 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
525 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
526 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
527 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
528 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
529 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
530 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
533 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
534 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
535 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
536 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
537 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
538 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
539 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
540 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
541 }
542
543 static void
544 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
545 {
546 const struct tu_subpass *subpass = cmd->state.subpass;
547 const enum a3xx_msaa_samples samples =
548 tu_msaa_samples(subpass->max_sample_count);
549
550 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
551 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
552 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
553 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
556 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
557 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
558 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
559
560 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
561 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
562 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
563 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
564
565 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
566 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
567 }
568
569 static void
570 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
571 {
572 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
573 const uint32_t bin_w = tiling->tile0.extent.width;
574 const uint32_t bin_h = tiling->tile0.extent.height;
575
576 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
577 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
578 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
579
580 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
581 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
582 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
583
584 /* no flag for RB_BIN_CONTROL2... */
585 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
586 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
587 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
588 }
589
590 static void
591 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
592 struct tu_cs *cs,
593 bool binning)
594 {
595 uint32_t cntl = 0;
596 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
597 if (binning)
598 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
599
600 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
601 tu_cs_emit(cs, 0x2);
602 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
603 tu_cs_emit(cs, cntl);
604 }
605
606 static void
607 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
608 {
609 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
610 const uint32_t x1 = render_area->offset.x;
611 const uint32_t y1 = render_area->offset.y;
612 const uint32_t x2 = x1 + render_area->extent.width - 1;
613 const uint32_t y2 = y1 + render_area->extent.height - 1;
614
615 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
616 tu_cs_emit(cs,
617 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
618 tu_cs_emit(cs,
619 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
620 }
621
622 static void
623 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
624 struct tu_cs *cs,
625 const struct tu_image_view *iview,
626 uint32_t gmem_offset,
627 uint32_t blit_info)
628 {
629 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
630 tu_cs_emit(cs, blit_info);
631
632 const struct tu_native_format *format =
633 tu6_get_native_format(iview->vk_format);
634 assert(format && format->rb >= 0);
635
636 enum a6xx_tile_mode tile_mode =
637 tu6_get_image_tile_mode(iview->image, iview->base_mip);
638 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
639 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
640 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
641 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
642 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
643 COND(iview->image->ubwc_size, A6XX_RB_BLIT_DST_INFO_FLAGS));
644 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
645 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
646 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layer_size));
647
648 if (iview->image->ubwc_size) {
649 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
650 tu6_emit_flag_buffer(cs, iview);
651 }
652
653 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
654 tu_cs_emit(cs, gmem_offset);
655 }
656
657 static void
658 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
659 struct tu_cs *cs,
660 const struct tu_image_view *iview,
661 uint32_t gmem_offset,
662 const VkClearValue *clear_value)
663 {
664 const struct tu_native_format *format =
665 tu6_get_native_format(iview->vk_format);
666 assert(format && format->rb >= 0);
667
668 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
669 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
670
671 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
672 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
673
674 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
675 tu_cs_emit(cs, gmem_offset);
676
677 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
678 tu_cs_emit(cs, 0);
679
680 uint32_t clear_vals[4] = { 0 };
681 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
682
683 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
684 tu_cs_emit(cs, clear_vals[0]);
685 tu_cs_emit(cs, clear_vals[1]);
686 tu_cs_emit(cs, clear_vals[2]);
687 tu_cs_emit(cs, clear_vals[3]);
688 }
689
690 static void
691 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
692 {
693 tu6_emit_marker(cmd, cs);
694 tu6_emit_event_write(cmd, cs, BLIT, false);
695 tu6_emit_marker(cmd, cs);
696 }
697
698 static void
699 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
700 struct tu_cs *cs,
701 uint32_t x1,
702 uint32_t y1,
703 uint32_t x2,
704 uint32_t y2)
705 {
706 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
707 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
708 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
709 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
710 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
711
712 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
713 tu_cs_emit(
714 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
715 tu_cs_emit(
716 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
717 }
718
719 static void
720 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
721 struct tu_cs *cs,
722 uint32_t x1,
723 uint32_t y1)
724 {
725 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
726 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
727
728 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
729 tu_cs_emit(cs,
730 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
731
732 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
733 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
734
735 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
736 tu_cs_emit(
737 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
738 }
739
740 static void
741 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
742 struct tu_cs *cs,
743 const struct tu_tile *tile)
744 {
745 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
746 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
747
748 tu6_emit_marker(cmd, cs);
749 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
750 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
751 tu6_emit_marker(cmd, cs);
752
753 const uint32_t x1 = tile->begin.x;
754 const uint32_t y1 = tile->begin.y;
755 const uint32_t x2 = tile->end.x - 1;
756 const uint32_t y2 = tile->end.y - 1;
757 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
758 tu6_emit_window_offset(cmd, cs, x1, y1);
759
760 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
761 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
762
763 if (false) {
764 /* hw binning? */
765 } else {
766 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
767 tu_cs_emit(cs, 0x1);
768
769 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
770 tu_cs_emit(cs, 0x0);
771 }
772 }
773
774 static void
775 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
776 struct tu_cs *cs,
777 uint32_t a,
778 uint32_t gmem_index)
779 {
780 const struct tu_framebuffer *fb = cmd->state.framebuffer;
781 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
782 const struct tu_attachment_state *attachments = cmd->state.attachments;
783
784 const struct tu_image_view *iview = fb->attachments[a].attachment;
785 const struct tu_attachment_state *att = attachments + a;
786 if (att->pending_clear_aspects) {
787 tu6_emit_blit_clear(cmd, cs, iview,
788 tiling->gmem_offsets[gmem_index],
789 &att->clear_value);
790 } else {
791 tu6_emit_blit_info(cmd, cs, iview,
792 tiling->gmem_offsets[gmem_index],
793 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
794 }
795
796 tu6_emit_blit(cmd, cs);
797 }
798
799 static void
800 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
801 {
802 const struct tu_subpass *subpass = cmd->state.subpass;
803
804 tu6_emit_blit_scissor(cmd, cs);
805
806 for (uint32_t i = 0; i < subpass->color_count; ++i) {
807 const uint32_t a = subpass->color_attachments[i].attachment;
808 if (a != VK_ATTACHMENT_UNUSED)
809 tu6_emit_tile_load_attachment(cmd, cs, a, i);
810 }
811
812 const uint32_t a = subpass->depth_stencil_attachment.attachment;
813 if (a != VK_ATTACHMENT_UNUSED)
814 tu6_emit_tile_load_attachment(cmd, cs, a, subpass->color_count);
815 }
816
817 static void
818 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
819 struct tu_cs *cs,
820 uint32_t a,
821 uint32_t gmem_index)
822 {
823 const struct tu_framebuffer *fb = cmd->state.framebuffer;
824 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
825
826 if (a == VK_ATTACHMENT_UNUSED)
827 return;
828
829 tu6_emit_blit_info(cmd, cs, fb->attachments[a].attachment,
830 tiling->gmem_offsets[gmem_index], 0);
831 tu6_emit_blit(cmd, cs);
832 }
833
834 static void
835 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
836 {
837 const struct tu_framebuffer *fb = cmd->state.framebuffer;
838 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
839 const struct tu_subpass *subpass = cmd->state.subpass;
840
841 if (false) {
842 /* hw binning? */
843 }
844
845 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
846 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
847 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
848 CP_SET_DRAW_STATE__0_GROUP_ID(0));
849 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
850 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
851
852 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
853 tu_cs_emit(cs, 0x0);
854
855 tu6_emit_marker(cmd, cs);
856 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
857 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
858 tu6_emit_marker(cmd, cs);
859
860 tu6_emit_blit_scissor(cmd, cs);
861
862 for (uint32_t i = 0; i < subpass->color_count; ++i) {
863 tu6_emit_store_attachment(cmd, cs,
864 subpass->color_attachments[i].attachment,
865 i);
866 if (subpass->resolve_attachments) {
867 tu6_emit_store_attachment(cmd, cs,
868 subpass->resolve_attachments[i].attachment,
869 i);
870 }
871 }
872
873 tu6_emit_store_attachment(cmd, cs,
874 subpass->depth_stencil_attachment.attachment,
875 subpass->color_count);
876 }
877
878 static void
879 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
880 {
881 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
882 tu_cs_emit(cs, restart_index);
883 }
884
885 static void
886 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
887 {
888 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
889 if (result != VK_SUCCESS) {
890 cmd->record_result = result;
891 return;
892 }
893
894 tu6_emit_cache_flush(cmd, cs);
895
896 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
897
898 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
899 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
900 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
901 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
902 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
903 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
904 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
905 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
906 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
907
908 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
909 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
910 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
911 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
912 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
913 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
914 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
915 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
916 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
917 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
919 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
920 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
921 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
922
923 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
924
925 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
926 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
928
929 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
940 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
941
942 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
943 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
944
945 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
946 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
947
948 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
949 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
950
951 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
952 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
953 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
954
955 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
956 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
959
960 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
961
962 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
963 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
965 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
970 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
972 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
974 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
975 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
976 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
977 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
978 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
983
984 tu6_emit_marker(cmd, cs);
985
986 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
987
988 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
989
990 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
991
992 /* we don't use this yet.. probably best to disable.. */
993 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
994 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
995 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
996 CP_SET_DRAW_STATE__0_GROUP_ID(0));
997 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
998 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
999
1000 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1001 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1002 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1003 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1004
1005 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1006 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1007 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1008
1009 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1010 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1011
1012 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1013 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1014
1015 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1016 tu_cs_emit(cs, 0x00000000);
1017 tu_cs_emit(cs, 0x00000000);
1018 tu_cs_emit(cs, 0x00000000);
1019
1020 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1021 tu_cs_emit(cs, 0x00000000);
1022 tu_cs_emit(cs, 0x00000000);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025 tu_cs_emit(cs, 0x00000000);
1026 tu_cs_emit(cs, 0x00000000);
1027
1028 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1029 tu_cs_emit(cs, 0x00000000);
1030 tu_cs_emit(cs, 0x00000000);
1031 tu_cs_emit(cs, 0x00000000);
1032 tu_cs_emit(cs, 0x00000000);
1033 tu_cs_emit(cs, 0x00000000);
1034 tu_cs_emit(cs, 0x00000000);
1035
1036 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1037 tu_cs_emit(cs, 0x00000000);
1038 tu_cs_emit(cs, 0x00000000);
1039 tu_cs_emit(cs, 0x00000000);
1040
1041 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1042 tu_cs_emit(cs, 0x00000000);
1043
1044 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1045 tu_cs_emit(cs, 0x00000000);
1046
1047 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1048 tu_cs_emit(cs, 0x00000000);
1049
1050 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1051 tu_cs_emit(cs, 0x00000000);
1052
1053 tu_cs_sanity_check(cs);
1054 }
1055
1056 static void
1057 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1058 {
1059 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1060 if (result != VK_SUCCESS) {
1061 cmd->record_result = result;
1062 return;
1063 }
1064
1065 tu6_emit_lrz_flush(cmd, cs);
1066
1067 /* lrz clear? */
1068
1069 tu6_emit_cache_flush(cmd, cs);
1070
1071 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1072 tu_cs_emit(cs, 0x0);
1073
1074 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1075 tu6_emit_wfi(cmd, cs);
1076 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1077 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1078
1079 tu6_emit_zs(cmd, cs);
1080 tu6_emit_mrt(cmd, cs);
1081 tu6_emit_msaa(cmd, cs);
1082
1083 if (false) {
1084 /* hw binning? */
1085 } else {
1086 tu6_emit_bin_size(cmd, cs, 0x6000000);
1087 /* no draws */
1088 }
1089
1090 tu6_emit_render_cntl(cmd, cs, false);
1091
1092 tu_cs_sanity_check(cs);
1093 }
1094
1095 static void
1096 tu6_render_tile(struct tu_cmd_buffer *cmd,
1097 struct tu_cs *cs,
1098 const struct tu_tile *tile)
1099 {
1100 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1101 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1102 if (result != VK_SUCCESS) {
1103 cmd->record_result = result;
1104 return;
1105 }
1106
1107 tu6_emit_tile_select(cmd, cs, tile);
1108 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1109
1110 tu_cs_emit_call(cs, &cmd->draw_cs);
1111 cmd->wait_for_idle = true;
1112
1113 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1114
1115 tu_cs_sanity_check(cs);
1116 }
1117
1118 static void
1119 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1120 {
1121 const struct tu_subpass *subpass = cmd->state.subpass;
1122 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1123
1124 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1125 if (result != VK_SUCCESS) {
1126 cmd->record_result = result;
1127 return;
1128 }
1129
1130 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1131 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1132
1133 tu6_emit_lrz_flush(cmd, cs);
1134
1135 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1136
1137 tu_cs_sanity_check(cs);
1138 }
1139
1140 static void
1141 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1142 {
1143 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1144
1145 tu6_render_begin(cmd, &cmd->cs);
1146
1147 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1148 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1149 struct tu_tile tile;
1150 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1151 tu6_render_tile(cmd, &cmd->cs, &tile);
1152 }
1153 }
1154
1155 tu6_render_end(cmd, &cmd->cs);
1156 }
1157
1158 static void
1159 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1160 {
1161 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1162 const struct tu_subpass *subpass = cmd->state.subpass;
1163 struct tu_attachment_state *attachments = cmd->state.attachments;
1164 struct tu_cs sub_cs;
1165
1166 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1167 tile_load_space, &sub_cs);
1168 if (result != VK_SUCCESS) {
1169 cmd->record_result = result;
1170 return;
1171 }
1172
1173 /* emit to tile-load sub_cs */
1174 tu6_emit_tile_load(cmd, &sub_cs);
1175
1176 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1177
1178 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1179 const uint32_t a = subpass->color_attachments[i].attachment;
1180 if (a != VK_ATTACHMENT_UNUSED)
1181 attachments[a].pending_clear_aspects = 0;
1182 }
1183 }
1184
1185 static void
1186 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1187 {
1188 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1189 struct tu_cs sub_cs;
1190
1191 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1192 tile_store_space, &sub_cs);
1193 if (result != VK_SUCCESS) {
1194 cmd->record_result = result;
1195 return;
1196 }
1197
1198 /* emit to tile-store sub_cs */
1199 tu6_emit_tile_store(cmd, &sub_cs);
1200
1201 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1202 }
1203
1204 static void
1205 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1206 const VkRect2D *render_area)
1207 {
1208 const struct tu_device *dev = cmd->device;
1209 const struct tu_render_pass *pass = cmd->state.pass;
1210 const struct tu_subpass *subpass = cmd->state.subpass;
1211 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1212
1213 uint32_t buffer_cpp[MAX_RTS + 2];
1214 uint32_t buffer_count = 0;
1215
1216 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1217 const uint32_t a = subpass->color_attachments[i].attachment;
1218 if (a == VK_ATTACHMENT_UNUSED) {
1219 buffer_cpp[buffer_count++] = 0;
1220 continue;
1221 }
1222
1223 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1224 buffer_cpp[buffer_count++] =
1225 vk_format_get_blocksize(att->format) * att->samples;
1226 }
1227
1228 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1229 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1230 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1231
1232 /* TODO */
1233 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1234
1235 buffer_cpp[buffer_count++] =
1236 vk_format_get_blocksize(att->format) * att->samples;
1237 }
1238
1239 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1240 render_area);
1241 }
1242
1243 const struct tu_dynamic_state default_dynamic_state = {
1244 .viewport =
1245 {
1246 .count = 0,
1247 },
1248 .scissor =
1249 {
1250 .count = 0,
1251 },
1252 .line_width = 1.0f,
1253 .depth_bias =
1254 {
1255 .bias = 0.0f,
1256 .clamp = 0.0f,
1257 .slope = 0.0f,
1258 },
1259 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1260 .depth_bounds =
1261 {
1262 .min = 0.0f,
1263 .max = 1.0f,
1264 },
1265 .stencil_compare_mask =
1266 {
1267 .front = ~0u,
1268 .back = ~0u,
1269 },
1270 .stencil_write_mask =
1271 {
1272 .front = ~0u,
1273 .back = ~0u,
1274 },
1275 .stencil_reference =
1276 {
1277 .front = 0u,
1278 .back = 0u,
1279 },
1280 };
1281
1282 static void UNUSED /* FINISHME */
1283 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1284 const struct tu_dynamic_state *src)
1285 {
1286 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1287 uint32_t copy_mask = src->mask;
1288 uint32_t dest_mask = 0;
1289
1290 tu_use_args(cmd_buffer); /* FINISHME */
1291
1292 /* Make sure to copy the number of viewports/scissors because they can
1293 * only be specified at pipeline creation time.
1294 */
1295 dest->viewport.count = src->viewport.count;
1296 dest->scissor.count = src->scissor.count;
1297 dest->discard_rectangle.count = src->discard_rectangle.count;
1298
1299 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1300 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1301 src->viewport.count * sizeof(VkViewport))) {
1302 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1303 src->viewport.count);
1304 dest_mask |= TU_DYNAMIC_VIEWPORT;
1305 }
1306 }
1307
1308 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1309 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1310 src->scissor.count * sizeof(VkRect2D))) {
1311 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1312 src->scissor.count);
1313 dest_mask |= TU_DYNAMIC_SCISSOR;
1314 }
1315 }
1316
1317 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1318 if (dest->line_width != src->line_width) {
1319 dest->line_width = src->line_width;
1320 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1321 }
1322 }
1323
1324 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1325 if (memcmp(&dest->depth_bias, &src->depth_bias,
1326 sizeof(src->depth_bias))) {
1327 dest->depth_bias = src->depth_bias;
1328 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1329 }
1330 }
1331
1332 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1333 if (memcmp(&dest->blend_constants, &src->blend_constants,
1334 sizeof(src->blend_constants))) {
1335 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1336 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1337 }
1338 }
1339
1340 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1341 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1342 sizeof(src->depth_bounds))) {
1343 dest->depth_bounds = src->depth_bounds;
1344 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1345 }
1346 }
1347
1348 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1349 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1350 sizeof(src->stencil_compare_mask))) {
1351 dest->stencil_compare_mask = src->stencil_compare_mask;
1352 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1353 }
1354 }
1355
1356 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1357 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1358 sizeof(src->stencil_write_mask))) {
1359 dest->stencil_write_mask = src->stencil_write_mask;
1360 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1361 }
1362 }
1363
1364 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1365 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1366 sizeof(src->stencil_reference))) {
1367 dest->stencil_reference = src->stencil_reference;
1368 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1369 }
1370 }
1371
1372 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1373 if (memcmp(&dest->discard_rectangle.rectangles,
1374 &src->discard_rectangle.rectangles,
1375 src->discard_rectangle.count * sizeof(VkRect2D))) {
1376 typed_memcpy(dest->discard_rectangle.rectangles,
1377 src->discard_rectangle.rectangles,
1378 src->discard_rectangle.count);
1379 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1380 }
1381 }
1382 }
1383
1384 static VkResult
1385 tu_create_cmd_buffer(struct tu_device *device,
1386 struct tu_cmd_pool *pool,
1387 VkCommandBufferLevel level,
1388 VkCommandBuffer *pCommandBuffer)
1389 {
1390 struct tu_cmd_buffer *cmd_buffer;
1391 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1392 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1393 if (cmd_buffer == NULL)
1394 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1395
1396 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1397 cmd_buffer->device = device;
1398 cmd_buffer->pool = pool;
1399 cmd_buffer->level = level;
1400
1401 if (pool) {
1402 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1403 cmd_buffer->queue_family_index = pool->queue_family_index;
1404
1405 } else {
1406 /* Init the pool_link so we can safely call list_del when we destroy
1407 * the command buffer
1408 */
1409 list_inithead(&cmd_buffer->pool_link);
1410 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1411 }
1412
1413 tu_bo_list_init(&cmd_buffer->bo_list);
1414 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1415 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1416 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1417 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1418
1419 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1420
1421 list_inithead(&cmd_buffer->upload.list);
1422
1423 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1424 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1425
1426 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1427 if (result != VK_SUCCESS)
1428 return result;
1429
1430 return VK_SUCCESS;
1431 }
1432
1433 static void
1434 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1435 {
1436 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1437
1438 list_del(&cmd_buffer->pool_link);
1439
1440 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1441 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1442
1443 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1444 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1445 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1446 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1447
1448 tu_bo_list_destroy(&cmd_buffer->bo_list);
1449 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1450 }
1451
1452 static VkResult
1453 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1454 {
1455 cmd_buffer->wait_for_idle = true;
1456
1457 cmd_buffer->record_result = VK_SUCCESS;
1458
1459 tu_bo_list_reset(&cmd_buffer->bo_list);
1460 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1461 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1462 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1463 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1464
1465 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1466 cmd_buffer->descriptors[i].dirty = 0;
1467 cmd_buffer->descriptors[i].valid = 0;
1468 cmd_buffer->descriptors[i].push_dirty = false;
1469 }
1470
1471 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1472
1473 return cmd_buffer->record_result;
1474 }
1475
1476 static VkResult
1477 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1478 const VkRenderPassBeginInfo *info)
1479 {
1480 struct tu_cmd_state *state = &cmd_buffer->state;
1481 const struct tu_framebuffer *fb = state->framebuffer;
1482 const struct tu_render_pass *pass = state->pass;
1483
1484 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1485 const struct tu_image_view *iview = fb->attachments[i].attachment;
1486 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1487 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1488 }
1489
1490 if (pass->attachment_count == 0) {
1491 state->attachments = NULL;
1492 return VK_SUCCESS;
1493 }
1494
1495 state->attachments =
1496 vk_alloc(&cmd_buffer->pool->alloc,
1497 pass->attachment_count * sizeof(state->attachments[0]), 8,
1498 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1499 if (state->attachments == NULL) {
1500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1501 return cmd_buffer->record_result;
1502 }
1503
1504 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1505 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1506 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1507 VkImageAspectFlags clear_aspects = 0;
1508
1509 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1510 /* color attachment */
1511 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1512 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1513 }
1514 } else {
1515 /* depthstencil attachment */
1516 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1517 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1518 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1519 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1520 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1521 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1522 }
1523 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1524 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1525 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1526 }
1527 }
1528
1529 state->attachments[i].pending_clear_aspects = clear_aspects;
1530 state->attachments[i].cleared_views = 0;
1531 if (clear_aspects && info) {
1532 assert(info->clearValueCount > i);
1533 state->attachments[i].clear_value = info->pClearValues[i];
1534 }
1535
1536 state->attachments[i].current_layout = att->initial_layout;
1537 }
1538
1539 return VK_SUCCESS;
1540 }
1541
1542 VkResult
1543 tu_AllocateCommandBuffers(VkDevice _device,
1544 const VkCommandBufferAllocateInfo *pAllocateInfo,
1545 VkCommandBuffer *pCommandBuffers)
1546 {
1547 TU_FROM_HANDLE(tu_device, device, _device);
1548 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1549
1550 VkResult result = VK_SUCCESS;
1551 uint32_t i;
1552
1553 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1554
1555 if (!list_is_empty(&pool->free_cmd_buffers)) {
1556 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1557 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1558
1559 list_del(&cmd_buffer->pool_link);
1560 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1561
1562 result = tu_reset_cmd_buffer(cmd_buffer);
1563 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1564 cmd_buffer->level = pAllocateInfo->level;
1565
1566 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1567 } else {
1568 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1569 &pCommandBuffers[i]);
1570 }
1571 if (result != VK_SUCCESS)
1572 break;
1573 }
1574
1575 if (result != VK_SUCCESS) {
1576 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1577 pCommandBuffers);
1578
1579 /* From the Vulkan 1.0.66 spec:
1580 *
1581 * "vkAllocateCommandBuffers can be used to create multiple
1582 * command buffers. If the creation of any of those command
1583 * buffers fails, the implementation must destroy all
1584 * successfully created command buffer objects from this
1585 * command, set all entries of the pCommandBuffers array to
1586 * NULL and return the error."
1587 */
1588 memset(pCommandBuffers, 0,
1589 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1590 }
1591
1592 return result;
1593 }
1594
1595 void
1596 tu_FreeCommandBuffers(VkDevice device,
1597 VkCommandPool commandPool,
1598 uint32_t commandBufferCount,
1599 const VkCommandBuffer *pCommandBuffers)
1600 {
1601 for (uint32_t i = 0; i < commandBufferCount; i++) {
1602 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1603
1604 if (cmd_buffer) {
1605 if (cmd_buffer->pool) {
1606 list_del(&cmd_buffer->pool_link);
1607 list_addtail(&cmd_buffer->pool_link,
1608 &cmd_buffer->pool->free_cmd_buffers);
1609 } else
1610 tu_cmd_buffer_destroy(cmd_buffer);
1611 }
1612 }
1613 }
1614
1615 VkResult
1616 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1617 VkCommandBufferResetFlags flags)
1618 {
1619 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1620 return tu_reset_cmd_buffer(cmd_buffer);
1621 }
1622
1623 VkResult
1624 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1625 const VkCommandBufferBeginInfo *pBeginInfo)
1626 {
1627 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1628 VkResult result = VK_SUCCESS;
1629
1630 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1631 /* If the command buffer has already been resetted with
1632 * vkResetCommandBuffer, no need to do it again.
1633 */
1634 result = tu_reset_cmd_buffer(cmd_buffer);
1635 if (result != VK_SUCCESS)
1636 return result;
1637 }
1638
1639 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1640 cmd_buffer->usage_flags = pBeginInfo->flags;
1641
1642 tu_cs_begin(&cmd_buffer->cs);
1643
1644 cmd_buffer->marker_seqno = 0;
1645 cmd_buffer->scratch_seqno = 0;
1646
1647 /* setup initial configuration into command buffer */
1648 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1649 switch (cmd_buffer->queue_family_index) {
1650 case TU_QUEUE_GENERAL:
1651 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1652 break;
1653 default:
1654 break;
1655 }
1656 }
1657
1658 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1659
1660 return VK_SUCCESS;
1661 }
1662
1663 void
1664 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1665 uint32_t firstBinding,
1666 uint32_t bindingCount,
1667 const VkBuffer *pBuffers,
1668 const VkDeviceSize *pOffsets)
1669 {
1670 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1671
1672 assert(firstBinding + bindingCount <= MAX_VBS);
1673
1674 for (uint32_t i = 0; i < bindingCount; i++) {
1675 cmd->state.vb.buffers[firstBinding + i] =
1676 tu_buffer_from_handle(pBuffers[i]);
1677 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1678 }
1679
1680 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1681 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1682 }
1683
1684 void
1685 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1686 VkBuffer buffer,
1687 VkDeviceSize offset,
1688 VkIndexType indexType)
1689 {
1690 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1691 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1692
1693 /* initialize/update the restart index */
1694 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1695 struct tu_cs *draw_cs = &cmd->draw_cs;
1696 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1697 if (result != VK_SUCCESS) {
1698 cmd->record_result = result;
1699 return;
1700 }
1701
1702 tu6_emit_restart_index(
1703 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1704
1705 tu_cs_sanity_check(draw_cs);
1706 }
1707
1708 /* track the BO */
1709 if (cmd->state.index_buffer != buf)
1710 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1711
1712 cmd->state.index_buffer = buf;
1713 cmd->state.index_offset = offset;
1714 cmd->state.index_type = indexType;
1715 }
1716
1717 void
1718 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1719 VkPipelineBindPoint pipelineBindPoint,
1720 VkPipelineLayout _layout,
1721 uint32_t firstSet,
1722 uint32_t descriptorSetCount,
1723 const VkDescriptorSet *pDescriptorSets,
1724 uint32_t dynamicOffsetCount,
1725 const uint32_t *pDynamicOffsets)
1726 {
1727 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1728 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1729 unsigned dyn_idx = 0;
1730
1731 struct tu_descriptor_state *descriptors_state =
1732 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1733
1734 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1735 unsigned idx = i + firstSet;
1736 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1737
1738 descriptors_state->sets[idx] = set;
1739 descriptors_state->valid |= (1u << idx);
1740
1741 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1742 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1743 assert(dyn_idx < dynamicOffsetCount);
1744
1745 descriptors_state->dynamic_buffers[idx] =
1746 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1747 }
1748 }
1749
1750 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1751 }
1752
1753 void
1754 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1755 VkPipelineLayout layout,
1756 VkShaderStageFlags stageFlags,
1757 uint32_t offset,
1758 uint32_t size,
1759 const void *pValues)
1760 {
1761 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1762 memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1763 }
1764
1765 VkResult
1766 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1767 {
1768 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1769
1770 if (cmd_buffer->scratch_seqno) {
1771 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1772 MSM_SUBMIT_BO_WRITE);
1773 }
1774
1775 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1776 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1777 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1778 }
1779
1780 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1781 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1782 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1783 }
1784
1785 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1786 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1787 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1788 }
1789
1790 tu_cs_end(&cmd_buffer->cs);
1791
1792 assert(!cmd_buffer->state.attachments);
1793
1794 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1795
1796 return cmd_buffer->record_result;
1797 }
1798
1799 void
1800 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1801 VkPipelineBindPoint pipelineBindPoint,
1802 VkPipeline _pipeline)
1803 {
1804 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1805 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1806
1807 switch (pipelineBindPoint) {
1808 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1809 cmd->state.pipeline = pipeline;
1810 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1811 break;
1812 case VK_PIPELINE_BIND_POINT_COMPUTE:
1813 tu_finishme("binding compute pipeline");
1814 break;
1815 default:
1816 unreachable("unrecognized pipeline bind point");
1817 break;
1818 }
1819 }
1820
1821 void
1822 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1823 uint32_t firstViewport,
1824 uint32_t viewportCount,
1825 const VkViewport *pViewports)
1826 {
1827 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1828 struct tu_cs *draw_cs = &cmd->draw_cs;
1829
1830 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1831 if (result != VK_SUCCESS) {
1832 cmd->record_result = result;
1833 return;
1834 }
1835
1836 assert(firstViewport == 0 && viewportCount == 1);
1837 tu6_emit_viewport(draw_cs, pViewports);
1838
1839 tu_cs_sanity_check(draw_cs);
1840 }
1841
1842 void
1843 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1844 uint32_t firstScissor,
1845 uint32_t scissorCount,
1846 const VkRect2D *pScissors)
1847 {
1848 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1849 struct tu_cs *draw_cs = &cmd->draw_cs;
1850
1851 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1852 if (result != VK_SUCCESS) {
1853 cmd->record_result = result;
1854 return;
1855 }
1856
1857 assert(firstScissor == 0 && scissorCount == 1);
1858 tu6_emit_scissor(draw_cs, pScissors);
1859
1860 tu_cs_sanity_check(draw_cs);
1861 }
1862
1863 void
1864 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1865 {
1866 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1867
1868 cmd->state.dynamic.line_width = lineWidth;
1869
1870 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1871 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1872 }
1873
1874 void
1875 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1876 float depthBiasConstantFactor,
1877 float depthBiasClamp,
1878 float depthBiasSlopeFactor)
1879 {
1880 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1881 struct tu_cs *draw_cs = &cmd->draw_cs;
1882
1883 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1884 if (result != VK_SUCCESS) {
1885 cmd->record_result = result;
1886 return;
1887 }
1888
1889 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1890 depthBiasSlopeFactor);
1891
1892 tu_cs_sanity_check(draw_cs);
1893 }
1894
1895 void
1896 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1897 const float blendConstants[4])
1898 {
1899 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1900 struct tu_cs *draw_cs = &cmd->draw_cs;
1901
1902 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1903 if (result != VK_SUCCESS) {
1904 cmd->record_result = result;
1905 return;
1906 }
1907
1908 tu6_emit_blend_constants(draw_cs, blendConstants);
1909
1910 tu_cs_sanity_check(draw_cs);
1911 }
1912
1913 void
1914 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1915 float minDepthBounds,
1916 float maxDepthBounds)
1917 {
1918 }
1919
1920 void
1921 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1922 VkStencilFaceFlags faceMask,
1923 uint32_t compareMask)
1924 {
1925 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1926
1927 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1928 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1929 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1930 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1931
1932 /* the front/back compare masks must be updated together */
1933 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1934 }
1935
1936 void
1937 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1938 VkStencilFaceFlags faceMask,
1939 uint32_t writeMask)
1940 {
1941 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1942
1943 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1944 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1945 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1946 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1947
1948 /* the front/back write masks must be updated together */
1949 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1950 }
1951
1952 void
1953 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1954 VkStencilFaceFlags faceMask,
1955 uint32_t reference)
1956 {
1957 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1958
1959 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1960 cmd->state.dynamic.stencil_reference.front = reference;
1961 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1962 cmd->state.dynamic.stencil_reference.back = reference;
1963
1964 /* the front/back references must be updated together */
1965 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1966 }
1967
1968 void
1969 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1970 uint32_t commandBufferCount,
1971 const VkCommandBuffer *pCmdBuffers)
1972 {
1973 }
1974
1975 VkResult
1976 tu_CreateCommandPool(VkDevice _device,
1977 const VkCommandPoolCreateInfo *pCreateInfo,
1978 const VkAllocationCallbacks *pAllocator,
1979 VkCommandPool *pCmdPool)
1980 {
1981 TU_FROM_HANDLE(tu_device, device, _device);
1982 struct tu_cmd_pool *pool;
1983
1984 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1985 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1986 if (pool == NULL)
1987 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1988
1989 if (pAllocator)
1990 pool->alloc = *pAllocator;
1991 else
1992 pool->alloc = device->alloc;
1993
1994 list_inithead(&pool->cmd_buffers);
1995 list_inithead(&pool->free_cmd_buffers);
1996
1997 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1998
1999 *pCmdPool = tu_cmd_pool_to_handle(pool);
2000
2001 return VK_SUCCESS;
2002 }
2003
2004 void
2005 tu_DestroyCommandPool(VkDevice _device,
2006 VkCommandPool commandPool,
2007 const VkAllocationCallbacks *pAllocator)
2008 {
2009 TU_FROM_HANDLE(tu_device, device, _device);
2010 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2011
2012 if (!pool)
2013 return;
2014
2015 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2016 &pool->cmd_buffers, pool_link)
2017 {
2018 tu_cmd_buffer_destroy(cmd_buffer);
2019 }
2020
2021 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2022 &pool->free_cmd_buffers, pool_link)
2023 {
2024 tu_cmd_buffer_destroy(cmd_buffer);
2025 }
2026
2027 vk_free2(&device->alloc, pAllocator, pool);
2028 }
2029
2030 VkResult
2031 tu_ResetCommandPool(VkDevice device,
2032 VkCommandPool commandPool,
2033 VkCommandPoolResetFlags flags)
2034 {
2035 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2036 VkResult result;
2037
2038 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2039 pool_link)
2040 {
2041 result = tu_reset_cmd_buffer(cmd_buffer);
2042 if (result != VK_SUCCESS)
2043 return result;
2044 }
2045
2046 return VK_SUCCESS;
2047 }
2048
2049 void
2050 tu_TrimCommandPool(VkDevice device,
2051 VkCommandPool commandPool,
2052 VkCommandPoolTrimFlags flags)
2053 {
2054 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2055
2056 if (!pool)
2057 return;
2058
2059 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2060 &pool->free_cmd_buffers, pool_link)
2061 {
2062 tu_cmd_buffer_destroy(cmd_buffer);
2063 }
2064 }
2065
2066 void
2067 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2068 const VkRenderPassBeginInfo *pRenderPassBegin,
2069 VkSubpassContents contents)
2070 {
2071 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2072 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2073 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2074 VkResult result;
2075
2076 cmd_buffer->state.pass = pass;
2077 cmd_buffer->state.subpass = pass->subpasses;
2078 cmd_buffer->state.framebuffer = framebuffer;
2079
2080 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2081 if (result != VK_SUCCESS)
2082 return;
2083
2084 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2085 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2086 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2087
2088 /* draw_cs should contain entries only for this render pass */
2089 assert(!cmd_buffer->draw_cs.entry_count);
2090 tu_cs_begin(&cmd_buffer->draw_cs);
2091 }
2092
2093 void
2094 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2095 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2096 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2097 {
2098 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2099 pSubpassBeginInfo->contents);
2100 }
2101
2102 void
2103 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2104 {
2105 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2106
2107 tu_cmd_render_tiles(cmd);
2108
2109 cmd->state.subpass++;
2110
2111 tu_cmd_update_tiling_config(cmd, NULL);
2112 tu_cmd_prepare_tile_load_ib(cmd);
2113 tu_cmd_prepare_tile_store_ib(cmd);
2114 }
2115
2116 void
2117 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2118 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2119 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2120 {
2121 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2122 }
2123
2124 struct tu_draw_info
2125 {
2126 /**
2127 * Number of vertices.
2128 */
2129 uint32_t count;
2130
2131 /**
2132 * Index of the first vertex.
2133 */
2134 int32_t vertex_offset;
2135
2136 /**
2137 * First instance id.
2138 */
2139 uint32_t first_instance;
2140
2141 /**
2142 * Number of instances.
2143 */
2144 uint32_t instance_count;
2145
2146 /**
2147 * First index (indexed draws only).
2148 */
2149 uint32_t first_index;
2150
2151 /**
2152 * Whether it's an indexed draw.
2153 */
2154 bool indexed;
2155
2156 /**
2157 * Indirect draw parameters resource.
2158 */
2159 struct tu_buffer *indirect;
2160 uint64_t indirect_offset;
2161 uint32_t stride;
2162
2163 /**
2164 * Draw count parameters resource.
2165 */
2166 struct tu_buffer *count_buffer;
2167 uint64_t count_buffer_offset;
2168 };
2169
2170 enum tu_draw_state_group_id
2171 {
2172 TU_DRAW_STATE_PROGRAM,
2173 TU_DRAW_STATE_PROGRAM_BINNING,
2174 TU_DRAW_STATE_VI,
2175 TU_DRAW_STATE_VI_BINNING,
2176 TU_DRAW_STATE_VP,
2177 TU_DRAW_STATE_RAST,
2178 TU_DRAW_STATE_DS,
2179 TU_DRAW_STATE_BLEND,
2180 TU_DRAW_STATE_VS_CONST,
2181 TU_DRAW_STATE_FS_CONST,
2182 TU_DRAW_STATE_VS_TEX,
2183 TU_DRAW_STATE_FS_TEX,
2184
2185 TU_DRAW_STATE_COUNT,
2186 };
2187
2188 struct tu_draw_state_group
2189 {
2190 enum tu_draw_state_group_id id;
2191 uint32_t enable_mask;
2192 struct tu_cs_entry ib;
2193 };
2194
2195 static struct tu_sampler*
2196 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2197 const struct tu_descriptor_map *map, unsigned i)
2198 {
2199 assert(descriptors_state->valid & (1 << map->set[i]));
2200
2201 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2202 assert(map->binding[i] < set->layout->binding_count);
2203
2204 const struct tu_descriptor_set_binding_layout *layout =
2205 &set->layout->binding[map->binding[i]];
2206
2207 switch (layout->type) {
2208 case VK_DESCRIPTOR_TYPE_SAMPLER:
2209 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2210 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2211 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2212 default:
2213 unreachable("unimplemented descriptor type");
2214 break;
2215 }
2216 }
2217
2218 static uint32_t*
2219 texture_ptr(struct tu_descriptor_state *descriptors_state,
2220 const struct tu_descriptor_map *map, unsigned i)
2221 {
2222 assert(descriptors_state->valid & (1 << map->set[i]));
2223
2224 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2225 assert(map->binding[i] < set->layout->binding_count);
2226
2227 const struct tu_descriptor_set_binding_layout *layout =
2228 &set->layout->binding[map->binding[i]];
2229
2230 switch (layout->type) {
2231 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2232 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2233 return &set->mapped_ptr[layout->offset / 4];
2234 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2235 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2236 return &set->mapped_ptr[layout->offset / 4];
2237 default:
2238 unreachable("unimplemented descriptor type");
2239 break;
2240 }
2241 }
2242
2243 static uint64_t
2244 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2245 const struct tu_descriptor_map *map,
2246 unsigned i)
2247 {
2248 assert(descriptors_state->valid & (1 << map->set[i]));
2249
2250 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2251 assert(map->binding[i] < set->layout->binding_count);
2252
2253 const struct tu_descriptor_set_binding_layout *layout =
2254 &set->layout->binding[map->binding[i]];
2255
2256 switch (layout->type) {
2257 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2258 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2259 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2260 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2261 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2262 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2263 set->mapped_ptr[layout->offset / 4];
2264 default:
2265 unreachable("unimplemented descriptor type");
2266 break;
2267 }
2268 }
2269
2270 static inline uint32_t
2271 tu6_stage2opcode(gl_shader_stage type)
2272 {
2273 switch (type) {
2274 case MESA_SHADER_VERTEX:
2275 case MESA_SHADER_TESS_CTRL:
2276 case MESA_SHADER_TESS_EVAL:
2277 case MESA_SHADER_GEOMETRY:
2278 return CP_LOAD_STATE6_GEOM;
2279 case MESA_SHADER_FRAGMENT:
2280 case MESA_SHADER_COMPUTE:
2281 case MESA_SHADER_KERNEL:
2282 return CP_LOAD_STATE6_FRAG;
2283 default:
2284 unreachable("bad shader type");
2285 }
2286 }
2287
2288 static inline enum a6xx_state_block
2289 tu6_stage2shadersb(gl_shader_stage type)
2290 {
2291 switch (type) {
2292 case MESA_SHADER_VERTEX:
2293 return SB6_VS_SHADER;
2294 case MESA_SHADER_FRAGMENT:
2295 return SB6_FS_SHADER;
2296 case MESA_SHADER_COMPUTE:
2297 case MESA_SHADER_KERNEL:
2298 return SB6_CS_SHADER;
2299 default:
2300 unreachable("bad shader type");
2301 return ~0;
2302 }
2303 }
2304
2305 static void
2306 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2307 struct tu_descriptor_state *descriptors_state,
2308 gl_shader_stage type,
2309 uint32_t *push_constants)
2310 {
2311 const struct tu_program_descriptor_linkage *link =
2312 &pipeline->program.link[type];
2313 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2314
2315 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2316 if (state->range[i].start < state->range[i].end) {
2317 uint32_t size = state->range[i].end - state->range[i].start;
2318 uint32_t offset = state->range[i].start;
2319
2320 /* and even if the start of the const buffer is before
2321 * first_immediate, the end may not be:
2322 */
2323 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2324
2325 if (size == 0)
2326 continue;
2327
2328 /* things should be aligned to vec4: */
2329 debug_assert((state->range[i].offset % 16) == 0);
2330 debug_assert((size % 16) == 0);
2331 debug_assert((offset % 16) == 0);
2332
2333 if (i == 0) {
2334 /* push constants */
2335 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2336 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2337 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2338 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2339 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2340 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2341 tu_cs_emit(cs, 0);
2342 tu_cs_emit(cs, 0);
2343 for (unsigned i = 0; i < size / 4; i++)
2344 tu_cs_emit(cs, push_constants[i + offset / 4]);
2345 continue;
2346 }
2347
2348 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2349
2350 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2351 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2352 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2353 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2354 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2355 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2356 tu_cs_emit_qw(cs, va + offset);
2357 }
2358 }
2359 }
2360
2361 static void
2362 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2363 struct tu_descriptor_state *descriptors_state,
2364 gl_shader_stage type)
2365 {
2366 const struct tu_program_descriptor_linkage *link =
2367 &pipeline->program.link[type];
2368
2369 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2370 uint32_t anum = align(num, 2);
2371 uint32_t i;
2372
2373 if (!num)
2374 return;
2375
2376 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2377 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2378 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2379 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2380 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2381 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2382 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2383 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2384
2385 for (i = 0; i < num; i++)
2386 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2387
2388 for (; i < anum; i++) {
2389 tu_cs_emit(cs, 0xffffffff);
2390 tu_cs_emit(cs, 0xffffffff);
2391 }
2392 }
2393
2394 static struct tu_cs_entry
2395 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2396 const struct tu_pipeline *pipeline,
2397 struct tu_descriptor_state *descriptors_state,
2398 gl_shader_stage type)
2399 {
2400 struct tu_cs cs;
2401 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2402
2403 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2404 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2405
2406 return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2407 }
2408
2409 static struct tu_cs_entry
2410 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2411 const struct tu_pipeline *pipeline,
2412 struct tu_descriptor_state *descriptors_state,
2413 gl_shader_stage type, bool *needs_border)
2414 {
2415 const struct tu_program_descriptor_linkage *link =
2416 &pipeline->program.link[type];
2417
2418 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2419 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2420 if (!size)
2421 return (struct tu_cs_entry) {};
2422
2423 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2424 enum a6xx_state_block sb;
2425
2426 switch (type) {
2427 case MESA_SHADER_VERTEX:
2428 sb = SB6_VS_TEX;
2429 opcode = CP_LOAD_STATE6_GEOM;
2430 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2431 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2432 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2433 break;
2434 case MESA_SHADER_FRAGMENT:
2435 sb = SB6_FS_TEX;
2436 opcode = CP_LOAD_STATE6_FRAG;
2437 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2438 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2439 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2440 break;
2441 case MESA_SHADER_COMPUTE:
2442 sb = SB6_CS_TEX;
2443 opcode = CP_LOAD_STATE6_FRAG;
2444 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2445 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2446 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2447 break;
2448 default:
2449 unreachable("bad state block");
2450 }
2451
2452 struct tu_cs cs;
2453 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2454
2455 for (unsigned i = 0; i < link->texture_map.num; i++) {
2456 uint32_t *ptr = texture_ptr(descriptors_state, &link->texture_map, i);
2457
2458 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2459 tu_cs_emit(&cs, ptr[j]);
2460 }
2461
2462 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2463 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2464
2465 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2466 tu_cs_emit(&cs, sampler->state[j]);
2467
2468 *needs_border |= sampler->needs_border;
2469 }
2470
2471 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2472
2473 uint64_t tex_addr = entry.bo->iova + entry.offset;
2474 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2475
2476 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2477
2478 /* output sampler state: */
2479 tu_cs_emit_pkt7(&cs, opcode, 3);
2480 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2481 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2482 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2483 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2484 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2485 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2486
2487 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2488 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2489
2490 /* emit texture state: */
2491 tu_cs_emit_pkt7(&cs, opcode, 3);
2492 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2493 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2494 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2495 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2496 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2497 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2498
2499 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2500 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2501
2502 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2503 tu_cs_emit(&cs, link->texture_map.num);
2504
2505 return tu_cs_end_sub_stream(draw_state, &cs);
2506 }
2507
2508 static void
2509 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2510 struct tu_cs *cs)
2511 {
2512 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2513
2514 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2515 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2516 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2517 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2518 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2519
2520 struct tu_cs border_cs;
2521 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2522
2523 /* TODO: actually fill with border color */
2524 for (unsigned i = 0; i < size; i++)
2525 tu_cs_emit(&border_cs, 0);
2526
2527 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2528
2529 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2530 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2531 }
2532
2533 static void
2534 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2535 struct tu_cs *cs,
2536 const struct tu_draw_info *draw)
2537 {
2538 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2539 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2540 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2541 uint32_t draw_state_group_count = 0;
2542
2543 struct tu_descriptor_state *descriptors_state =
2544 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2545
2546 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2547 if (result != VK_SUCCESS) {
2548 cmd->record_result = result;
2549 return;
2550 }
2551
2552 /* TODO lrz */
2553
2554 uint32_t pc_primitive_cntl = 0;
2555 if (pipeline->ia.primitive_restart && draw->indexed)
2556 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2557
2558 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2559 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2560 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2561
2562 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2563 tu_cs_emit(cs, pc_primitive_cntl);
2564
2565 if (cmd->state.dirty &
2566 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2567 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2568 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2569 dynamic->line_width);
2570 }
2571
2572 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2573 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2574 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2575 dynamic->stencil_compare_mask.back);
2576 }
2577
2578 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2579 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2580 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2581 dynamic->stencil_write_mask.back);
2582 }
2583
2584 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2585 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2586 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2587 dynamic->stencil_reference.back);
2588 }
2589
2590 if (cmd->state.dirty &
2591 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2592 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2593 const uint32_t binding = pipeline->vi.bindings[i];
2594 const uint32_t stride = pipeline->vi.strides[i];
2595 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2596 const VkDeviceSize offset = buf->bo_offset +
2597 cmd->state.vb.offsets[binding] +
2598 pipeline->vi.offsets[i];
2599 const VkDeviceSize size =
2600 offset < buf->bo->size ? buf->bo->size - offset : 0;
2601
2602 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2603 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2604 tu_cs_emit(cs, size);
2605 tu_cs_emit(cs, stride);
2606 }
2607 }
2608
2609 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2610 draw_state_groups[draw_state_group_count++] =
2611 (struct tu_draw_state_group) {
2612 .id = TU_DRAW_STATE_PROGRAM,
2613 .enable_mask = 0x6,
2614 .ib = pipeline->program.state_ib,
2615 };
2616 draw_state_groups[draw_state_group_count++] =
2617 (struct tu_draw_state_group) {
2618 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2619 .enable_mask = 0x1,
2620 .ib = pipeline->program.binning_state_ib,
2621 };
2622 draw_state_groups[draw_state_group_count++] =
2623 (struct tu_draw_state_group) {
2624 .id = TU_DRAW_STATE_VI,
2625 .enable_mask = 0x6,
2626 .ib = pipeline->vi.state_ib,
2627 };
2628 draw_state_groups[draw_state_group_count++] =
2629 (struct tu_draw_state_group) {
2630 .id = TU_DRAW_STATE_VI_BINNING,
2631 .enable_mask = 0x1,
2632 .ib = pipeline->vi.binning_state_ib,
2633 };
2634 draw_state_groups[draw_state_group_count++] =
2635 (struct tu_draw_state_group) {
2636 .id = TU_DRAW_STATE_VP,
2637 .enable_mask = 0x7,
2638 .ib = pipeline->vp.state_ib,
2639 };
2640 draw_state_groups[draw_state_group_count++] =
2641 (struct tu_draw_state_group) {
2642 .id = TU_DRAW_STATE_RAST,
2643 .enable_mask = 0x7,
2644 .ib = pipeline->rast.state_ib,
2645 };
2646 draw_state_groups[draw_state_group_count++] =
2647 (struct tu_draw_state_group) {
2648 .id = TU_DRAW_STATE_DS,
2649 .enable_mask = 0x7,
2650 .ib = pipeline->ds.state_ib,
2651 };
2652 draw_state_groups[draw_state_group_count++] =
2653 (struct tu_draw_state_group) {
2654 .id = TU_DRAW_STATE_BLEND,
2655 .enable_mask = 0x7,
2656 .ib = pipeline->blend.state_ib,
2657 };
2658 }
2659
2660 if (cmd->state.dirty &
2661 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2662 bool needs_border = false;
2663
2664 draw_state_groups[draw_state_group_count++] =
2665 (struct tu_draw_state_group) {
2666 .id = TU_DRAW_STATE_VS_CONST,
2667 .enable_mask = 0x7,
2668 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2669 };
2670 draw_state_groups[draw_state_group_count++] =
2671 (struct tu_draw_state_group) {
2672 .id = TU_DRAW_STATE_FS_CONST,
2673 .enable_mask = 0x6,
2674 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2675 };
2676 draw_state_groups[draw_state_group_count++] =
2677 (struct tu_draw_state_group) {
2678 .id = TU_DRAW_STATE_VS_TEX,
2679 .enable_mask = 0x7,
2680 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2681 descriptors_state, MESA_SHADER_VERTEX,
2682 &needs_border)
2683 };
2684 draw_state_groups[draw_state_group_count++] =
2685 (struct tu_draw_state_group) {
2686 .id = TU_DRAW_STATE_FS_TEX,
2687 .enable_mask = 0x6,
2688 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2689 descriptors_state, MESA_SHADER_FRAGMENT,
2690 &needs_border)
2691 };
2692
2693 if (needs_border)
2694 tu6_emit_border_color(cmd, cs);
2695 }
2696
2697 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2698 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2699 const struct tu_draw_state_group *group = &draw_state_groups[i];
2700
2701 uint32_t cp_set_draw_state =
2702 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2703 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2704 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2705 uint64_t iova;
2706 if (group->ib.size) {
2707 iova = group->ib.bo->iova + group->ib.offset;
2708 } else {
2709 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2710 iova = 0;
2711 }
2712
2713 tu_cs_emit(cs, cp_set_draw_state);
2714 tu_cs_emit_qw(cs, iova);
2715 }
2716
2717 tu_cs_sanity_check(cs);
2718
2719 /* track BOs */
2720 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2721 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2722 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2723 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2724 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2725 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2726 }
2727 }
2728 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2729 for (uint32_t i = 0; i < MAX_VBS; i++) {
2730 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2731 if (buf)
2732 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2733 }
2734 }
2735 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2736 unsigned i;
2737 for_each_bit(i, descriptors_state->valid) {
2738 struct tu_descriptor_set *set = descriptors_state->sets[i];
2739 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2740 if (set->descriptors[j]) {
2741 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2742 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2743 }
2744 }
2745 }
2746 cmd->state.dirty = 0;
2747 }
2748
2749 static void
2750 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2751 struct tu_cs *cs,
2752 const struct tu_draw_info *draw)
2753 {
2754
2755 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2756
2757 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2758 tu_cs_emit(cs, draw->vertex_offset);
2759 tu_cs_emit(cs, draw->first_instance);
2760
2761 /* TODO hw binning */
2762 if (draw->indexed) {
2763 const enum a4xx_index_size index_size =
2764 tu6_index_size(cmd->state.index_type);
2765 const uint32_t index_bytes =
2766 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2767 const struct tu_buffer *buf = cmd->state.index_buffer;
2768 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2769 index_bytes * draw->first_index;
2770 const uint32_t size = index_bytes * draw->count;
2771
2772 const uint32_t cp_draw_indx =
2773 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2774 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2775 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2776 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2777
2778 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2779 tu_cs_emit(cs, cp_draw_indx);
2780 tu_cs_emit(cs, draw->instance_count);
2781 tu_cs_emit(cs, draw->count);
2782 tu_cs_emit(cs, 0x0); /* XXX */
2783 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2784 tu_cs_emit(cs, size);
2785 } else {
2786 const uint32_t cp_draw_indx =
2787 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2788 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2789 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2790
2791 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2792 tu_cs_emit(cs, cp_draw_indx);
2793 tu_cs_emit(cs, draw->instance_count);
2794 tu_cs_emit(cs, draw->count);
2795 }
2796 }
2797
2798 static void
2799 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2800 {
2801 struct tu_cs *cs = &cmd->draw_cs;
2802
2803 tu6_bind_draw_states(cmd, cs, draw);
2804
2805 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2806 if (result != VK_SUCCESS) {
2807 cmd->record_result = result;
2808 return;
2809 }
2810
2811 if (draw->indirect) {
2812 tu_finishme("indirect draw");
2813 return;
2814 }
2815
2816 /* TODO tu6_emit_marker should pick different regs depending on cs */
2817 tu6_emit_marker(cmd, cs);
2818 tu6_emit_draw_direct(cmd, cs, draw);
2819 tu6_emit_marker(cmd, cs);
2820
2821 cmd->wait_for_idle = true;
2822
2823 tu_cs_sanity_check(cs);
2824 }
2825
2826 void
2827 tu_CmdDraw(VkCommandBuffer commandBuffer,
2828 uint32_t vertexCount,
2829 uint32_t instanceCount,
2830 uint32_t firstVertex,
2831 uint32_t firstInstance)
2832 {
2833 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2834 struct tu_draw_info info = {};
2835
2836 info.count = vertexCount;
2837 info.instance_count = instanceCount;
2838 info.first_instance = firstInstance;
2839 info.vertex_offset = firstVertex;
2840
2841 tu_draw(cmd_buffer, &info);
2842 }
2843
2844 void
2845 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2846 uint32_t indexCount,
2847 uint32_t instanceCount,
2848 uint32_t firstIndex,
2849 int32_t vertexOffset,
2850 uint32_t firstInstance)
2851 {
2852 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2853 struct tu_draw_info info = {};
2854
2855 info.indexed = true;
2856 info.count = indexCount;
2857 info.instance_count = instanceCount;
2858 info.first_index = firstIndex;
2859 info.vertex_offset = vertexOffset;
2860 info.first_instance = firstInstance;
2861
2862 tu_draw(cmd_buffer, &info);
2863 }
2864
2865 void
2866 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2867 VkBuffer _buffer,
2868 VkDeviceSize offset,
2869 uint32_t drawCount,
2870 uint32_t stride)
2871 {
2872 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2873 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2874 struct tu_draw_info info = {};
2875
2876 info.count = drawCount;
2877 info.indirect = buffer;
2878 info.indirect_offset = offset;
2879 info.stride = stride;
2880
2881 tu_draw(cmd_buffer, &info);
2882 }
2883
2884 void
2885 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2886 VkBuffer _buffer,
2887 VkDeviceSize offset,
2888 uint32_t drawCount,
2889 uint32_t stride)
2890 {
2891 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2892 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2893 struct tu_draw_info info = {};
2894
2895 info.indexed = true;
2896 info.count = drawCount;
2897 info.indirect = buffer;
2898 info.indirect_offset = offset;
2899 info.stride = stride;
2900
2901 tu_draw(cmd_buffer, &info);
2902 }
2903
2904 struct tu_dispatch_info
2905 {
2906 /**
2907 * Determine the layout of the grid (in block units) to be used.
2908 */
2909 uint32_t blocks[3];
2910
2911 /**
2912 * A starting offset for the grid. If unaligned is set, the offset
2913 * must still be aligned.
2914 */
2915 uint32_t offsets[3];
2916 /**
2917 * Whether it's an unaligned compute dispatch.
2918 */
2919 bool unaligned;
2920
2921 /**
2922 * Indirect compute parameters resource.
2923 */
2924 struct tu_buffer *indirect;
2925 uint64_t indirect_offset;
2926 };
2927
2928 static void
2929 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2930 const struct tu_dispatch_info *info)
2931 {
2932 }
2933
2934 void
2935 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2936 uint32_t base_x,
2937 uint32_t base_y,
2938 uint32_t base_z,
2939 uint32_t x,
2940 uint32_t y,
2941 uint32_t z)
2942 {
2943 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2944 struct tu_dispatch_info info = {};
2945
2946 info.blocks[0] = x;
2947 info.blocks[1] = y;
2948 info.blocks[2] = z;
2949
2950 info.offsets[0] = base_x;
2951 info.offsets[1] = base_y;
2952 info.offsets[2] = base_z;
2953 tu_dispatch(cmd_buffer, &info);
2954 }
2955
2956 void
2957 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2958 uint32_t x,
2959 uint32_t y,
2960 uint32_t z)
2961 {
2962 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2963 }
2964
2965 void
2966 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2967 VkBuffer _buffer,
2968 VkDeviceSize offset)
2969 {
2970 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2971 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2972 struct tu_dispatch_info info = {};
2973
2974 info.indirect = buffer;
2975 info.indirect_offset = offset;
2976
2977 tu_dispatch(cmd_buffer, &info);
2978 }
2979
2980 void
2981 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2982 {
2983 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2984
2985 tu_cs_end(&cmd_buffer->draw_cs);
2986
2987 tu_cmd_render_tiles(cmd_buffer);
2988
2989 /* discard draw_cs entries now that the tiles are rendered */
2990 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2991
2992 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2993 cmd_buffer->state.attachments = NULL;
2994
2995 cmd_buffer->state.pass = NULL;
2996 cmd_buffer->state.subpass = NULL;
2997 cmd_buffer->state.framebuffer = NULL;
2998 }
2999
3000 void
3001 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3002 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3003 {
3004 tu_CmdEndRenderPass(commandBuffer);
3005 }
3006
3007 struct tu_barrier_info
3008 {
3009 uint32_t eventCount;
3010 const VkEvent *pEvents;
3011 VkPipelineStageFlags srcStageMask;
3012 };
3013
3014 static void
3015 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3016 uint32_t memoryBarrierCount,
3017 const VkMemoryBarrier *pMemoryBarriers,
3018 uint32_t bufferMemoryBarrierCount,
3019 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3020 uint32_t imageMemoryBarrierCount,
3021 const VkImageMemoryBarrier *pImageMemoryBarriers,
3022 const struct tu_barrier_info *info)
3023 {
3024 }
3025
3026 void
3027 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3028 VkPipelineStageFlags srcStageMask,
3029 VkPipelineStageFlags destStageMask,
3030 VkBool32 byRegion,
3031 uint32_t memoryBarrierCount,
3032 const VkMemoryBarrier *pMemoryBarriers,
3033 uint32_t bufferMemoryBarrierCount,
3034 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3035 uint32_t imageMemoryBarrierCount,
3036 const VkImageMemoryBarrier *pImageMemoryBarriers)
3037 {
3038 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3039 struct tu_barrier_info info;
3040
3041 info.eventCount = 0;
3042 info.pEvents = NULL;
3043 info.srcStageMask = srcStageMask;
3044
3045 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3046 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3047 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3048 }
3049
3050 static void
3051 write_event(struct tu_cmd_buffer *cmd_buffer,
3052 struct tu_event *event,
3053 VkPipelineStageFlags stageMask,
3054 unsigned value)
3055 {
3056 }
3057
3058 void
3059 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3060 VkEvent _event,
3061 VkPipelineStageFlags stageMask)
3062 {
3063 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3064 TU_FROM_HANDLE(tu_event, event, _event);
3065
3066 write_event(cmd_buffer, event, stageMask, 1);
3067 }
3068
3069 void
3070 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3071 VkEvent _event,
3072 VkPipelineStageFlags stageMask)
3073 {
3074 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3075 TU_FROM_HANDLE(tu_event, event, _event);
3076
3077 write_event(cmd_buffer, event, stageMask, 0);
3078 }
3079
3080 void
3081 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3082 uint32_t eventCount,
3083 const VkEvent *pEvents,
3084 VkPipelineStageFlags srcStageMask,
3085 VkPipelineStageFlags dstStageMask,
3086 uint32_t memoryBarrierCount,
3087 const VkMemoryBarrier *pMemoryBarriers,
3088 uint32_t bufferMemoryBarrierCount,
3089 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3090 uint32_t imageMemoryBarrierCount,
3091 const VkImageMemoryBarrier *pImageMemoryBarriers)
3092 {
3093 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3094 struct tu_barrier_info info;
3095
3096 info.eventCount = eventCount;
3097 info.pEvents = pEvents;
3098 info.srcStageMask = 0;
3099
3100 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3101 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3102 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3103 }
3104
3105 void
3106 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3107 {
3108 /* No-op */
3109 }