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freedreno/a6xx: use single format enum
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32
33 #include "vk_format.h"
34
35 #include "tu_cs.h"
36 #include "tu_blit.h"
37
38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
39
40 void
41 tu_bo_list_init(struct tu_bo_list *list)
42 {
43 list->count = list->capacity = 0;
44 list->bo_infos = NULL;
45 }
46
47 void
48 tu_bo_list_destroy(struct tu_bo_list *list)
49 {
50 free(list->bo_infos);
51 }
52
53 void
54 tu_bo_list_reset(struct tu_bo_list *list)
55 {
56 list->count = 0;
57 }
58
59 /**
60 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
61 */
62 static uint32_t
63 tu_bo_list_add_info(struct tu_bo_list *list,
64 const struct drm_msm_gem_submit_bo *bo_info)
65 {
66 assert(bo_info->handle != 0);
67
68 for (uint32_t i = 0; i < list->count; ++i) {
69 if (list->bo_infos[i].handle == bo_info->handle) {
70 assert(list->bo_infos[i].presumed == bo_info->presumed);
71 list->bo_infos[i].flags |= bo_info->flags;
72 return i;
73 }
74 }
75
76 /* grow list->bo_infos if needed */
77 if (list->count == list->capacity) {
78 uint32_t new_capacity = MAX2(2 * list->count, 16);
79 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
80 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
81 if (!new_bo_infos)
82 return TU_BO_LIST_FAILED;
83 list->bo_infos = new_bo_infos;
84 list->capacity = new_capacity;
85 }
86
87 list->bo_infos[list->count] = *bo_info;
88 return list->count++;
89 }
90
91 uint32_t
92 tu_bo_list_add(struct tu_bo_list *list,
93 const struct tu_bo *bo,
94 uint32_t flags)
95 {
96 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
97 .flags = flags,
98 .handle = bo->gem_handle,
99 .presumed = bo->iova,
100 });
101 }
102
103 VkResult
104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
105 {
106 for (uint32_t i = 0; i < other->count; i++) {
107 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
108 return VK_ERROR_OUT_OF_HOST_MEMORY;
109 }
110
111 return VK_SUCCESS;
112 }
113
114 static void
115 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
116 const struct tu_device *dev,
117 uint32_t pixels)
118 {
119 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
120 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
121 const uint32_t max_tile_width = 1024; /* A6xx */
122
123 tiling->tile0.offset = (VkOffset2D) {
124 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
125 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
126 };
127
128 const uint32_t ra_width =
129 tiling->render_area.extent.width +
130 (tiling->render_area.offset.x - tiling->tile0.offset.x);
131 const uint32_t ra_height =
132 tiling->render_area.extent.height +
133 (tiling->render_area.offset.y - tiling->tile0.offset.y);
134
135 /* start from 1 tile */
136 tiling->tile_count = (VkExtent2D) {
137 .width = 1,
138 .height = 1,
139 };
140 tiling->tile0.extent = (VkExtent2D) {
141 .width = align(ra_width, tile_align_w),
142 .height = align(ra_height, tile_align_h),
143 };
144
145 /* do not exceed max tile width */
146 while (tiling->tile0.extent.width > max_tile_width) {
147 tiling->tile_count.width++;
148 tiling->tile0.extent.width =
149 align(ra_width / tiling->tile_count.width, tile_align_w);
150 }
151
152 /* do not exceed gmem size */
153 while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
154 if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
155 tiling->tile_count.width++;
156 tiling->tile0.extent.width =
157 align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
158 } else {
159 /* if this assert fails then layout is impossible.. */
160 assert(tiling->tile0.extent.height > tile_align_h);
161 tiling->tile_count.height++;
162 tiling->tile0.extent.height =
163 align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
164 }
165 }
166 }
167
168 static void
169 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
170 const struct tu_device *dev)
171 {
172 const uint32_t max_pipe_count = 32; /* A6xx */
173
174 /* start from 1 tile per pipe */
175 tiling->pipe0 = (VkExtent2D) {
176 .width = 1,
177 .height = 1,
178 };
179 tiling->pipe_count = tiling->tile_count;
180
181 /* do not exceed max pipe count vertically */
182 while (tiling->pipe_count.height > max_pipe_count) {
183 tiling->pipe0.height += 2;
184 tiling->pipe_count.height =
185 (tiling->tile_count.height + tiling->pipe0.height - 1) /
186 tiling->pipe0.height;
187 }
188
189 /* do not exceed max pipe count */
190 while (tiling->pipe_count.width * tiling->pipe_count.height >
191 max_pipe_count) {
192 tiling->pipe0.width += 1;
193 tiling->pipe_count.width =
194 (tiling->tile_count.width + tiling->pipe0.width - 1) /
195 tiling->pipe0.width;
196 }
197 }
198
199 static void
200 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
201 const struct tu_device *dev)
202 {
203 const uint32_t max_pipe_count = 32; /* A6xx */
204 const uint32_t used_pipe_count =
205 tiling->pipe_count.width * tiling->pipe_count.height;
206 const VkExtent2D last_pipe = {
207 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
208 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
209 };
210
211 assert(used_pipe_count <= max_pipe_count);
212 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
213
214 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
215 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
216 const uint32_t pipe_x = tiling->pipe0.width * x;
217 const uint32_t pipe_y = tiling->pipe0.height * y;
218 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
219 ? last_pipe.width
220 : tiling->pipe0.width;
221 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
222 ? last_pipe.height
223 : tiling->pipe0.height;
224 const uint32_t n = tiling->pipe_count.width * y + x;
225
226 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
227 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
228 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
229 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
230 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
231 }
232 }
233
234 memset(tiling->pipe_config + used_pipe_count, 0,
235 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
236 }
237
238 static void
239 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
240 const struct tu_device *dev,
241 uint32_t tx,
242 uint32_t ty,
243 struct tu_tile *tile)
244 {
245 /* find the pipe and the slot for tile (tx, ty) */
246 const uint32_t px = tx / tiling->pipe0.width;
247 const uint32_t py = ty / tiling->pipe0.height;
248 const uint32_t sx = tx - tiling->pipe0.width * px;
249 const uint32_t sy = ty - tiling->pipe0.height * py;
250
251 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
252 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
253 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
254
255 /* convert to 1D indices */
256 tile->pipe = tiling->pipe_count.width * py + px;
257 tile->slot = tiling->pipe0.width * sy + sx;
258
259 /* get the blit area for the tile */
260 tile->begin = (VkOffset2D) {
261 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
262 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
263 };
264 tile->end.x =
265 (tx == tiling->tile_count.width - 1)
266 ? tiling->render_area.offset.x + tiling->render_area.extent.width
267 : tile->begin.x + tiling->tile0.extent.width;
268 tile->end.y =
269 (ty == tiling->tile_count.height - 1)
270 ? tiling->render_area.offset.y + tiling->render_area.extent.height
271 : tile->begin.y + tiling->tile0.extent.height;
272 }
273
274 enum a3xx_msaa_samples
275 tu_msaa_samples(uint32_t samples)
276 {
277 switch (samples) {
278 case 1:
279 return MSAA_ONE;
280 case 2:
281 return MSAA_TWO;
282 case 4:
283 return MSAA_FOUR;
284 case 8:
285 return MSAA_EIGHT;
286 default:
287 assert(!"invalid sample count");
288 return MSAA_ONE;
289 }
290 }
291
292 static enum a4xx_index_size
293 tu6_index_size(VkIndexType type)
294 {
295 switch (type) {
296 case VK_INDEX_TYPE_UINT16:
297 return INDEX4_SIZE_16_BIT;
298 case VK_INDEX_TYPE_UINT32:
299 return INDEX4_SIZE_32_BIT;
300 default:
301 unreachable("invalid VkIndexType");
302 return INDEX4_SIZE_8_BIT;
303 }
304 }
305
306 static void
307 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
308 {
309 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
310 }
311
312 unsigned
313 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
314 struct tu_cs *cs,
315 enum vgt_event_type event,
316 bool need_seqno)
317 {
318 unsigned seqno = 0;
319
320 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
321 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
322 if (need_seqno) {
323 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
324 seqno = ++cmd->scratch_seqno;
325 tu_cs_emit(cs, seqno);
326 }
327
328 return seqno;
329 }
330
331 static void
332 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
333 {
334 tu6_emit_event_write(cmd, cs, 0x31, false);
335 }
336
337 static void
338 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
339 {
340 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
341 }
342
343 static void
344 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
345 {
346 if (cmd->wait_for_idle) {
347 tu_cs_emit_wfi(cs);
348 cmd->wait_for_idle = false;
349 }
350 }
351
352 #define tu_image_view_ubwc_pitches(iview) \
353 .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
354 .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
355
356 static void
357 tu6_emit_zs(struct tu_cmd_buffer *cmd,
358 const struct tu_subpass *subpass,
359 struct tu_cs *cs)
360 {
361 const struct tu_framebuffer *fb = cmd->state.framebuffer;
362
363 const uint32_t a = subpass->depth_stencil_attachment.attachment;
364 if (a == VK_ATTACHMENT_UNUSED) {
365 tu_cs_emit_regs(cs,
366 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
367 A6XX_RB_DEPTH_BUFFER_PITCH(0),
368 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
369 A6XX_RB_DEPTH_BUFFER_BASE(0),
370 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
371
372 tu_cs_emit_regs(cs,
373 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
374
375 tu_cs_emit_regs(cs,
376 A6XX_GRAS_LRZ_BUFFER_BASE(0),
377 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
378 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
379
380 tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
381
382 return;
383 }
384
385 const struct tu_image_view *iview = fb->attachments[a].attachment;
386 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
387
388 tu_cs_emit_regs(cs,
389 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
390 A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
391 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
392 A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
393 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
394
395 tu_cs_emit_regs(cs,
396 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
397
398 tu_cs_emit_regs(cs,
399 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
401
402 tu_cs_emit_regs(cs,
403 A6XX_GRAS_LRZ_BUFFER_BASE(0),
404 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
405 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
406
407 tu_cs_emit_regs(cs,
408 A6XX_RB_STENCIL_INFO(0));
409
410 /* enable zs? */
411 }
412
413 static void
414 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
415 const struct tu_subpass *subpass,
416 struct tu_cs *cs)
417 {
418 const struct tu_framebuffer *fb = cmd->state.framebuffer;
419 unsigned char mrt_comp[MAX_RTS] = { 0 };
420 unsigned srgb_cntl = 0;
421
422 for (uint32_t i = 0; i < subpass->color_count; ++i) {
423 uint32_t a = subpass->color_attachments[i].attachment;
424 if (a == VK_ATTACHMENT_UNUSED)
425 continue;
426
427 const struct tu_image_view *iview = fb->attachments[a].attachment;
428 const enum a6xx_tile_mode tile_mode =
429 tu6_get_image_tile_mode(iview->image, iview->base_mip);
430
431 mrt_comp[i] = 0xf;
432
433 if (vk_format_is_srgb(iview->vk_format))
434 srgb_cntl |= (1 << i);
435
436 const struct tu_native_format *format =
437 tu6_get_native_format(iview->vk_format);
438 assert(format && format->rb >= 0);
439
440 tu_cs_emit_regs(cs,
441 A6XX_RB_MRT_BUF_INFO(i,
442 .color_tile_mode = tile_mode,
443 .color_format = format->rb,
444 .color_swap = format->swap),
445 A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
446 A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
447 A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
448 A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
449
450 tu_cs_emit_regs(cs,
451 A6XX_SP_FS_MRT_REG(i,
452 .color_format = format->rb,
453 .color_sint = vk_format_is_sint(iview->vk_format),
454 .color_uint = vk_format_is_uint(iview->vk_format)));
455
456 tu_cs_emit_regs(cs,
457 A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
458 A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
459 }
460
461 tu_cs_emit_regs(cs,
462 A6XX_RB_SRGB_CNTL(srgb_cntl));
463
464 tu_cs_emit_regs(cs,
465 A6XX_SP_SRGB_CNTL(srgb_cntl));
466
467 tu_cs_emit_regs(cs,
468 A6XX_RB_RENDER_COMPONENTS(
469 .rt0 = mrt_comp[0],
470 .rt1 = mrt_comp[1],
471 .rt2 = mrt_comp[2],
472 .rt3 = mrt_comp[3],
473 .rt4 = mrt_comp[4],
474 .rt5 = mrt_comp[5],
475 .rt6 = mrt_comp[6],
476 .rt7 = mrt_comp[7]));
477
478 tu_cs_emit_regs(cs,
479 A6XX_SP_FS_RENDER_COMPONENTS(
480 .rt0 = mrt_comp[0],
481 .rt1 = mrt_comp[1],
482 .rt2 = mrt_comp[2],
483 .rt3 = mrt_comp[3],
484 .rt4 = mrt_comp[4],
485 .rt5 = mrt_comp[5],
486 .rt6 = mrt_comp[6],
487 .rt7 = mrt_comp[7]));
488 }
489
490 static void
491 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
492 const struct tu_subpass *subpass,
493 struct tu_cs *cs)
494 {
495 const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
496 bool msaa_disable = samples == MSAA_ONE;
497
498 tu_cs_emit_regs(cs,
499 A6XX_SP_TP_RAS_MSAA_CNTL(samples),
500 A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
501 .msaa_disable = msaa_disable));
502
503 tu_cs_emit_regs(cs,
504 A6XX_GRAS_RAS_MSAA_CNTL(samples),
505 A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
506 .msaa_disable = msaa_disable));
507
508 tu_cs_emit_regs(cs,
509 A6XX_RB_RAS_MSAA_CNTL(samples),
510 A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
511 .msaa_disable = msaa_disable));
512
513 tu_cs_emit_regs(cs,
514 A6XX_RB_MSAA_CNTL(samples));
515 }
516
517 static void
518 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
519 {
520 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
521 const uint32_t bin_w = tiling->tile0.extent.width;
522 const uint32_t bin_h = tiling->tile0.extent.height;
523
524 tu_cs_emit_regs(cs,
525 A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
526 .binh = bin_h,
527 .dword = flags));
528
529 tu_cs_emit_regs(cs,
530 A6XX_RB_BIN_CONTROL(.binw = bin_w,
531 .binh = bin_h,
532 .dword = flags));
533
534 /* no flag for RB_BIN_CONTROL2... */
535 tu_cs_emit_regs(cs,
536 A6XX_RB_BIN_CONTROL2(.binw = bin_w,
537 .binh = bin_h));
538 }
539
540 static void
541 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
542 struct tu_cs *cs,
543 bool binning)
544 {
545 uint32_t cntl = 0;
546 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
547 if (binning)
548 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
549
550 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
551 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
552 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
553 tu_cs_emit(cs, cntl);
554 }
555
556 static void
557 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
558 {
559 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
560 uint32_t x1 = render_area->offset.x;
561 uint32_t y1 = render_area->offset.y;
562 uint32_t x2 = x1 + render_area->extent.width - 1;
563 uint32_t y2 = y1 + render_area->extent.height - 1;
564
565 /* TODO: alignment requirement seems to be less than tile_align_w/h */
566 if (align) {
567 x1 = x1 & ~cmd->device->physical_device->tile_align_w;
568 y1 = y1 & ~cmd->device->physical_device->tile_align_h;
569 x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
570 y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
571 }
572
573 tu_cs_emit_regs(cs,
574 A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
575 A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
576 }
577
578 static void
579 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
580 struct tu_cs *cs,
581 const struct tu_image_view *iview,
582 uint32_t gmem_offset,
583 bool resolve)
584 {
585 tu_cs_emit_regs(cs,
586 A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
587
588 const struct tu_native_format *format =
589 tu6_get_native_format(iview->vk_format);
590 assert(format && format->rb >= 0);
591
592 enum a6xx_tile_mode tile_mode =
593 tu6_get_image_tile_mode(iview->image, iview->base_mip);
594 tu_cs_emit_regs(cs,
595 A6XX_RB_BLIT_DST_INFO(
596 .tile_mode = tile_mode,
597 .samples = tu_msaa_samples(iview->image->samples),
598 .color_format = format->rb,
599 .color_swap = format->swap,
600 .flags = iview->image->layout.ubwc_layer_size != 0),
601 A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
602 A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
603 A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
604
605 if (iview->image->layout.ubwc_layer_size) {
606 tu_cs_emit_regs(cs,
607 A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
608 A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
609 }
610
611 tu_cs_emit_regs(cs,
612 A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
613 }
614
615 static void
616 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
617 {
618 tu6_emit_marker(cmd, cs);
619 tu6_emit_event_write(cmd, cs, BLIT, false);
620 tu6_emit_marker(cmd, cs);
621 }
622
623 static void
624 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
625 struct tu_cs *cs,
626 uint32_t x1,
627 uint32_t y1,
628 uint32_t x2,
629 uint32_t y2)
630 {
631 tu_cs_emit_regs(cs,
632 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
633 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
634
635 tu_cs_emit_regs(cs,
636 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
637 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
638 }
639
640 static void
641 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
642 struct tu_cs *cs,
643 uint32_t x1,
644 uint32_t y1)
645 {
646 tu_cs_emit_regs(cs,
647 A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
648
649 tu_cs_emit_regs(cs,
650 A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
651
652 tu_cs_emit_regs(cs,
653 A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
654
655 tu_cs_emit_regs(cs,
656 A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
657 }
658
659 static bool
660 use_hw_binning(struct tu_cmd_buffer *cmd)
661 {
662 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
663
664 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
665 return false;
666
667 return (tiling->tile_count.width * tiling->tile_count.height) > 2;
668 }
669
670 static void
671 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
672 struct tu_cs *cs,
673 const struct tu_tile *tile)
674 {
675 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
676 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
677
678 tu6_emit_marker(cmd, cs);
679 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
680 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
681 tu6_emit_marker(cmd, cs);
682
683 const uint32_t x1 = tile->begin.x;
684 const uint32_t y1 = tile->begin.y;
685 const uint32_t x2 = tile->end.x - 1;
686 const uint32_t y2 = tile->end.y - 1;
687 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
688 tu6_emit_window_offset(cmd, cs, x1, y1);
689
690 tu_cs_emit_regs(cs,
691 A6XX_VPC_SO_OVERRIDE(.so_disable = true));
692
693 if (use_hw_binning(cmd)) {
694 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
695
696 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
697 tu_cs_emit(cs, 0x0);
698
699 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
700 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
701 A6XX_CP_REG_TEST_0_BIT(0) |
702 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
703
704 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
705 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
706 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
707
708 /* if (no overflow) */ {
709 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
710 tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
711 CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
712 tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
713 tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
714 tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
715
716 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
717 tu_cs_emit(cs, 0x0);
718
719 /* use a NOP packet to skip over the 'else' side: */
720 tu_cs_emit_pkt7(cs, CP_NOP, 2);
721 } /* else */ {
722 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
723 tu_cs_emit(cs, 0x1);
724 }
725
726 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
727 tu_cs_emit(cs, 0x0);
728
729 tu_cs_emit_regs(cs,
730 A6XX_RB_UNKNOWN_8804(0));
731
732 tu_cs_emit_regs(cs,
733 A6XX_SP_TP_UNKNOWN_B304(0));
734
735 tu_cs_emit_regs(cs,
736 A6XX_GRAS_UNKNOWN_80A4(0));
737 } else {
738 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
739 tu_cs_emit(cs, 0x1);
740
741 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
742 tu_cs_emit(cs, 0x0);
743 }
744 }
745
746 static void
747 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
748 {
749 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
750 const struct tu_framebuffer *fb = cmd->state.framebuffer;
751 const struct tu_image_view *iview = fb->attachments[a].attachment;
752 const struct tu_render_pass_attachment *attachment =
753 &cmd->state.pass->attachments[a];
754
755 if (attachment->gmem_offset < 0)
756 return;
757
758 const uint32_t x1 = tiling->render_area.offset.x;
759 const uint32_t y1 = tiling->render_area.offset.y;
760 const uint32_t x2 = x1 + tiling->render_area.extent.width;
761 const uint32_t y2 = y1 + tiling->render_area.extent.height;
762 const uint32_t tile_x2 =
763 tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
764 const uint32_t tile_y2 =
765 tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
766 bool need_load =
767 x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
768 y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
769
770 if (need_load)
771 tu_finishme("improve handling of unaligned render area");
772
773 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
774 need_load = true;
775
776 if (vk_format_has_stencil(iview->vk_format) &&
777 attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
778 need_load = true;
779
780 if (need_load) {
781 tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
782 tu6_emit_blit(cmd, cs);
783 }
784 }
785
786 static void
787 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
788 uint32_t a,
789 const VkRenderPassBeginInfo *info)
790 {
791 const struct tu_framebuffer *fb = cmd->state.framebuffer;
792 const struct tu_image_view *iview = fb->attachments[a].attachment;
793 const struct tu_render_pass_attachment *attachment =
794 &cmd->state.pass->attachments[a];
795 unsigned clear_mask = 0;
796
797 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
798 if (attachment->gmem_offset < 0)
799 return;
800
801 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
802 clear_mask = 0xf;
803
804 if (vk_format_has_stencil(iview->vk_format)) {
805 clear_mask &= 0x1;
806 if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
807 clear_mask |= 0x2;
808 }
809 if (!clear_mask)
810 return;
811
812 const struct tu_native_format *format =
813 tu6_get_native_format(iview->vk_format);
814 assert(format && format->rb >= 0);
815
816 tu_cs_emit_regs(cs,
817 A6XX_RB_BLIT_DST_INFO(.color_format = format->rb));
818
819 tu_cs_emit_regs(cs,
820 A6XX_RB_BLIT_INFO(.gmem = true,
821 .clear_mask = clear_mask));
822
823 tu_cs_emit_regs(cs,
824 A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
825
826 tu_cs_emit_regs(cs,
827 A6XX_RB_UNKNOWN_88D0(0));
828
829 uint32_t clear_vals[4] = { 0 };
830 tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
831
832 tu_cs_emit_regs(cs,
833 A6XX_RB_BLIT_CLEAR_COLOR_DW0(clear_vals[0]),
834 A6XX_RB_BLIT_CLEAR_COLOR_DW1(clear_vals[1]),
835 A6XX_RB_BLIT_CLEAR_COLOR_DW2(clear_vals[2]),
836 A6XX_RB_BLIT_CLEAR_COLOR_DW3(clear_vals[3]));
837
838 tu6_emit_blit(cmd, cs);
839 }
840
841 static void
842 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
843 struct tu_cs *cs,
844 uint32_t a,
845 uint32_t gmem_a)
846 {
847 if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
848 return;
849
850 tu6_emit_blit_info(cmd, cs,
851 cmd->state.framebuffer->attachments[a].attachment,
852 cmd->state.pass->attachments[gmem_a].gmem_offset, true);
853 tu6_emit_blit(cmd, cs);
854 }
855
856 static void
857 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
858 {
859 const struct tu_render_pass *pass = cmd->state.pass;
860 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
861
862 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
863 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
864 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
865 CP_SET_DRAW_STATE__0_GROUP_ID(0));
866 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
867 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
868
869 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
870 tu_cs_emit(cs, 0x0);
871
872 tu6_emit_marker(cmd, cs);
873 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
874 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
875 tu6_emit_marker(cmd, cs);
876
877 tu6_emit_blit_scissor(cmd, cs, true);
878
879 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
880 if (pass->attachments[a].gmem_offset >= 0)
881 tu6_emit_store_attachment(cmd, cs, a, a);
882 }
883
884 if (subpass->resolve_attachments) {
885 for (unsigned i = 0; i < subpass->color_count; i++) {
886 uint32_t a = subpass->resolve_attachments[i].attachment;
887 if (a != VK_ATTACHMENT_UNUSED)
888 tu6_emit_store_attachment(cmd, cs, a,
889 subpass->color_attachments[i].attachment);
890 }
891 }
892 }
893
894 static void
895 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
896 {
897 tu_cs_emit_regs(cs,
898 A6XX_PC_RESTART_INDEX(restart_index));
899 }
900
901 static void
902 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
903 {
904 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
905 if (result != VK_SUCCESS) {
906 cmd->record_result = result;
907 return;
908 }
909
910 tu6_emit_cache_flush(cmd, cs);
911
912 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
913
914 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
915 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
916 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
917 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
919 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
920 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
921 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
922 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
923
924 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
926 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
928 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
930 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
932 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
935 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
937 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
938
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
940
941 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
942 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
943 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
944
945 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
946 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
947 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
948 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
949 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
950 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
951 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
952 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
953 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
954 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
955 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
956 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
959 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
960
961 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
962 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
963
964 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
965 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
966
967 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
970
971 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
972 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
973
974 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
975
976 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
981 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
983 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
984 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
985 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
986 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
987 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
988 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
989 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
990 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
991 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
992 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
993 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
994 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
995 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
996 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
997 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
998 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
999
1000 tu6_emit_marker(cmd, cs);
1001
1002 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1003
1004 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1005
1006 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1007
1008 /* we don't use this yet.. probably best to disable.. */
1009 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1010 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1011 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1012 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1013 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1014 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1015
1016 tu_cs_emit_regs(cs,
1017 A6XX_VPC_SO_BUFFER_BASE(0),
1018 A6XX_VPC_SO_BUFFER_SIZE(0));
1019
1020 tu_cs_emit_regs(cs,
1021 A6XX_VPC_SO_FLUSH_BASE(0));
1022
1023 tu_cs_emit_regs(cs,
1024 A6XX_VPC_SO_BUF_CNTL(0));
1025
1026 tu_cs_emit_regs(cs,
1027 A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1028
1029 tu_cs_emit_regs(cs,
1030 A6XX_VPC_SO_BUFFER_BASE(1, 0),
1031 A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1032
1033 tu_cs_emit_regs(cs,
1034 A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1035 A6XX_VPC_SO_FLUSH_BASE(1, 0),
1036 A6XX_VPC_SO_BUFFER_BASE(2, 0),
1037 A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1038
1039 tu_cs_emit_regs(cs,
1040 A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1041 A6XX_VPC_SO_FLUSH_BASE(2, 0),
1042 A6XX_VPC_SO_BUFFER_BASE(3, 0),
1043 A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1044
1045 tu_cs_emit_regs(cs,
1046 A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1047 A6XX_VPC_SO_FLUSH_BASE(3, 0));
1048
1049 tu_cs_emit_regs(cs,
1050 A6XX_SP_HS_CTRL_REG0(0));
1051
1052 tu_cs_emit_regs(cs,
1053 A6XX_SP_GS_CTRL_REG0(0));
1054
1055 tu_cs_emit_regs(cs,
1056 A6XX_GRAS_LRZ_CNTL(0));
1057
1058 tu_cs_emit_regs(cs,
1059 A6XX_RB_LRZ_CNTL(0));
1060
1061 tu_cs_sanity_check(cs);
1062 }
1063
1064 static void
1065 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1066 {
1067 unsigned seqno;
1068
1069 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1070
1071 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1072 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1073 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1074 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1075 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1076 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1077 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1078
1079 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1080
1081 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1082 tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1083 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1084 tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1085 }
1086
1087 static void
1088 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1089 {
1090 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1091
1092 tu_cs_emit_regs(cs,
1093 A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1094 .height = tiling->tile0.extent.height),
1095 A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
1096 .bo_offset = 32 * cmd->vsc_data_pitch));
1097
1098 tu_cs_emit_regs(cs,
1099 A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1100 .ny = tiling->tile_count.height));
1101
1102 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1103 for (unsigned i = 0; i < 32; i++)
1104 tu_cs_emit(cs, tiling->pipe_config[i]);
1105
1106 tu_cs_emit_regs(cs,
1107 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1108 A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1109 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1110
1111 tu_cs_emit_regs(cs,
1112 A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1113 A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1114 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1115 }
1116
1117 static void
1118 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1119 {
1120 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1121 const uint32_t used_pipe_count =
1122 tiling->pipe_count.width * tiling->pipe_count.height;
1123
1124 /* Clear vsc_scratch: */
1125 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1126 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1127 tu_cs_emit(cs, 0x0);
1128
1129 /* Check for overflow, write vsc_scratch if detected: */
1130 for (int i = 0; i < used_pipe_count; i++) {
1131 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1132 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1133 CP_COND_WRITE5_0_WRITE_MEMORY);
1134 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1135 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1136 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1137 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1138 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1139 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1140
1141 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1142 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1143 CP_COND_WRITE5_0_WRITE_MEMORY);
1144 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1145 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1146 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1147 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1148 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1149 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1150 }
1151
1152 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1153
1154 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1155
1156 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1157 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1158 CP_MEM_TO_REG_0_CNT(1 - 1));
1159 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1160
1161 /*
1162 * This is a bit awkward, we really want a way to invert the
1163 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1164 * execute cmds to use hwbinning when a bit is *not* set. This
1165 * dance is to invert OVERFLOW_FLAG_REG
1166 *
1167 * A CP_NOP packet is used to skip executing the 'else' clause
1168 * if (b0 set)..
1169 */
1170
1171 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1172 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1173 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1174 A6XX_CP_REG_TEST_0_BIT(0) |
1175 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1176
1177 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1178 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1179 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1180
1181 /* if (b0 set) */ {
1182 /*
1183 * On overflow, mirror the value to control->vsc_overflow
1184 * which CPU is checking to detect overflow (see
1185 * check_vsc_overflow())
1186 */
1187 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1188 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1189 CP_REG_TO_MEM_0_CNT(0));
1190 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1191
1192 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1193 tu_cs_emit(cs, 0x0);
1194
1195 tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
1196 } /* else */ {
1197 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1198 tu_cs_emit(cs, 0x1);
1199 }
1200 }
1201
1202 static void
1203 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1204 {
1205 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1206
1207 uint32_t x1 = tiling->tile0.offset.x;
1208 uint32_t y1 = tiling->tile0.offset.y;
1209 uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1210 uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1211
1212 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1213
1214 tu6_emit_marker(cmd, cs);
1215 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1216 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1217 tu6_emit_marker(cmd, cs);
1218
1219 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1220 tu_cs_emit(cs, 0x1);
1221
1222 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1223 tu_cs_emit(cs, 0x1);
1224
1225 tu_cs_emit_wfi(cs);
1226
1227 tu_cs_emit_regs(cs,
1228 A6XX_VFD_MODE_CNTL(.binning_pass = true));
1229
1230 update_vsc_pipe(cmd, cs);
1231
1232 tu_cs_emit_regs(cs,
1233 A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
1234
1235 tu_cs_emit_regs(cs,
1236 A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
1237
1238 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1239 tu_cs_emit(cs, UNK_2C);
1240
1241 tu_cs_emit_regs(cs,
1242 A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1243
1244 tu_cs_emit_regs(cs,
1245 A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1246
1247 /* emit IB to binning drawcmds: */
1248 tu_cs_emit_call(cs, &cmd->draw_cs);
1249
1250 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1251 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1252 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1253 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1254 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1255 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1256
1257 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1258 tu_cs_emit(cs, UNK_2D);
1259
1260 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1261 tu6_cache_flush(cmd, cs);
1262
1263 tu_cs_emit_wfi(cs);
1264
1265 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1266
1267 emit_vsc_overflow_test(cmd, cs);
1268
1269 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1270 tu_cs_emit(cs, 0x0);
1271
1272 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1273 tu_cs_emit(cs, 0x0);
1274
1275 tu_cs_emit_wfi(cs);
1276
1277 tu_cs_emit_regs(cs,
1278 A6XX_RB_CCU_CNTL(.unknown = 0x7c400004));
1279
1280 cmd->wait_for_idle = false;
1281 }
1282
1283 static void
1284 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1285 {
1286 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1287 if (result != VK_SUCCESS) {
1288 cmd->record_result = result;
1289 return;
1290 }
1291
1292 tu6_emit_lrz_flush(cmd, cs);
1293
1294 /* lrz clear? */
1295
1296 tu6_emit_cache_flush(cmd, cs);
1297
1298 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1299 tu_cs_emit(cs, 0x0);
1300
1301 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1302 tu6_emit_wfi(cmd, cs);
1303 tu_cs_emit_regs(cs,
1304 A6XX_RB_CCU_CNTL(0x7c400004));
1305
1306 if (use_hw_binning(cmd)) {
1307 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1308
1309 tu6_emit_render_cntl(cmd, cs, true);
1310
1311 tu6_emit_binning_pass(cmd, cs);
1312
1313 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1314
1315 tu_cs_emit_regs(cs,
1316 A6XX_VFD_MODE_CNTL(0));
1317
1318 tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
1319
1320 tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
1321
1322 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1323 tu_cs_emit(cs, 0x1);
1324 } else {
1325 tu6_emit_bin_size(cmd, cs, 0x6000000);
1326 }
1327
1328 tu6_emit_render_cntl(cmd, cs, false);
1329
1330 tu_cs_sanity_check(cs);
1331 }
1332
1333 static void
1334 tu6_render_tile(struct tu_cmd_buffer *cmd,
1335 struct tu_cs *cs,
1336 const struct tu_tile *tile)
1337 {
1338 const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1339 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1340 if (result != VK_SUCCESS) {
1341 cmd->record_result = result;
1342 return;
1343 }
1344
1345 tu6_emit_tile_select(cmd, cs, tile);
1346 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1347
1348 tu_cs_emit_call(cs, &cmd->draw_cs);
1349 cmd->wait_for_idle = true;
1350
1351 if (use_hw_binning(cmd)) {
1352 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1353 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1354 A6XX_CP_REG_TEST_0_BIT(0) |
1355 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1356
1357 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1358 tu_cs_emit(cs, 0x10000000);
1359 tu_cs_emit(cs, 2); /* conditionally execute next 2 dwords */
1360
1361 /* if (no overflow) */ {
1362 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1363 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1364 }
1365 }
1366
1367 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1368
1369 tu_cs_sanity_check(cs);
1370 }
1371
1372 static void
1373 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1374 {
1375 const uint32_t space = 16 + tu_cs_get_call_size(&cmd->draw_epilogue_cs);
1376 VkResult result = tu_cs_reserve_space(cmd->device, cs, space);
1377 if (result != VK_SUCCESS) {
1378 cmd->record_result = result;
1379 return;
1380 }
1381
1382 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1383
1384 tu_cs_emit_regs(cs,
1385 A6XX_GRAS_LRZ_CNTL(0));
1386
1387 tu6_emit_lrz_flush(cmd, cs);
1388
1389 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1390
1391 tu_cs_sanity_check(cs);
1392 }
1393
1394 static void
1395 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1396 {
1397 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1398
1399 tu6_render_begin(cmd, &cmd->cs);
1400
1401 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1402 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1403 struct tu_tile tile;
1404 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1405 tu6_render_tile(cmd, &cmd->cs, &tile);
1406 }
1407 }
1408
1409 tu6_render_end(cmd, &cmd->cs);
1410 }
1411
1412 static void
1413 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1414 const VkRenderPassBeginInfo *info)
1415 {
1416 const uint32_t tile_load_space =
1417 8 + (23+19) * cmd->state.pass->attachment_count +
1418 21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1419
1420 struct tu_cs sub_cs;
1421
1422 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1423 tile_load_space, &sub_cs);
1424 if (result != VK_SUCCESS) {
1425 cmd->record_result = result;
1426 return;
1427 }
1428
1429 tu6_emit_blit_scissor(cmd, &sub_cs, true);
1430
1431 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1432 tu6_emit_load_attachment(cmd, &sub_cs, i);
1433
1434 tu6_emit_blit_scissor(cmd, &sub_cs, false);
1435
1436 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1437 tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1438
1439 /* invalidate because reading input attachments will cache GMEM and
1440 * the cache isn''t updated when GMEM is written
1441 * TODO: is there a no-cache bit for textures?
1442 */
1443 if (cmd->state.subpass->input_count)
1444 tu6_emit_event_write(cmd, &sub_cs, CACHE_INVALIDATE, false);
1445
1446 tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1447 tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1448 tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1449
1450 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1451 }
1452
1453 static void
1454 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1455 {
1456 const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1457 struct tu_cs sub_cs;
1458
1459 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1460 tile_store_space, &sub_cs);
1461 if (result != VK_SUCCESS) {
1462 cmd->record_result = result;
1463 return;
1464 }
1465
1466 /* emit to tile-store sub_cs */
1467 tu6_emit_tile_store(cmd, &sub_cs);
1468
1469 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1470 }
1471
1472 static void
1473 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1474 const VkRect2D *render_area)
1475 {
1476 const struct tu_device *dev = cmd->device;
1477 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1478
1479 tiling->render_area = *render_area;
1480
1481 tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1482 tu_tiling_config_update_pipe_layout(tiling, dev);
1483 tu_tiling_config_update_pipes(tiling, dev);
1484 }
1485
1486 const struct tu_dynamic_state default_dynamic_state = {
1487 .viewport =
1488 {
1489 .count = 0,
1490 },
1491 .scissor =
1492 {
1493 .count = 0,
1494 },
1495 .line_width = 1.0f,
1496 .depth_bias =
1497 {
1498 .bias = 0.0f,
1499 .clamp = 0.0f,
1500 .slope = 0.0f,
1501 },
1502 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1503 .depth_bounds =
1504 {
1505 .min = 0.0f,
1506 .max = 1.0f,
1507 },
1508 .stencil_compare_mask =
1509 {
1510 .front = ~0u,
1511 .back = ~0u,
1512 },
1513 .stencil_write_mask =
1514 {
1515 .front = ~0u,
1516 .back = ~0u,
1517 },
1518 .stencil_reference =
1519 {
1520 .front = 0u,
1521 .back = 0u,
1522 },
1523 };
1524
1525 static void UNUSED /* FINISHME */
1526 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1527 const struct tu_dynamic_state *src)
1528 {
1529 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1530 uint32_t copy_mask = src->mask;
1531 uint32_t dest_mask = 0;
1532
1533 tu_use_args(cmd_buffer); /* FINISHME */
1534
1535 /* Make sure to copy the number of viewports/scissors because they can
1536 * only be specified at pipeline creation time.
1537 */
1538 dest->viewport.count = src->viewport.count;
1539 dest->scissor.count = src->scissor.count;
1540 dest->discard_rectangle.count = src->discard_rectangle.count;
1541
1542 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1543 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1544 src->viewport.count * sizeof(VkViewport))) {
1545 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1546 src->viewport.count);
1547 dest_mask |= TU_DYNAMIC_VIEWPORT;
1548 }
1549 }
1550
1551 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1552 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1553 src->scissor.count * sizeof(VkRect2D))) {
1554 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1555 src->scissor.count);
1556 dest_mask |= TU_DYNAMIC_SCISSOR;
1557 }
1558 }
1559
1560 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1561 if (dest->line_width != src->line_width) {
1562 dest->line_width = src->line_width;
1563 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1564 }
1565 }
1566
1567 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1568 if (memcmp(&dest->depth_bias, &src->depth_bias,
1569 sizeof(src->depth_bias))) {
1570 dest->depth_bias = src->depth_bias;
1571 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1572 }
1573 }
1574
1575 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1576 if (memcmp(&dest->blend_constants, &src->blend_constants,
1577 sizeof(src->blend_constants))) {
1578 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1579 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1580 }
1581 }
1582
1583 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1584 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1585 sizeof(src->depth_bounds))) {
1586 dest->depth_bounds = src->depth_bounds;
1587 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1588 }
1589 }
1590
1591 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1592 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1593 sizeof(src->stencil_compare_mask))) {
1594 dest->stencil_compare_mask = src->stencil_compare_mask;
1595 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1596 }
1597 }
1598
1599 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1600 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1601 sizeof(src->stencil_write_mask))) {
1602 dest->stencil_write_mask = src->stencil_write_mask;
1603 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1604 }
1605 }
1606
1607 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1608 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1609 sizeof(src->stencil_reference))) {
1610 dest->stencil_reference = src->stencil_reference;
1611 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1612 }
1613 }
1614
1615 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1616 if (memcmp(&dest->discard_rectangle.rectangles,
1617 &src->discard_rectangle.rectangles,
1618 src->discard_rectangle.count * sizeof(VkRect2D))) {
1619 typed_memcpy(dest->discard_rectangle.rectangles,
1620 src->discard_rectangle.rectangles,
1621 src->discard_rectangle.count);
1622 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1623 }
1624 }
1625 }
1626
1627 static VkResult
1628 tu_create_cmd_buffer(struct tu_device *device,
1629 struct tu_cmd_pool *pool,
1630 VkCommandBufferLevel level,
1631 VkCommandBuffer *pCommandBuffer)
1632 {
1633 struct tu_cmd_buffer *cmd_buffer;
1634 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1635 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1636 if (cmd_buffer == NULL)
1637 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1638
1639 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1640 cmd_buffer->device = device;
1641 cmd_buffer->pool = pool;
1642 cmd_buffer->level = level;
1643
1644 if (pool) {
1645 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1646 cmd_buffer->queue_family_index = pool->queue_family_index;
1647
1648 } else {
1649 /* Init the pool_link so we can safely call list_del when we destroy
1650 * the command buffer
1651 */
1652 list_inithead(&cmd_buffer->pool_link);
1653 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1654 }
1655
1656 tu_bo_list_init(&cmd_buffer->bo_list);
1657 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1658 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1659 tu_cs_init(&cmd_buffer->draw_epilogue_cs, TU_CS_MODE_GROW, 4096);
1660 tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1661
1662 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1663
1664 list_inithead(&cmd_buffer->upload.list);
1665
1666 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1667 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1668
1669 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1670 if (result != VK_SUCCESS)
1671 goto fail_scratch_bo;
1672
1673 /* TODO: resize on overflow */
1674 cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1675 cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1676 cmd_buffer->vsc_data = device->vsc_data;
1677 cmd_buffer->vsc_data2 = device->vsc_data2;
1678
1679 return VK_SUCCESS;
1680
1681 fail_scratch_bo:
1682 list_del(&cmd_buffer->pool_link);
1683 return result;
1684 }
1685
1686 static void
1687 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1688 {
1689 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1690
1691 list_del(&cmd_buffer->pool_link);
1692
1693 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1694 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1695
1696 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1697 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1698 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_epilogue_cs);
1699 tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1700
1701 tu_bo_list_destroy(&cmd_buffer->bo_list);
1702 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1703 }
1704
1705 static VkResult
1706 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1707 {
1708 cmd_buffer->wait_for_idle = true;
1709
1710 cmd_buffer->record_result = VK_SUCCESS;
1711
1712 tu_bo_list_reset(&cmd_buffer->bo_list);
1713 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1714 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1715 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_epilogue_cs);
1716 tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1717
1718 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1719 cmd_buffer->descriptors[i].valid = 0;
1720 cmd_buffer->descriptors[i].push_dirty = false;
1721 }
1722
1723 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1724
1725 return cmd_buffer->record_result;
1726 }
1727
1728 VkResult
1729 tu_AllocateCommandBuffers(VkDevice _device,
1730 const VkCommandBufferAllocateInfo *pAllocateInfo,
1731 VkCommandBuffer *pCommandBuffers)
1732 {
1733 TU_FROM_HANDLE(tu_device, device, _device);
1734 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1735
1736 VkResult result = VK_SUCCESS;
1737 uint32_t i;
1738
1739 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1740
1741 if (!list_is_empty(&pool->free_cmd_buffers)) {
1742 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1743 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1744
1745 list_del(&cmd_buffer->pool_link);
1746 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1747
1748 result = tu_reset_cmd_buffer(cmd_buffer);
1749 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1750 cmd_buffer->level = pAllocateInfo->level;
1751
1752 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1753 } else {
1754 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1755 &pCommandBuffers[i]);
1756 }
1757 if (result != VK_SUCCESS)
1758 break;
1759 }
1760
1761 if (result != VK_SUCCESS) {
1762 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1763 pCommandBuffers);
1764
1765 /* From the Vulkan 1.0.66 spec:
1766 *
1767 * "vkAllocateCommandBuffers can be used to create multiple
1768 * command buffers. If the creation of any of those command
1769 * buffers fails, the implementation must destroy all
1770 * successfully created command buffer objects from this
1771 * command, set all entries of the pCommandBuffers array to
1772 * NULL and return the error."
1773 */
1774 memset(pCommandBuffers, 0,
1775 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1776 }
1777
1778 return result;
1779 }
1780
1781 void
1782 tu_FreeCommandBuffers(VkDevice device,
1783 VkCommandPool commandPool,
1784 uint32_t commandBufferCount,
1785 const VkCommandBuffer *pCommandBuffers)
1786 {
1787 for (uint32_t i = 0; i < commandBufferCount; i++) {
1788 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1789
1790 if (cmd_buffer) {
1791 if (cmd_buffer->pool) {
1792 list_del(&cmd_buffer->pool_link);
1793 list_addtail(&cmd_buffer->pool_link,
1794 &cmd_buffer->pool->free_cmd_buffers);
1795 } else
1796 tu_cmd_buffer_destroy(cmd_buffer);
1797 }
1798 }
1799 }
1800
1801 VkResult
1802 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1803 VkCommandBufferResetFlags flags)
1804 {
1805 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1806 return tu_reset_cmd_buffer(cmd_buffer);
1807 }
1808
1809 VkResult
1810 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1811 const VkCommandBufferBeginInfo *pBeginInfo)
1812 {
1813 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1814 VkResult result = VK_SUCCESS;
1815
1816 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1817 /* If the command buffer has already been resetted with
1818 * vkResetCommandBuffer, no need to do it again.
1819 */
1820 result = tu_reset_cmd_buffer(cmd_buffer);
1821 if (result != VK_SUCCESS)
1822 return result;
1823 }
1824
1825 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1826 cmd_buffer->usage_flags = pBeginInfo->flags;
1827
1828 tu_cs_begin(&cmd_buffer->cs);
1829 tu_cs_begin(&cmd_buffer->draw_cs);
1830 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
1831
1832 cmd_buffer->marker_seqno = 0;
1833 cmd_buffer->scratch_seqno = 0;
1834
1835 /* setup initial configuration into command buffer */
1836 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1837 switch (cmd_buffer->queue_family_index) {
1838 case TU_QUEUE_GENERAL:
1839 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1840 break;
1841 default:
1842 break;
1843 }
1844 } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1845 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1846 assert(pBeginInfo->pInheritanceInfo);
1847 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1848 cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1849 }
1850
1851 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1852
1853 return VK_SUCCESS;
1854 }
1855
1856 void
1857 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1858 uint32_t firstBinding,
1859 uint32_t bindingCount,
1860 const VkBuffer *pBuffers,
1861 const VkDeviceSize *pOffsets)
1862 {
1863 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1864
1865 assert(firstBinding + bindingCount <= MAX_VBS);
1866
1867 for (uint32_t i = 0; i < bindingCount; i++) {
1868 cmd->state.vb.buffers[firstBinding + i] =
1869 tu_buffer_from_handle(pBuffers[i]);
1870 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1871 }
1872
1873 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1874 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1875 }
1876
1877 void
1878 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1879 VkBuffer buffer,
1880 VkDeviceSize offset,
1881 VkIndexType indexType)
1882 {
1883 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1884 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1885
1886 /* initialize/update the restart index */
1887 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1888 struct tu_cs *draw_cs = &cmd->draw_cs;
1889 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1890 if (result != VK_SUCCESS) {
1891 cmd->record_result = result;
1892 return;
1893 }
1894
1895 tu6_emit_restart_index(
1896 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1897
1898 tu_cs_sanity_check(draw_cs);
1899 }
1900
1901 /* track the BO */
1902 if (cmd->state.index_buffer != buf)
1903 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1904
1905 cmd->state.index_buffer = buf;
1906 cmd->state.index_offset = offset;
1907 cmd->state.index_type = indexType;
1908 }
1909
1910 void
1911 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1912 VkPipelineBindPoint pipelineBindPoint,
1913 VkPipelineLayout _layout,
1914 uint32_t firstSet,
1915 uint32_t descriptorSetCount,
1916 const VkDescriptorSet *pDescriptorSets,
1917 uint32_t dynamicOffsetCount,
1918 const uint32_t *pDynamicOffsets)
1919 {
1920 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1921 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1922 unsigned dyn_idx = 0;
1923
1924 struct tu_descriptor_state *descriptors_state =
1925 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1926
1927 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1928 unsigned idx = i + firstSet;
1929 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1930
1931 descriptors_state->sets[idx] = set;
1932 descriptors_state->valid |= (1u << idx);
1933
1934 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1935 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1936 assert(dyn_idx < dynamicOffsetCount);
1937
1938 descriptors_state->dynamic_buffers[idx] =
1939 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1940 }
1941 }
1942
1943 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1944 }
1945
1946 void
1947 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1948 VkPipelineLayout layout,
1949 VkShaderStageFlags stageFlags,
1950 uint32_t offset,
1951 uint32_t size,
1952 const void *pValues)
1953 {
1954 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1955 memcpy((void*) cmd->push_constants + offset, pValues, size);
1956 cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1957 }
1958
1959 VkResult
1960 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1961 {
1962 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1963
1964 if (cmd_buffer->scratch_seqno) {
1965 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1966 MSM_SUBMIT_BO_WRITE);
1967 }
1968
1969 if (cmd_buffer->use_vsc_data) {
1970 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
1971 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1972 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
1973 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1974 }
1975
1976 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1977 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1978 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1979 }
1980
1981 for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
1982 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
1983 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1984 }
1985
1986 for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
1987 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
1988 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1989 }
1990
1991 tu_cs_end(&cmd_buffer->cs);
1992 tu_cs_end(&cmd_buffer->draw_cs);
1993 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
1994
1995 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1996
1997 return cmd_buffer->record_result;
1998 }
1999
2000 void
2001 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2002 VkPipelineBindPoint pipelineBindPoint,
2003 VkPipeline _pipeline)
2004 {
2005 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2006 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2007
2008 switch (pipelineBindPoint) {
2009 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2010 cmd->state.pipeline = pipeline;
2011 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2012 break;
2013 case VK_PIPELINE_BIND_POINT_COMPUTE:
2014 cmd->state.compute_pipeline = pipeline;
2015 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2016 break;
2017 default:
2018 unreachable("unrecognized pipeline bind point");
2019 break;
2020 }
2021
2022 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2023 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2024 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2025 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2026 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2027 }
2028 }
2029
2030 void
2031 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2032 uint32_t firstViewport,
2033 uint32_t viewportCount,
2034 const VkViewport *pViewports)
2035 {
2036 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2037 struct tu_cs *draw_cs = &cmd->draw_cs;
2038
2039 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2040 if (result != VK_SUCCESS) {
2041 cmd->record_result = result;
2042 return;
2043 }
2044
2045 assert(firstViewport == 0 && viewportCount == 1);
2046 tu6_emit_viewport(draw_cs, pViewports);
2047
2048 tu_cs_sanity_check(draw_cs);
2049 }
2050
2051 void
2052 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2053 uint32_t firstScissor,
2054 uint32_t scissorCount,
2055 const VkRect2D *pScissors)
2056 {
2057 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2058 struct tu_cs *draw_cs = &cmd->draw_cs;
2059
2060 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2061 if (result != VK_SUCCESS) {
2062 cmd->record_result = result;
2063 return;
2064 }
2065
2066 assert(firstScissor == 0 && scissorCount == 1);
2067 tu6_emit_scissor(draw_cs, pScissors);
2068
2069 tu_cs_sanity_check(draw_cs);
2070 }
2071
2072 void
2073 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2074 {
2075 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2076
2077 cmd->state.dynamic.line_width = lineWidth;
2078
2079 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2080 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2081 }
2082
2083 void
2084 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2085 float depthBiasConstantFactor,
2086 float depthBiasClamp,
2087 float depthBiasSlopeFactor)
2088 {
2089 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2090 struct tu_cs *draw_cs = &cmd->draw_cs;
2091
2092 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2093 if (result != VK_SUCCESS) {
2094 cmd->record_result = result;
2095 return;
2096 }
2097
2098 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2099 depthBiasSlopeFactor);
2100
2101 tu_cs_sanity_check(draw_cs);
2102 }
2103
2104 void
2105 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2106 const float blendConstants[4])
2107 {
2108 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2109 struct tu_cs *draw_cs = &cmd->draw_cs;
2110
2111 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2112 if (result != VK_SUCCESS) {
2113 cmd->record_result = result;
2114 return;
2115 }
2116
2117 tu6_emit_blend_constants(draw_cs, blendConstants);
2118
2119 tu_cs_sanity_check(draw_cs);
2120 }
2121
2122 void
2123 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2124 float minDepthBounds,
2125 float maxDepthBounds)
2126 {
2127 }
2128
2129 void
2130 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2131 VkStencilFaceFlags faceMask,
2132 uint32_t compareMask)
2133 {
2134 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2135
2136 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2137 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2138 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2139 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2140
2141 /* the front/back compare masks must be updated together */
2142 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2143 }
2144
2145 void
2146 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2147 VkStencilFaceFlags faceMask,
2148 uint32_t writeMask)
2149 {
2150 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2151
2152 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2153 cmd->state.dynamic.stencil_write_mask.front = writeMask;
2154 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2155 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2156
2157 /* the front/back write masks must be updated together */
2158 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2159 }
2160
2161 void
2162 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2163 VkStencilFaceFlags faceMask,
2164 uint32_t reference)
2165 {
2166 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2167
2168 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2169 cmd->state.dynamic.stencil_reference.front = reference;
2170 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2171 cmd->state.dynamic.stencil_reference.back = reference;
2172
2173 /* the front/back references must be updated together */
2174 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2175 }
2176
2177 void
2178 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2179 uint32_t commandBufferCount,
2180 const VkCommandBuffer *pCmdBuffers)
2181 {
2182 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2183 VkResult result;
2184
2185 assert(commandBufferCount > 0);
2186
2187 for (uint32_t i = 0; i < commandBufferCount; i++) {
2188 TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2189
2190 result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2191 if (result != VK_SUCCESS) {
2192 cmd->record_result = result;
2193 break;
2194 }
2195
2196 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2197 if (result != VK_SUCCESS) {
2198 cmd->record_result = result;
2199 break;
2200 }
2201
2202 result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2203 &secondary->draw_epilogue_cs);
2204 if (result != VK_SUCCESS) {
2205 cmd->record_result = result;
2206 break;
2207 }
2208 }
2209 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2210 }
2211
2212 VkResult
2213 tu_CreateCommandPool(VkDevice _device,
2214 const VkCommandPoolCreateInfo *pCreateInfo,
2215 const VkAllocationCallbacks *pAllocator,
2216 VkCommandPool *pCmdPool)
2217 {
2218 TU_FROM_HANDLE(tu_device, device, _device);
2219 struct tu_cmd_pool *pool;
2220
2221 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2223 if (pool == NULL)
2224 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2225
2226 if (pAllocator)
2227 pool->alloc = *pAllocator;
2228 else
2229 pool->alloc = device->alloc;
2230
2231 list_inithead(&pool->cmd_buffers);
2232 list_inithead(&pool->free_cmd_buffers);
2233
2234 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2235
2236 *pCmdPool = tu_cmd_pool_to_handle(pool);
2237
2238 return VK_SUCCESS;
2239 }
2240
2241 void
2242 tu_DestroyCommandPool(VkDevice _device,
2243 VkCommandPool commandPool,
2244 const VkAllocationCallbacks *pAllocator)
2245 {
2246 TU_FROM_HANDLE(tu_device, device, _device);
2247 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2248
2249 if (!pool)
2250 return;
2251
2252 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2253 &pool->cmd_buffers, pool_link)
2254 {
2255 tu_cmd_buffer_destroy(cmd_buffer);
2256 }
2257
2258 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2259 &pool->free_cmd_buffers, pool_link)
2260 {
2261 tu_cmd_buffer_destroy(cmd_buffer);
2262 }
2263
2264 vk_free2(&device->alloc, pAllocator, pool);
2265 }
2266
2267 VkResult
2268 tu_ResetCommandPool(VkDevice device,
2269 VkCommandPool commandPool,
2270 VkCommandPoolResetFlags flags)
2271 {
2272 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2273 VkResult result;
2274
2275 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2276 pool_link)
2277 {
2278 result = tu_reset_cmd_buffer(cmd_buffer);
2279 if (result != VK_SUCCESS)
2280 return result;
2281 }
2282
2283 return VK_SUCCESS;
2284 }
2285
2286 void
2287 tu_TrimCommandPool(VkDevice device,
2288 VkCommandPool commandPool,
2289 VkCommandPoolTrimFlags flags)
2290 {
2291 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2292
2293 if (!pool)
2294 return;
2295
2296 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2297 &pool->free_cmd_buffers, pool_link)
2298 {
2299 tu_cmd_buffer_destroy(cmd_buffer);
2300 }
2301 }
2302
2303 void
2304 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2305 const VkRenderPassBeginInfo *pRenderPassBegin,
2306 VkSubpassContents contents)
2307 {
2308 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2309 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2310 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2311
2312 cmd->state.pass = pass;
2313 cmd->state.subpass = pass->subpasses;
2314 cmd->state.framebuffer = fb;
2315
2316 tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2317 tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2318 tu_cmd_prepare_tile_store_ib(cmd);
2319
2320 /* note: use_hw_binning only checks tiling config */
2321 if (use_hw_binning(cmd))
2322 cmd->use_vsc_data = true;
2323
2324 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2325 const struct tu_image_view *iview = fb->attachments[i].attachment;
2326 tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2327 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2328 }
2329 }
2330
2331 void
2332 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2333 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2334 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2335 {
2336 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2337 pSubpassBeginInfo->contents);
2338 }
2339
2340 void
2341 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2342 {
2343 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2344 const struct tu_render_pass *pass = cmd->state.pass;
2345 struct tu_cs *cs = &cmd->draw_cs;
2346
2347 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2348 if (result != VK_SUCCESS) {
2349 cmd->record_result = result;
2350 return;
2351 }
2352
2353 const struct tu_subpass *subpass = cmd->state.subpass++;
2354 /* TODO:
2355 * if msaa samples change between subpasses,
2356 * attachment store is broken for some attachments
2357 */
2358 if (subpass->resolve_attachments) {
2359 tu6_emit_blit_scissor(cmd, cs, true);
2360 for (unsigned i = 0; i < subpass->color_count; i++) {
2361 uint32_t a = subpass->resolve_attachments[i].attachment;
2362 if (a != VK_ATTACHMENT_UNUSED) {
2363 tu6_emit_store_attachment(cmd, cs, a,
2364 subpass->color_attachments[i].attachment);
2365 }
2366 }
2367 }
2368
2369 /* invalidate because reading input attachments will cache GMEM and
2370 * the cache isn''t updated when GMEM is written
2371 * TODO: is there a no-cache bit for textures?
2372 */
2373 if (cmd->state.subpass->input_count)
2374 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2375
2376 /* emit mrt/zs/msaa state for the subpass that is starting */
2377 tu6_emit_zs(cmd, cmd->state.subpass, cs);
2378 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2379 tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2380
2381 /* TODO:
2382 * since we don't know how to do GMEM->GMEM resolve,
2383 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2384 */
2385 if (subpass->resolve_attachments) {
2386 for (unsigned i = 0; i < subpass->color_count; i++) {
2387 uint32_t a = subpass->resolve_attachments[i].attachment;
2388 const struct tu_image_view *iview =
2389 cmd->state.framebuffer->attachments[a].attachment;
2390 if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2391 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2392 tu6_emit_blit_info(cmd, cs, iview, pass->attachments[a].gmem_offset, false);
2393 tu6_emit_blit(cmd, cs);
2394 }
2395 }
2396 }
2397 }
2398
2399 void
2400 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2401 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2402 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2403 {
2404 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2405 }
2406
2407 struct tu_draw_info
2408 {
2409 /**
2410 * Number of vertices.
2411 */
2412 uint32_t count;
2413
2414 /**
2415 * Index of the first vertex.
2416 */
2417 int32_t vertex_offset;
2418
2419 /**
2420 * First instance id.
2421 */
2422 uint32_t first_instance;
2423
2424 /**
2425 * Number of instances.
2426 */
2427 uint32_t instance_count;
2428
2429 /**
2430 * First index (indexed draws only).
2431 */
2432 uint32_t first_index;
2433
2434 /**
2435 * Whether it's an indexed draw.
2436 */
2437 bool indexed;
2438
2439 /**
2440 * Indirect draw parameters resource.
2441 */
2442 struct tu_buffer *indirect;
2443 uint64_t indirect_offset;
2444 uint32_t stride;
2445
2446 /**
2447 * Draw count parameters resource.
2448 */
2449 struct tu_buffer *count_buffer;
2450 uint64_t count_buffer_offset;
2451 };
2452
2453 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2454 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2455
2456 enum tu_draw_state_group_id
2457 {
2458 TU_DRAW_STATE_PROGRAM,
2459 TU_DRAW_STATE_PROGRAM_BINNING,
2460 TU_DRAW_STATE_VI,
2461 TU_DRAW_STATE_VI_BINNING,
2462 TU_DRAW_STATE_VP,
2463 TU_DRAW_STATE_RAST,
2464 TU_DRAW_STATE_DS,
2465 TU_DRAW_STATE_BLEND,
2466 TU_DRAW_STATE_VS_CONST,
2467 TU_DRAW_STATE_FS_CONST,
2468 TU_DRAW_STATE_VS_TEX,
2469 TU_DRAW_STATE_FS_TEX,
2470 TU_DRAW_STATE_FS_IBO,
2471 TU_DRAW_STATE_VS_PARAMS,
2472
2473 TU_DRAW_STATE_COUNT,
2474 };
2475
2476 struct tu_draw_state_group
2477 {
2478 enum tu_draw_state_group_id id;
2479 uint32_t enable_mask;
2480 struct tu_cs_entry ib;
2481 };
2482
2483 const static struct tu_sampler*
2484 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2485 const struct tu_descriptor_map *map, unsigned i,
2486 unsigned array_index)
2487 {
2488 assert(descriptors_state->valid & (1 << map->set[i]));
2489
2490 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2491 assert(map->binding[i] < set->layout->binding_count);
2492
2493 const struct tu_descriptor_set_binding_layout *layout =
2494 &set->layout->binding[map->binding[i]];
2495
2496 if (layout->immutable_samplers_offset) {
2497 const struct tu_sampler *immutable_samplers =
2498 tu_immutable_samplers(set->layout, layout);
2499
2500 return &immutable_samplers[array_index];
2501 }
2502
2503 switch (layout->type) {
2504 case VK_DESCRIPTOR_TYPE_SAMPLER:
2505 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2506 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2507 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2508 array_index *
2509 (A6XX_TEX_CONST_DWORDS +
2510 sizeof(struct tu_sampler) / 4)];
2511 default:
2512 unreachable("unimplemented descriptor type");
2513 break;
2514 }
2515 }
2516
2517 static void
2518 write_tex_const(struct tu_cmd_buffer *cmd,
2519 uint32_t *dst,
2520 struct tu_descriptor_state *descriptors_state,
2521 const struct tu_descriptor_map *map,
2522 unsigned i, unsigned array_index)
2523 {
2524 assert(descriptors_state->valid & (1 << map->set[i]));
2525
2526 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2527 assert(map->binding[i] < set->layout->binding_count);
2528
2529 const struct tu_descriptor_set_binding_layout *layout =
2530 &set->layout->binding[map->binding[i]];
2531
2532 switch (layout->type) {
2533 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2534 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2535 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2536 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2537 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2538 array_index * A6XX_TEX_CONST_DWORDS],
2539 A6XX_TEX_CONST_DWORDS * 4);
2540 break;
2541 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2542 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2543 array_index *
2544 (A6XX_TEX_CONST_DWORDS +
2545 sizeof(struct tu_sampler) / 4)],
2546 A6XX_TEX_CONST_DWORDS * 4);
2547 break;
2548 default:
2549 unreachable("unimplemented descriptor type");
2550 break;
2551 }
2552
2553 if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2554 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2555 uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2556 array_index].attachment;
2557 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2558
2559 assert(att->gmem_offset >= 0);
2560
2561 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2562 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2563 dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2564 dst[2] |=
2565 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2566 A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2567 dst[3] = 0;
2568 dst[4] = 0x100000 + att->gmem_offset;
2569 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2570 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2571 dst[i] = 0;
2572
2573 if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2574 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2575 }
2576 }
2577
2578 static void
2579 write_image_ibo(struct tu_cmd_buffer *cmd,
2580 uint32_t *dst,
2581 struct tu_descriptor_state *descriptors_state,
2582 const struct tu_descriptor_map *map,
2583 unsigned i, unsigned array_index)
2584 {
2585 assert(descriptors_state->valid & (1 << map->set[i]));
2586
2587 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2588 assert(map->binding[i] < set->layout->binding_count);
2589
2590 const struct tu_descriptor_set_binding_layout *layout =
2591 &set->layout->binding[map->binding[i]];
2592
2593 assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2594
2595 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2596 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2597 A6XX_TEX_CONST_DWORDS * 4);
2598 }
2599
2600 static uint64_t
2601 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2602 const struct tu_descriptor_map *map,
2603 unsigned i, unsigned array_index)
2604 {
2605 assert(descriptors_state->valid & (1 << map->set[i]));
2606
2607 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2608 assert(map->binding[i] < set->layout->binding_count);
2609
2610 const struct tu_descriptor_set_binding_layout *layout =
2611 &set->layout->binding[map->binding[i]];
2612
2613 switch (layout->type) {
2614 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2615 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2616 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2617 array_index];
2618 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2619 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2620 return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2621 set->mapped_ptr[layout->offset / 4 + array_index * 2];
2622 default:
2623 unreachable("unimplemented descriptor type");
2624 break;
2625 }
2626 }
2627
2628 static inline uint32_t
2629 tu6_stage2opcode(gl_shader_stage type)
2630 {
2631 switch (type) {
2632 case MESA_SHADER_VERTEX:
2633 case MESA_SHADER_TESS_CTRL:
2634 case MESA_SHADER_TESS_EVAL:
2635 case MESA_SHADER_GEOMETRY:
2636 return CP_LOAD_STATE6_GEOM;
2637 case MESA_SHADER_FRAGMENT:
2638 case MESA_SHADER_COMPUTE:
2639 case MESA_SHADER_KERNEL:
2640 return CP_LOAD_STATE6_FRAG;
2641 default:
2642 unreachable("bad shader type");
2643 }
2644 }
2645
2646 static inline enum a6xx_state_block
2647 tu6_stage2shadersb(gl_shader_stage type)
2648 {
2649 switch (type) {
2650 case MESA_SHADER_VERTEX:
2651 return SB6_VS_SHADER;
2652 case MESA_SHADER_FRAGMENT:
2653 return SB6_FS_SHADER;
2654 case MESA_SHADER_COMPUTE:
2655 case MESA_SHADER_KERNEL:
2656 return SB6_CS_SHADER;
2657 default:
2658 unreachable("bad shader type");
2659 return ~0;
2660 }
2661 }
2662
2663 static void
2664 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2665 struct tu_descriptor_state *descriptors_state,
2666 gl_shader_stage type,
2667 uint32_t *push_constants)
2668 {
2669 const struct tu_program_descriptor_linkage *link =
2670 &pipeline->program.link[type];
2671 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2672
2673 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2674 if (state->range[i].start < state->range[i].end) {
2675 uint32_t size = state->range[i].end - state->range[i].start;
2676 uint32_t offset = state->range[i].start;
2677
2678 /* and even if the start of the const buffer is before
2679 * first_immediate, the end may not be:
2680 */
2681 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2682
2683 if (size == 0)
2684 continue;
2685
2686 /* things should be aligned to vec4: */
2687 debug_assert((state->range[i].offset % 16) == 0);
2688 debug_assert((size % 16) == 0);
2689 debug_assert((offset % 16) == 0);
2690
2691 if (i == 0) {
2692 /* push constants */
2693 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2694 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2695 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2696 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2697 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2698 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2699 tu_cs_emit(cs, 0);
2700 tu_cs_emit(cs, 0);
2701 for (unsigned i = 0; i < size / 4; i++)
2702 tu_cs_emit(cs, push_constants[i + offset / 4]);
2703 continue;
2704 }
2705
2706 /* Look through the UBO map to find our UBO index, and get the VA for
2707 * that UBO.
2708 */
2709 uint64_t va = 0;
2710 uint32_t ubo_idx = i - 1;
2711 uint32_t ubo_map_base = 0;
2712 for (int j = 0; j < link->ubo_map.num; j++) {
2713 if (ubo_idx >= ubo_map_base &&
2714 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2715 va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2716 ubo_idx - ubo_map_base);
2717 break;
2718 }
2719 ubo_map_base += link->ubo_map.array_size[j];
2720 }
2721 assert(va);
2722
2723 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2724 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2725 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2726 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2727 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2728 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2729 tu_cs_emit_qw(cs, va + offset);
2730 }
2731 }
2732 }
2733
2734 static void
2735 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2736 struct tu_descriptor_state *descriptors_state,
2737 gl_shader_stage type)
2738 {
2739 const struct tu_program_descriptor_linkage *link =
2740 &pipeline->program.link[type];
2741
2742 uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2743 uint32_t anum = align(num, 2);
2744
2745 if (!num)
2746 return;
2747
2748 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2749 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2750 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2751 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2752 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2753 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2754 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2755 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2756
2757 unsigned emitted = 0;
2758 for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2759 for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2760 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2761 emitted++;
2762 }
2763 }
2764
2765 for (; emitted < anum; emitted++) {
2766 tu_cs_emit(cs, 0xffffffff);
2767 tu_cs_emit(cs, 0xffffffff);
2768 }
2769 }
2770
2771 static struct tu_cs_entry
2772 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2773 const struct tu_pipeline *pipeline,
2774 struct tu_descriptor_state *descriptors_state,
2775 gl_shader_stage type)
2776 {
2777 struct tu_cs cs;
2778 tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2779
2780 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2781 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2782
2783 return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2784 }
2785
2786 static VkResult
2787 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2788 const struct tu_draw_info *draw,
2789 struct tu_cs_entry *entry)
2790 {
2791 /* TODO: fill out more than just base instance */
2792 const struct tu_program_descriptor_linkage *link =
2793 &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2794 const struct ir3_const_state *const_state = &link->const_state;
2795 struct tu_cs cs;
2796
2797 if (const_state->offsets.driver_param >= link->constlen) {
2798 *entry = (struct tu_cs_entry) {};
2799 return VK_SUCCESS;
2800 }
2801
2802 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 8, &cs);
2803 if (result != VK_SUCCESS)
2804 return result;
2805
2806 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2807 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2808 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2809 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2810 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2811 CP_LOAD_STATE6_0_NUM_UNIT(1));
2812 tu_cs_emit(&cs, 0);
2813 tu_cs_emit(&cs, 0);
2814
2815 STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2816
2817 tu_cs_emit(&cs, 0);
2818 tu_cs_emit(&cs, 0);
2819 tu_cs_emit(&cs, draw->first_instance);
2820 tu_cs_emit(&cs, 0);
2821
2822 *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2823 return VK_SUCCESS;
2824 }
2825
2826 static VkResult
2827 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2828 const struct tu_pipeline *pipeline,
2829 struct tu_descriptor_state *descriptors_state,
2830 gl_shader_stage type,
2831 struct tu_cs_entry *entry,
2832 bool *needs_border)
2833 {
2834 struct tu_device *device = cmd->device;
2835 struct tu_cs *draw_state = &cmd->sub_cs;
2836 const struct tu_program_descriptor_linkage *link =
2837 &pipeline->program.link[type];
2838 VkResult result;
2839
2840 if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
2841 *entry = (struct tu_cs_entry) {};
2842 return VK_SUCCESS;
2843 }
2844
2845 /* allocate and fill texture state */
2846 struct ts_cs_memory tex_const;
2847 result = tu_cs_alloc(device, draw_state, link->texture_map.num_desc,
2848 A6XX_TEX_CONST_DWORDS, &tex_const);
2849 if (result != VK_SUCCESS)
2850 return result;
2851
2852 int tex_index = 0;
2853 for (unsigned i = 0; i < link->texture_map.num; i++) {
2854 for (int j = 0; j < link->texture_map.array_size[i]; j++) {
2855 write_tex_const(cmd,
2856 &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
2857 descriptors_state, &link->texture_map, i, j);
2858 }
2859 }
2860
2861 /* allocate and fill sampler state */
2862 struct ts_cs_memory tex_samp = { 0 };
2863 if (link->sampler_map.num_desc) {
2864 result = tu_cs_alloc(device, draw_state, link->sampler_map.num_desc,
2865 A6XX_TEX_SAMP_DWORDS, &tex_samp);
2866 if (result != VK_SUCCESS)
2867 return result;
2868
2869 int sampler_index = 0;
2870 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2871 for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
2872 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
2873 &link->sampler_map,
2874 i, j);
2875 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
2876 sampler->state, sizeof(sampler->state));
2877 *needs_border |= sampler->needs_border;
2878 }
2879 }
2880 }
2881
2882 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2883 enum a6xx_state_block sb;
2884
2885 switch (type) {
2886 case MESA_SHADER_VERTEX:
2887 sb = SB6_VS_TEX;
2888 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2889 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2890 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2891 break;
2892 case MESA_SHADER_FRAGMENT:
2893 sb = SB6_FS_TEX;
2894 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2895 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2896 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2897 break;
2898 case MESA_SHADER_COMPUTE:
2899 sb = SB6_CS_TEX;
2900 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2901 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2902 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2903 break;
2904 default:
2905 unreachable("bad state block");
2906 }
2907
2908 struct tu_cs cs;
2909 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2910 if (result != VK_SUCCESS)
2911 return result;
2912
2913 if (link->sampler_map.num_desc) {
2914 /* output sampler state: */
2915 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2916 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2917 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2918 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2919 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2920 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
2921 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2922
2923 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2924 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2925 }
2926
2927 /* emit texture state: */
2928 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2929 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2930 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2931 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2932 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2933 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
2934 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2935
2936 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2937 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2938
2939 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2940 tu_cs_emit(&cs, link->texture_map.num_desc);
2941
2942 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2943 return VK_SUCCESS;
2944 }
2945
2946 static VkResult
2947 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
2948 const struct tu_pipeline *pipeline,
2949 struct tu_descriptor_state *descriptors_state,
2950 gl_shader_stage type,
2951 struct tu_cs_entry *entry)
2952 {
2953 struct tu_device *device = cmd->device;
2954 struct tu_cs *draw_state = &cmd->sub_cs;
2955 const struct tu_program_descriptor_linkage *link =
2956 &pipeline->program.link[type];
2957 VkResult result;
2958
2959 unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
2960
2961 if (num_desc == 0) {
2962 *entry = (struct tu_cs_entry) {};
2963 return VK_SUCCESS;
2964 }
2965
2966 struct ts_cs_memory ibo_const;
2967 result = tu_cs_alloc(device, draw_state, num_desc,
2968 A6XX_TEX_CONST_DWORDS, &ibo_const);
2969 if (result != VK_SUCCESS)
2970 return result;
2971
2972 int ssbo_index = 0;
2973 for (unsigned i = 0; i < link->ssbo_map.num; i++) {
2974 for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
2975 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
2976
2977 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
2978 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2979 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2980
2981 dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
2982 dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2983 A6XX_IBO_1_HEIGHT(sz >> 15);
2984 dst[2] = A6XX_IBO_2_UNK4 |
2985 A6XX_IBO_2_UNK31 |
2986 A6XX_IBO_2_TYPE(A6XX_TEX_1D);
2987 dst[3] = 0;
2988 dst[4] = va;
2989 dst[5] = va >> 32;
2990 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2991 dst[i] = 0;
2992
2993 ssbo_index++;
2994 }
2995 }
2996
2997 for (unsigned i = 0; i < link->image_map.num; i++) {
2998 for (int j = 0; j < link->image_map.array_size[i]; j++) {
2999 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3000
3001 write_image_ibo(cmd, dst,
3002 descriptors_state, &link->image_map, i, j);
3003
3004 ssbo_index++;
3005 }
3006 }
3007
3008 assert(ssbo_index == num_desc);
3009
3010 struct tu_cs cs;
3011 result = tu_cs_begin_sub_stream(device, draw_state, 7, &cs);
3012 if (result != VK_SUCCESS)
3013 return result;
3014
3015 uint32_t opcode, ibo_addr_reg;
3016 enum a6xx_state_block sb;
3017 enum a6xx_state_type st;
3018
3019 switch (type) {
3020 case MESA_SHADER_FRAGMENT:
3021 opcode = CP_LOAD_STATE6;
3022 st = ST6_SHADER;
3023 sb = SB6_IBO;
3024 ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3025 break;
3026 case MESA_SHADER_COMPUTE:
3027 opcode = CP_LOAD_STATE6_FRAG;
3028 st = ST6_IBO;
3029 sb = SB6_CS_SHADER;
3030 ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3031 break;
3032 default:
3033 unreachable("unsupported stage for ibos");
3034 }
3035
3036 /* emit texture state: */
3037 tu_cs_emit_pkt7(&cs, opcode, 3);
3038 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3039 CP_LOAD_STATE6_0_STATE_TYPE(st) |
3040 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3041 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3042 CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3043 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3044
3045 tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3046 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3047
3048 *entry = tu_cs_end_sub_stream(draw_state, &cs);
3049 return VK_SUCCESS;
3050 }
3051
3052 struct PACKED bcolor_entry {
3053 uint32_t fp32[4];
3054 uint16_t ui16[4];
3055 int16_t si16[4];
3056 uint16_t fp16[4];
3057 uint16_t rgb565;
3058 uint16_t rgb5a1;
3059 uint16_t rgba4;
3060 uint8_t __pad0[2];
3061 uint8_t ui8[4];
3062 int8_t si8[4];
3063 uint32_t rgb10a2;
3064 uint32_t z24; /* also s8? */
3065 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
3066 uint8_t __pad1[56];
3067 } border_color[] = {
3068 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3069 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3070 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3071 .fp32[3] = 0x3f800000,
3072 .ui16[3] = 0xffff,
3073 .si16[3] = 0x7fff,
3074 .fp16[3] = 0x3c00,
3075 .rgb5a1 = 0x8000,
3076 .rgba4 = 0xf000,
3077 .ui8[3] = 0xff,
3078 .si8[3] = 0x7f,
3079 .rgb10a2 = 0xc0000000,
3080 .srgb[3] = 0x3c00,
3081 },
3082 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3083 .fp32[3] = 1,
3084 .fp16[3] = 1,
3085 },
3086 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3087 .fp32[0 ... 3] = 0x3f800000,
3088 .ui16[0 ... 3] = 0xffff,
3089 .si16[0 ... 3] = 0x7fff,
3090 .fp16[0 ... 3] = 0x3c00,
3091 .rgb565 = 0xffff,
3092 .rgb5a1 = 0xffff,
3093 .rgba4 = 0xffff,
3094 .ui8[0 ... 3] = 0xff,
3095 .si8[0 ... 3] = 0x7f,
3096 .rgb10a2 = 0xffffffff,
3097 .z24 = 0xffffff,
3098 .srgb[0 ... 3] = 0x3c00,
3099 },
3100 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3101 .fp32[0 ... 3] = 1,
3102 .fp16[0 ... 3] = 1,
3103 },
3104 };
3105
3106 static VkResult
3107 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3108 struct tu_cs *cs)
3109 {
3110 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3111
3112 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3113 struct tu_descriptor_state *descriptors_state =
3114 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3115 const struct tu_descriptor_map *vs_sampler =
3116 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3117 const struct tu_descriptor_map *fs_sampler =
3118 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3119 struct ts_cs_memory ptr;
3120
3121 VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
3122 vs_sampler->num_desc + fs_sampler->num_desc,
3123 128 / 4,
3124 &ptr);
3125 if (result != VK_SUCCESS)
3126 return result;
3127
3128 for (unsigned i = 0; i < vs_sampler->num; i++) {
3129 for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3130 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3131 vs_sampler, i, j);
3132 memcpy(ptr.map, &border_color[sampler->border], 128);
3133 ptr.map += 128 / 4;
3134 }
3135 }
3136
3137 for (unsigned i = 0; i < fs_sampler->num; i++) {
3138 for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3139 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3140 fs_sampler, i, j);
3141 memcpy(ptr.map, &border_color[sampler->border], 128);
3142 ptr.map += 128 / 4;
3143 }
3144 }
3145
3146 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3147 tu_cs_emit_qw(cs, ptr.iova);
3148 return VK_SUCCESS;
3149 }
3150
3151 static VkResult
3152 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3153 struct tu_cs *cs,
3154 const struct tu_draw_info *draw)
3155 {
3156 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3157 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3158 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3159 uint32_t draw_state_group_count = 0;
3160
3161 struct tu_descriptor_state *descriptors_state =
3162 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3163
3164 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3165 if (result != VK_SUCCESS)
3166 return result;
3167
3168 /* TODO lrz */
3169
3170 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3171 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3172 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3173
3174 tu_cs_emit_regs(cs,
3175 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3176 pipeline->ia.primitive_restart && draw->indexed));
3177
3178 if (cmd->state.dirty &
3179 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3180 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3181 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3182 dynamic->line_width);
3183 }
3184
3185 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3186 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3187 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3188 dynamic->stencil_compare_mask.back);
3189 }
3190
3191 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3192 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3193 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3194 dynamic->stencil_write_mask.back);
3195 }
3196
3197 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3198 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3199 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3200 dynamic->stencil_reference.back);
3201 }
3202
3203 if (cmd->state.dirty &
3204 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3205 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3206 const uint32_t binding = pipeline->vi.bindings[i];
3207 const uint32_t stride = pipeline->vi.strides[i];
3208 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3209 const VkDeviceSize offset = buf->bo_offset +
3210 cmd->state.vb.offsets[binding] +
3211 pipeline->vi.offsets[i];
3212 const VkDeviceSize size =
3213 offset < buf->bo->size ? buf->bo->size - offset : 0;
3214
3215 tu_cs_emit_regs(cs,
3216 A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3217 A6XX_VFD_FETCH_SIZE(i, size),
3218 A6XX_VFD_FETCH_STRIDE(i, stride));
3219 }
3220 }
3221
3222 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3223 draw_state_groups[draw_state_group_count++] =
3224 (struct tu_draw_state_group) {
3225 .id = TU_DRAW_STATE_PROGRAM,
3226 .enable_mask = ENABLE_DRAW,
3227 .ib = pipeline->program.state_ib,
3228 };
3229 draw_state_groups[draw_state_group_count++] =
3230 (struct tu_draw_state_group) {
3231 .id = TU_DRAW_STATE_PROGRAM_BINNING,
3232 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3233 .ib = pipeline->program.binning_state_ib,
3234 };
3235 draw_state_groups[draw_state_group_count++] =
3236 (struct tu_draw_state_group) {
3237 .id = TU_DRAW_STATE_VI,
3238 .enable_mask = ENABLE_DRAW,
3239 .ib = pipeline->vi.state_ib,
3240 };
3241 draw_state_groups[draw_state_group_count++] =
3242 (struct tu_draw_state_group) {
3243 .id = TU_DRAW_STATE_VI_BINNING,
3244 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3245 .ib = pipeline->vi.binning_state_ib,
3246 };
3247 draw_state_groups[draw_state_group_count++] =
3248 (struct tu_draw_state_group) {
3249 .id = TU_DRAW_STATE_VP,
3250 .enable_mask = ENABLE_ALL,
3251 .ib = pipeline->vp.state_ib,
3252 };
3253 draw_state_groups[draw_state_group_count++] =
3254 (struct tu_draw_state_group) {
3255 .id = TU_DRAW_STATE_RAST,
3256 .enable_mask = ENABLE_ALL,
3257 .ib = pipeline->rast.state_ib,
3258 };
3259 draw_state_groups[draw_state_group_count++] =
3260 (struct tu_draw_state_group) {
3261 .id = TU_DRAW_STATE_DS,
3262 .enable_mask = ENABLE_ALL,
3263 .ib = pipeline->ds.state_ib,
3264 };
3265 draw_state_groups[draw_state_group_count++] =
3266 (struct tu_draw_state_group) {
3267 .id = TU_DRAW_STATE_BLEND,
3268 .enable_mask = ENABLE_ALL,
3269 .ib = pipeline->blend.state_ib,
3270 };
3271 }
3272
3273 if (cmd->state.dirty &
3274 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3275 draw_state_groups[draw_state_group_count++] =
3276 (struct tu_draw_state_group) {
3277 .id = TU_DRAW_STATE_VS_CONST,
3278 .enable_mask = ENABLE_ALL,
3279 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3280 };
3281 draw_state_groups[draw_state_group_count++] =
3282 (struct tu_draw_state_group) {
3283 .id = TU_DRAW_STATE_FS_CONST,
3284 .enable_mask = ENABLE_DRAW,
3285 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3286 };
3287 }
3288
3289 if (cmd->state.dirty &
3290 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3291 bool needs_border = false;
3292 struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
3293
3294 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3295 MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3296 if (result != VK_SUCCESS)
3297 return result;
3298
3299 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3300 MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3301 if (result != VK_SUCCESS)
3302 return result;
3303
3304 result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3305 MESA_SHADER_FRAGMENT, &fs_ibo);
3306 if (result != VK_SUCCESS)
3307 return result;
3308
3309 draw_state_groups[draw_state_group_count++] =
3310 (struct tu_draw_state_group) {
3311 .id = TU_DRAW_STATE_VS_TEX,
3312 .enable_mask = ENABLE_ALL,
3313 .ib = vs_tex,
3314 };
3315 draw_state_groups[draw_state_group_count++] =
3316 (struct tu_draw_state_group) {
3317 .id = TU_DRAW_STATE_FS_TEX,
3318 .enable_mask = ENABLE_DRAW,
3319 .ib = fs_tex,
3320 };
3321 draw_state_groups[draw_state_group_count++] =
3322 (struct tu_draw_state_group) {
3323 .id = TU_DRAW_STATE_FS_IBO,
3324 .enable_mask = ENABLE_DRAW,
3325 .ib = fs_ibo,
3326 };
3327
3328 if (needs_border) {
3329 result = tu6_emit_border_color(cmd, cs);
3330 if (result != VK_SUCCESS)
3331 return result;
3332 }
3333 }
3334
3335 struct tu_cs_entry vs_params;
3336 result = tu6_emit_vs_params(cmd, draw, &vs_params);
3337 if (result != VK_SUCCESS)
3338 return result;
3339
3340 draw_state_groups[draw_state_group_count++] =
3341 (struct tu_draw_state_group) {
3342 .id = TU_DRAW_STATE_VS_PARAMS,
3343 .enable_mask = ENABLE_ALL,
3344 .ib = vs_params,
3345 };
3346
3347 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3348 for (uint32_t i = 0; i < draw_state_group_count; i++) {
3349 const struct tu_draw_state_group *group = &draw_state_groups[i];
3350 debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3351 uint32_t cp_set_draw_state =
3352 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3353 group->enable_mask |
3354 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3355 uint64_t iova;
3356 if (group->ib.size) {
3357 iova = group->ib.bo->iova + group->ib.offset;
3358 } else {
3359 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3360 iova = 0;
3361 }
3362
3363 tu_cs_emit(cs, cp_set_draw_state);
3364 tu_cs_emit_qw(cs, iova);
3365 }
3366
3367 tu_cs_sanity_check(cs);
3368
3369 /* track BOs */
3370 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3371 for (uint32_t i = 0; i < MAX_VBS; i++) {
3372 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3373 if (buf)
3374 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3375 }
3376 }
3377 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3378 unsigned i;
3379 for_each_bit(i, descriptors_state->valid) {
3380 struct tu_descriptor_set *set = descriptors_state->sets[i];
3381 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3382 if (set->descriptors[j]) {
3383 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3384 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3385 }
3386 }
3387 }
3388
3389 /* Fragment shader state overwrites compute shader state, so flag the
3390 * compute pipeline for re-emit.
3391 */
3392 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3393 return VK_SUCCESS;
3394 }
3395
3396 static void
3397 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3398 struct tu_cs *cs,
3399 const struct tu_draw_info *draw)
3400 {
3401
3402 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3403
3404 tu_cs_emit_regs(cs,
3405 A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3406 A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3407
3408 /* TODO hw binning */
3409 if (draw->indexed) {
3410 const enum a4xx_index_size index_size =
3411 tu6_index_size(cmd->state.index_type);
3412 const uint32_t index_bytes =
3413 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3414 const struct tu_buffer *buf = cmd->state.index_buffer;
3415 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3416 index_bytes * draw->first_index;
3417 const uint32_t size = index_bytes * draw->count;
3418
3419 const uint32_t cp_draw_indx =
3420 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3421 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3422 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3423 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3424
3425 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3426 tu_cs_emit(cs, cp_draw_indx);
3427 tu_cs_emit(cs, draw->instance_count);
3428 tu_cs_emit(cs, draw->count);
3429 tu_cs_emit(cs, 0x0); /* XXX */
3430 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3431 tu_cs_emit(cs, size);
3432 } else {
3433 const uint32_t cp_draw_indx =
3434 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3435 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3436 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3437
3438 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3439 tu_cs_emit(cs, cp_draw_indx);
3440 tu_cs_emit(cs, draw->instance_count);
3441 tu_cs_emit(cs, draw->count);
3442 }
3443 }
3444
3445 static void
3446 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3447 {
3448 struct tu_cs *cs = &cmd->draw_cs;
3449 VkResult result;
3450
3451 result = tu6_bind_draw_states(cmd, cs, draw);
3452 if (result != VK_SUCCESS) {
3453 cmd->record_result = result;
3454 return;
3455 }
3456
3457 result = tu_cs_reserve_space(cmd->device, cs, 32);
3458 if (result != VK_SUCCESS) {
3459 cmd->record_result = result;
3460 return;
3461 }
3462
3463 if (draw->indirect) {
3464 tu_finishme("indirect draw");
3465 return;
3466 }
3467
3468 /* TODO tu6_emit_marker should pick different regs depending on cs */
3469
3470 tu6_emit_marker(cmd, cs);
3471 tu6_emit_draw_direct(cmd, cs, draw);
3472 tu6_emit_marker(cmd, cs);
3473
3474 cmd->wait_for_idle = true;
3475
3476 tu_cs_sanity_check(cs);
3477 }
3478
3479 void
3480 tu_CmdDraw(VkCommandBuffer commandBuffer,
3481 uint32_t vertexCount,
3482 uint32_t instanceCount,
3483 uint32_t firstVertex,
3484 uint32_t firstInstance)
3485 {
3486 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3487 struct tu_draw_info info = {};
3488
3489 info.count = vertexCount;
3490 info.instance_count = instanceCount;
3491 info.first_instance = firstInstance;
3492 info.vertex_offset = firstVertex;
3493
3494 tu_draw(cmd_buffer, &info);
3495 }
3496
3497 void
3498 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3499 uint32_t indexCount,
3500 uint32_t instanceCount,
3501 uint32_t firstIndex,
3502 int32_t vertexOffset,
3503 uint32_t firstInstance)
3504 {
3505 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3506 struct tu_draw_info info = {};
3507
3508 info.indexed = true;
3509 info.count = indexCount;
3510 info.instance_count = instanceCount;
3511 info.first_index = firstIndex;
3512 info.vertex_offset = vertexOffset;
3513 info.first_instance = firstInstance;
3514
3515 tu_draw(cmd_buffer, &info);
3516 }
3517
3518 void
3519 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3520 VkBuffer _buffer,
3521 VkDeviceSize offset,
3522 uint32_t drawCount,
3523 uint32_t stride)
3524 {
3525 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3526 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3527 struct tu_draw_info info = {};
3528
3529 info.count = drawCount;
3530 info.indirect = buffer;
3531 info.indirect_offset = offset;
3532 info.stride = stride;
3533
3534 tu_draw(cmd_buffer, &info);
3535 }
3536
3537 void
3538 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3539 VkBuffer _buffer,
3540 VkDeviceSize offset,
3541 uint32_t drawCount,
3542 uint32_t stride)
3543 {
3544 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3545 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3546 struct tu_draw_info info = {};
3547
3548 info.indexed = true;
3549 info.count = drawCount;
3550 info.indirect = buffer;
3551 info.indirect_offset = offset;
3552 info.stride = stride;
3553
3554 tu_draw(cmd_buffer, &info);
3555 }
3556
3557 struct tu_dispatch_info
3558 {
3559 /**
3560 * Determine the layout of the grid (in block units) to be used.
3561 */
3562 uint32_t blocks[3];
3563
3564 /**
3565 * A starting offset for the grid. If unaligned is set, the offset
3566 * must still be aligned.
3567 */
3568 uint32_t offsets[3];
3569 /**
3570 * Whether it's an unaligned compute dispatch.
3571 */
3572 bool unaligned;
3573
3574 /**
3575 * Indirect compute parameters resource.
3576 */
3577 struct tu_buffer *indirect;
3578 uint64_t indirect_offset;
3579 };
3580
3581 static void
3582 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3583 const struct tu_dispatch_info *info)
3584 {
3585 gl_shader_stage type = MESA_SHADER_COMPUTE;
3586 const struct tu_program_descriptor_linkage *link =
3587 &pipeline->program.link[type];
3588 const struct ir3_const_state *const_state = &link->const_state;
3589 uint32_t offset = const_state->offsets.driver_param;
3590
3591 if (link->constlen <= offset)
3592 return;
3593
3594 if (!info->indirect) {
3595 uint32_t driver_params[IR3_DP_CS_COUNT] = {
3596 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3597 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3598 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3599 [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3600 [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3601 [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3602 };
3603
3604 uint32_t num_consts = MIN2(const_state->num_driver_params,
3605 (link->constlen - offset) * 4);
3606 /* push constants */
3607 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3608 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3609 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3610 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3611 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3612 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3613 tu_cs_emit(cs, 0);
3614 tu_cs_emit(cs, 0);
3615 uint32_t i;
3616 for (i = 0; i < num_consts; i++)
3617 tu_cs_emit(cs, driver_params[i]);
3618 } else {
3619 tu_finishme("Indirect driver params");
3620 }
3621 }
3622
3623 static void
3624 tu_dispatch(struct tu_cmd_buffer *cmd,
3625 const struct tu_dispatch_info *info)
3626 {
3627 struct tu_cs *cs = &cmd->cs;
3628 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3629 struct tu_descriptor_state *descriptors_state =
3630 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3631
3632 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3633 if (result != VK_SUCCESS) {
3634 cmd->record_result = result;
3635 return;
3636 }
3637
3638 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3639 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3640
3641 struct tu_cs_entry ib;
3642
3643 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3644 if (ib.size)
3645 tu_cs_emit_ib(cs, &ib);
3646
3647 tu_emit_compute_driver_params(cs, pipeline, info);
3648
3649 bool needs_border;
3650 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3651 MESA_SHADER_COMPUTE, &ib, &needs_border);
3652 if (result != VK_SUCCESS) {
3653 cmd->record_result = result;
3654 return;
3655 }
3656
3657 if (ib.size)
3658 tu_cs_emit_ib(cs, &ib);
3659
3660 if (needs_border)
3661 tu_finishme("compute border color");
3662
3663 result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3664 if (result != VK_SUCCESS) {
3665 cmd->record_result = result;
3666 return;
3667 }
3668
3669 if (ib.size)
3670 tu_cs_emit_ib(cs, &ib);
3671
3672 /* track BOs */
3673 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3674 unsigned i;
3675 for_each_bit(i, descriptors_state->valid) {
3676 struct tu_descriptor_set *set = descriptors_state->sets[i];
3677 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3678 if (set->descriptors[j]) {
3679 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3680 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3681 }
3682 }
3683 }
3684
3685 /* Compute shader state overwrites fragment shader state, so we flag the
3686 * graphics pipeline for re-emit.
3687 */
3688 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3689
3690 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3691 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3692
3693 const uint32_t *local_size = pipeline->compute.local_size;
3694 const uint32_t *num_groups = info->blocks;
3695 tu_cs_emit_regs(cs,
3696 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3697 .localsizex = local_size[0] - 1,
3698 .localsizey = local_size[1] - 1,
3699 .localsizez = local_size[2] - 1),
3700 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3701 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3702 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3703 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3704 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3705 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3706
3707 tu_cs_emit_regs(cs,
3708 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3709 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3710 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3711
3712 if (info->indirect) {
3713 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3714
3715 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3716 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3717
3718 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3719 tu_cs_emit(cs, 0x00000000);
3720 tu_cs_emit_qw(cs, iova);
3721 tu_cs_emit(cs,
3722 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3723 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3724 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3725 } else {
3726 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3727 tu_cs_emit(cs, 0x00000000);
3728 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3729 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3730 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3731 }
3732
3733 tu_cs_emit_wfi(cs);
3734
3735 tu6_emit_cache_flush(cmd, cs);
3736 }
3737
3738 void
3739 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3740 uint32_t base_x,
3741 uint32_t base_y,
3742 uint32_t base_z,
3743 uint32_t x,
3744 uint32_t y,
3745 uint32_t z)
3746 {
3747 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3748 struct tu_dispatch_info info = {};
3749
3750 info.blocks[0] = x;
3751 info.blocks[1] = y;
3752 info.blocks[2] = z;
3753
3754 info.offsets[0] = base_x;
3755 info.offsets[1] = base_y;
3756 info.offsets[2] = base_z;
3757 tu_dispatch(cmd_buffer, &info);
3758 }
3759
3760 void
3761 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3762 uint32_t x,
3763 uint32_t y,
3764 uint32_t z)
3765 {
3766 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3767 }
3768
3769 void
3770 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3771 VkBuffer _buffer,
3772 VkDeviceSize offset)
3773 {
3774 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3775 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3776 struct tu_dispatch_info info = {};
3777
3778 info.indirect = buffer;
3779 info.indirect_offset = offset;
3780
3781 tu_dispatch(cmd_buffer, &info);
3782 }
3783
3784 void
3785 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3786 {
3787 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3788
3789 tu_cs_end(&cmd_buffer->draw_cs);
3790 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3791
3792 tu_cmd_render_tiles(cmd_buffer);
3793
3794 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3795 rendered */
3796 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3797 tu_cs_begin(&cmd_buffer->draw_cs);
3798 tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
3799 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
3800
3801 cmd_buffer->state.pass = NULL;
3802 cmd_buffer->state.subpass = NULL;
3803 cmd_buffer->state.framebuffer = NULL;
3804 }
3805
3806 void
3807 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3808 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3809 {
3810 tu_CmdEndRenderPass(commandBuffer);
3811 }
3812
3813 struct tu_barrier_info
3814 {
3815 uint32_t eventCount;
3816 const VkEvent *pEvents;
3817 VkPipelineStageFlags srcStageMask;
3818 };
3819
3820 static void
3821 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3822 uint32_t memoryBarrierCount,
3823 const VkMemoryBarrier *pMemoryBarriers,
3824 uint32_t bufferMemoryBarrierCount,
3825 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3826 uint32_t imageMemoryBarrierCount,
3827 const VkImageMemoryBarrier *pImageMemoryBarriers,
3828 const struct tu_barrier_info *info)
3829 {
3830 }
3831
3832 void
3833 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3834 VkPipelineStageFlags srcStageMask,
3835 VkPipelineStageFlags destStageMask,
3836 VkBool32 byRegion,
3837 uint32_t memoryBarrierCount,
3838 const VkMemoryBarrier *pMemoryBarriers,
3839 uint32_t bufferMemoryBarrierCount,
3840 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3841 uint32_t imageMemoryBarrierCount,
3842 const VkImageMemoryBarrier *pImageMemoryBarriers)
3843 {
3844 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3845 struct tu_barrier_info info;
3846
3847 info.eventCount = 0;
3848 info.pEvents = NULL;
3849 info.srcStageMask = srcStageMask;
3850
3851 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3852 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3853 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3854 }
3855
3856 static void
3857 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
3858 {
3859 struct tu_cs *cs = &cmd->cs;
3860
3861 VkResult result = tu_cs_reserve_space(cmd->device, cs, 4);
3862 if (result != VK_SUCCESS) {
3863 cmd->record_result = result;
3864 return;
3865 }
3866
3867 tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
3868
3869 /* TODO: any flush required before/after ? */
3870
3871 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
3872 tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
3873 tu_cs_emit(cs, value);
3874 }
3875
3876 void
3877 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3878 VkEvent _event,
3879 VkPipelineStageFlags stageMask)
3880 {
3881 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3882 TU_FROM_HANDLE(tu_event, event, _event);
3883
3884 write_event(cmd, event, 1);
3885 }
3886
3887 void
3888 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3889 VkEvent _event,
3890 VkPipelineStageFlags stageMask)
3891 {
3892 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3893 TU_FROM_HANDLE(tu_event, event, _event);
3894
3895 write_event(cmd, event, 0);
3896 }
3897
3898 void
3899 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3900 uint32_t eventCount,
3901 const VkEvent *pEvents,
3902 VkPipelineStageFlags srcStageMask,
3903 VkPipelineStageFlags dstStageMask,
3904 uint32_t memoryBarrierCount,
3905 const VkMemoryBarrier *pMemoryBarriers,
3906 uint32_t bufferMemoryBarrierCount,
3907 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3908 uint32_t imageMemoryBarrierCount,
3909 const VkImageMemoryBarrier *pImageMemoryBarriers)
3910 {
3911 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3912 struct tu_cs *cs = &cmd->cs;
3913
3914 VkResult result = tu_cs_reserve_space(cmd->device, cs, eventCount * 7);
3915 if (result != VK_SUCCESS) {
3916 cmd->record_result = result;
3917 return;
3918 }
3919
3920 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3921
3922 for (uint32_t i = 0; i < eventCount; i++) {
3923 const struct tu_event *event = (const struct tu_event*) pEvents[i];
3924
3925 tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
3926
3927 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
3928 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
3929 CP_WAIT_REG_MEM_0_POLL_MEMORY);
3930 tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
3931 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
3932 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
3933 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3934 }
3935 }
3936
3937 void
3938 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3939 {
3940 /* No-op */
3941 }