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turnip: Reuse tu6_stage2opcode() more.
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 for (uint32_t i = 0; i < list->count; ++i) {
66 if (list->bo_infos[i].handle == bo_info->handle) {
67 assert(list->bo_infos[i].presumed == bo_info->presumed);
68 list->bo_infos[i].flags |= bo_info->flags;
69 return i;
70 }
71 }
72
73 /* grow list->bo_infos if needed */
74 if (list->count == list->capacity) {
75 uint32_t new_capacity = MAX2(2 * list->count, 16);
76 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
77 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
78 if (!new_bo_infos)
79 return TU_BO_LIST_FAILED;
80 list->bo_infos = new_bo_infos;
81 list->capacity = new_capacity;
82 }
83
84 list->bo_infos[list->count] = *bo_info;
85 return list->count++;
86 }
87
88 uint32_t
89 tu_bo_list_add(struct tu_bo_list *list,
90 const struct tu_bo *bo,
91 uint32_t flags)
92 {
93 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
94 .flags = flags,
95 .handle = bo->gem_handle,
96 .presumed = bo->iova,
97 });
98 }
99
100 VkResult
101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
102 {
103 for (uint32_t i = 0; i < other->count; i++) {
104 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
105 return VK_ERROR_OUT_OF_HOST_MEMORY;
106 }
107
108 return VK_SUCCESS;
109 }
110
111 static VkResult
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
113 const struct tu_device *dev)
114 {
115 const uint32_t gmem_size = dev->physical_device->gmem_size;
116 uint32_t offset = 0;
117
118 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
119 /* 16KB-aligned */
120 offset = align(offset, 0x4000);
121
122 tiling->gmem_offsets[i] = offset;
123 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
124 tiling->buffer_cpp[i];
125 }
126
127 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
128 }
129
130 static void
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
132 const struct tu_device *dev)
133 {
134 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
135 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
136 const uint32_t max_tile_width = 1024; /* A6xx */
137
138 tiling->tile0.offset = (VkOffset2D) {
139 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
140 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
141 };
142
143 const uint32_t ra_width =
144 tiling->render_area.extent.width +
145 (tiling->render_area.offset.x - tiling->tile0.offset.x);
146 const uint32_t ra_height =
147 tiling->render_area.extent.height +
148 (tiling->render_area.offset.y - tiling->tile0.offset.y);
149
150 /* start from 1 tile */
151 tiling->tile_count = (VkExtent2D) {
152 .width = 1,
153 .height = 1,
154 };
155 tiling->tile0.extent = (VkExtent2D) {
156 .width = align(ra_width, tile_align_w),
157 .height = align(ra_height, tile_align_h),
158 };
159
160 /* do not exceed max tile width */
161 while (tiling->tile0.extent.width > max_tile_width) {
162 tiling->tile_count.width++;
163 tiling->tile0.extent.width =
164 align(ra_width / tiling->tile_count.width, tile_align_w);
165 }
166
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
169 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
170 tiling->tile_count.width++;
171 tiling->tile0.extent.width =
172 align(ra_width / tiling->tile_count.width, tile_align_w);
173 } else {
174 tiling->tile_count.height++;
175 tiling->tile0.extent.height =
176 align(ra_height / tiling->tile_count.height, tile_align_h);
177 }
178 }
179 }
180
181 static void
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
183 const struct tu_device *dev)
184 {
185 const uint32_t max_pipe_count = 32; /* A6xx */
186
187 /* start from 1 tile per pipe */
188 tiling->pipe0 = (VkExtent2D) {
189 .width = 1,
190 .height = 1,
191 };
192 tiling->pipe_count = tiling->tile_count;
193
194 /* do not exceed max pipe count vertically */
195 while (tiling->pipe_count.height > max_pipe_count) {
196 tiling->pipe0.height += 2;
197 tiling->pipe_count.height =
198 (tiling->tile_count.height + tiling->pipe0.height - 1) /
199 tiling->pipe0.height;
200 }
201
202 /* do not exceed max pipe count */
203 while (tiling->pipe_count.width * tiling->pipe_count.height >
204 max_pipe_count) {
205 tiling->pipe0.width += 1;
206 tiling->pipe_count.width =
207 (tiling->tile_count.width + tiling->pipe0.width - 1) /
208 tiling->pipe0.width;
209 }
210 }
211
212 static void
213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
214 const struct tu_device *dev)
215 {
216 const uint32_t max_pipe_count = 32; /* A6xx */
217 const uint32_t used_pipe_count =
218 tiling->pipe_count.width * tiling->pipe_count.height;
219 const VkExtent2D last_pipe = {
220 .width = tiling->tile_count.width % tiling->pipe0.width,
221 .height = tiling->tile_count.height % tiling->pipe0.height,
222 };
223
224 assert(used_pipe_count <= max_pipe_count);
225 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
226
227 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
228 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
229 const uint32_t pipe_x = tiling->pipe0.width * x;
230 const uint32_t pipe_y = tiling->pipe0.height * y;
231 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
232 ? last_pipe.width
233 : tiling->pipe0.width;
234 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
235 ? last_pipe.height
236 : tiling->pipe0.height;
237 const uint32_t n = tiling->pipe_count.width * y + x;
238
239 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
243 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
244 }
245 }
246
247 memset(tiling->pipe_config + used_pipe_count, 0,
248 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
249 }
250
251 static void
252 tu_tiling_config_update(struct tu_tiling_config *tiling,
253 const struct tu_device *dev,
254 const uint32_t *buffer_cpp,
255 uint32_t buffer_count,
256 const VkRect2D *render_area)
257 {
258 /* see if there is any real change */
259 const bool ra_changed =
260 render_area &&
261 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
262 const bool buf_changed = tiling->buffer_count != buffer_count ||
263 memcmp(tiling->buffer_cpp, buffer_cpp,
264 sizeof(*buffer_cpp) * buffer_count);
265 if (!ra_changed && !buf_changed)
266 return;
267
268 if (ra_changed)
269 tiling->render_area = *render_area;
270
271 if (buf_changed) {
272 memcpy(tiling->buffer_cpp, buffer_cpp,
273 sizeof(*buffer_cpp) * buffer_count);
274 tiling->buffer_count = buffer_count;
275 }
276
277 tu_tiling_config_update_tile_layout(tiling, dev);
278 tu_tiling_config_update_pipe_layout(tiling, dev);
279 tu_tiling_config_update_pipes(tiling, dev);
280 }
281
282 static void
283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
284 const struct tu_device *dev,
285 uint32_t tx,
286 uint32_t ty,
287 struct tu_tile *tile)
288 {
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px = tx / tiling->pipe0.width;
291 const uint32_t py = ty / tiling->pipe0.height;
292 const uint32_t sx = tx - tiling->pipe0.width * px;
293 const uint32_t sy = ty - tiling->pipe0.height * py;
294
295 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
296 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
297 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
298
299 /* convert to 1D indices */
300 tile->pipe = tiling->pipe_count.width * py + px;
301 tile->slot = tiling->pipe0.width * sy + sx;
302
303 /* get the blit area for the tile */
304 tile->begin = (VkOffset2D) {
305 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
306 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
307 };
308 tile->end.x =
309 (tx == tiling->tile_count.width - 1)
310 ? tiling->render_area.offset.x + tiling->render_area.extent.width
311 : tile->begin.x + tiling->tile0.extent.width;
312 tile->end.y =
313 (ty == tiling->tile_count.height - 1)
314 ? tiling->render_area.offset.y + tiling->render_area.extent.height
315 : tile->begin.y + tiling->tile0.extent.height;
316 }
317
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples)
320 {
321 switch (samples) {
322 case 1:
323 return MSAA_ONE;
324 case 2:
325 return MSAA_TWO;
326 case 4:
327 return MSAA_FOUR;
328 case 8:
329 return MSAA_EIGHT;
330 default:
331 assert(!"invalid sample count");
332 return MSAA_ONE;
333 }
334 }
335
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type)
338 {
339 switch (type) {
340 case VK_INDEX_TYPE_UINT16:
341 return INDEX4_SIZE_16_BIT;
342 case VK_INDEX_TYPE_UINT32:
343 return INDEX4_SIZE_32_BIT;
344 default:
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT;
347 }
348 }
349
350 static void
351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
354 }
355
356 void
357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
358 struct tu_cs *cs,
359 enum vgt_event_type event,
360 bool need_seqno)
361 {
362 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
363 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
364 if (need_seqno) {
365 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
366 tu_cs_emit(cs, ++cmd->scratch_seqno);
367 }
368 }
369
370 static void
371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
372 {
373 tu6_emit_event_write(cmd, cs, 0x31, false);
374 }
375
376 static void
377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
378 {
379 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
380 }
381
382 static void
383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
384 {
385 if (cmd->wait_for_idle) {
386 tu_cs_emit_wfi(cs);
387 cmd->wait_for_idle = false;
388 }
389 }
390
391 static void
392 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
393 {
394 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
395 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
396 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
397 if (iview->image->ubwc_size) {
398 tu_cs_emit_qw(cs, va);
399 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
401 } else {
402 tu_cs_emit_qw(cs, 0);
403 tu_cs_emit(cs, 0);
404 }
405 }
406
407 static void
408 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
409 {
410 const struct tu_framebuffer *fb = cmd->state.framebuffer;
411 const struct tu_subpass *subpass = cmd->state.subpass;
412 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
413
414 const uint32_t a = subpass->depth_stencil_attachment.attachment;
415 if (a == VK_ATTACHMENT_UNUSED) {
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
417 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
418 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
419 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
422 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
423
424 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
425 tu_cs_emit(cs,
426 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
429 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
430 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
431 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
432 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
433 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
436 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
437
438 return;
439 }
440
441 const struct tu_image_view *iview = fb->attachments[a].attachment;
442 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
443
444 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
445 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
446 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
447 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layer_size));
448 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
449 tu_cs_emit(cs, tiling->gmem_offsets[subpass->color_count]);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
452 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
453
454 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
455 tu6_emit_flag_buffer(cs, iview);
456
457 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
458 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
459 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
460 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
461 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
462 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
465 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
466
467 /* enable zs? */
468 }
469
470 static void
471 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
472 {
473 const struct tu_framebuffer *fb = cmd->state.framebuffer;
474 const struct tu_subpass *subpass = cmd->state.subpass;
475 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
476 unsigned char mrt_comp[MAX_RTS] = { 0 };
477 unsigned srgb_cntl = 0;
478
479 for (uint32_t i = 0; i < subpass->color_count; ++i) {
480 uint32_t a = subpass->color_attachments[i].attachment;
481 if (a == VK_ATTACHMENT_UNUSED)
482 continue;
483
484 const struct tu_image_view *iview = fb->attachments[a].attachment;
485 const enum a6xx_tile_mode tile_mode =
486 tu6_get_image_tile_mode(iview->image, iview->base_mip);
487
488 mrt_comp[i] = 0xf;
489
490 if (vk_format_is_srgb(iview->vk_format))
491 srgb_cntl |= (1 << i);
492
493 const struct tu_native_format *format =
494 tu6_get_native_format(iview->vk_format);
495 assert(format && format->rb >= 0);
496
497 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
498 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
499 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
500 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
501 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
502 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layer_size));
503 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
504 tu_cs_emit(
505 cs, tiling->gmem_offsets[i]); /* RB_MRT[i].BASE_GMEM */
506
507 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
508 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
509 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
510 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
511
512 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
513 tu6_emit_flag_buffer(cs, iview);
514 }
515
516 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
517 tu_cs_emit(cs, srgb_cntl);
518
519 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
520 tu_cs_emit(cs, srgb_cntl);
521
522 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
523 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
524 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
525 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
526 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
527 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
528 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
529 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
530 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
533 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
534 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
535 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
536 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
537 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
538 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
539 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
540 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
541 }
542
543 static void
544 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
545 {
546 const struct tu_subpass *subpass = cmd->state.subpass;
547 const enum a3xx_msaa_samples samples =
548 tu_msaa_samples(subpass->max_sample_count);
549
550 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
551 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
552 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
553 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
556 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
557 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
558 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
559
560 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
561 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
562 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
563 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
564
565 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
566 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
567 }
568
569 static void
570 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
571 {
572 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
573 const uint32_t bin_w = tiling->tile0.extent.width;
574 const uint32_t bin_h = tiling->tile0.extent.height;
575
576 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
577 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
578 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
579
580 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
581 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
582 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
583
584 /* no flag for RB_BIN_CONTROL2... */
585 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
586 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
587 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
588 }
589
590 static void
591 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
592 struct tu_cs *cs,
593 bool binning)
594 {
595 uint32_t cntl = 0;
596 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
597 if (binning)
598 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
599
600 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
601 tu_cs_emit(cs, 0x2);
602 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
603 tu_cs_emit(cs, cntl);
604 }
605
606 static void
607 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
608 {
609 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
610 const uint32_t x1 = render_area->offset.x;
611 const uint32_t y1 = render_area->offset.y;
612 const uint32_t x2 = x1 + render_area->extent.width - 1;
613 const uint32_t y2 = y1 + render_area->extent.height - 1;
614
615 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
616 tu_cs_emit(cs,
617 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
618 tu_cs_emit(cs,
619 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
620 }
621
622 static void
623 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
624 struct tu_cs *cs,
625 const struct tu_image_view *iview,
626 uint32_t gmem_offset,
627 uint32_t blit_info)
628 {
629 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
630 tu_cs_emit(cs, blit_info);
631
632 const struct tu_native_format *format =
633 tu6_get_native_format(iview->vk_format);
634 assert(format && format->rb >= 0);
635
636 enum a6xx_tile_mode tile_mode =
637 tu6_get_image_tile_mode(iview->image, iview->base_mip);
638 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
639 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
640 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
641 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
642 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
643 COND(iview->image->ubwc_size, A6XX_RB_BLIT_DST_INFO_FLAGS));
644 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
645 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
646 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layer_size));
647
648 if (iview->image->ubwc_size) {
649 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
650 tu6_emit_flag_buffer(cs, iview);
651 }
652
653 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
654 tu_cs_emit(cs, gmem_offset);
655 }
656
657 static void
658 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
659 struct tu_cs *cs,
660 const struct tu_image_view *iview,
661 uint32_t gmem_offset,
662 const VkClearValue *clear_value)
663 {
664 const struct tu_native_format *format =
665 tu6_get_native_format(iview->vk_format);
666 assert(format && format->rb >= 0);
667
668 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
669 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
670
671 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
672 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
673
674 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
675 tu_cs_emit(cs, gmem_offset);
676
677 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
678 tu_cs_emit(cs, 0);
679
680 uint32_t clear_vals[4] = { 0 };
681 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
682
683 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
684 tu_cs_emit(cs, clear_vals[0]);
685 tu_cs_emit(cs, clear_vals[1]);
686 tu_cs_emit(cs, clear_vals[2]);
687 tu_cs_emit(cs, clear_vals[3]);
688 }
689
690 static void
691 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
692 {
693 tu6_emit_marker(cmd, cs);
694 tu6_emit_event_write(cmd, cs, BLIT, false);
695 tu6_emit_marker(cmd, cs);
696 }
697
698 static void
699 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
700 struct tu_cs *cs,
701 uint32_t x1,
702 uint32_t y1,
703 uint32_t x2,
704 uint32_t y2)
705 {
706 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
707 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
708 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
709 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
710 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
711
712 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
713 tu_cs_emit(
714 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
715 tu_cs_emit(
716 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
717 }
718
719 static void
720 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
721 struct tu_cs *cs,
722 uint32_t x1,
723 uint32_t y1)
724 {
725 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
726 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
727
728 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
729 tu_cs_emit(cs,
730 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
731
732 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
733 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
734
735 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
736 tu_cs_emit(
737 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
738 }
739
740 static void
741 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
742 struct tu_cs *cs,
743 const struct tu_tile *tile)
744 {
745 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
746 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
747
748 tu6_emit_marker(cmd, cs);
749 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
750 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
751 tu6_emit_marker(cmd, cs);
752
753 const uint32_t x1 = tile->begin.x;
754 const uint32_t y1 = tile->begin.y;
755 const uint32_t x2 = tile->end.x - 1;
756 const uint32_t y2 = tile->end.y - 1;
757 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
758 tu6_emit_window_offset(cmd, cs, x1, y1);
759
760 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
761 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
762
763 if (false) {
764 /* hw binning? */
765 } else {
766 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
767 tu_cs_emit(cs, 0x1);
768
769 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
770 tu_cs_emit(cs, 0x0);
771 }
772 }
773
774 static void
775 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
776 struct tu_cs *cs,
777 uint32_t a,
778 uint32_t gmem_index)
779 {
780 const struct tu_framebuffer *fb = cmd->state.framebuffer;
781 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
782 const struct tu_attachment_state *attachments = cmd->state.attachments;
783
784 const struct tu_image_view *iview = fb->attachments[a].attachment;
785 const struct tu_attachment_state *att = attachments + a;
786 if (att->pending_clear_aspects) {
787 tu6_emit_blit_clear(cmd, cs, iview,
788 tiling->gmem_offsets[gmem_index],
789 &att->clear_value);
790 } else {
791 tu6_emit_blit_info(cmd, cs, iview,
792 tiling->gmem_offsets[gmem_index],
793 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
794 }
795
796 tu6_emit_blit(cmd, cs);
797 }
798
799 static void
800 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
801 {
802 const struct tu_subpass *subpass = cmd->state.subpass;
803
804 tu6_emit_blit_scissor(cmd, cs);
805
806 for (uint32_t i = 0; i < subpass->color_count; ++i) {
807 const uint32_t a = subpass->color_attachments[i].attachment;
808 if (a != VK_ATTACHMENT_UNUSED)
809 tu6_emit_tile_load_attachment(cmd, cs, a, i);
810 }
811
812 const uint32_t a = subpass->depth_stencil_attachment.attachment;
813 if (a != VK_ATTACHMENT_UNUSED)
814 tu6_emit_tile_load_attachment(cmd, cs, a, subpass->color_count);
815 }
816
817 static void
818 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
819 struct tu_cs *cs,
820 uint32_t a,
821 uint32_t gmem_index)
822 {
823 const struct tu_framebuffer *fb = cmd->state.framebuffer;
824 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
825
826 if (a == VK_ATTACHMENT_UNUSED)
827 return;
828
829 tu6_emit_blit_info(cmd, cs, fb->attachments[a].attachment,
830 tiling->gmem_offsets[gmem_index], 0);
831 tu6_emit_blit(cmd, cs);
832 }
833
834 static void
835 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
836 {
837 const struct tu_subpass *subpass = cmd->state.subpass;
838
839 if (false) {
840 /* hw binning? */
841 }
842
843 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
844 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
845 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
846 CP_SET_DRAW_STATE__0_GROUP_ID(0));
847 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
848 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
849
850 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
851 tu_cs_emit(cs, 0x0);
852
853 tu6_emit_marker(cmd, cs);
854 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
855 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
856 tu6_emit_marker(cmd, cs);
857
858 tu6_emit_blit_scissor(cmd, cs);
859
860 for (uint32_t i = 0; i < subpass->color_count; ++i) {
861 tu6_emit_store_attachment(cmd, cs,
862 subpass->color_attachments[i].attachment,
863 i);
864 if (subpass->resolve_attachments) {
865 tu6_emit_store_attachment(cmd, cs,
866 subpass->resolve_attachments[i].attachment,
867 i);
868 }
869 }
870
871 tu6_emit_store_attachment(cmd, cs,
872 subpass->depth_stencil_attachment.attachment,
873 subpass->color_count);
874 }
875
876 static void
877 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
878 {
879 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
880 tu_cs_emit(cs, restart_index);
881 }
882
883 static void
884 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
885 {
886 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
887 if (result != VK_SUCCESS) {
888 cmd->record_result = result;
889 return;
890 }
891
892 tu6_emit_cache_flush(cmd, cs);
893
894 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
895
896 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
897 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
898 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
899 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
900 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
901 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
902 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
903 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
904 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
905
906 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
907 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
908 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
909 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
910 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
911 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
912 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
913 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
914 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
915 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
916 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
917 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
918 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
919 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
920
921 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
922
923 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
924 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
926
927 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
928 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
939
940 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
941 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
942
943 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
944 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
945
946 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
947 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
948
949 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
950 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
951 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
952
953 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
954 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
955
956 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
959
960 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
961 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
962 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
963 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
965 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
968 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
970 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
972 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
974 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
975 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
976 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
977 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
978 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
981
982 tu6_emit_marker(cmd, cs);
983
984 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
985
986 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
987
988 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
989
990 /* we don't use this yet.. probably best to disable.. */
991 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
992 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
993 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
994 CP_SET_DRAW_STATE__0_GROUP_ID(0));
995 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
996 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
997
998 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
999 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1000 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1001 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1002
1003 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1004 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1005 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1008 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1009
1010 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1011 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1012
1013 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1014 tu_cs_emit(cs, 0x00000000);
1015 tu_cs_emit(cs, 0x00000000);
1016 tu_cs_emit(cs, 0x00000000);
1017
1018 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1019 tu_cs_emit(cs, 0x00000000);
1020 tu_cs_emit(cs, 0x00000000);
1021 tu_cs_emit(cs, 0x00000000);
1022 tu_cs_emit(cs, 0x00000000);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025
1026 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1027 tu_cs_emit(cs, 0x00000000);
1028 tu_cs_emit(cs, 0x00000000);
1029 tu_cs_emit(cs, 0x00000000);
1030 tu_cs_emit(cs, 0x00000000);
1031 tu_cs_emit(cs, 0x00000000);
1032 tu_cs_emit(cs, 0x00000000);
1033
1034 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1035 tu_cs_emit(cs, 0x00000000);
1036 tu_cs_emit(cs, 0x00000000);
1037 tu_cs_emit(cs, 0x00000000);
1038
1039 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1040 tu_cs_emit(cs, 0x00000000);
1041
1042 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1043 tu_cs_emit(cs, 0x00000000);
1044
1045 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1046 tu_cs_emit(cs, 0x00000000);
1047
1048 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1049 tu_cs_emit(cs, 0x00000000);
1050
1051 tu_cs_sanity_check(cs);
1052 }
1053
1054 static void
1055 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1056 {
1057 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1058 if (result != VK_SUCCESS) {
1059 cmd->record_result = result;
1060 return;
1061 }
1062
1063 tu6_emit_lrz_flush(cmd, cs);
1064
1065 /* lrz clear? */
1066
1067 tu6_emit_cache_flush(cmd, cs);
1068
1069 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1070 tu_cs_emit(cs, 0x0);
1071
1072 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1073 tu6_emit_wfi(cmd, cs);
1074 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1075 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1076
1077 tu6_emit_zs(cmd, cs);
1078 tu6_emit_mrt(cmd, cs);
1079 tu6_emit_msaa(cmd, cs);
1080
1081 if (false) {
1082 /* hw binning? */
1083 } else {
1084 tu6_emit_bin_size(cmd, cs, 0x6000000);
1085 /* no draws */
1086 }
1087
1088 tu6_emit_render_cntl(cmd, cs, false);
1089
1090 tu_cs_sanity_check(cs);
1091 }
1092
1093 static void
1094 tu6_render_tile(struct tu_cmd_buffer *cmd,
1095 struct tu_cs *cs,
1096 const struct tu_tile *tile)
1097 {
1098 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1099 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1100 if (result != VK_SUCCESS) {
1101 cmd->record_result = result;
1102 return;
1103 }
1104
1105 tu6_emit_tile_select(cmd, cs, tile);
1106 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1107
1108 tu_cs_emit_call(cs, &cmd->draw_cs);
1109 cmd->wait_for_idle = true;
1110
1111 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1112
1113 tu_cs_sanity_check(cs);
1114 }
1115
1116 static void
1117 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1118 {
1119 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1120 if (result != VK_SUCCESS) {
1121 cmd->record_result = result;
1122 return;
1123 }
1124
1125 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1126 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1127
1128 tu6_emit_lrz_flush(cmd, cs);
1129
1130 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1131
1132 tu_cs_sanity_check(cs);
1133 }
1134
1135 static void
1136 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1137 {
1138 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1139
1140 tu6_render_begin(cmd, &cmd->cs);
1141
1142 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1143 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1144 struct tu_tile tile;
1145 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1146 tu6_render_tile(cmd, &cmd->cs, &tile);
1147 }
1148 }
1149
1150 tu6_render_end(cmd, &cmd->cs);
1151 }
1152
1153 static void
1154 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1155 {
1156 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1157 const struct tu_subpass *subpass = cmd->state.subpass;
1158 struct tu_attachment_state *attachments = cmd->state.attachments;
1159 struct tu_cs sub_cs;
1160
1161 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1162 tile_load_space, &sub_cs);
1163 if (result != VK_SUCCESS) {
1164 cmd->record_result = result;
1165 return;
1166 }
1167
1168 /* emit to tile-load sub_cs */
1169 tu6_emit_tile_load(cmd, &sub_cs);
1170
1171 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1172
1173 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1174 const uint32_t a = subpass->color_attachments[i].attachment;
1175 if (a != VK_ATTACHMENT_UNUSED)
1176 attachments[a].pending_clear_aspects = 0;
1177 }
1178 }
1179
1180 static void
1181 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1182 {
1183 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1184 struct tu_cs sub_cs;
1185
1186 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1187 tile_store_space, &sub_cs);
1188 if (result != VK_SUCCESS) {
1189 cmd->record_result = result;
1190 return;
1191 }
1192
1193 /* emit to tile-store sub_cs */
1194 tu6_emit_tile_store(cmd, &sub_cs);
1195
1196 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1197 }
1198
1199 static void
1200 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1201 const VkRect2D *render_area)
1202 {
1203 const struct tu_device *dev = cmd->device;
1204 const struct tu_render_pass *pass = cmd->state.pass;
1205 const struct tu_subpass *subpass = cmd->state.subpass;
1206 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1207
1208 uint32_t buffer_cpp[MAX_RTS + 2];
1209 uint32_t buffer_count = 0;
1210
1211 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1212 const uint32_t a = subpass->color_attachments[i].attachment;
1213 if (a == VK_ATTACHMENT_UNUSED) {
1214 buffer_cpp[buffer_count++] = 0;
1215 continue;
1216 }
1217
1218 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1219 buffer_cpp[buffer_count++] =
1220 vk_format_get_blocksize(att->format) * att->samples;
1221 }
1222
1223 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1224 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1225 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1226
1227 /* TODO */
1228 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1229
1230 buffer_cpp[buffer_count++] =
1231 vk_format_get_blocksize(att->format) * att->samples;
1232 }
1233
1234 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1235 render_area);
1236 }
1237
1238 const struct tu_dynamic_state default_dynamic_state = {
1239 .viewport =
1240 {
1241 .count = 0,
1242 },
1243 .scissor =
1244 {
1245 .count = 0,
1246 },
1247 .line_width = 1.0f,
1248 .depth_bias =
1249 {
1250 .bias = 0.0f,
1251 .clamp = 0.0f,
1252 .slope = 0.0f,
1253 },
1254 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1255 .depth_bounds =
1256 {
1257 .min = 0.0f,
1258 .max = 1.0f,
1259 },
1260 .stencil_compare_mask =
1261 {
1262 .front = ~0u,
1263 .back = ~0u,
1264 },
1265 .stencil_write_mask =
1266 {
1267 .front = ~0u,
1268 .back = ~0u,
1269 },
1270 .stencil_reference =
1271 {
1272 .front = 0u,
1273 .back = 0u,
1274 },
1275 };
1276
1277 static void UNUSED /* FINISHME */
1278 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1279 const struct tu_dynamic_state *src)
1280 {
1281 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1282 uint32_t copy_mask = src->mask;
1283 uint32_t dest_mask = 0;
1284
1285 tu_use_args(cmd_buffer); /* FINISHME */
1286
1287 /* Make sure to copy the number of viewports/scissors because they can
1288 * only be specified at pipeline creation time.
1289 */
1290 dest->viewport.count = src->viewport.count;
1291 dest->scissor.count = src->scissor.count;
1292 dest->discard_rectangle.count = src->discard_rectangle.count;
1293
1294 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1295 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1296 src->viewport.count * sizeof(VkViewport))) {
1297 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1298 src->viewport.count);
1299 dest_mask |= TU_DYNAMIC_VIEWPORT;
1300 }
1301 }
1302
1303 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1304 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1305 src->scissor.count * sizeof(VkRect2D))) {
1306 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1307 src->scissor.count);
1308 dest_mask |= TU_DYNAMIC_SCISSOR;
1309 }
1310 }
1311
1312 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1313 if (dest->line_width != src->line_width) {
1314 dest->line_width = src->line_width;
1315 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1316 }
1317 }
1318
1319 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1320 if (memcmp(&dest->depth_bias, &src->depth_bias,
1321 sizeof(src->depth_bias))) {
1322 dest->depth_bias = src->depth_bias;
1323 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1324 }
1325 }
1326
1327 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1328 if (memcmp(&dest->blend_constants, &src->blend_constants,
1329 sizeof(src->blend_constants))) {
1330 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1331 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1332 }
1333 }
1334
1335 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1336 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1337 sizeof(src->depth_bounds))) {
1338 dest->depth_bounds = src->depth_bounds;
1339 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1340 }
1341 }
1342
1343 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1344 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1345 sizeof(src->stencil_compare_mask))) {
1346 dest->stencil_compare_mask = src->stencil_compare_mask;
1347 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1348 }
1349 }
1350
1351 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1352 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1353 sizeof(src->stencil_write_mask))) {
1354 dest->stencil_write_mask = src->stencil_write_mask;
1355 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1356 }
1357 }
1358
1359 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1360 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1361 sizeof(src->stencil_reference))) {
1362 dest->stencil_reference = src->stencil_reference;
1363 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1364 }
1365 }
1366
1367 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1368 if (memcmp(&dest->discard_rectangle.rectangles,
1369 &src->discard_rectangle.rectangles,
1370 src->discard_rectangle.count * sizeof(VkRect2D))) {
1371 typed_memcpy(dest->discard_rectangle.rectangles,
1372 src->discard_rectangle.rectangles,
1373 src->discard_rectangle.count);
1374 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1375 }
1376 }
1377 }
1378
1379 static VkResult
1380 tu_create_cmd_buffer(struct tu_device *device,
1381 struct tu_cmd_pool *pool,
1382 VkCommandBufferLevel level,
1383 VkCommandBuffer *pCommandBuffer)
1384 {
1385 struct tu_cmd_buffer *cmd_buffer;
1386 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1387 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1388 if (cmd_buffer == NULL)
1389 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1390
1391 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1392 cmd_buffer->device = device;
1393 cmd_buffer->pool = pool;
1394 cmd_buffer->level = level;
1395
1396 if (pool) {
1397 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1398 cmd_buffer->queue_family_index = pool->queue_family_index;
1399
1400 } else {
1401 /* Init the pool_link so we can safely call list_del when we destroy
1402 * the command buffer
1403 */
1404 list_inithead(&cmd_buffer->pool_link);
1405 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1406 }
1407
1408 tu_bo_list_init(&cmd_buffer->bo_list);
1409 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1410 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1411 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1412 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1413
1414 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1415
1416 list_inithead(&cmd_buffer->upload.list);
1417
1418 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1419 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1420
1421 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1422 if (result != VK_SUCCESS)
1423 return result;
1424
1425 return VK_SUCCESS;
1426 }
1427
1428 static void
1429 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1430 {
1431 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1432
1433 list_del(&cmd_buffer->pool_link);
1434
1435 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1436 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1437
1438 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1439 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1440 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1441 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1442
1443 tu_bo_list_destroy(&cmd_buffer->bo_list);
1444 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1445 }
1446
1447 static VkResult
1448 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1449 {
1450 cmd_buffer->wait_for_idle = true;
1451
1452 cmd_buffer->record_result = VK_SUCCESS;
1453
1454 tu_bo_list_reset(&cmd_buffer->bo_list);
1455 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1456 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1457 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1458 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1459
1460 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1461 cmd_buffer->descriptors[i].dirty = 0;
1462 cmd_buffer->descriptors[i].valid = 0;
1463 cmd_buffer->descriptors[i].push_dirty = false;
1464 }
1465
1466 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1467
1468 return cmd_buffer->record_result;
1469 }
1470
1471 static VkResult
1472 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1473 const VkRenderPassBeginInfo *info)
1474 {
1475 struct tu_cmd_state *state = &cmd_buffer->state;
1476 const struct tu_framebuffer *fb = state->framebuffer;
1477 const struct tu_render_pass *pass = state->pass;
1478
1479 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1480 const struct tu_image_view *iview = fb->attachments[i].attachment;
1481 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1482 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1483 }
1484
1485 if (pass->attachment_count == 0) {
1486 state->attachments = NULL;
1487 return VK_SUCCESS;
1488 }
1489
1490 state->attachments =
1491 vk_alloc(&cmd_buffer->pool->alloc,
1492 pass->attachment_count * sizeof(state->attachments[0]), 8,
1493 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1494 if (state->attachments == NULL) {
1495 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1496 return cmd_buffer->record_result;
1497 }
1498
1499 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1500 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1501 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1502 VkImageAspectFlags clear_aspects = 0;
1503
1504 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1505 /* color attachment */
1506 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1507 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1508 }
1509 } else {
1510 /* depthstencil attachment */
1511 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1512 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1513 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1514 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1515 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1516 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1517 }
1518 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1519 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1520 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1521 }
1522 }
1523
1524 state->attachments[i].pending_clear_aspects = clear_aspects;
1525 state->attachments[i].cleared_views = 0;
1526 if (clear_aspects && info) {
1527 assert(info->clearValueCount > i);
1528 state->attachments[i].clear_value = info->pClearValues[i];
1529 }
1530
1531 state->attachments[i].current_layout = att->initial_layout;
1532 }
1533
1534 return VK_SUCCESS;
1535 }
1536
1537 VkResult
1538 tu_AllocateCommandBuffers(VkDevice _device,
1539 const VkCommandBufferAllocateInfo *pAllocateInfo,
1540 VkCommandBuffer *pCommandBuffers)
1541 {
1542 TU_FROM_HANDLE(tu_device, device, _device);
1543 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1544
1545 VkResult result = VK_SUCCESS;
1546 uint32_t i;
1547
1548 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1549
1550 if (!list_is_empty(&pool->free_cmd_buffers)) {
1551 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1552 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1553
1554 list_del(&cmd_buffer->pool_link);
1555 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1556
1557 result = tu_reset_cmd_buffer(cmd_buffer);
1558 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1559 cmd_buffer->level = pAllocateInfo->level;
1560
1561 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1562 } else {
1563 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1564 &pCommandBuffers[i]);
1565 }
1566 if (result != VK_SUCCESS)
1567 break;
1568 }
1569
1570 if (result != VK_SUCCESS) {
1571 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1572 pCommandBuffers);
1573
1574 /* From the Vulkan 1.0.66 spec:
1575 *
1576 * "vkAllocateCommandBuffers can be used to create multiple
1577 * command buffers. If the creation of any of those command
1578 * buffers fails, the implementation must destroy all
1579 * successfully created command buffer objects from this
1580 * command, set all entries of the pCommandBuffers array to
1581 * NULL and return the error."
1582 */
1583 memset(pCommandBuffers, 0,
1584 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1585 }
1586
1587 return result;
1588 }
1589
1590 void
1591 tu_FreeCommandBuffers(VkDevice device,
1592 VkCommandPool commandPool,
1593 uint32_t commandBufferCount,
1594 const VkCommandBuffer *pCommandBuffers)
1595 {
1596 for (uint32_t i = 0; i < commandBufferCount; i++) {
1597 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1598
1599 if (cmd_buffer) {
1600 if (cmd_buffer->pool) {
1601 list_del(&cmd_buffer->pool_link);
1602 list_addtail(&cmd_buffer->pool_link,
1603 &cmd_buffer->pool->free_cmd_buffers);
1604 } else
1605 tu_cmd_buffer_destroy(cmd_buffer);
1606 }
1607 }
1608 }
1609
1610 VkResult
1611 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1612 VkCommandBufferResetFlags flags)
1613 {
1614 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1615 return tu_reset_cmd_buffer(cmd_buffer);
1616 }
1617
1618 VkResult
1619 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1620 const VkCommandBufferBeginInfo *pBeginInfo)
1621 {
1622 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1623 VkResult result = VK_SUCCESS;
1624
1625 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1626 /* If the command buffer has already been resetted with
1627 * vkResetCommandBuffer, no need to do it again.
1628 */
1629 result = tu_reset_cmd_buffer(cmd_buffer);
1630 if (result != VK_SUCCESS)
1631 return result;
1632 }
1633
1634 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1635 cmd_buffer->usage_flags = pBeginInfo->flags;
1636
1637 tu_cs_begin(&cmd_buffer->cs);
1638 tu_cs_begin(&cmd_buffer->draw_cs);
1639
1640 cmd_buffer->marker_seqno = 0;
1641 cmd_buffer->scratch_seqno = 0;
1642
1643 /* setup initial configuration into command buffer */
1644 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1645 switch (cmd_buffer->queue_family_index) {
1646 case TU_QUEUE_GENERAL:
1647 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1648 break;
1649 default:
1650 break;
1651 }
1652 }
1653
1654 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1655
1656 return VK_SUCCESS;
1657 }
1658
1659 void
1660 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1661 uint32_t firstBinding,
1662 uint32_t bindingCount,
1663 const VkBuffer *pBuffers,
1664 const VkDeviceSize *pOffsets)
1665 {
1666 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1667
1668 assert(firstBinding + bindingCount <= MAX_VBS);
1669
1670 for (uint32_t i = 0; i < bindingCount; i++) {
1671 cmd->state.vb.buffers[firstBinding + i] =
1672 tu_buffer_from_handle(pBuffers[i]);
1673 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1674 }
1675
1676 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1677 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1678 }
1679
1680 void
1681 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1682 VkBuffer buffer,
1683 VkDeviceSize offset,
1684 VkIndexType indexType)
1685 {
1686 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1687 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1688
1689 /* initialize/update the restart index */
1690 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1691 struct tu_cs *draw_cs = &cmd->draw_cs;
1692 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1693 if (result != VK_SUCCESS) {
1694 cmd->record_result = result;
1695 return;
1696 }
1697
1698 tu6_emit_restart_index(
1699 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1700
1701 tu_cs_sanity_check(draw_cs);
1702 }
1703
1704 /* track the BO */
1705 if (cmd->state.index_buffer != buf)
1706 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1707
1708 cmd->state.index_buffer = buf;
1709 cmd->state.index_offset = offset;
1710 cmd->state.index_type = indexType;
1711 }
1712
1713 void
1714 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1715 VkPipelineBindPoint pipelineBindPoint,
1716 VkPipelineLayout _layout,
1717 uint32_t firstSet,
1718 uint32_t descriptorSetCount,
1719 const VkDescriptorSet *pDescriptorSets,
1720 uint32_t dynamicOffsetCount,
1721 const uint32_t *pDynamicOffsets)
1722 {
1723 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1724 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1725 unsigned dyn_idx = 0;
1726
1727 struct tu_descriptor_state *descriptors_state =
1728 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1729
1730 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1731 unsigned idx = i + firstSet;
1732 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1733
1734 descriptors_state->sets[idx] = set;
1735 descriptors_state->valid |= (1u << idx);
1736
1737 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1738 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1739 assert(dyn_idx < dynamicOffsetCount);
1740
1741 descriptors_state->dynamic_buffers[idx] =
1742 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1743 }
1744 }
1745
1746 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1747 }
1748
1749 void
1750 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1751 VkPipelineLayout layout,
1752 VkShaderStageFlags stageFlags,
1753 uint32_t offset,
1754 uint32_t size,
1755 const void *pValues)
1756 {
1757 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1758 memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1759 }
1760
1761 VkResult
1762 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1763 {
1764 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1765
1766 if (cmd_buffer->scratch_seqno) {
1767 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1768 MSM_SUBMIT_BO_WRITE);
1769 }
1770
1771 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1772 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1773 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1774 }
1775
1776 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1777 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1778 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1779 }
1780
1781 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1782 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1783 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1784 }
1785
1786 tu_cs_end(&cmd_buffer->cs);
1787 tu_cs_end(&cmd_buffer->draw_cs);
1788
1789 assert(!cmd_buffer->state.attachments);
1790
1791 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1792
1793 return cmd_buffer->record_result;
1794 }
1795
1796 void
1797 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1798 VkPipelineBindPoint pipelineBindPoint,
1799 VkPipeline _pipeline)
1800 {
1801 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1802 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1803
1804 switch (pipelineBindPoint) {
1805 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1806 cmd->state.pipeline = pipeline;
1807 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1808 break;
1809 case VK_PIPELINE_BIND_POINT_COMPUTE:
1810 tu_finishme("binding compute pipeline");
1811 break;
1812 default:
1813 unreachable("unrecognized pipeline bind point");
1814 break;
1815 }
1816 }
1817
1818 void
1819 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1820 uint32_t firstViewport,
1821 uint32_t viewportCount,
1822 const VkViewport *pViewports)
1823 {
1824 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1825 struct tu_cs *draw_cs = &cmd->draw_cs;
1826
1827 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1828 if (result != VK_SUCCESS) {
1829 cmd->record_result = result;
1830 return;
1831 }
1832
1833 assert(firstViewport == 0 && viewportCount == 1);
1834 tu6_emit_viewport(draw_cs, pViewports);
1835
1836 tu_cs_sanity_check(draw_cs);
1837 }
1838
1839 void
1840 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1841 uint32_t firstScissor,
1842 uint32_t scissorCount,
1843 const VkRect2D *pScissors)
1844 {
1845 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1846 struct tu_cs *draw_cs = &cmd->draw_cs;
1847
1848 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1849 if (result != VK_SUCCESS) {
1850 cmd->record_result = result;
1851 return;
1852 }
1853
1854 assert(firstScissor == 0 && scissorCount == 1);
1855 tu6_emit_scissor(draw_cs, pScissors);
1856
1857 tu_cs_sanity_check(draw_cs);
1858 }
1859
1860 void
1861 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1862 {
1863 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1864
1865 cmd->state.dynamic.line_width = lineWidth;
1866
1867 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1868 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1869 }
1870
1871 void
1872 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1873 float depthBiasConstantFactor,
1874 float depthBiasClamp,
1875 float depthBiasSlopeFactor)
1876 {
1877 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1878 struct tu_cs *draw_cs = &cmd->draw_cs;
1879
1880 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1881 if (result != VK_SUCCESS) {
1882 cmd->record_result = result;
1883 return;
1884 }
1885
1886 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1887 depthBiasSlopeFactor);
1888
1889 tu_cs_sanity_check(draw_cs);
1890 }
1891
1892 void
1893 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1894 const float blendConstants[4])
1895 {
1896 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1897 struct tu_cs *draw_cs = &cmd->draw_cs;
1898
1899 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1900 if (result != VK_SUCCESS) {
1901 cmd->record_result = result;
1902 return;
1903 }
1904
1905 tu6_emit_blend_constants(draw_cs, blendConstants);
1906
1907 tu_cs_sanity_check(draw_cs);
1908 }
1909
1910 void
1911 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1912 float minDepthBounds,
1913 float maxDepthBounds)
1914 {
1915 }
1916
1917 void
1918 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1919 VkStencilFaceFlags faceMask,
1920 uint32_t compareMask)
1921 {
1922 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1923
1924 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1925 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1926 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1927 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1928
1929 /* the front/back compare masks must be updated together */
1930 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1931 }
1932
1933 void
1934 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1935 VkStencilFaceFlags faceMask,
1936 uint32_t writeMask)
1937 {
1938 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1939
1940 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1941 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1942 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1943 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1944
1945 /* the front/back write masks must be updated together */
1946 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1947 }
1948
1949 void
1950 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1951 VkStencilFaceFlags faceMask,
1952 uint32_t reference)
1953 {
1954 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1955
1956 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1957 cmd->state.dynamic.stencil_reference.front = reference;
1958 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1959 cmd->state.dynamic.stencil_reference.back = reference;
1960
1961 /* the front/back references must be updated together */
1962 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1963 }
1964
1965 void
1966 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1967 uint32_t commandBufferCount,
1968 const VkCommandBuffer *pCmdBuffers)
1969 {
1970 }
1971
1972 VkResult
1973 tu_CreateCommandPool(VkDevice _device,
1974 const VkCommandPoolCreateInfo *pCreateInfo,
1975 const VkAllocationCallbacks *pAllocator,
1976 VkCommandPool *pCmdPool)
1977 {
1978 TU_FROM_HANDLE(tu_device, device, _device);
1979 struct tu_cmd_pool *pool;
1980
1981 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1982 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1983 if (pool == NULL)
1984 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1985
1986 if (pAllocator)
1987 pool->alloc = *pAllocator;
1988 else
1989 pool->alloc = device->alloc;
1990
1991 list_inithead(&pool->cmd_buffers);
1992 list_inithead(&pool->free_cmd_buffers);
1993
1994 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1995
1996 *pCmdPool = tu_cmd_pool_to_handle(pool);
1997
1998 return VK_SUCCESS;
1999 }
2000
2001 void
2002 tu_DestroyCommandPool(VkDevice _device,
2003 VkCommandPool commandPool,
2004 const VkAllocationCallbacks *pAllocator)
2005 {
2006 TU_FROM_HANDLE(tu_device, device, _device);
2007 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2008
2009 if (!pool)
2010 return;
2011
2012 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2013 &pool->cmd_buffers, pool_link)
2014 {
2015 tu_cmd_buffer_destroy(cmd_buffer);
2016 }
2017
2018 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2019 &pool->free_cmd_buffers, pool_link)
2020 {
2021 tu_cmd_buffer_destroy(cmd_buffer);
2022 }
2023
2024 vk_free2(&device->alloc, pAllocator, pool);
2025 }
2026
2027 VkResult
2028 tu_ResetCommandPool(VkDevice device,
2029 VkCommandPool commandPool,
2030 VkCommandPoolResetFlags flags)
2031 {
2032 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2033 VkResult result;
2034
2035 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2036 pool_link)
2037 {
2038 result = tu_reset_cmd_buffer(cmd_buffer);
2039 if (result != VK_SUCCESS)
2040 return result;
2041 }
2042
2043 return VK_SUCCESS;
2044 }
2045
2046 void
2047 tu_TrimCommandPool(VkDevice device,
2048 VkCommandPool commandPool,
2049 VkCommandPoolTrimFlags flags)
2050 {
2051 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2052
2053 if (!pool)
2054 return;
2055
2056 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2057 &pool->free_cmd_buffers, pool_link)
2058 {
2059 tu_cmd_buffer_destroy(cmd_buffer);
2060 }
2061 }
2062
2063 void
2064 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2065 const VkRenderPassBeginInfo *pRenderPassBegin,
2066 VkSubpassContents contents)
2067 {
2068 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2069 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2070 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2071 VkResult result;
2072
2073 cmd_buffer->state.pass = pass;
2074 cmd_buffer->state.subpass = pass->subpasses;
2075 cmd_buffer->state.framebuffer = framebuffer;
2076
2077 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2078 if (result != VK_SUCCESS)
2079 return;
2080
2081 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2082 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2083 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2084 }
2085
2086 void
2087 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2088 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2089 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2090 {
2091 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2092 pSubpassBeginInfo->contents);
2093 }
2094
2095 void
2096 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2097 {
2098 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2099
2100 tu_cmd_render_tiles(cmd);
2101
2102 cmd->state.subpass++;
2103
2104 tu_cmd_update_tiling_config(cmd, NULL);
2105 tu_cmd_prepare_tile_load_ib(cmd);
2106 tu_cmd_prepare_tile_store_ib(cmd);
2107 }
2108
2109 void
2110 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2111 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2112 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2113 {
2114 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2115 }
2116
2117 struct tu_draw_info
2118 {
2119 /**
2120 * Number of vertices.
2121 */
2122 uint32_t count;
2123
2124 /**
2125 * Index of the first vertex.
2126 */
2127 int32_t vertex_offset;
2128
2129 /**
2130 * First instance id.
2131 */
2132 uint32_t first_instance;
2133
2134 /**
2135 * Number of instances.
2136 */
2137 uint32_t instance_count;
2138
2139 /**
2140 * First index (indexed draws only).
2141 */
2142 uint32_t first_index;
2143
2144 /**
2145 * Whether it's an indexed draw.
2146 */
2147 bool indexed;
2148
2149 /**
2150 * Indirect draw parameters resource.
2151 */
2152 struct tu_buffer *indirect;
2153 uint64_t indirect_offset;
2154 uint32_t stride;
2155
2156 /**
2157 * Draw count parameters resource.
2158 */
2159 struct tu_buffer *count_buffer;
2160 uint64_t count_buffer_offset;
2161 };
2162
2163 enum tu_draw_state_group_id
2164 {
2165 TU_DRAW_STATE_PROGRAM,
2166 TU_DRAW_STATE_PROGRAM_BINNING,
2167 TU_DRAW_STATE_VI,
2168 TU_DRAW_STATE_VI_BINNING,
2169 TU_DRAW_STATE_VP,
2170 TU_DRAW_STATE_RAST,
2171 TU_DRAW_STATE_DS,
2172 TU_DRAW_STATE_BLEND,
2173 TU_DRAW_STATE_VS_CONST,
2174 TU_DRAW_STATE_FS_CONST,
2175 TU_DRAW_STATE_VS_TEX,
2176 TU_DRAW_STATE_FS_TEX,
2177
2178 TU_DRAW_STATE_COUNT,
2179 };
2180
2181 struct tu_draw_state_group
2182 {
2183 enum tu_draw_state_group_id id;
2184 uint32_t enable_mask;
2185 struct tu_cs_entry ib;
2186 };
2187
2188 static struct tu_sampler*
2189 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2190 const struct tu_descriptor_map *map, unsigned i)
2191 {
2192 assert(descriptors_state->valid & (1 << map->set[i]));
2193
2194 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2195 assert(map->binding[i] < set->layout->binding_count);
2196
2197 const struct tu_descriptor_set_binding_layout *layout =
2198 &set->layout->binding[map->binding[i]];
2199
2200 switch (layout->type) {
2201 case VK_DESCRIPTOR_TYPE_SAMPLER:
2202 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2203 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2204 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2205 default:
2206 unreachable("unimplemented descriptor type");
2207 break;
2208 }
2209 }
2210
2211 static uint32_t*
2212 texture_ptr(struct tu_descriptor_state *descriptors_state,
2213 const struct tu_descriptor_map *map, unsigned i)
2214 {
2215 assert(descriptors_state->valid & (1 << map->set[i]));
2216
2217 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2218 assert(map->binding[i] < set->layout->binding_count);
2219
2220 const struct tu_descriptor_set_binding_layout *layout =
2221 &set->layout->binding[map->binding[i]];
2222
2223 switch (layout->type) {
2224 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2225 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2226 return &set->mapped_ptr[layout->offset / 4];
2227 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2228 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2229 return &set->mapped_ptr[layout->offset / 4];
2230 default:
2231 unreachable("unimplemented descriptor type");
2232 break;
2233 }
2234 }
2235
2236 static uint64_t
2237 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2238 const struct tu_descriptor_map *map,
2239 unsigned i)
2240 {
2241 assert(descriptors_state->valid & (1 << map->set[i]));
2242
2243 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2244 assert(map->binding[i] < set->layout->binding_count);
2245
2246 const struct tu_descriptor_set_binding_layout *layout =
2247 &set->layout->binding[map->binding[i]];
2248
2249 switch (layout->type) {
2250 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2251 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2252 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2253 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2254 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2255 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2256 set->mapped_ptr[layout->offset / 4];
2257 default:
2258 unreachable("unimplemented descriptor type");
2259 break;
2260 }
2261 }
2262
2263 static inline uint32_t
2264 tu6_stage2opcode(gl_shader_stage type)
2265 {
2266 switch (type) {
2267 case MESA_SHADER_VERTEX:
2268 case MESA_SHADER_TESS_CTRL:
2269 case MESA_SHADER_TESS_EVAL:
2270 case MESA_SHADER_GEOMETRY:
2271 return CP_LOAD_STATE6_GEOM;
2272 case MESA_SHADER_FRAGMENT:
2273 case MESA_SHADER_COMPUTE:
2274 case MESA_SHADER_KERNEL:
2275 return CP_LOAD_STATE6_FRAG;
2276 default:
2277 unreachable("bad shader type");
2278 }
2279 }
2280
2281 static inline enum a6xx_state_block
2282 tu6_stage2shadersb(gl_shader_stage type)
2283 {
2284 switch (type) {
2285 case MESA_SHADER_VERTEX:
2286 return SB6_VS_SHADER;
2287 case MESA_SHADER_FRAGMENT:
2288 return SB6_FS_SHADER;
2289 case MESA_SHADER_COMPUTE:
2290 case MESA_SHADER_KERNEL:
2291 return SB6_CS_SHADER;
2292 default:
2293 unreachable("bad shader type");
2294 return ~0;
2295 }
2296 }
2297
2298 static void
2299 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2300 struct tu_descriptor_state *descriptors_state,
2301 gl_shader_stage type,
2302 uint32_t *push_constants)
2303 {
2304 const struct tu_program_descriptor_linkage *link =
2305 &pipeline->program.link[type];
2306 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2307
2308 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2309 if (state->range[i].start < state->range[i].end) {
2310 uint32_t size = state->range[i].end - state->range[i].start;
2311 uint32_t offset = state->range[i].start;
2312
2313 /* and even if the start of the const buffer is before
2314 * first_immediate, the end may not be:
2315 */
2316 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2317
2318 if (size == 0)
2319 continue;
2320
2321 /* things should be aligned to vec4: */
2322 debug_assert((state->range[i].offset % 16) == 0);
2323 debug_assert((size % 16) == 0);
2324 debug_assert((offset % 16) == 0);
2325
2326 if (i == 0) {
2327 /* push constants */
2328 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2329 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2330 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2331 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2332 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2333 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2334 tu_cs_emit(cs, 0);
2335 tu_cs_emit(cs, 0);
2336 for (unsigned i = 0; i < size / 4; i++)
2337 tu_cs_emit(cs, push_constants[i + offset / 4]);
2338 continue;
2339 }
2340
2341 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2342
2343 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2344 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2345 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2346 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2347 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2348 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2349 tu_cs_emit_qw(cs, va + offset);
2350 }
2351 }
2352 }
2353
2354 static void
2355 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2356 struct tu_descriptor_state *descriptors_state,
2357 gl_shader_stage type)
2358 {
2359 const struct tu_program_descriptor_linkage *link =
2360 &pipeline->program.link[type];
2361
2362 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2363 uint32_t anum = align(num, 2);
2364 uint32_t i;
2365
2366 if (!num)
2367 return;
2368
2369 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2370 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2371 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2372 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2373 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2374 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2375 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2376 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2377
2378 for (i = 0; i < num; i++)
2379 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2380
2381 for (; i < anum; i++) {
2382 tu_cs_emit(cs, 0xffffffff);
2383 tu_cs_emit(cs, 0xffffffff);
2384 }
2385 }
2386
2387 static struct tu_cs_entry
2388 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2389 const struct tu_pipeline *pipeline,
2390 struct tu_descriptor_state *descriptors_state,
2391 gl_shader_stage type)
2392 {
2393 struct tu_cs cs;
2394 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2395
2396 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2397 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2398
2399 return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2400 }
2401
2402 static struct tu_cs_entry
2403 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2404 const struct tu_pipeline *pipeline,
2405 struct tu_descriptor_state *descriptors_state,
2406 gl_shader_stage type, bool *needs_border)
2407 {
2408 const struct tu_program_descriptor_linkage *link =
2409 &pipeline->program.link[type];
2410
2411 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2412 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2413 if (!size)
2414 return (struct tu_cs_entry) {};
2415
2416 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2417 enum a6xx_state_block sb;
2418
2419 switch (type) {
2420 case MESA_SHADER_VERTEX:
2421 sb = SB6_VS_TEX;
2422 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2423 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2424 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2425 break;
2426 case MESA_SHADER_FRAGMENT:
2427 sb = SB6_FS_TEX;
2428 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2429 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2430 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2431 break;
2432 case MESA_SHADER_COMPUTE:
2433 sb = SB6_CS_TEX;
2434 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2435 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2436 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2437 break;
2438 default:
2439 unreachable("bad state block");
2440 }
2441
2442 struct tu_cs cs;
2443 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2444
2445 for (unsigned i = 0; i < link->texture_map.num; i++) {
2446 uint32_t *ptr = texture_ptr(descriptors_state, &link->texture_map, i);
2447
2448 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2449 tu_cs_emit(&cs, ptr[j]);
2450 }
2451
2452 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2453 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2454
2455 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2456 tu_cs_emit(&cs, sampler->state[j]);
2457
2458 *needs_border |= sampler->needs_border;
2459 }
2460
2461 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2462
2463 uint64_t tex_addr = entry.bo->iova + entry.offset;
2464 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2465
2466 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2467
2468 /* output sampler state: */
2469 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2470 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2471 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2472 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2473 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2474 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2475 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2476
2477 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2478 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2479
2480 /* emit texture state: */
2481 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2482 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2483 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2484 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2485 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2486 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2487 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2488
2489 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2490 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2491
2492 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2493 tu_cs_emit(&cs, link->texture_map.num);
2494
2495 return tu_cs_end_sub_stream(draw_state, &cs);
2496 }
2497
2498 static void
2499 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2500 struct tu_cs *cs)
2501 {
2502 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2503
2504 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2505 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2506 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2507 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2508 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2509
2510 struct tu_cs border_cs;
2511 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2512
2513 /* TODO: actually fill with border color */
2514 for (unsigned i = 0; i < size; i++)
2515 tu_cs_emit(&border_cs, 0);
2516
2517 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2518
2519 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2520 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2521 }
2522
2523 static void
2524 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2525 struct tu_cs *cs,
2526 const struct tu_draw_info *draw)
2527 {
2528 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2529 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2530 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2531 uint32_t draw_state_group_count = 0;
2532
2533 struct tu_descriptor_state *descriptors_state =
2534 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2535
2536 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2537 if (result != VK_SUCCESS) {
2538 cmd->record_result = result;
2539 return;
2540 }
2541
2542 /* TODO lrz */
2543
2544 uint32_t pc_primitive_cntl = 0;
2545 if (pipeline->ia.primitive_restart && draw->indexed)
2546 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2547
2548 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2549 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2550 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2551
2552 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2553 tu_cs_emit(cs, pc_primitive_cntl);
2554
2555 if (cmd->state.dirty &
2556 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2557 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2558 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2559 dynamic->line_width);
2560 }
2561
2562 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2563 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2564 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2565 dynamic->stencil_compare_mask.back);
2566 }
2567
2568 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2569 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2570 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2571 dynamic->stencil_write_mask.back);
2572 }
2573
2574 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2575 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2576 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2577 dynamic->stencil_reference.back);
2578 }
2579
2580 if (cmd->state.dirty &
2581 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2582 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2583 const uint32_t binding = pipeline->vi.bindings[i];
2584 const uint32_t stride = pipeline->vi.strides[i];
2585 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2586 const VkDeviceSize offset = buf->bo_offset +
2587 cmd->state.vb.offsets[binding] +
2588 pipeline->vi.offsets[i];
2589 const VkDeviceSize size =
2590 offset < buf->bo->size ? buf->bo->size - offset : 0;
2591
2592 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2593 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2594 tu_cs_emit(cs, size);
2595 tu_cs_emit(cs, stride);
2596 }
2597 }
2598
2599 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2600 draw_state_groups[draw_state_group_count++] =
2601 (struct tu_draw_state_group) {
2602 .id = TU_DRAW_STATE_PROGRAM,
2603 .enable_mask = 0x6,
2604 .ib = pipeline->program.state_ib,
2605 };
2606 draw_state_groups[draw_state_group_count++] =
2607 (struct tu_draw_state_group) {
2608 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2609 .enable_mask = 0x1,
2610 .ib = pipeline->program.binning_state_ib,
2611 };
2612 draw_state_groups[draw_state_group_count++] =
2613 (struct tu_draw_state_group) {
2614 .id = TU_DRAW_STATE_VI,
2615 .enable_mask = 0x6,
2616 .ib = pipeline->vi.state_ib,
2617 };
2618 draw_state_groups[draw_state_group_count++] =
2619 (struct tu_draw_state_group) {
2620 .id = TU_DRAW_STATE_VI_BINNING,
2621 .enable_mask = 0x1,
2622 .ib = pipeline->vi.binning_state_ib,
2623 };
2624 draw_state_groups[draw_state_group_count++] =
2625 (struct tu_draw_state_group) {
2626 .id = TU_DRAW_STATE_VP,
2627 .enable_mask = 0x7,
2628 .ib = pipeline->vp.state_ib,
2629 };
2630 draw_state_groups[draw_state_group_count++] =
2631 (struct tu_draw_state_group) {
2632 .id = TU_DRAW_STATE_RAST,
2633 .enable_mask = 0x7,
2634 .ib = pipeline->rast.state_ib,
2635 };
2636 draw_state_groups[draw_state_group_count++] =
2637 (struct tu_draw_state_group) {
2638 .id = TU_DRAW_STATE_DS,
2639 .enable_mask = 0x7,
2640 .ib = pipeline->ds.state_ib,
2641 };
2642 draw_state_groups[draw_state_group_count++] =
2643 (struct tu_draw_state_group) {
2644 .id = TU_DRAW_STATE_BLEND,
2645 .enable_mask = 0x7,
2646 .ib = pipeline->blend.state_ib,
2647 };
2648 }
2649
2650 if (cmd->state.dirty &
2651 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2652 bool needs_border = false;
2653
2654 draw_state_groups[draw_state_group_count++] =
2655 (struct tu_draw_state_group) {
2656 .id = TU_DRAW_STATE_VS_CONST,
2657 .enable_mask = 0x7,
2658 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2659 };
2660 draw_state_groups[draw_state_group_count++] =
2661 (struct tu_draw_state_group) {
2662 .id = TU_DRAW_STATE_FS_CONST,
2663 .enable_mask = 0x6,
2664 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2665 };
2666 draw_state_groups[draw_state_group_count++] =
2667 (struct tu_draw_state_group) {
2668 .id = TU_DRAW_STATE_VS_TEX,
2669 .enable_mask = 0x7,
2670 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2671 descriptors_state, MESA_SHADER_VERTEX,
2672 &needs_border)
2673 };
2674 draw_state_groups[draw_state_group_count++] =
2675 (struct tu_draw_state_group) {
2676 .id = TU_DRAW_STATE_FS_TEX,
2677 .enable_mask = 0x6,
2678 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2679 descriptors_state, MESA_SHADER_FRAGMENT,
2680 &needs_border)
2681 };
2682
2683 if (needs_border)
2684 tu6_emit_border_color(cmd, cs);
2685 }
2686
2687 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2688 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2689 const struct tu_draw_state_group *group = &draw_state_groups[i];
2690
2691 uint32_t cp_set_draw_state =
2692 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2693 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2694 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2695 uint64_t iova;
2696 if (group->ib.size) {
2697 iova = group->ib.bo->iova + group->ib.offset;
2698 } else {
2699 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2700 iova = 0;
2701 }
2702
2703 tu_cs_emit(cs, cp_set_draw_state);
2704 tu_cs_emit_qw(cs, iova);
2705 }
2706
2707 tu_cs_sanity_check(cs);
2708
2709 /* track BOs */
2710 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2711 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2712 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2713 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2714 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2715 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2716 }
2717 }
2718 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2719 for (uint32_t i = 0; i < MAX_VBS; i++) {
2720 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2721 if (buf)
2722 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2723 }
2724 }
2725 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2726 unsigned i;
2727 for_each_bit(i, descriptors_state->valid) {
2728 struct tu_descriptor_set *set = descriptors_state->sets[i];
2729 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2730 if (set->descriptors[j]) {
2731 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2732 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2733 }
2734 }
2735 }
2736 cmd->state.dirty = 0;
2737 }
2738
2739 static void
2740 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2741 struct tu_cs *cs,
2742 const struct tu_draw_info *draw)
2743 {
2744
2745 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2746
2747 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2748 tu_cs_emit(cs, draw->vertex_offset);
2749 tu_cs_emit(cs, draw->first_instance);
2750
2751 /* TODO hw binning */
2752 if (draw->indexed) {
2753 const enum a4xx_index_size index_size =
2754 tu6_index_size(cmd->state.index_type);
2755 const uint32_t index_bytes =
2756 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2757 const struct tu_buffer *buf = cmd->state.index_buffer;
2758 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2759 index_bytes * draw->first_index;
2760 const uint32_t size = index_bytes * draw->count;
2761
2762 const uint32_t cp_draw_indx =
2763 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2764 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2765 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2766 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2767
2768 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2769 tu_cs_emit(cs, cp_draw_indx);
2770 tu_cs_emit(cs, draw->instance_count);
2771 tu_cs_emit(cs, draw->count);
2772 tu_cs_emit(cs, 0x0); /* XXX */
2773 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2774 tu_cs_emit(cs, size);
2775 } else {
2776 const uint32_t cp_draw_indx =
2777 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2778 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2779 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2780
2781 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2782 tu_cs_emit(cs, cp_draw_indx);
2783 tu_cs_emit(cs, draw->instance_count);
2784 tu_cs_emit(cs, draw->count);
2785 }
2786 }
2787
2788 static void
2789 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2790 {
2791 struct tu_cs *cs = &cmd->draw_cs;
2792
2793 tu6_bind_draw_states(cmd, cs, draw);
2794
2795 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2796 if (result != VK_SUCCESS) {
2797 cmd->record_result = result;
2798 return;
2799 }
2800
2801 if (draw->indirect) {
2802 tu_finishme("indirect draw");
2803 return;
2804 }
2805
2806 /* TODO tu6_emit_marker should pick different regs depending on cs */
2807 tu6_emit_marker(cmd, cs);
2808 tu6_emit_draw_direct(cmd, cs, draw);
2809 tu6_emit_marker(cmd, cs);
2810
2811 cmd->wait_for_idle = true;
2812
2813 tu_cs_sanity_check(cs);
2814 }
2815
2816 void
2817 tu_CmdDraw(VkCommandBuffer commandBuffer,
2818 uint32_t vertexCount,
2819 uint32_t instanceCount,
2820 uint32_t firstVertex,
2821 uint32_t firstInstance)
2822 {
2823 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2824 struct tu_draw_info info = {};
2825
2826 info.count = vertexCount;
2827 info.instance_count = instanceCount;
2828 info.first_instance = firstInstance;
2829 info.vertex_offset = firstVertex;
2830
2831 tu_draw(cmd_buffer, &info);
2832 }
2833
2834 void
2835 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2836 uint32_t indexCount,
2837 uint32_t instanceCount,
2838 uint32_t firstIndex,
2839 int32_t vertexOffset,
2840 uint32_t firstInstance)
2841 {
2842 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2843 struct tu_draw_info info = {};
2844
2845 info.indexed = true;
2846 info.count = indexCount;
2847 info.instance_count = instanceCount;
2848 info.first_index = firstIndex;
2849 info.vertex_offset = vertexOffset;
2850 info.first_instance = firstInstance;
2851
2852 tu_draw(cmd_buffer, &info);
2853 }
2854
2855 void
2856 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2857 VkBuffer _buffer,
2858 VkDeviceSize offset,
2859 uint32_t drawCount,
2860 uint32_t stride)
2861 {
2862 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2863 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2864 struct tu_draw_info info = {};
2865
2866 info.count = drawCount;
2867 info.indirect = buffer;
2868 info.indirect_offset = offset;
2869 info.stride = stride;
2870
2871 tu_draw(cmd_buffer, &info);
2872 }
2873
2874 void
2875 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2876 VkBuffer _buffer,
2877 VkDeviceSize offset,
2878 uint32_t drawCount,
2879 uint32_t stride)
2880 {
2881 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2882 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2883 struct tu_draw_info info = {};
2884
2885 info.indexed = true;
2886 info.count = drawCount;
2887 info.indirect = buffer;
2888 info.indirect_offset = offset;
2889 info.stride = stride;
2890
2891 tu_draw(cmd_buffer, &info);
2892 }
2893
2894 struct tu_dispatch_info
2895 {
2896 /**
2897 * Determine the layout of the grid (in block units) to be used.
2898 */
2899 uint32_t blocks[3];
2900
2901 /**
2902 * A starting offset for the grid. If unaligned is set, the offset
2903 * must still be aligned.
2904 */
2905 uint32_t offsets[3];
2906 /**
2907 * Whether it's an unaligned compute dispatch.
2908 */
2909 bool unaligned;
2910
2911 /**
2912 * Indirect compute parameters resource.
2913 */
2914 struct tu_buffer *indirect;
2915 uint64_t indirect_offset;
2916 };
2917
2918 static void
2919 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2920 const struct tu_dispatch_info *info)
2921 {
2922 }
2923
2924 void
2925 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2926 uint32_t base_x,
2927 uint32_t base_y,
2928 uint32_t base_z,
2929 uint32_t x,
2930 uint32_t y,
2931 uint32_t z)
2932 {
2933 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2934 struct tu_dispatch_info info = {};
2935
2936 info.blocks[0] = x;
2937 info.blocks[1] = y;
2938 info.blocks[2] = z;
2939
2940 info.offsets[0] = base_x;
2941 info.offsets[1] = base_y;
2942 info.offsets[2] = base_z;
2943 tu_dispatch(cmd_buffer, &info);
2944 }
2945
2946 void
2947 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2948 uint32_t x,
2949 uint32_t y,
2950 uint32_t z)
2951 {
2952 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2953 }
2954
2955 void
2956 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2957 VkBuffer _buffer,
2958 VkDeviceSize offset)
2959 {
2960 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2961 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2962 struct tu_dispatch_info info = {};
2963
2964 info.indirect = buffer;
2965 info.indirect_offset = offset;
2966
2967 tu_dispatch(cmd_buffer, &info);
2968 }
2969
2970 void
2971 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2972 {
2973 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2974
2975 tu_cs_end(&cmd_buffer->draw_cs);
2976
2977 tu_cmd_render_tiles(cmd_buffer);
2978
2979 /* discard draw_cs entries now that the tiles are rendered */
2980 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2981 tu_cs_begin(&cmd_buffer->draw_cs);
2982
2983 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2984 cmd_buffer->state.attachments = NULL;
2985
2986 cmd_buffer->state.pass = NULL;
2987 cmd_buffer->state.subpass = NULL;
2988 cmd_buffer->state.framebuffer = NULL;
2989 }
2990
2991 void
2992 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
2993 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2994 {
2995 tu_CmdEndRenderPass(commandBuffer);
2996 }
2997
2998 struct tu_barrier_info
2999 {
3000 uint32_t eventCount;
3001 const VkEvent *pEvents;
3002 VkPipelineStageFlags srcStageMask;
3003 };
3004
3005 static void
3006 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3007 uint32_t memoryBarrierCount,
3008 const VkMemoryBarrier *pMemoryBarriers,
3009 uint32_t bufferMemoryBarrierCount,
3010 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3011 uint32_t imageMemoryBarrierCount,
3012 const VkImageMemoryBarrier *pImageMemoryBarriers,
3013 const struct tu_barrier_info *info)
3014 {
3015 }
3016
3017 void
3018 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3019 VkPipelineStageFlags srcStageMask,
3020 VkPipelineStageFlags destStageMask,
3021 VkBool32 byRegion,
3022 uint32_t memoryBarrierCount,
3023 const VkMemoryBarrier *pMemoryBarriers,
3024 uint32_t bufferMemoryBarrierCount,
3025 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3026 uint32_t imageMemoryBarrierCount,
3027 const VkImageMemoryBarrier *pImageMemoryBarriers)
3028 {
3029 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3030 struct tu_barrier_info info;
3031
3032 info.eventCount = 0;
3033 info.pEvents = NULL;
3034 info.srcStageMask = srcStageMask;
3035
3036 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3037 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3038 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3039 }
3040
3041 static void
3042 write_event(struct tu_cmd_buffer *cmd_buffer,
3043 struct tu_event *event,
3044 VkPipelineStageFlags stageMask,
3045 unsigned value)
3046 {
3047 }
3048
3049 void
3050 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3051 VkEvent _event,
3052 VkPipelineStageFlags stageMask)
3053 {
3054 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3055 TU_FROM_HANDLE(tu_event, event, _event);
3056
3057 write_event(cmd_buffer, event, stageMask, 1);
3058 }
3059
3060 void
3061 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3062 VkEvent _event,
3063 VkPipelineStageFlags stageMask)
3064 {
3065 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3066 TU_FROM_HANDLE(tu_event, event, _event);
3067
3068 write_event(cmd_buffer, event, stageMask, 0);
3069 }
3070
3071 void
3072 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3073 uint32_t eventCount,
3074 const VkEvent *pEvents,
3075 VkPipelineStageFlags srcStageMask,
3076 VkPipelineStageFlags dstStageMask,
3077 uint32_t memoryBarrierCount,
3078 const VkMemoryBarrier *pMemoryBarriers,
3079 uint32_t bufferMemoryBarrierCount,
3080 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3081 uint32_t imageMemoryBarrierCount,
3082 const VkImageMemoryBarrier *pImageMemoryBarriers)
3083 {
3084 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3085 struct tu_barrier_info info;
3086
3087 info.eventCount = eventCount;
3088 info.pEvents = pEvents;
3089 info.srcStageMask = 0;
3090
3091 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3092 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3093 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3094 }
3095
3096 void
3097 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3098 {
3099 /* No-op */
3100 }