src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36 #include "tu_blit.h"
  37
  38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  39
  40 void
  41 tu_bo_list_init(struct tu_bo_list *list)
  42 {
  43    list->count = list->capacity = 0;
  44    list->bo_infos = NULL;
  45 }
  46
  47 void
  48 tu_bo_list_destroy(struct tu_bo_list *list)
  49 {
  50    free(list->bo_infos);
  51 }
  52
  53 void
  54 tu_bo_list_reset(struct tu_bo_list *list)
  55 {
  56    list->count = 0;
  57 }
  58
  59 /**
  60  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  61  */
  62 static uint32_t
  63 tu_bo_list_add_info(struct tu_bo_list *list,
  64                     const struct drm_msm_gem_submit_bo *bo_info)
  65 {
  66    assert(bo_info->handle != 0);
  67
  68    for (uint32_t i = 0; i < list->count; ++i) {
  69       if (list->bo_infos[i].handle == bo_info->handle) {
  70          assert(list->bo_infos[i].presumed == bo_info->presumed);
  71          list->bo_infos[i].flags |= bo_info->flags;
  72          return i;
  73       }
  74    }
  75
  76    /* grow list->bo_infos if needed */
  77    if (list->count == list->capacity) {
  78       uint32_t new_capacity = MAX2(2 * list->count, 16);
  79       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  80          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  81       if (!new_bo_infos)
  82          return TU_BO_LIST_FAILED;
  83       list->bo_infos = new_bo_infos;
  84       list->capacity = new_capacity;
  85    }
  86
  87    list->bo_infos[list->count] = *bo_info;
  88    return list->count++;
  89 }
  90
  91 uint32_t
  92 tu_bo_list_add(struct tu_bo_list *list,
  93                const struct tu_bo *bo,
  94                uint32_t flags)
  95 {
  96    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  97                                        .flags = flags,
  98                                        .handle = bo->gem_handle,
  99                                        .presumed = bo->iova,
 100                                     });
 101 }
 102
 103 VkResult
 104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 105 {
 106    for (uint32_t i = 0; i < other->count; i++) {
 107       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 108          return VK_ERROR_OUT_OF_HOST_MEMORY;
 109    }
 110
 111    return VK_SUCCESS;
 112 }
 113
 114 static bool
 115 is_linear_mipmapped(const struct tu_image_view *iview)
 116 {
 117    return iview->image->layout.tile_mode == TILE6_LINEAR &&
 118           iview->base_mip != iview->image->level_count - 1;
 119 }
 120
 121 static bool
 122 force_sysmem(const struct tu_cmd_buffer *cmd,
 123              const struct VkRect2D *render_area)
 124 {
 125    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 126    const struct tu_physical_device *device = cmd->device->physical_device;
 127    bool has_linear_mipmapped_store = false;
 128    const struct tu_render_pass *pass = cmd->state.pass;
 129
 130    /* Iterate over all the places we call tu6_emit_store_attachment() */
 131    for (unsigned i = 0; i < pass->subpass_count; i++) {
 132       const struct tu_subpass *subpass = &pass->subpasses[i];
 133       if (subpass->resolve_attachments) {
 134          for (unsigned i = 0; i < subpass->color_count; i++) {
 135             uint32_t a = subpass->resolve_attachments[i].attachment;
 136             if (a != VK_ATTACHMENT_UNUSED &&
 137                 cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 138                const struct tu_image_view *iview = fb->attachments[a].attachment;
 139                if (is_linear_mipmapped(iview)) {
 140                   has_linear_mipmapped_store = true;
 141                   break;
 142                }
 143             }
 144          }
 145       }
 146    }
 147
 148    for (unsigned i = 0; i < pass->attachment_count; i++) {
 149       if (pass->attachments[i].gmem_offset >= 0 &&
 150           cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 151          const struct tu_image_view *iview = fb->attachments[i].attachment;
 152          if (is_linear_mipmapped(iview)) {
 153             has_linear_mipmapped_store = true;
 154             break;
 155          }
 156       }
 157    }
 158
 159    /* Linear textures cannot have any padding between mipmap levels and their
 160     * height isn't padded, while at the same time the GMEM->MEM resolve does
 161     * not have per-pixel granularity, so if the image height isn't aligned to
 162     * the resolve granularity and the render area is tall enough, we may wind
 163     * up writing past the bottom of the image into the next miplevel or even
 164     * past the end of the image. For the last miplevel, the layout code should
 165     * insert enough padding so that the overdraw writes to the padding.  To
 166     * work around this, we force-enable sysmem rendering.
 167     */
 168    const uint32_t y2 = render_area->offset.y + render_area->extent.height;
 169    const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
 170
 171    return has_linear_mipmapped_store && aligned_y2 > fb->height;
 172 }
 173
 174 static void
 175 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 176                                     const struct tu_device *dev,
 177                                     uint32_t pixels)
 178 {
 179    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 180    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 181    const uint32_t max_tile_width = 1024; /* A6xx */
 182
 183    tiling->tile0.offset = (VkOffset2D) {
 184       .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
 185       .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
 186    };
 187
 188    const uint32_t ra_width =
 189       tiling->render_area.extent.width +
 190       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 191    const uint32_t ra_height =
 192       tiling->render_area.extent.height +
 193       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 194
 195    /* start from 1 tile */
 196    tiling->tile_count = (VkExtent2D) {
 197       .width = 1,
 198       .height = 1,
 199    };
 200    tiling->tile0.extent = (VkExtent2D) {
 201       .width = align(ra_width, tile_align_w),
 202       .height = align(ra_height, tile_align_h),
 203    };
 204
 205    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 206       /* start with 2x2 tiles */
 207       tiling->tile_count.width = 2;
 208       tiling->tile_count.height = 2;
 209       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 210       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 211    }
 212
 213    /* do not exceed max tile width */
 214    while (tiling->tile0.extent.width > max_tile_width) {
 215       tiling->tile_count.width++;
 216       tiling->tile0.extent.width =
 217          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 218    }
 219
 220    /* do not exceed gmem size */
 221    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 222       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 223          tiling->tile_count.width++;
 224          tiling->tile0.extent.width =
 225             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 226       } else {
 227          /* if this assert fails then layout is impossible.. */
 228          assert(tiling->tile0.extent.height > tile_align_h);
 229          tiling->tile_count.height++;
 230          tiling->tile0.extent.height =
 231             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 232       }
 233    }
 234 }
 235
 236 static void
 237 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 238                                     const struct tu_device *dev)
 239 {
 240    const uint32_t max_pipe_count = 32; /* A6xx */
 241
 242    /* start from 1 tile per pipe */
 243    tiling->pipe0 = (VkExtent2D) {
 244       .width = 1,
 245       .height = 1,
 246    };
 247    tiling->pipe_count = tiling->tile_count;
 248
 249    /* do not exceed max pipe count vertically */
 250    while (tiling->pipe_count.height > max_pipe_count) {
 251       tiling->pipe0.height += 2;
 252       tiling->pipe_count.height =
 253          (tiling->tile_count.height + tiling->pipe0.height - 1) /
 254          tiling->pipe0.height;
 255    }
 256
 257    /* do not exceed max pipe count */
 258    while (tiling->pipe_count.width * tiling->pipe_count.height >
 259           max_pipe_count) {
 260       tiling->pipe0.width += 1;
 261       tiling->pipe_count.width =
 262          (tiling->tile_count.width + tiling->pipe0.width - 1) /
 263          tiling->pipe0.width;
 264    }
 265 }
 266
 267 static void
 268 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 269                               const struct tu_device *dev)
 270 {
 271    const uint32_t max_pipe_count = 32; /* A6xx */
 272    const uint32_t used_pipe_count =
 273       tiling->pipe_count.width * tiling->pipe_count.height;
 274    const VkExtent2D last_pipe = {
 275       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 276       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 277    };
 278
 279    assert(used_pipe_count <= max_pipe_count);
 280    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 281
 282    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 283       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 284          const uint32_t pipe_x = tiling->pipe0.width * x;
 285          const uint32_t pipe_y = tiling->pipe0.height * y;
 286          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 287                                     ? last_pipe.width
 288                                     : tiling->pipe0.width;
 289          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 290                                     ? last_pipe.height
 291                                     : tiling->pipe0.height;
 292          const uint32_t n = tiling->pipe_count.width * y + x;
 293
 294          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 295                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 296                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 297                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 298          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 299       }
 300    }
 301
 302    memset(tiling->pipe_config + used_pipe_count, 0,
 303           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 304 }
 305
 306 static void
 307 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 308                           const struct tu_device *dev,
 309                           uint32_t tx,
 310                           uint32_t ty,
 311                           struct tu_tile *tile)
 312 {
 313    /* find the pipe and the slot for tile (tx, ty) */
 314    const uint32_t px = tx / tiling->pipe0.width;
 315    const uint32_t py = ty / tiling->pipe0.height;
 316    const uint32_t sx = tx - tiling->pipe0.width * px;
 317    const uint32_t sy = ty - tiling->pipe0.height * py;
 318
 319    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 320    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 321    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 322
 323    /* convert to 1D indices */
 324    tile->pipe = tiling->pipe_count.width * py + px;
 325    tile->slot = tiling->pipe0.width * sy + sx;
 326
 327    /* get the blit area for the tile */
 328    tile->begin = (VkOffset2D) {
 329       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 330       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 331    };
 332    tile->end.x =
 333       (tx == tiling->tile_count.width - 1)
 334          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 335          : tile->begin.x + tiling->tile0.extent.width;
 336    tile->end.y =
 337       (ty == tiling->tile_count.height - 1)
 338          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 339          : tile->begin.y + tiling->tile0.extent.height;
 340 }
 341
 342 enum a3xx_msaa_samples
 343 tu_msaa_samples(uint32_t samples)
 344 {
 345    switch (samples) {
 346    case 1:
 347       return MSAA_ONE;
 348    case 2:
 349       return MSAA_TWO;
 350    case 4:
 351       return MSAA_FOUR;
 352    case 8:
 353       return MSAA_EIGHT;
 354    default:
 355       assert(!"invalid sample count");
 356       return MSAA_ONE;
 357    }
 358 }
 359
 360 static enum a4xx_index_size
 361 tu6_index_size(VkIndexType type)
 362 {
 363    switch (type) {
 364    case VK_INDEX_TYPE_UINT16:
 365       return INDEX4_SIZE_16_BIT;
 366    case VK_INDEX_TYPE_UINT32:
 367       return INDEX4_SIZE_32_BIT;
 368    default:
 369       unreachable("invalid VkIndexType");
 370       return INDEX4_SIZE_8_BIT;
 371    }
 372 }
 373
 374 unsigned
 375 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 376                      struct tu_cs *cs,
 377                      enum vgt_event_type event,
 378                      bool need_seqno)
 379 {
 380    unsigned seqno = 0;
 381
 382    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 383    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 384    if (need_seqno) {
 385       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 386       seqno = ++cmd->scratch_seqno;
 387       tu_cs_emit(cs, seqno);
 388    }
 389
 390    return seqno;
 391 }
 392
 393 static void
 394 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 395 {
 396    tu6_emit_event_write(cmd, cs, 0x31, false);
 397 }
 398
 399 static void
 400 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 401 {
 402    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 403 }
 404
 405 static void
 406 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 407 {
 408    if (cmd->wait_for_idle) {
 409       tu_cs_emit_wfi(cs);
 410       cmd->wait_for_idle = false;
 411    }
 412 }
 413
 414 #define tu_image_view_ubwc_pitches(iview)                                \
 415    .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip),          \
 416    .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
 417
 418 static void
 419 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 420             const struct tu_subpass *subpass,
 421             struct tu_cs *cs)
 422 {
 423    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 424
 425    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 426    if (a == VK_ATTACHMENT_UNUSED) {
 427       tu_cs_emit_regs(cs,
 428                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 429                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 430                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 431                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 432                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 433
 434       tu_cs_emit_regs(cs,
 435                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 436
 437       tu_cs_emit_regs(cs,
 438                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 439                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 440                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 441
 442       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 443
 444       return;
 445    }
 446
 447    const struct tu_image_view *iview = fb->attachments[a].attachment;
 448    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 449
 450    tu_cs_emit_regs(cs,
 451                    A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
 452                    A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 453                    A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
 454                    A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
 455                    A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
 456
 457    tu_cs_emit_regs(cs,
 458                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 459
 460    tu_cs_emit_regs(cs,
 461                    A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
 462                    A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
 463
 464    tu_cs_emit_regs(cs,
 465                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 466                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 467                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 468
 469    tu_cs_emit_regs(cs,
 470                    A6XX_RB_STENCIL_INFO(0));
 471
 472    /* enable zs? */
 473 }
 474
 475 static void
 476 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 477              const struct tu_subpass *subpass,
 478              struct tu_cs *cs)
 479 {
 480    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 481    unsigned char mrt_comp[MAX_RTS] = { 0 };
 482    unsigned srgb_cntl = 0;
 483
 484    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 485       uint32_t a = subpass->color_attachments[i].attachment;
 486       if (a == VK_ATTACHMENT_UNUSED)
 487          continue;
 488
 489       const struct tu_image_view *iview = fb->attachments[a].attachment;
 490       const enum a6xx_tile_mode tile_mode =
 491          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 492
 493       mrt_comp[i] = 0xf;
 494
 495       if (vk_format_is_srgb(iview->vk_format))
 496          srgb_cntl |= (1 << i);
 497
 498       const struct tu_native_format format =
 499          tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 500
 501       tu_cs_emit_regs(cs,
 502                       A6XX_RB_MRT_BUF_INFO(i,
 503                                            .color_tile_mode = tile_mode,
 504                                            .color_format = format.fmt,
 505                                            .color_swap = format.swap),
 506                       A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
 507                       A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
 508                       A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
 509                       A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
 510
 511       tu_cs_emit_regs(cs,
 512                       A6XX_SP_FS_MRT_REG(i,
 513                                          .color_format = format.fmt,
 514                                          .color_sint = vk_format_is_sint(iview->vk_format),
 515                                          .color_uint = vk_format_is_uint(iview->vk_format)));
 516
 517       tu_cs_emit_regs(cs,
 518                       A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
 519                       A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
 520    }
 521
 522    tu_cs_emit_regs(cs,
 523                    A6XX_RB_SRGB_CNTL(srgb_cntl));
 524
 525    tu_cs_emit_regs(cs,
 526                    A6XX_SP_SRGB_CNTL(srgb_cntl));
 527
 528    tu_cs_emit_regs(cs,
 529                    A6XX_RB_RENDER_COMPONENTS(
 530                       .rt0 = mrt_comp[0],
 531                       .rt1 = mrt_comp[1],
 532                       .rt2 = mrt_comp[2],
 533                       .rt3 = mrt_comp[3],
 534                       .rt4 = mrt_comp[4],
 535                       .rt5 = mrt_comp[5],
 536                       .rt6 = mrt_comp[6],
 537                       .rt7 = mrt_comp[7]));
 538
 539    tu_cs_emit_regs(cs,
 540                    A6XX_SP_FS_RENDER_COMPONENTS(
 541                       .rt0 = mrt_comp[0],
 542                       .rt1 = mrt_comp[1],
 543                       .rt2 = mrt_comp[2],
 544                       .rt3 = mrt_comp[3],
 545                       .rt4 = mrt_comp[4],
 546                       .rt5 = mrt_comp[5],
 547                       .rt6 = mrt_comp[6],
 548                       .rt7 = mrt_comp[7]));
 549 }
 550
 551 static void
 552 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
 553               const struct tu_subpass *subpass,
 554               struct tu_cs *cs)
 555 {
 556    const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
 557    bool msaa_disable = samples == MSAA_ONE;
 558
 559    tu_cs_emit_regs(cs,
 560                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 561                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 562                                              .msaa_disable = msaa_disable));
 563
 564    tu_cs_emit_regs(cs,
 565                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 566                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 567                                             .msaa_disable = msaa_disable));
 568
 569    tu_cs_emit_regs(cs,
 570                    A6XX_RB_RAS_MSAA_CNTL(samples),
 571                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 572                                           .msaa_disable = msaa_disable));
 573
 574    tu_cs_emit_regs(cs,
 575                    A6XX_RB_MSAA_CNTL(samples));
 576 }
 577
 578 static void
 579 tu6_emit_bin_size(struct tu_cs *cs,
 580                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 581 {
 582    tu_cs_emit_regs(cs,
 583                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 584                                          .binh = bin_h,
 585                                          .dword = flags));
 586
 587    tu_cs_emit_regs(cs,
 588                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 589                                        .binh = bin_h,
 590                                        .dword = flags));
 591
 592    /* no flag for RB_BIN_CONTROL2... */
 593    tu_cs_emit_regs(cs,
 594                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 595                                         .binh = bin_h));
 596 }
 597
 598 static void
 599 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 600                      const struct tu_subpass *subpass,
 601                      struct tu_cs *cs,
 602                      bool binning)
 603 {
 604    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 605    uint32_t cntl = 0;
 606    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 607    if (binning) {
 608       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 609    } else {
 610       uint32_t mrts_ubwc_enable = 0;
 611       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 612          uint32_t a = subpass->color_attachments[i].attachment;
 613          if (a == VK_ATTACHMENT_UNUSED)
 614             continue;
 615
 616          const struct tu_image_view *iview = fb->attachments[a].attachment;
 617          if (iview->image->layout.ubwc_layer_size != 0)
 618             mrts_ubwc_enable |= 1 << i;
 619       }
 620
 621       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 622
 623       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 624       if (a != VK_ATTACHMENT_UNUSED) {
 625          const struct tu_image_view *iview = fb->attachments[a].attachment;
 626          if (iview->image->layout.ubwc_layer_size != 0)
 627             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 628       }
 629
 630       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 631        * in order to set it correctly for the different subpasses. However,
 632        * that means the packets we're emitting also happen during binning. So
 633        * we need to guard the write on !BINNING at CP execution time.
 634        */
 635       tu_cs_reserve(cs, 3 + 4);
 636       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 637       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 638                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 639       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 640    }
 641
 642    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 643    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 644    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 645    tu_cs_emit(cs, cntl);
 646 }
 647
 648 static void
 649 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 650 {
 651    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 652    uint32_t x1 = render_area->offset.x;
 653    uint32_t y1 = render_area->offset.y;
 654    uint32_t x2 = x1 + render_area->extent.width - 1;
 655    uint32_t y2 = y1 + render_area->extent.height - 1;
 656
 657    /* TODO: alignment requirement seems to be less than tile_align_w/h */
 658    if (align) {
 659       x1 = x1 & ~cmd->device->physical_device->tile_align_w;
 660       y1 = y1 & ~cmd->device->physical_device->tile_align_h;
 661       x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
 662       y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
 663    }
 664
 665    tu_cs_emit_regs(cs,
 666                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 667                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 668 }
 669
 670 static void
 671 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 672                    struct tu_cs *cs,
 673                    const struct tu_image_view *iview,
 674                    uint32_t gmem_offset,
 675                    bool resolve)
 676 {
 677    tu_cs_emit_regs(cs,
 678                    A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
 679
 680    const struct tu_native_format format =
 681       tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
 682
 683    enum a6xx_tile_mode tile_mode =
 684       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 685    tu_cs_emit_regs(cs,
 686                    A6XX_RB_BLIT_DST_INFO(
 687                       .tile_mode = tile_mode,
 688                       .samples = tu_msaa_samples(iview->image->samples),
 689                       .color_format = format.fmt,
 690                       .color_swap = format.swap,
 691                       .flags = iview->image->layout.ubwc_layer_size != 0),
 692                    A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
 693                    A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 694                    A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
 695
 696    if (iview->image->layout.ubwc_layer_size) {
 697       tu_cs_emit_regs(cs,
 698                       A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
 699                       A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
 700    }
 701
 702    tu_cs_emit_regs(cs,
 703                    A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
 704 }
 705
 706 static void
 707 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 708 {
 709    tu6_emit_event_write(cmd, cs, BLIT, false);
 710 }
 711
 712 static void
 713 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 714                         struct tu_cs *cs,
 715                         uint32_t x1,
 716                         uint32_t y1,
 717                         uint32_t x2,
 718                         uint32_t y2)
 719 {
 720    tu_cs_emit_regs(cs,
 721                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 722                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 723
 724    tu_cs_emit_regs(cs,
 725                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 726                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 727 }
 728
 729 static void
 730 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 731                        struct tu_cs *cs,
 732                        uint32_t x1,
 733                        uint32_t y1)
 734 {
 735    tu_cs_emit_regs(cs,
 736                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 737
 738    tu_cs_emit_regs(cs,
 739                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 740
 741    tu_cs_emit_regs(cs,
 742                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 743
 744    tu_cs_emit_regs(cs,
 745                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 746 }
 747
 748 static bool
 749 use_hw_binning(struct tu_cmd_buffer *cmd)
 750 {
 751    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 752
 753    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 754       return false;
 755
 756    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 757       return true;
 758
 759    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 760 }
 761
 762 static bool
 763 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 764 {
 765    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 766       return true;
 767
 768    return cmd->state.tiling_config.force_sysmem;
 769 }
 770
 771 static void
 772 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 773                      struct tu_cs *cs,
 774                      const struct tu_tile *tile)
 775 {
 776    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 777    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 778
 779    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 780    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 781
 782    const uint32_t x1 = tile->begin.x;
 783    const uint32_t y1 = tile->begin.y;
 784    const uint32_t x2 = tile->end.x - 1;
 785    const uint32_t y2 = tile->end.y - 1;
 786    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 787    tu6_emit_window_offset(cmd, cs, x1, y1);
 788
 789    tu_cs_emit_regs(cs,
 790                    A6XX_VPC_SO_OVERRIDE(.so_disable = true));
 791
 792    if (use_hw_binning(cmd)) {
 793       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 794
 795       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 796       tu_cs_emit(cs, 0x0);
 797
 798       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 799       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 800                      A6XX_CP_REG_TEST_0_BIT(0) |
 801                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 802
 803       tu_cs_reserve(cs, 3 + 11);
 804       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 805       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 806       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 807
 808       /* if (no overflow) */ {
 809          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 810          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 811                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 812          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 813          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 814          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 815
 816          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 817          tu_cs_emit(cs, 0x0);
 818
 819          /* use a NOP packet to skip over the 'else' side: */
 820          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 821       } /* else */ {
 822          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 823          tu_cs_emit(cs, 0x1);
 824       }
 825
 826       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 827       tu_cs_emit(cs, 0x0);
 828
 829       tu_cs_emit_regs(cs,
 830                       A6XX_RB_UNKNOWN_8804(0));
 831
 832       tu_cs_emit_regs(cs,
 833                       A6XX_SP_TP_UNKNOWN_B304(0));
 834
 835       tu_cs_emit_regs(cs,
 836                       A6XX_GRAS_UNKNOWN_80A4(0));
 837    } else {
 838       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 839       tu_cs_emit(cs, 0x1);
 840
 841       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 842       tu_cs_emit(cs, 0x0);
 843    }
 844 }
 845
 846 static void
 847 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
 848 {
 849    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 850    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 851    const struct tu_image_view *iview = fb->attachments[a].attachment;
 852    const struct tu_render_pass_attachment *attachment =
 853       &cmd->state.pass->attachments[a];
 854
 855    if (attachment->gmem_offset < 0)
 856       return;
 857
 858    const uint32_t x1 = tiling->render_area.offset.x;
 859    const uint32_t y1 = tiling->render_area.offset.y;
 860    const uint32_t x2 = x1 + tiling->render_area.extent.width;
 861    const uint32_t y2 = y1 + tiling->render_area.extent.height;
 862    const uint32_t tile_x2 =
 863       tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
 864    const uint32_t tile_y2 =
 865       tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
 866    bool need_load =
 867       x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
 868       y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
 869
 870    if (need_load)
 871       tu_finishme("improve handling of unaligned render area");
 872
 873    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 874       need_load = true;
 875
 876    if (vk_format_has_stencil(iview->vk_format) &&
 877        attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 878       need_load = true;
 879
 880    if (need_load) {
 881       tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
 882       tu6_emit_blit(cmd, cs);
 883    }
 884 }
 885
 886 static void
 887 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 888                           uint32_t a,
 889                           const VkRenderPassBeginInfo *info)
 890 {
 891    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 892    const struct tu_image_view *iview = fb->attachments[a].attachment;
 893    const struct tu_render_pass_attachment *attachment =
 894       &cmd->state.pass->attachments[a];
 895    unsigned clear_mask = 0;
 896
 897    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
 898    if (attachment->gmem_offset < 0)
 899       return;
 900
 901    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 902       clear_mask = 0xf;
 903
 904    if (vk_format_has_stencil(iview->vk_format)) {
 905       clear_mask &= 0x1;
 906       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 907          clear_mask |= 0x2;
 908    }
 909    if (!clear_mask)
 910       return;
 911
 912    tu_clear_gmem_attachment(cmd, cs, a, clear_mask,
 913                             &info->pClearValues[a]);
 914 }
 915
 916 static void
 917 tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
 918                          struct tu_cs *cs,
 919                          uint32_t a,
 920                          uint32_t gmem_a,
 921                          bool resolve)
 922 {
 923    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
 924
 925    tu6_emit_blit_info(cmd, cs,
 926                       cmd->state.framebuffer->attachments[a].attachment,
 927                       cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
 928    tu6_emit_blit(cmd, cs);
 929
 930    tu_cond_exec_end(cs);
 931 }
 932
 933 static void
 934 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 935                         struct tu_cs *cs,
 936                         uint32_t a,
 937                         uint32_t gmem_a)
 938 {
 939    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 940    const struct tu_image_view *dst = fb->attachments[a].attachment;
 941    const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 942
 943    tu_blit(cmd, cs, &(struct tu_blit) {
 944       .dst = sysmem_attachment_surf(dst, dst->base_layer,
 945                                     &cmd->state.tiling_config.render_area),
 946       .src = sysmem_attachment_surf(src, src->base_layer,
 947                                     &cmd->state.tiling_config.render_area),
 948       .layers = fb->layers,
 949    });
 950 }
 951
 952
 953 /* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
 954 static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
 955                              struct tu_cs *cs,
 956                              uint32_t a,
 957                              uint32_t gmem_a)
 958 {
 959    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 960       return;
 961
 962    tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
 963
 964    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
 965    tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
 966    tu_cond_exec_end(cs);
 967 }
 968
 969 static void
 970 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
 971                           struct tu_cs *cs,
 972                           uint32_t a,
 973                           uint32_t gmem_a)
 974 {
 975    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 976       return;
 977
 978    tu6_emit_blit_info(cmd, cs,
 979                       cmd->state.framebuffer->attachments[a].attachment,
 980                       cmd->state.pass->attachments[gmem_a].gmem_offset, true);
 981    tu6_emit_blit(cmd, cs);
 982 }
 983
 984 static void
 985 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 986 {
 987    const struct tu_render_pass *pass = cmd->state.pass;
 988    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 989
 990    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 991    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 992                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 993                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 994    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 995    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 996
 997    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 998    tu_cs_emit(cs, 0x0);
 999
1000    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1001    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1002
1003    tu6_emit_blit_scissor(cmd, cs, true);
1004
1005    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1006       if (pass->attachments[a].gmem_offset >= 0)
1007          tu6_emit_store_attachment(cmd, cs, a, a);
1008    }
1009
1010    if (subpass->resolve_attachments) {
1011       for (unsigned i = 0; i < subpass->color_count; i++) {
1012          uint32_t a = subpass->resolve_attachments[i].attachment;
1013          if (a != VK_ATTACHMENT_UNUSED)
1014             tu6_emit_store_attachment(cmd, cs, a,
1015                                       subpass->color_attachments[i].attachment);
1016       }
1017    }
1018 }
1019
1020 static void
1021 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
1022 {
1023    tu_cs_emit_regs(cs,
1024                    A6XX_PC_RESTART_INDEX(restart_index));
1025 }
1026
1027 static void
1028 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1029 {
1030    tu6_emit_cache_flush(cmd, cs);
1031
1032    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
1033
1034    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x10000000);
1035    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1036    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1037    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
1038    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1039    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
1040    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1041    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1042    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1043
1044    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
1045    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1046    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1047    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1048    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
1049    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1050    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1051    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1052    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
1053    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1054    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
1055    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
1056    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1057    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
1058
1059    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1060    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1061    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
1062
1063    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
1064
1065    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1066
1067    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1068    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
1069    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1070    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1071    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1072    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1073    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1074    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1075    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1076    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1077    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1078
1079    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1080    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
1081
1082    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1083    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1084
1085    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1086                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1087
1088    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1089    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1090    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1091    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
1092
1093    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1094    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1095
1096    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1097
1098    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1099
1100    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1101    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1102    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1103    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1104    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1105    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1106    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1107    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1108    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1109    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1110    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1111    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1112    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1113    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1114    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1115    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1116    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1117    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1118    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1119    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1120    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1121
1122    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1123
1124    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1125
1126    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1127
1128    /* we don't use this yet.. probably best to disable.. */
1129    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1130    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1131                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1132                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1133    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1134    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1135
1136    tu_cs_emit_regs(cs,
1137                    A6XX_VPC_SO_BUFFER_BASE(0),
1138                    A6XX_VPC_SO_BUFFER_SIZE(0));
1139
1140    tu_cs_emit_regs(cs,
1141                    A6XX_VPC_SO_FLUSH_BASE(0));
1142
1143    tu_cs_emit_regs(cs,
1144                    A6XX_VPC_SO_BUF_CNTL(0));
1145
1146    tu_cs_emit_regs(cs,
1147                    A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1148
1149    tu_cs_emit_regs(cs,
1150                    A6XX_VPC_SO_BUFFER_BASE(1, 0),
1151                    A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1152
1153    tu_cs_emit_regs(cs,
1154                    A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1155                    A6XX_VPC_SO_FLUSH_BASE(1, 0),
1156                    A6XX_VPC_SO_BUFFER_BASE(2, 0),
1157                    A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1158
1159    tu_cs_emit_regs(cs,
1160                    A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1161                    A6XX_VPC_SO_FLUSH_BASE(2, 0),
1162                    A6XX_VPC_SO_BUFFER_BASE(3, 0),
1163                    A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1164
1165    tu_cs_emit_regs(cs,
1166                    A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1167                    A6XX_VPC_SO_FLUSH_BASE(3, 0));
1168
1169    tu_cs_emit_regs(cs,
1170                    A6XX_SP_HS_CTRL_REG0(0));
1171
1172    tu_cs_emit_regs(cs,
1173                    A6XX_SP_GS_CTRL_REG0(0));
1174
1175    tu_cs_emit_regs(cs,
1176                    A6XX_GRAS_LRZ_CNTL(0));
1177
1178    tu_cs_emit_regs(cs,
1179                    A6XX_RB_LRZ_CNTL(0));
1180
1181    tu_cs_sanity_check(cs);
1182 }
1183
1184 static void
1185 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1186 {
1187    unsigned seqno;
1188
1189    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1190
1191    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1192    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1193                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
1194    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1195    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1196    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1197    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1198
1199    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1200
1201    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1202    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1203    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1204    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1205 }
1206
1207 static void
1208 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1209 {
1210    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1211
1212    tu_cs_emit_regs(cs,
1213                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1214                                      .height = tiling->tile0.extent.height),
1215                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
1216                                          .bo_offset = 32 * cmd->vsc_data_pitch));
1217
1218    tu_cs_emit_regs(cs,
1219                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1220                                       .ny = tiling->tile_count.height));
1221
1222    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1223    for (unsigned i = 0; i < 32; i++)
1224       tu_cs_emit(cs, tiling->pipe_config[i]);
1225
1226    tu_cs_emit_regs(cs,
1227                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1228                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1229                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1230
1231    tu_cs_emit_regs(cs,
1232                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1233                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1234                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1235 }
1236
1237 static void
1238 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1239 {
1240    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1241    const uint32_t used_pipe_count =
1242       tiling->pipe_count.width * tiling->pipe_count.height;
1243
1244    /* Clear vsc_scratch: */
1245    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1246    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1247    tu_cs_emit(cs, 0x0);
1248
1249    /* Check for overflow, write vsc_scratch if detected: */
1250    for (int i = 0; i < used_pipe_count; i++) {
1251       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1252       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1253             CP_COND_WRITE5_0_WRITE_MEMORY);
1254       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1255       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1256       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1257       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1258       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1259       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1260
1261       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1262       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1263             CP_COND_WRITE5_0_WRITE_MEMORY);
1264       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1265       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1266       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1267       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1268       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1269       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1270    }
1271
1272    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1273
1274    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1275
1276    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1277    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1278          CP_MEM_TO_REG_0_CNT(1 - 1));
1279    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1280
1281    /*
1282     * This is a bit awkward, we really want a way to invert the
1283     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1284     * execute cmds to use hwbinning when a bit is *not* set.  This
1285     * dance is to invert OVERFLOW_FLAG_REG
1286     *
1287     * A CP_NOP packet is used to skip executing the 'else' clause
1288     * if (b0 set)..
1289     */
1290
1291    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1292    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1293    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1294          A6XX_CP_REG_TEST_0_BIT(0) |
1295          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1296
1297    tu_cs_reserve(cs, 3 + 7);
1298    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1299    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1300    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1301
1302    /* if (b0 set) */ {
1303       /*
1304        * On overflow, mirror the value to control->vsc_overflow
1305        * which CPU is checking to detect overflow (see
1306        * check_vsc_overflow())
1307        */
1308       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1309       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1310             CP_REG_TO_MEM_0_CNT(0));
1311       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1312
1313       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1314       tu_cs_emit(cs, 0x0);
1315
1316       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1317    } /* else */ {
1318       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1319       tu_cs_emit(cs, 0x1);
1320    }
1321 }
1322
1323 static void
1324 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1325 {
1326    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1327    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1328
1329    uint32_t x1 = tiling->tile0.offset.x;
1330    uint32_t y1 = tiling->tile0.offset.y;
1331    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1332    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1333
1334    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1335
1336    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1337    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1338
1339    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1340    tu_cs_emit(cs, 0x1);
1341
1342    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1343    tu_cs_emit(cs, 0x1);
1344
1345    tu_cs_emit_wfi(cs);
1346
1347    tu_cs_emit_regs(cs,
1348                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1349
1350    update_vsc_pipe(cmd, cs);
1351
1352    tu_cs_emit_regs(cs,
1353                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1354
1355    tu_cs_emit_regs(cs,
1356                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1357
1358    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1359    tu_cs_emit(cs, UNK_2C);
1360
1361    tu_cs_emit_regs(cs,
1362                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1363
1364    tu_cs_emit_regs(cs,
1365                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1366
1367    /* emit IB to binning drawcmds: */
1368    tu_cs_emit_call(cs, &cmd->draw_cs);
1369
1370    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1371    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1372                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1373                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1374    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1375    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1376
1377    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1378    tu_cs_emit(cs, UNK_2D);
1379
1380    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1381    tu6_cache_flush(cmd, cs);
1382
1383    tu_cs_emit_wfi(cs);
1384
1385    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1386
1387    emit_vsc_overflow_test(cmd, cs);
1388
1389    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1390    tu_cs_emit(cs, 0x0);
1391
1392    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1393    tu_cs_emit(cs, 0x0);
1394
1395    tu_cs_emit_wfi(cs);
1396
1397    tu_cs_emit_regs(cs,
1398                    A6XX_RB_CCU_CNTL(.unknown = phys_dev->magic.RB_CCU_CNTL_gmem));
1399
1400    cmd->wait_for_idle = false;
1401 }
1402
1403 static void
1404 tu_emit_sysmem_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1405                                 uint32_t a,
1406                                 const VkRenderPassBeginInfo *info)
1407 {
1408    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1409    const struct tu_image_view *iview = fb->attachments[a].attachment;
1410    const struct tu_render_pass_attachment *attachment =
1411       &cmd->state.pass->attachments[a];
1412    unsigned clear_mask = 0;
1413
1414    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
1415    if (attachment->gmem_offset < 0)
1416       return;
1417
1418    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1419       clear_mask = 0xf;
1420    }
1421
1422    if (vk_format_has_stencil(iview->vk_format)) {
1423       clear_mask &= 0x1;
1424       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1425          clear_mask |= 0x2;
1426       if (clear_mask != 0x3)
1427          tu_finishme("depth/stencil only load op");
1428    }
1429
1430    if (!clear_mask)
1431       return;
1432
1433    tu_clear_sysmem_attachment(cmd, cs, a,
1434                               &info->pClearValues[a], &(struct VkClearRect) {
1435       .rect = info->renderArea,
1436       .baseArrayLayer = iview->base_layer,
1437       .layerCount = iview->layer_count,
1438    });
1439 }
1440
1441 static void
1442 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1443                    const VkRenderPassBeginInfo *info)
1444 {
1445    struct tu_cs *cs = &cmd->draw_cs;
1446
1447    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1448
1449    tu6_emit_blit_scissor(cmd, cs, true);
1450
1451    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1452       tu6_emit_load_attachment(cmd, cs, i);
1453
1454    tu6_emit_blit_scissor(cmd, cs, false);
1455
1456    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1457       tu6_emit_clear_attachment(cmd, cs, i, info);
1458
1459    tu_cond_exec_end(cs);
1460
1461    /* invalidate because reading input attachments will cache GMEM and
1462     * the cache isn''t updated when GMEM is written
1463     * TODO: is there a no-cache bit for textures?
1464     */
1465    if (cmd->state.subpass->input_count)
1466       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1467
1468    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1469
1470    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1471       tu_emit_sysmem_clear_attachment(cmd, cs, i, info);
1472
1473    tu_cond_exec_end(cs);
1474 }
1475
1476 static void
1477 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1478                         const struct VkRect2D *renderArea)
1479 {
1480    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1481    if (fb->width > 0 && fb->height > 0) {
1482       tu6_emit_window_scissor(cmd, cs,
1483                               0, 0, fb->width - 1, fb->height - 1);
1484    } else {
1485       tu6_emit_window_scissor(cmd, cs, 0, 0, 0, 0);
1486    }
1487
1488    tu6_emit_window_offset(cmd, cs, 0, 0);
1489
1490    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1491
1492    tu6_emit_lrz_flush(cmd, cs);
1493
1494    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1495    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1496
1497    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1498    tu_cs_emit(cs, 0x0);
1499
1500    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1501    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1502    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1503
1504    tu6_emit_wfi(cmd, cs);
1505    tu_cs_emit_regs(cs,
1506                    A6XX_RB_CCU_CNTL(0x10000000));
1507
1508    /* enable stream-out, with sysmem there is only one pass: */
1509    tu_cs_emit_regs(cs,
1510                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1511
1512    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1513    tu_cs_emit(cs, 0x1);
1514
1515    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1516    tu_cs_emit(cs, 0x0);
1517
1518    tu_cs_sanity_check(cs);
1519 }
1520
1521 static void
1522 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1523 {
1524    /* Do any resolves of the last subpass. These are handled in the
1525     * tile_store_ib in the gmem path.
1526     */
1527
1528    const struct tu_subpass *subpass = cmd->state.subpass;
1529    if (subpass->resolve_attachments) {
1530       for (unsigned i = 0; i < subpass->color_count; i++) {
1531          uint32_t a = subpass->resolve_attachments[i].attachment;
1532          if (a != VK_ATTACHMENT_UNUSED)
1533             tu6_emit_sysmem_resolve(cmd, cs, a,
1534                                     subpass->color_attachments[i].attachment);
1535       }
1536    }
1537
1538    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1539
1540    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1541    tu_cs_emit(cs, 0x0);
1542
1543    tu6_emit_lrz_flush(cmd, cs);
1544
1545    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1546    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1547
1548    tu_cs_sanity_check(cs);
1549 }
1550
1551
1552 static void
1553 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1554 {
1555    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1556
1557    tu6_emit_lrz_flush(cmd, cs);
1558
1559    /* lrz clear? */
1560
1561    tu6_emit_cache_flush(cmd, cs);
1562
1563    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1564    tu_cs_emit(cs, 0x0);
1565
1566    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1567    tu6_emit_wfi(cmd, cs);
1568    tu_cs_emit_regs(cs,
1569                    A6XX_RB_CCU_CNTL(phys_dev->magic.RB_CCU_CNTL_gmem));
1570
1571    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1572    if (use_hw_binning(cmd)) {
1573       tu6_emit_bin_size(cs,
1574                         tiling->tile0.extent.width,
1575                         tiling->tile0.extent.height,
1576                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1577
1578       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1579
1580       tu6_emit_binning_pass(cmd, cs);
1581
1582       tu6_emit_bin_size(cs,
1583                         tiling->tile0.extent.width,
1584                         tiling->tile0.extent.height,
1585                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1586
1587       tu_cs_emit_regs(cs,
1588                       A6XX_VFD_MODE_CNTL(0));
1589
1590       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1591
1592       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1593
1594       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1595       tu_cs_emit(cs, 0x1);
1596    } else {
1597       tu6_emit_bin_size(cs,
1598                         tiling->tile0.extent.width,
1599                         tiling->tile0.extent.height,
1600                         0x6000000);
1601    }
1602
1603    tu_cs_sanity_check(cs);
1604 }
1605
1606 static void
1607 tu6_render_tile(struct tu_cmd_buffer *cmd,
1608                 struct tu_cs *cs,
1609                 const struct tu_tile *tile)
1610 {
1611    tu6_emit_tile_select(cmd, cs, tile);
1612
1613    tu_cs_emit_call(cs, &cmd->draw_cs);
1614    cmd->wait_for_idle = true;
1615
1616    if (use_hw_binning(cmd)) {
1617       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1618       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1619                      A6XX_CP_REG_TEST_0_BIT(0) |
1620                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1621
1622       tu_cs_reserve(cs, 3 + 2);
1623       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1624       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1625       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1626
1627       /* if (no overflow) */ {
1628          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1629          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1630       }
1631    }
1632
1633    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1634
1635    tu_cs_sanity_check(cs);
1636 }
1637
1638 static void
1639 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1640 {
1641    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1642
1643    tu_cs_emit_regs(cs,
1644                    A6XX_GRAS_LRZ_CNTL(0));
1645
1646    tu6_emit_lrz_flush(cmd, cs);
1647
1648    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1649
1650    tu_cs_sanity_check(cs);
1651 }
1652
1653 static void
1654 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1655 {
1656    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1657
1658    tu6_tile_render_begin(cmd, &cmd->cs);
1659
1660    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1661       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1662          struct tu_tile tile;
1663          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1664          tu6_render_tile(cmd, &cmd->cs, &tile);
1665       }
1666    }
1667
1668    tu6_tile_render_end(cmd, &cmd->cs);
1669 }
1670
1671 static void
1672 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1673 {
1674    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1675
1676    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1677
1678    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1679    cmd->wait_for_idle = true;
1680
1681    tu6_sysmem_render_end(cmd, &cmd->cs);
1682 }
1683
1684 static void
1685 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1686 {
1687    const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1688    struct tu_cs sub_cs;
1689
1690    VkResult result =
1691       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1692    if (result != VK_SUCCESS) {
1693       cmd->record_result = result;
1694       return;
1695    }
1696
1697    /* emit to tile-store sub_cs */
1698    tu6_emit_tile_store(cmd, &sub_cs);
1699
1700    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1701 }
1702
1703 static void
1704 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1705                             const VkRect2D *render_area)
1706 {
1707    const struct tu_device *dev = cmd->device;
1708    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1709
1710    tiling->render_area = *render_area;
1711    tiling->force_sysmem = force_sysmem(cmd, render_area);
1712
1713    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1714    tu_tiling_config_update_pipe_layout(tiling, dev);
1715    tu_tiling_config_update_pipes(tiling, dev);
1716 }
1717
1718 const struct tu_dynamic_state default_dynamic_state = {
1719    .viewport =
1720      {
1721        .count = 0,
1722      },
1723    .scissor =
1724      {
1725        .count = 0,
1726      },
1727    .line_width = 1.0f,
1728    .depth_bias =
1729      {
1730        .bias = 0.0f,
1731        .clamp = 0.0f,
1732        .slope = 0.0f,
1733      },
1734    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1735    .depth_bounds =
1736      {
1737        .min = 0.0f,
1738        .max = 1.0f,
1739      },
1740    .stencil_compare_mask =
1741      {
1742        .front = ~0u,
1743        .back = ~0u,
1744      },
1745    .stencil_write_mask =
1746      {
1747        .front = ~0u,
1748        .back = ~0u,
1749      },
1750    .stencil_reference =
1751      {
1752        .front = 0u,
1753        .back = 0u,
1754      },
1755 };
1756
1757 static void UNUSED /* FINISHME */
1758 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1759                       const struct tu_dynamic_state *src)
1760 {
1761    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1762    uint32_t copy_mask = src->mask;
1763    uint32_t dest_mask = 0;
1764
1765    tu_use_args(cmd_buffer); /* FINISHME */
1766
1767    /* Make sure to copy the number of viewports/scissors because they can
1768     * only be specified at pipeline creation time.
1769     */
1770    dest->viewport.count = src->viewport.count;
1771    dest->scissor.count = src->scissor.count;
1772    dest->discard_rectangle.count = src->discard_rectangle.count;
1773
1774    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1775       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1776                  src->viewport.count * sizeof(VkViewport))) {
1777          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1778                       src->viewport.count);
1779          dest_mask |= TU_DYNAMIC_VIEWPORT;
1780       }
1781    }
1782
1783    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1784       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1785                  src->scissor.count * sizeof(VkRect2D))) {
1786          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1787                       src->scissor.count);
1788          dest_mask |= TU_DYNAMIC_SCISSOR;
1789       }
1790    }
1791
1792    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1793       if (dest->line_width != src->line_width) {
1794          dest->line_width = src->line_width;
1795          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1796       }
1797    }
1798
1799    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1800       if (memcmp(&dest->depth_bias, &src->depth_bias,
1801                  sizeof(src->depth_bias))) {
1802          dest->depth_bias = src->depth_bias;
1803          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1804       }
1805    }
1806
1807    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1808       if (memcmp(&dest->blend_constants, &src->blend_constants,
1809                  sizeof(src->blend_constants))) {
1810          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1811          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1812       }
1813    }
1814
1815    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1816       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1817                  sizeof(src->depth_bounds))) {
1818          dest->depth_bounds = src->depth_bounds;
1819          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1820       }
1821    }
1822
1823    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1824       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1825                  sizeof(src->stencil_compare_mask))) {
1826          dest->stencil_compare_mask = src->stencil_compare_mask;
1827          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1828       }
1829    }
1830
1831    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1832       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1833                  sizeof(src->stencil_write_mask))) {
1834          dest->stencil_write_mask = src->stencil_write_mask;
1835          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1836       }
1837    }
1838
1839    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1840       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1841                  sizeof(src->stencil_reference))) {
1842          dest->stencil_reference = src->stencil_reference;
1843          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1844       }
1845    }
1846
1847    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1848       if (memcmp(&dest->discard_rectangle.rectangles,
1849                  &src->discard_rectangle.rectangles,
1850                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1851          typed_memcpy(dest->discard_rectangle.rectangles,
1852                       src->discard_rectangle.rectangles,
1853                       src->discard_rectangle.count);
1854          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1855       }
1856    }
1857 }
1858
1859 static VkResult
1860 tu_create_cmd_buffer(struct tu_device *device,
1861                      struct tu_cmd_pool *pool,
1862                      VkCommandBufferLevel level,
1863                      VkCommandBuffer *pCommandBuffer)
1864 {
1865    struct tu_cmd_buffer *cmd_buffer;
1866    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1867                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1868    if (cmd_buffer == NULL)
1869       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1870
1871    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1872    cmd_buffer->device = device;
1873    cmd_buffer->pool = pool;
1874    cmd_buffer->level = level;
1875
1876    if (pool) {
1877       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1878       cmd_buffer->queue_family_index = pool->queue_family_index;
1879
1880    } else {
1881       /* Init the pool_link so we can safely call list_del when we destroy
1882        * the command buffer
1883        */
1884       list_inithead(&cmd_buffer->pool_link);
1885       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1886    }
1887
1888    tu_bo_list_init(&cmd_buffer->bo_list);
1889    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1890    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1891    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1892    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1893
1894    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1895
1896    list_inithead(&cmd_buffer->upload.list);
1897
1898    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1899    if (result != VK_SUCCESS)
1900       goto fail_scratch_bo;
1901
1902    /* TODO: resize on overflow */
1903    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1904    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1905    cmd_buffer->vsc_data = device->vsc_data;
1906    cmd_buffer->vsc_data2 = device->vsc_data2;
1907
1908    return VK_SUCCESS;
1909
1910 fail_scratch_bo:
1911    list_del(&cmd_buffer->pool_link);
1912    return result;
1913 }
1914
1915 static void
1916 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1917 {
1918    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1919
1920    list_del(&cmd_buffer->pool_link);
1921
1922    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1923       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1924
1925    tu_cs_finish(&cmd_buffer->cs);
1926    tu_cs_finish(&cmd_buffer->draw_cs);
1927    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1928    tu_cs_finish(&cmd_buffer->sub_cs);
1929
1930    tu_bo_list_destroy(&cmd_buffer->bo_list);
1931    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1932 }
1933
1934 static VkResult
1935 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1936 {
1937    cmd_buffer->wait_for_idle = true;
1938
1939    cmd_buffer->record_result = VK_SUCCESS;
1940
1941    tu_bo_list_reset(&cmd_buffer->bo_list);
1942    tu_cs_reset(&cmd_buffer->cs);
1943    tu_cs_reset(&cmd_buffer->draw_cs);
1944    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1945    tu_cs_reset(&cmd_buffer->sub_cs);
1946
1947    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1948       cmd_buffer->descriptors[i].valid = 0;
1949       cmd_buffer->descriptors[i].push_dirty = false;
1950    }
1951
1952    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1953
1954    return cmd_buffer->record_result;
1955 }
1956
1957 VkResult
1958 tu_AllocateCommandBuffers(VkDevice _device,
1959                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1960                           VkCommandBuffer *pCommandBuffers)
1961 {
1962    TU_FROM_HANDLE(tu_device, device, _device);
1963    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1964
1965    VkResult result = VK_SUCCESS;
1966    uint32_t i;
1967
1968    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1969
1970       if (!list_is_empty(&pool->free_cmd_buffers)) {
1971          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1972             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1973
1974          list_del(&cmd_buffer->pool_link);
1975          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1976
1977          result = tu_reset_cmd_buffer(cmd_buffer);
1978          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1979          cmd_buffer->level = pAllocateInfo->level;
1980
1981          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1982       } else {
1983          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1984                                        &pCommandBuffers[i]);
1985       }
1986       if (result != VK_SUCCESS)
1987          break;
1988    }
1989
1990    if (result != VK_SUCCESS) {
1991       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1992                             pCommandBuffers);
1993
1994       /* From the Vulkan 1.0.66 spec:
1995        *
1996        * "vkAllocateCommandBuffers can be used to create multiple
1997        *  command buffers. If the creation of any of those command
1998        *  buffers fails, the implementation must destroy all
1999        *  successfully created command buffer objects from this
2000        *  command, set all entries of the pCommandBuffers array to
2001        *  NULL and return the error."
2002        */
2003       memset(pCommandBuffers, 0,
2004              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2005    }
2006
2007    return result;
2008 }
2009
2010 void
2011 tu_FreeCommandBuffers(VkDevice device,
2012                       VkCommandPool commandPool,
2013                       uint32_t commandBufferCount,
2014                       const VkCommandBuffer *pCommandBuffers)
2015 {
2016    for (uint32_t i = 0; i < commandBufferCount; i++) {
2017       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2018
2019       if (cmd_buffer) {
2020          if (cmd_buffer->pool) {
2021             list_del(&cmd_buffer->pool_link);
2022             list_addtail(&cmd_buffer->pool_link,
2023                          &cmd_buffer->pool->free_cmd_buffers);
2024          } else
2025             tu_cmd_buffer_destroy(cmd_buffer);
2026       }
2027    }
2028 }
2029
2030 VkResult
2031 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
2032                       VkCommandBufferResetFlags flags)
2033 {
2034    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2035    return tu_reset_cmd_buffer(cmd_buffer);
2036 }
2037
2038 VkResult
2039 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2040                       const VkCommandBufferBeginInfo *pBeginInfo)
2041 {
2042    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2043    VkResult result = VK_SUCCESS;
2044
2045    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
2046       /* If the command buffer has already been resetted with
2047        * vkResetCommandBuffer, no need to do it again.
2048        */
2049       result = tu_reset_cmd_buffer(cmd_buffer);
2050       if (result != VK_SUCCESS)
2051          return result;
2052    }
2053
2054    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2055    cmd_buffer->usage_flags = pBeginInfo->flags;
2056
2057    tu_cs_begin(&cmd_buffer->cs);
2058    tu_cs_begin(&cmd_buffer->draw_cs);
2059    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2060
2061    cmd_buffer->scratch_seqno = 0;
2062
2063    /* setup initial configuration into command buffer */
2064    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2065       switch (cmd_buffer->queue_family_index) {
2066       case TU_QUEUE_GENERAL:
2067          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
2068          break;
2069       default:
2070          break;
2071       }
2072    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2073               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2074       assert(pBeginInfo->pInheritanceInfo);
2075       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2076       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2077    }
2078
2079    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
2080
2081    return VK_SUCCESS;
2082 }
2083
2084 void
2085 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
2086                         uint32_t firstBinding,
2087                         uint32_t bindingCount,
2088                         const VkBuffer *pBuffers,
2089                         const VkDeviceSize *pOffsets)
2090 {
2091    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2092
2093    assert(firstBinding + bindingCount <= MAX_VBS);
2094
2095    for (uint32_t i = 0; i < bindingCount; i++) {
2096       cmd->state.vb.buffers[firstBinding + i] =
2097          tu_buffer_from_handle(pBuffers[i]);
2098       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
2099    }
2100
2101    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
2102    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2103 }
2104
2105 void
2106 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
2107                       VkBuffer buffer,
2108                       VkDeviceSize offset,
2109                       VkIndexType indexType)
2110 {
2111    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2112    TU_FROM_HANDLE(tu_buffer, buf, buffer);
2113
2114    /* initialize/update the restart index */
2115    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
2116       struct tu_cs *draw_cs = &cmd->draw_cs;
2117
2118       tu6_emit_restart_index(
2119          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
2120
2121       tu_cs_sanity_check(draw_cs);
2122    }
2123
2124    /* track the BO */
2125    if (cmd->state.index_buffer != buf)
2126       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2127
2128    cmd->state.index_buffer = buf;
2129    cmd->state.index_offset = offset;
2130    cmd->state.index_type = indexType;
2131 }
2132
2133 void
2134 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
2135                          VkPipelineBindPoint pipelineBindPoint,
2136                          VkPipelineLayout _layout,
2137                          uint32_t firstSet,
2138                          uint32_t descriptorSetCount,
2139                          const VkDescriptorSet *pDescriptorSets,
2140                          uint32_t dynamicOffsetCount,
2141                          const uint32_t *pDynamicOffsets)
2142 {
2143    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2144    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
2145    unsigned dyn_idx = 0;
2146
2147    struct tu_descriptor_state *descriptors_state =
2148       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2149
2150    for (unsigned i = 0; i < descriptorSetCount; ++i) {
2151       unsigned idx = i + firstSet;
2152       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
2153
2154       descriptors_state->sets[idx] = set;
2155       descriptors_state->valid |= (1u << idx);
2156
2157       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2158          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2159          assert(dyn_idx < dynamicOffsetCount);
2160
2161          descriptors_state->dynamic_buffers[idx] =
2162          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
2163       }
2164    }
2165
2166    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
2167 }
2168
2169 void
2170 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2171                     VkPipelineLayout layout,
2172                     VkShaderStageFlags stageFlags,
2173                     uint32_t offset,
2174                     uint32_t size,
2175                     const void *pValues)
2176 {
2177    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2178    memcpy((void*) cmd->push_constants + offset, pValues, size);
2179    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2180 }
2181
2182 VkResult
2183 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2184 {
2185    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2186
2187    if (cmd_buffer->scratch_seqno) {
2188       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2189                      MSM_SUBMIT_BO_WRITE);
2190    }
2191
2192    if (cmd_buffer->use_vsc_data) {
2193       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2194                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2195       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2196                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2197    }
2198
2199    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2200       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2201                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2202    }
2203
2204    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
2205       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
2206                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2207    }
2208
2209    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2210       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2211                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2212    }
2213
2214    tu_cs_end(&cmd_buffer->cs);
2215    tu_cs_end(&cmd_buffer->draw_cs);
2216    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2217
2218    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2219
2220    return cmd_buffer->record_result;
2221 }
2222
2223 void
2224 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2225                    VkPipelineBindPoint pipelineBindPoint,
2226                    VkPipeline _pipeline)
2227 {
2228    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2229    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2230
2231    switch (pipelineBindPoint) {
2232    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2233       cmd->state.pipeline = pipeline;
2234       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2235       break;
2236    case VK_PIPELINE_BIND_POINT_COMPUTE:
2237       cmd->state.compute_pipeline = pipeline;
2238       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2239       break;
2240    default:
2241       unreachable("unrecognized pipeline bind point");
2242       break;
2243    }
2244
2245    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2246                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2247    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2248       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2249                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2250    }
2251 }
2252
2253 void
2254 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2255                   uint32_t firstViewport,
2256                   uint32_t viewportCount,
2257                   const VkViewport *pViewports)
2258 {
2259    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2260    struct tu_cs *draw_cs = &cmd->draw_cs;
2261
2262    assert(firstViewport == 0 && viewportCount == 1);
2263    tu6_emit_viewport(draw_cs, pViewports);
2264
2265    tu_cs_sanity_check(draw_cs);
2266 }
2267
2268 void
2269 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2270                  uint32_t firstScissor,
2271                  uint32_t scissorCount,
2272                  const VkRect2D *pScissors)
2273 {
2274    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2275    struct tu_cs *draw_cs = &cmd->draw_cs;
2276
2277    assert(firstScissor == 0 && scissorCount == 1);
2278    tu6_emit_scissor(draw_cs, pScissors);
2279
2280    tu_cs_sanity_check(draw_cs);
2281 }
2282
2283 void
2284 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2285 {
2286    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2287
2288    cmd->state.dynamic.line_width = lineWidth;
2289
2290    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2291    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2292 }
2293
2294 void
2295 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2296                    float depthBiasConstantFactor,
2297                    float depthBiasClamp,
2298                    float depthBiasSlopeFactor)
2299 {
2300    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2301    struct tu_cs *draw_cs = &cmd->draw_cs;
2302
2303    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2304                        depthBiasSlopeFactor);
2305
2306    tu_cs_sanity_check(draw_cs);
2307 }
2308
2309 void
2310 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2311                         const float blendConstants[4])
2312 {
2313    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2314    struct tu_cs *draw_cs = &cmd->draw_cs;
2315
2316    tu6_emit_blend_constants(draw_cs, blendConstants);
2317
2318    tu_cs_sanity_check(draw_cs);
2319 }
2320
2321 void
2322 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2323                      float minDepthBounds,
2324                      float maxDepthBounds)
2325 {
2326 }
2327
2328 void
2329 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2330                             VkStencilFaceFlags faceMask,
2331                             uint32_t compareMask)
2332 {
2333    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2334
2335    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2336       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2337    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2338       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2339
2340    /* the front/back compare masks must be updated together */
2341    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2342 }
2343
2344 void
2345 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2346                           VkStencilFaceFlags faceMask,
2347                           uint32_t writeMask)
2348 {
2349    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2350
2351    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2352       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2353    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2354       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2355
2356    /* the front/back write masks must be updated together */
2357    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2358 }
2359
2360 void
2361 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2362                           VkStencilFaceFlags faceMask,
2363                           uint32_t reference)
2364 {
2365    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2366
2367    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2368       cmd->state.dynamic.stencil_reference.front = reference;
2369    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2370       cmd->state.dynamic.stencil_reference.back = reference;
2371
2372    /* the front/back references must be updated together */
2373    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2374 }
2375
2376 void
2377 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2378                       uint32_t commandBufferCount,
2379                       const VkCommandBuffer *pCmdBuffers)
2380 {
2381    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2382    VkResult result;
2383
2384    assert(commandBufferCount > 0);
2385
2386    for (uint32_t i = 0; i < commandBufferCount; i++) {
2387       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2388
2389       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2390       if (result != VK_SUCCESS) {
2391          cmd->record_result = result;
2392          break;
2393       }
2394
2395       result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2396       if (result != VK_SUCCESS) {
2397          cmd->record_result = result;
2398          break;
2399       }
2400
2401       result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2402             &secondary->draw_epilogue_cs);
2403       if (result != VK_SUCCESS) {
2404          cmd->record_result = result;
2405          break;
2406       }
2407    }
2408    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2409 }
2410
2411 VkResult
2412 tu_CreateCommandPool(VkDevice _device,
2413                      const VkCommandPoolCreateInfo *pCreateInfo,
2414                      const VkAllocationCallbacks *pAllocator,
2415                      VkCommandPool *pCmdPool)
2416 {
2417    TU_FROM_HANDLE(tu_device, device, _device);
2418    struct tu_cmd_pool *pool;
2419
2420    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2421                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2422    if (pool == NULL)
2423       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2424
2425    if (pAllocator)
2426       pool->alloc = *pAllocator;
2427    else
2428       pool->alloc = device->alloc;
2429
2430    list_inithead(&pool->cmd_buffers);
2431    list_inithead(&pool->free_cmd_buffers);
2432
2433    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2434
2435    *pCmdPool = tu_cmd_pool_to_handle(pool);
2436
2437    return VK_SUCCESS;
2438 }
2439
2440 void
2441 tu_DestroyCommandPool(VkDevice _device,
2442                       VkCommandPool commandPool,
2443                       const VkAllocationCallbacks *pAllocator)
2444 {
2445    TU_FROM_HANDLE(tu_device, device, _device);
2446    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2447
2448    if (!pool)
2449       return;
2450
2451    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2452                             &pool->cmd_buffers, pool_link)
2453    {
2454       tu_cmd_buffer_destroy(cmd_buffer);
2455    }
2456
2457    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2458                             &pool->free_cmd_buffers, pool_link)
2459    {
2460       tu_cmd_buffer_destroy(cmd_buffer);
2461    }
2462
2463    vk_free2(&device->alloc, pAllocator, pool);
2464 }
2465
2466 VkResult
2467 tu_ResetCommandPool(VkDevice device,
2468                     VkCommandPool commandPool,
2469                     VkCommandPoolResetFlags flags)
2470 {
2471    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2472    VkResult result;
2473
2474    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2475                        pool_link)
2476    {
2477       result = tu_reset_cmd_buffer(cmd_buffer);
2478       if (result != VK_SUCCESS)
2479          return result;
2480    }
2481
2482    return VK_SUCCESS;
2483 }
2484
2485 void
2486 tu_TrimCommandPool(VkDevice device,
2487                    VkCommandPool commandPool,
2488                    VkCommandPoolTrimFlags flags)
2489 {
2490    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2491
2492    if (!pool)
2493       return;
2494
2495    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2496                             &pool->free_cmd_buffers, pool_link)
2497    {
2498       tu_cmd_buffer_destroy(cmd_buffer);
2499    }
2500 }
2501
2502 void
2503 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2504                       const VkRenderPassBeginInfo *pRenderPassBegin,
2505                       VkSubpassContents contents)
2506 {
2507    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2508    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2509    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2510
2511    cmd->state.pass = pass;
2512    cmd->state.subpass = pass->subpasses;
2513    cmd->state.framebuffer = fb;
2514
2515    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2516    tu_cmd_prepare_tile_store_ib(cmd);
2517
2518    tu_emit_load_clear(cmd, pRenderPassBegin);
2519
2520    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2521    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2522    tu6_emit_msaa(cmd, cmd->state.subpass, &cmd->draw_cs);
2523    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2524
2525    /* note: use_hw_binning only checks tiling config */
2526    if (use_hw_binning(cmd))
2527       cmd->use_vsc_data = true;
2528
2529    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2530       const struct tu_image_view *iview = fb->attachments[i].attachment;
2531       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2532                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2533    }
2534 }
2535
2536 void
2537 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2538                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2539                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2540 {
2541    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2542                          pSubpassBeginInfo->contents);
2543 }
2544
2545 void
2546 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2547 {
2548    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2549    const struct tu_render_pass *pass = cmd->state.pass;
2550    struct tu_cs *cs = &cmd->draw_cs;
2551
2552    const struct tu_subpass *subpass = cmd->state.subpass++;
2553    /* TODO:
2554     * if msaa samples change between subpasses,
2555     * attachment store is broken for some attachments
2556     */
2557    if (subpass->resolve_attachments) {
2558       tu6_emit_blit_scissor(cmd, cs, true);
2559       for (unsigned i = 0; i < subpass->color_count; i++) {
2560          uint32_t a = subpass->resolve_attachments[i].attachment;
2561          if (a != VK_ATTACHMENT_UNUSED) {
2562             tu6_emit_resolve(cmd, cs, a,
2563                              subpass->color_attachments[i].attachment);
2564          }
2565       }
2566    }
2567
2568    /* invalidate because reading input attachments will cache GMEM and
2569     * the cache isn''t updated when GMEM is written
2570     * TODO: is there a no-cache bit for textures?
2571     */
2572    if (cmd->state.subpass->input_count)
2573       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2574
2575    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2576    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2577    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2578    tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2579    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2580
2581    /* Emit flushes so that input attachments will read the correct value. This
2582     * is for sysmem only, although it shouldn't do much harm on gmem.
2583     */
2584    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2585    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2586
2587    /* TODO:
2588     * since we don't know how to do GMEM->GMEM resolve,
2589     * resolve attachments are resolved to memory then loaded to GMEM again if needed
2590     */
2591    if (subpass->resolve_attachments) {
2592       for (unsigned i = 0; i < subpass->color_count; i++) {
2593          uint32_t a = subpass->resolve_attachments[i].attachment;
2594          if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2595                tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2596                tu6_emit_predicated_blit(cmd, cs, a, a, false);
2597          }
2598       }
2599    }
2600 }
2601
2602 void
2603 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2604                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2605                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2606 {
2607    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2608 }
2609
2610 struct tu_draw_info
2611 {
2612    /**
2613     * Number of vertices.
2614     */
2615    uint32_t count;
2616
2617    /**
2618     * Index of the first vertex.
2619     */
2620    int32_t vertex_offset;
2621
2622    /**
2623     * First instance id.
2624     */
2625    uint32_t first_instance;
2626
2627    /**
2628     * Number of instances.
2629     */
2630    uint32_t instance_count;
2631
2632    /**
2633     * First index (indexed draws only).
2634     */
2635    uint32_t first_index;
2636
2637    /**
2638     * Whether it's an indexed draw.
2639     */
2640    bool indexed;
2641
2642    /**
2643     * Indirect draw parameters resource.
2644     */
2645    struct tu_buffer *indirect;
2646    uint64_t indirect_offset;
2647    uint32_t stride;
2648
2649    /**
2650     * Draw count parameters resource.
2651     */
2652    struct tu_buffer *count_buffer;
2653    uint64_t count_buffer_offset;
2654 };
2655
2656 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2657 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2658
2659 enum tu_draw_state_group_id
2660 {
2661    TU_DRAW_STATE_PROGRAM,
2662    TU_DRAW_STATE_PROGRAM_BINNING,
2663    TU_DRAW_STATE_VI,
2664    TU_DRAW_STATE_VI_BINNING,
2665    TU_DRAW_STATE_VP,
2666    TU_DRAW_STATE_RAST,
2667    TU_DRAW_STATE_DS,
2668    TU_DRAW_STATE_BLEND,
2669    TU_DRAW_STATE_VS_CONST,
2670    TU_DRAW_STATE_FS_CONST,
2671    TU_DRAW_STATE_VS_TEX,
2672    TU_DRAW_STATE_FS_TEX_SYSMEM,
2673    TU_DRAW_STATE_FS_TEX_GMEM,
2674    TU_DRAW_STATE_FS_IBO,
2675    TU_DRAW_STATE_VS_PARAMS,
2676
2677    TU_DRAW_STATE_COUNT,
2678 };
2679
2680 struct tu_draw_state_group
2681 {
2682    enum tu_draw_state_group_id id;
2683    uint32_t enable_mask;
2684    struct tu_cs_entry ib;
2685 };
2686
2687 const static struct tu_sampler*
2688 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2689             const struct tu_descriptor_map *map, unsigned i,
2690             unsigned array_index)
2691 {
2692    assert(descriptors_state->valid & (1 << map->set[i]));
2693
2694    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2695    assert(map->binding[i] < set->layout->binding_count);
2696
2697    const struct tu_descriptor_set_binding_layout *layout =
2698       &set->layout->binding[map->binding[i]];
2699
2700    if (layout->immutable_samplers_offset) {
2701       const struct tu_sampler *immutable_samplers =
2702          tu_immutable_samplers(set->layout, layout);
2703
2704       return &immutable_samplers[array_index];
2705    }
2706
2707    switch (layout->type) {
2708    case VK_DESCRIPTOR_TYPE_SAMPLER:
2709       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2710    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2711       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2712                                                    array_index *
2713                                                    (A6XX_TEX_CONST_DWORDS +
2714                                                     sizeof(struct tu_sampler) / 4)];
2715    default:
2716       unreachable("unimplemented descriptor type");
2717       break;
2718    }
2719 }
2720
2721 static void
2722 write_tex_const(struct tu_cmd_buffer *cmd,
2723                 uint32_t *dst,
2724                 struct tu_descriptor_state *descriptors_state,
2725                 const struct tu_descriptor_map *map,
2726                 unsigned i, unsigned array_index, bool is_sysmem)
2727 {
2728    assert(descriptors_state->valid & (1 << map->set[i]));
2729
2730    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2731    assert(map->binding[i] < set->layout->binding_count);
2732
2733    const struct tu_descriptor_set_binding_layout *layout =
2734       &set->layout->binding[map->binding[i]];
2735
2736    switch (layout->type) {
2737    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2738    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2739    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2740    case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2741       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2742                                    array_index * A6XX_TEX_CONST_DWORDS],
2743              A6XX_TEX_CONST_DWORDS * 4);
2744       break;
2745    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2746       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2747                                    array_index *
2748                                    (A6XX_TEX_CONST_DWORDS +
2749                                     sizeof(struct tu_sampler) / 4)],
2750              A6XX_TEX_CONST_DWORDS * 4);
2751       break;
2752    default:
2753       unreachable("unimplemented descriptor type");
2754       break;
2755    }
2756
2757    if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
2758       const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2759       uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2760                                                          array_index].attachment;
2761       const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2762
2763       assert(att->gmem_offset >= 0);
2764
2765       dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2766       dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2767       dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2768       dst[2] |=
2769          A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2770          A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2771       dst[3] = 0;
2772       dst[4] = 0x100000 + att->gmem_offset;
2773       dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2774       for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2775          dst[i] = 0;
2776
2777       if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2778          tu_finishme("patch input attachment pitch for secondary cmd buffer");
2779    }
2780 }
2781
2782 static void
2783 write_image_ibo(struct tu_cmd_buffer *cmd,
2784                 uint32_t *dst,
2785                 struct tu_descriptor_state *descriptors_state,
2786                 const struct tu_descriptor_map *map,
2787                 unsigned i, unsigned array_index)
2788 {
2789    assert(descriptors_state->valid & (1 << map->set[i]));
2790
2791    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2792    assert(map->binding[i] < set->layout->binding_count);
2793
2794    const struct tu_descriptor_set_binding_layout *layout =
2795       &set->layout->binding[map->binding[i]];
2796
2797    assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2798
2799    memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2800                                 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2801           A6XX_TEX_CONST_DWORDS * 4);
2802 }
2803
2804 static uint64_t
2805 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2806            const struct tu_descriptor_map *map,
2807            unsigned i, unsigned array_index)
2808 {
2809    assert(descriptors_state->valid & (1 << map->set[i]));
2810
2811    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2812    assert(map->binding[i] < set->layout->binding_count);
2813
2814    const struct tu_descriptor_set_binding_layout *layout =
2815       &set->layout->binding[map->binding[i]];
2816
2817    switch (layout->type) {
2818    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2819    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2820       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2821                                                 array_index];
2822    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2823    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2824       return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2825                         set->mapped_ptr[layout->offset / 4 + array_index * 2];
2826    default:
2827       unreachable("unimplemented descriptor type");
2828       break;
2829    }
2830 }
2831
2832 static inline uint32_t
2833 tu6_stage2opcode(gl_shader_stage type)
2834 {
2835    switch (type) {
2836    case MESA_SHADER_VERTEX:
2837    case MESA_SHADER_TESS_CTRL:
2838    case MESA_SHADER_TESS_EVAL:
2839    case MESA_SHADER_GEOMETRY:
2840       return CP_LOAD_STATE6_GEOM;
2841    case MESA_SHADER_FRAGMENT:
2842    case MESA_SHADER_COMPUTE:
2843    case MESA_SHADER_KERNEL:
2844       return CP_LOAD_STATE6_FRAG;
2845    default:
2846       unreachable("bad shader type");
2847    }
2848 }
2849
2850 static inline enum a6xx_state_block
2851 tu6_stage2shadersb(gl_shader_stage type)
2852 {
2853    switch (type) {
2854    case MESA_SHADER_VERTEX:
2855       return SB6_VS_SHADER;
2856    case MESA_SHADER_FRAGMENT:
2857       return SB6_FS_SHADER;
2858    case MESA_SHADER_COMPUTE:
2859    case MESA_SHADER_KERNEL:
2860       return SB6_CS_SHADER;
2861    default:
2862       unreachable("bad shader type");
2863       return ~0;
2864    }
2865 }
2866
2867 static void
2868 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2869                      struct tu_descriptor_state *descriptors_state,
2870                      gl_shader_stage type,
2871                      uint32_t *push_constants)
2872 {
2873    const struct tu_program_descriptor_linkage *link =
2874       &pipeline->program.link[type];
2875    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2876
2877    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2878       if (state->range[i].start < state->range[i].end) {
2879          uint32_t size = state->range[i].end - state->range[i].start;
2880          uint32_t offset = state->range[i].start;
2881
2882          /* and even if the start of the const buffer is before
2883           * first_immediate, the end may not be:
2884           */
2885          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2886
2887          if (size == 0)
2888             continue;
2889
2890          /* things should be aligned to vec4: */
2891          debug_assert((state->range[i].offset % 16) == 0);
2892          debug_assert((size % 16) == 0);
2893          debug_assert((offset % 16) == 0);
2894
2895          if (i == 0) {
2896             /* push constants */
2897             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2898             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2899                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2900                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2901                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2902                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2903             tu_cs_emit(cs, 0);
2904             tu_cs_emit(cs, 0);
2905             for (unsigned i = 0; i < size / 4; i++)
2906                tu_cs_emit(cs, push_constants[i + offset / 4]);
2907             continue;
2908          }
2909
2910          /* Look through the UBO map to find our UBO index, and get the VA for
2911           * that UBO.
2912           */
2913          uint64_t va = 0;
2914          uint32_t ubo_idx = i - 1;
2915          uint32_t ubo_map_base = 0;
2916          for (int j = 0; j < link->ubo_map.num; j++) {
2917             if (ubo_idx >= ubo_map_base &&
2918                 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2919                va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2920                                ubo_idx - ubo_map_base);
2921                break;
2922             }
2923             ubo_map_base += link->ubo_map.array_size[j];
2924          }
2925          assert(va);
2926
2927          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2928          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2929                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2930                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2931                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2932                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2933          tu_cs_emit_qw(cs, va + offset);
2934       }
2935    }
2936 }
2937
2938 static void
2939 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2940               struct tu_descriptor_state *descriptors_state,
2941               gl_shader_stage type)
2942 {
2943    const struct tu_program_descriptor_linkage *link =
2944       &pipeline->program.link[type];
2945
2946    uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2947    uint32_t anum = align(num, 2);
2948
2949    if (!num)
2950       return;
2951
2952    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2953    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2954          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2955          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2956          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2957          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2958    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2959    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2960
2961    unsigned emitted = 0;
2962    for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2963       for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2964          tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2965          emitted++;
2966       }
2967    }
2968
2969    for (; emitted < anum; emitted++) {
2970       tu_cs_emit(cs, 0xffffffff);
2971       tu_cs_emit(cs, 0xffffffff);
2972    }
2973 }
2974
2975 static struct tu_cs_entry
2976 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2977                 const struct tu_pipeline *pipeline,
2978                 struct tu_descriptor_state *descriptors_state,
2979                 gl_shader_stage type)
2980 {
2981    struct tu_cs cs;
2982    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2983
2984    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2985    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2986
2987    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2988 }
2989
2990 static VkResult
2991 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2992                    const struct tu_draw_info *draw,
2993                    struct tu_cs_entry *entry)
2994 {
2995    /* TODO: fill out more than just base instance */
2996    const struct tu_program_descriptor_linkage *link =
2997       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2998    const struct ir3_const_state *const_state = &link->const_state;
2999    struct tu_cs cs;
3000
3001    if (const_state->offsets.driver_param >= link->constlen) {
3002       *entry = (struct tu_cs_entry) {};
3003       return VK_SUCCESS;
3004    }
3005
3006    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
3007    if (result != VK_SUCCESS)
3008       return result;
3009
3010    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3011    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
3012          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3013          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3014          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
3015          CP_LOAD_STATE6_0_NUM_UNIT(1));
3016    tu_cs_emit(&cs, 0);
3017    tu_cs_emit(&cs, 0);
3018
3019    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
3020
3021    tu_cs_emit(&cs, 0);
3022    tu_cs_emit(&cs, 0);
3023    tu_cs_emit(&cs, draw->first_instance);
3024    tu_cs_emit(&cs, 0);
3025
3026    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3027    return VK_SUCCESS;
3028 }
3029
3030 static VkResult
3031 tu6_emit_textures(struct tu_cmd_buffer *cmd,
3032                   const struct tu_pipeline *pipeline,
3033                   struct tu_descriptor_state *descriptors_state,
3034                   gl_shader_stage type,
3035                   struct tu_cs_entry *entry,
3036                   bool *needs_border,
3037                   bool is_sysmem)
3038 {
3039    struct tu_cs *draw_state = &cmd->sub_cs;
3040    const struct tu_program_descriptor_linkage *link =
3041       &pipeline->program.link[type];
3042    VkResult result;
3043
3044    if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
3045       *entry = (struct tu_cs_entry) {};
3046       return VK_SUCCESS;
3047    }
3048
3049    /* allocate and fill texture state */
3050    struct ts_cs_memory tex_const;
3051    result = tu_cs_alloc(draw_state, link->texture_map.num_desc,
3052                         A6XX_TEX_CONST_DWORDS, &tex_const);
3053    if (result != VK_SUCCESS)
3054       return result;
3055
3056    int tex_index = 0;
3057    for (unsigned i = 0; i < link->texture_map.num; i++) {
3058       for (int j = 0; j < link->texture_map.array_size[i]; j++) {
3059          write_tex_const(cmd,
3060                          &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
3061                          descriptors_state, &link->texture_map, i, j,
3062                          is_sysmem);
3063       }
3064    }
3065
3066    /* allocate and fill sampler state */
3067    struct ts_cs_memory tex_samp = { 0 };
3068    if (link->sampler_map.num_desc) {
3069       result = tu_cs_alloc(draw_state, link->sampler_map.num_desc,
3070                            A6XX_TEX_SAMP_DWORDS, &tex_samp);
3071       if (result != VK_SUCCESS)
3072          return result;
3073
3074       int sampler_index = 0;
3075       for (unsigned i = 0; i < link->sampler_map.num; i++) {
3076          for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
3077             const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3078                                                            &link->sampler_map,
3079                                                            i, j);
3080             memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
3081                    sampler->state, sizeof(sampler->state));
3082             *needs_border |= sampler->needs_border;
3083          }
3084       }
3085    }
3086
3087    unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
3088    enum a6xx_state_block sb;
3089
3090    switch (type) {
3091    case MESA_SHADER_VERTEX:
3092       sb = SB6_VS_TEX;
3093       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
3094       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
3095       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
3096       break;
3097    case MESA_SHADER_FRAGMENT:
3098       sb = SB6_FS_TEX;
3099       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
3100       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
3101       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
3102       break;
3103    case MESA_SHADER_COMPUTE:
3104       sb = SB6_CS_TEX;
3105       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
3106       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
3107       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
3108       break;
3109    default:
3110       unreachable("bad state block");
3111    }
3112
3113    struct tu_cs cs;
3114    result = tu_cs_begin_sub_stream(draw_state, 16, &cs);
3115    if (result != VK_SUCCESS)
3116       return result;
3117
3118    if (link->sampler_map.num_desc) {
3119       /* output sampler state: */
3120       tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3121       tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3122                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
3123                  CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3124                  CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3125                  CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
3126       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3127
3128       tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
3129       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3130    }
3131
3132    /* emit texture state: */
3133    tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3134    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3135       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3136       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3137       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3138       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
3139    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3140
3141    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
3142    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3143
3144    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
3145    tu_cs_emit(&cs, link->texture_map.num_desc);
3146
3147    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3148    return VK_SUCCESS;
3149 }
3150
3151 static VkResult
3152 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
3153              const struct tu_pipeline *pipeline,
3154              struct tu_descriptor_state *descriptors_state,
3155              gl_shader_stage type,
3156              struct tu_cs_entry *entry)
3157 {
3158    struct tu_cs *draw_state = &cmd->sub_cs;
3159    const struct tu_program_descriptor_linkage *link =
3160       &pipeline->program.link[type];
3161    VkResult result;
3162
3163    unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
3164
3165    if (num_desc == 0) {
3166       *entry = (struct tu_cs_entry) {};
3167       return VK_SUCCESS;
3168    }
3169
3170    struct ts_cs_memory ibo_const;
3171    result = tu_cs_alloc(draw_state, num_desc,
3172                         A6XX_TEX_CONST_DWORDS, &ibo_const);
3173    if (result != VK_SUCCESS)
3174       return result;
3175
3176    int ssbo_index = 0;
3177    for (unsigned i = 0; i < link->ssbo_map.num; i++) {
3178       for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
3179          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3180
3181          uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
3182          /* We don't expose robustBufferAccess, so leave the size unlimited. */
3183          uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
3184
3185          dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
3186          dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
3187                   A6XX_IBO_1_HEIGHT(sz >> 15);
3188          dst[2] = A6XX_IBO_2_UNK4 |
3189                   A6XX_IBO_2_UNK31 |
3190                   A6XX_IBO_2_TYPE(A6XX_TEX_1D);
3191          dst[3] = 0;
3192          dst[4] = va;
3193          dst[5] = va >> 32;
3194          for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
3195             dst[i] = 0;
3196
3197          ssbo_index++;
3198       }
3199    }
3200
3201    for (unsigned i = 0; i < link->image_map.num; i++) {
3202       for (int j = 0; j < link->image_map.array_size[i]; j++) {
3203          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3204
3205          write_image_ibo(cmd, dst,
3206                          descriptors_state, &link->image_map, i, j);
3207
3208          ssbo_index++;
3209       }
3210    }
3211
3212    assert(ssbo_index == num_desc);
3213
3214    struct tu_cs cs;
3215    result = tu_cs_begin_sub_stream(draw_state, 7, &cs);
3216    if (result != VK_SUCCESS)
3217       return result;
3218
3219    uint32_t opcode, ibo_addr_reg;
3220    enum a6xx_state_block sb;
3221    enum a6xx_state_type st;
3222
3223    switch (type) {
3224    case MESA_SHADER_FRAGMENT:
3225       opcode = CP_LOAD_STATE6;
3226       st = ST6_SHADER;
3227       sb = SB6_IBO;
3228       ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3229       break;
3230    case MESA_SHADER_COMPUTE:
3231       opcode = CP_LOAD_STATE6_FRAG;
3232       st = ST6_IBO;
3233       sb = SB6_CS_SHADER;
3234       ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3235       break;
3236    default:
3237       unreachable("unsupported stage for ibos");
3238    }
3239
3240    /* emit texture state: */
3241    tu_cs_emit_pkt7(&cs, opcode, 3);
3242    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3243               CP_LOAD_STATE6_0_STATE_TYPE(st) |
3244               CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3245               CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3246               CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3247    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3248
3249    tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3250    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3251
3252    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3253    return VK_SUCCESS;
3254 }
3255
3256 struct PACKED bcolor_entry {
3257    uint32_t fp32[4];
3258    uint16_t ui16[4];
3259    int16_t  si16[4];
3260    uint16_t fp16[4];
3261    uint16_t rgb565;
3262    uint16_t rgb5a1;
3263    uint16_t rgba4;
3264    uint8_t __pad0[2];
3265    uint8_t  ui8[4];
3266    int8_t   si8[4];
3267    uint32_t rgb10a2;
3268    uint32_t z24; /* also s8? */
3269    uint16_t srgb[4];      /* appears to duplicate fp16[], but clamped, used for srgb */
3270    uint8_t  __pad1[56];
3271 } border_color[] = {
3272    [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3273    [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3274    [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3275       .fp32[3] = 0x3f800000,
3276       .ui16[3] = 0xffff,
3277       .si16[3] = 0x7fff,
3278       .fp16[3] = 0x3c00,
3279       .rgb5a1 = 0x8000,
3280       .rgba4 = 0xf000,
3281       .ui8[3] = 0xff,
3282       .si8[3] = 0x7f,
3283       .rgb10a2 = 0xc0000000,
3284       .srgb[3] = 0x3c00,
3285    },
3286    [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3287       .fp32[3] = 1,
3288       .fp16[3] = 1,
3289    },
3290    [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3291       .fp32[0 ... 3] = 0x3f800000,
3292       .ui16[0 ... 3] = 0xffff,
3293       .si16[0 ... 3] = 0x7fff,
3294       .fp16[0 ... 3] = 0x3c00,
3295       .rgb565 = 0xffff,
3296       .rgb5a1 = 0xffff,
3297       .rgba4 = 0xffff,
3298       .ui8[0 ... 3] = 0xff,
3299       .si8[0 ... 3] = 0x7f,
3300       .rgb10a2 = 0xffffffff,
3301       .z24 = 0xffffff,
3302       .srgb[0 ... 3] = 0x3c00,
3303    },
3304    [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3305       .fp32[0 ... 3] = 1,
3306       .fp16[0 ... 3] = 1,
3307    },
3308 };
3309
3310 static VkResult
3311 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3312                       struct tu_cs *cs)
3313 {
3314    STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3315
3316    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3317    struct tu_descriptor_state *descriptors_state =
3318       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3319    const struct tu_descriptor_map *vs_sampler =
3320       &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3321    const struct tu_descriptor_map *fs_sampler =
3322       &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3323    struct ts_cs_memory ptr;
3324
3325    VkResult result = tu_cs_alloc(&cmd->sub_cs,
3326                                  vs_sampler->num_desc + fs_sampler->num_desc,
3327                                  128 / 4,
3328                                  &ptr);
3329    if (result != VK_SUCCESS)
3330       return result;
3331
3332    for (unsigned i = 0; i < vs_sampler->num; i++) {
3333       for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3334          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3335                                                         vs_sampler, i, j);
3336          memcpy(ptr.map, &border_color[sampler->border], 128);
3337          ptr.map += 128 / 4;
3338       }
3339    }
3340
3341    for (unsigned i = 0; i < fs_sampler->num; i++) {
3342       for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3343          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3344                                                         fs_sampler, i, j);
3345          memcpy(ptr.map, &border_color[sampler->border], 128);
3346          ptr.map += 128 / 4;
3347       }
3348    }
3349
3350    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3351    tu_cs_emit_qw(cs, ptr.iova);
3352    return VK_SUCCESS;
3353 }
3354
3355 static VkResult
3356 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3357                      struct tu_cs *cs,
3358                      const struct tu_draw_info *draw)
3359 {
3360    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3361    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3362    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3363    uint32_t draw_state_group_count = 0;
3364    VkResult result;
3365
3366    struct tu_descriptor_state *descriptors_state =
3367       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3368
3369    /* TODO lrz */
3370
3371    tu_cs_emit_regs(cs,
3372                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3373                                             pipeline->ia.primitive_restart && draw->indexed));
3374
3375    if (cmd->state.dirty &
3376           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3377        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3378       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3379                             dynamic->line_width);
3380    }
3381
3382    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3383        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3384       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3385                                     dynamic->stencil_compare_mask.back);
3386    }
3387
3388    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3389        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3390       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3391                                   dynamic->stencil_write_mask.back);
3392    }
3393
3394    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3395        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3396       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3397                                  dynamic->stencil_reference.back);
3398    }
3399
3400    if (cmd->state.dirty &
3401        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3402       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3403          const uint32_t binding = pipeline->vi.bindings[i];
3404          const uint32_t stride = pipeline->vi.strides[i];
3405          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3406          const VkDeviceSize offset = buf->bo_offset +
3407                                      cmd->state.vb.offsets[binding] +
3408                                      pipeline->vi.offsets[i];
3409          const VkDeviceSize size =
3410             offset < buf->bo->size ? buf->bo->size - offset : 0;
3411
3412          tu_cs_emit_regs(cs,
3413                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3414                          A6XX_VFD_FETCH_SIZE(i, size),
3415                          A6XX_VFD_FETCH_STRIDE(i, stride));
3416       }
3417    }
3418
3419    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3420       draw_state_groups[draw_state_group_count++] =
3421          (struct tu_draw_state_group) {
3422             .id = TU_DRAW_STATE_PROGRAM,
3423             .enable_mask = ENABLE_DRAW,
3424             .ib = pipeline->program.state_ib,
3425          };
3426       draw_state_groups[draw_state_group_count++] =
3427          (struct tu_draw_state_group) {
3428             .id = TU_DRAW_STATE_PROGRAM_BINNING,
3429             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3430             .ib = pipeline->program.binning_state_ib,
3431          };
3432       draw_state_groups[draw_state_group_count++] =
3433          (struct tu_draw_state_group) {
3434             .id = TU_DRAW_STATE_VI,
3435             .enable_mask = ENABLE_DRAW,
3436             .ib = pipeline->vi.state_ib,
3437          };
3438       draw_state_groups[draw_state_group_count++] =
3439          (struct tu_draw_state_group) {
3440             .id = TU_DRAW_STATE_VI_BINNING,
3441             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3442             .ib = pipeline->vi.binning_state_ib,
3443          };
3444       draw_state_groups[draw_state_group_count++] =
3445          (struct tu_draw_state_group) {
3446             .id = TU_DRAW_STATE_VP,
3447             .enable_mask = ENABLE_ALL,
3448             .ib = pipeline->vp.state_ib,
3449          };
3450       draw_state_groups[draw_state_group_count++] =
3451          (struct tu_draw_state_group) {
3452             .id = TU_DRAW_STATE_RAST,
3453             .enable_mask = ENABLE_ALL,
3454             .ib = pipeline->rast.state_ib,
3455          };
3456       draw_state_groups[draw_state_group_count++] =
3457          (struct tu_draw_state_group) {
3458             .id = TU_DRAW_STATE_DS,
3459             .enable_mask = ENABLE_ALL,
3460             .ib = pipeline->ds.state_ib,
3461          };
3462       draw_state_groups[draw_state_group_count++] =
3463          (struct tu_draw_state_group) {
3464             .id = TU_DRAW_STATE_BLEND,
3465             .enable_mask = ENABLE_ALL,
3466             .ib = pipeline->blend.state_ib,
3467          };
3468    }
3469
3470    if (cmd->state.dirty &
3471          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3472       draw_state_groups[draw_state_group_count++] =
3473          (struct tu_draw_state_group) {
3474             .id = TU_DRAW_STATE_VS_CONST,
3475             .enable_mask = ENABLE_ALL,
3476             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3477          };
3478       draw_state_groups[draw_state_group_count++] =
3479          (struct tu_draw_state_group) {
3480             .id = TU_DRAW_STATE_FS_CONST,
3481             .enable_mask = ENABLE_DRAW,
3482             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3483          };
3484    }
3485
3486    if (cmd->state.dirty &
3487          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3488       bool needs_border = false;
3489       struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
3490
3491       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3492                                  MESA_SHADER_VERTEX, &vs_tex, &needs_border,
3493                                  false);
3494       if (result != VK_SUCCESS)
3495          return result;
3496
3497       /* TODO: we could emit just one texture descriptor draw state when there
3498        * are no input attachments, which is the most common case. We could
3499        * also split out the sampler state, which doesn't change even for input
3500        * attachments.
3501        */
3502       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3503                                  MESA_SHADER_FRAGMENT, &fs_tex_sysmem,
3504                                  &needs_border, true);
3505       if (result != VK_SUCCESS)
3506          return result;
3507
3508       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3509                                  MESA_SHADER_FRAGMENT, &fs_tex_gmem,
3510                                  &needs_border, false);
3511       if (result != VK_SUCCESS)
3512          return result;
3513
3514       result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3515                             MESA_SHADER_FRAGMENT, &fs_ibo);
3516       if (result != VK_SUCCESS)
3517          return result;
3518
3519       draw_state_groups[draw_state_group_count++] =
3520          (struct tu_draw_state_group) {
3521             .id = TU_DRAW_STATE_VS_TEX,
3522             .enable_mask = ENABLE_ALL,
3523             .ib = vs_tex,
3524          };
3525       draw_state_groups[draw_state_group_count++] =
3526          (struct tu_draw_state_group) {
3527             .id = TU_DRAW_STATE_FS_TEX_GMEM,
3528             .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3529             .ib = fs_tex_gmem,
3530          };
3531       draw_state_groups[draw_state_group_count++] =
3532          (struct tu_draw_state_group) {
3533             .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
3534             .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
3535             .ib = fs_tex_sysmem,
3536          };
3537       draw_state_groups[draw_state_group_count++] =
3538          (struct tu_draw_state_group) {
3539             .id = TU_DRAW_STATE_FS_IBO,
3540             .enable_mask = ENABLE_DRAW,
3541             .ib = fs_ibo,
3542          };
3543
3544       if (needs_border) {
3545          result = tu6_emit_border_color(cmd, cs);
3546          if (result != VK_SUCCESS)
3547             return result;
3548       }
3549    }
3550
3551    struct tu_cs_entry vs_params;
3552    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3553    if (result != VK_SUCCESS)
3554       return result;
3555
3556    draw_state_groups[draw_state_group_count++] =
3557       (struct tu_draw_state_group) {
3558          .id = TU_DRAW_STATE_VS_PARAMS,
3559          .enable_mask = ENABLE_ALL,
3560          .ib = vs_params,
3561       };
3562
3563    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3564    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3565       const struct tu_draw_state_group *group = &draw_state_groups[i];
3566       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3567       uint32_t cp_set_draw_state =
3568          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3569          group->enable_mask |
3570          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3571       uint64_t iova;
3572       if (group->ib.size) {
3573          iova = group->ib.bo->iova + group->ib.offset;
3574       } else {
3575          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3576          iova = 0;
3577       }
3578
3579       tu_cs_emit(cs, cp_set_draw_state);
3580       tu_cs_emit_qw(cs, iova);
3581    }
3582
3583    tu_cs_sanity_check(cs);
3584
3585    /* track BOs */
3586    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3587       for (uint32_t i = 0; i < MAX_VBS; i++) {
3588          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3589          if (buf)
3590             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3591       }
3592    }
3593    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3594       unsigned i;
3595       for_each_bit(i, descriptors_state->valid) {
3596          struct tu_descriptor_set *set = descriptors_state->sets[i];
3597          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3598             if (set->descriptors[j]) {
3599                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3600                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3601             }
3602       }
3603    }
3604
3605    /* Fragment shader state overwrites compute shader state, so flag the
3606     * compute pipeline for re-emit.
3607     */
3608    cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3609    return VK_SUCCESS;
3610 }
3611
3612 static void
3613 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3614                      struct tu_cs *cs,
3615                      const struct tu_draw_info *draw)
3616 {
3617
3618    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3619
3620    tu_cs_emit_regs(cs,
3621                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3622                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3623
3624    /* TODO hw binning */
3625    if (draw->indexed) {
3626       const enum a4xx_index_size index_size =
3627          tu6_index_size(cmd->state.index_type);
3628       const uint32_t index_bytes =
3629          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3630       const struct tu_buffer *buf = cmd->state.index_buffer;
3631       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3632                                   index_bytes * draw->first_index;
3633       const uint32_t size = index_bytes * draw->count;
3634
3635       const uint32_t cp_draw_indx =
3636          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3637          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3638          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3639          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3640
3641       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3642       tu_cs_emit(cs, cp_draw_indx);
3643       tu_cs_emit(cs, draw->instance_count);
3644       tu_cs_emit(cs, draw->count);
3645       tu_cs_emit(cs, 0x0); /* XXX */
3646       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3647       tu_cs_emit(cs, size);
3648    } else {
3649       const uint32_t cp_draw_indx =
3650          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3651          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3652          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3653
3654       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3655       tu_cs_emit(cs, cp_draw_indx);
3656       tu_cs_emit(cs, draw->instance_count);
3657       tu_cs_emit(cs, draw->count);
3658    }
3659 }
3660
3661 static void
3662 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3663 {
3664    struct tu_cs *cs = &cmd->draw_cs;
3665    VkResult result;
3666
3667    result = tu6_bind_draw_states(cmd, cs, draw);
3668    if (result != VK_SUCCESS) {
3669       cmd->record_result = result;
3670       return;
3671    }
3672
3673    if (draw->indirect) {
3674       tu_finishme("indirect draw");
3675       return;
3676    }
3677
3678    tu6_emit_draw_direct(cmd, cs, draw);
3679
3680    cmd->wait_for_idle = true;
3681
3682    tu_cs_sanity_check(cs);
3683 }
3684
3685 void
3686 tu_CmdDraw(VkCommandBuffer commandBuffer,
3687            uint32_t vertexCount,
3688            uint32_t instanceCount,
3689            uint32_t firstVertex,
3690            uint32_t firstInstance)
3691 {
3692    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3693    struct tu_draw_info info = {};
3694
3695    info.count = vertexCount;
3696    info.instance_count = instanceCount;
3697    info.first_instance = firstInstance;
3698    info.vertex_offset = firstVertex;
3699
3700    tu_draw(cmd_buffer, &info);
3701 }
3702
3703 void
3704 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3705                   uint32_t indexCount,
3706                   uint32_t instanceCount,
3707                   uint32_t firstIndex,
3708                   int32_t vertexOffset,
3709                   uint32_t firstInstance)
3710 {
3711    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3712    struct tu_draw_info info = {};
3713
3714    info.indexed = true;
3715    info.count = indexCount;
3716    info.instance_count = instanceCount;
3717    info.first_index = firstIndex;
3718    info.vertex_offset = vertexOffset;
3719    info.first_instance = firstInstance;
3720
3721    tu_draw(cmd_buffer, &info);
3722 }
3723
3724 void
3725 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3726                    VkBuffer _buffer,
3727                    VkDeviceSize offset,
3728                    uint32_t drawCount,
3729                    uint32_t stride)
3730 {
3731    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3732    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3733    struct tu_draw_info info = {};
3734
3735    info.count = drawCount;
3736    info.indirect = buffer;
3737    info.indirect_offset = offset;
3738    info.stride = stride;
3739
3740    tu_draw(cmd_buffer, &info);
3741 }
3742
3743 void
3744 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3745                           VkBuffer _buffer,
3746                           VkDeviceSize offset,
3747                           uint32_t drawCount,
3748                           uint32_t stride)
3749 {
3750    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3751    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3752    struct tu_draw_info info = {};
3753
3754    info.indexed = true;
3755    info.count = drawCount;
3756    info.indirect = buffer;
3757    info.indirect_offset = offset;
3758    info.stride = stride;
3759
3760    tu_draw(cmd_buffer, &info);
3761 }
3762
3763 struct tu_dispatch_info
3764 {
3765    /**
3766     * Determine the layout of the grid (in block units) to be used.
3767     */
3768    uint32_t blocks[3];
3769
3770    /**
3771     * A starting offset for the grid. If unaligned is set, the offset
3772     * must still be aligned.
3773     */
3774    uint32_t offsets[3];
3775    /**
3776     * Whether it's an unaligned compute dispatch.
3777     */
3778    bool unaligned;
3779
3780    /**
3781     * Indirect compute parameters resource.
3782     */
3783    struct tu_buffer *indirect;
3784    uint64_t indirect_offset;
3785 };
3786
3787 static void
3788 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3789                               const struct tu_dispatch_info *info)
3790 {
3791    gl_shader_stage type = MESA_SHADER_COMPUTE;
3792    const struct tu_program_descriptor_linkage *link =
3793       &pipeline->program.link[type];
3794    const struct ir3_const_state *const_state = &link->const_state;
3795    uint32_t offset = const_state->offsets.driver_param;
3796
3797    if (link->constlen <= offset)
3798       return;
3799
3800    if (!info->indirect) {
3801       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3802          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3803          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3804          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3805          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3806          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3807          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3808       };
3809
3810       uint32_t num_consts = MIN2(const_state->num_driver_params,
3811                                  (link->constlen - offset) * 4);
3812       /* push constants */
3813       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3814       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3815                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3816                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3817                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3818                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3819       tu_cs_emit(cs, 0);
3820       tu_cs_emit(cs, 0);
3821       uint32_t i;
3822       for (i = 0; i < num_consts; i++)
3823          tu_cs_emit(cs, driver_params[i]);
3824    } else {
3825       tu_finishme("Indirect driver params");
3826    }
3827 }
3828
3829 static void
3830 tu_dispatch(struct tu_cmd_buffer *cmd,
3831             const struct tu_dispatch_info *info)
3832 {
3833    struct tu_cs *cs = &cmd->cs;
3834    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3835    struct tu_descriptor_state *descriptors_state =
3836       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3837    VkResult result;
3838
3839    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3840       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3841
3842    struct tu_cs_entry ib;
3843
3844    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3845    if (ib.size)
3846       tu_cs_emit_ib(cs, &ib);
3847
3848    tu_emit_compute_driver_params(cs, pipeline, info);
3849
3850    bool needs_border;
3851    result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3852                               MESA_SHADER_COMPUTE, &ib, &needs_border, false);
3853    if (result != VK_SUCCESS) {
3854       cmd->record_result = result;
3855       return;
3856    }
3857
3858    if (ib.size)
3859       tu_cs_emit_ib(cs, &ib);
3860
3861    if (needs_border)
3862       tu_finishme("compute border color");
3863
3864    result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3865    if (result != VK_SUCCESS) {
3866       cmd->record_result = result;
3867       return;
3868    }
3869
3870    if (ib.size)
3871       tu_cs_emit_ib(cs, &ib);
3872
3873    /* track BOs */
3874    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3875       unsigned i;
3876       for_each_bit(i, descriptors_state->valid) {
3877          struct tu_descriptor_set *set = descriptors_state->sets[i];
3878          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3879             if (set->descriptors[j]) {
3880                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3881                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3882             }
3883       }
3884    }
3885
3886    /* Compute shader state overwrites fragment shader state, so we flag the
3887     * graphics pipeline for re-emit.
3888     */
3889    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3890
3891    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3892    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3893
3894    const uint32_t *local_size = pipeline->compute.local_size;
3895    const uint32_t *num_groups = info->blocks;
3896    tu_cs_emit_regs(cs,
3897                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3898                                           .localsizex = local_size[0] - 1,
3899                                           .localsizey = local_size[1] - 1,
3900                                           .localsizez = local_size[2] - 1),
3901                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3902                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3903                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3904                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3905                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3906                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3907
3908    tu_cs_emit_regs(cs,
3909                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3910                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3911                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3912
3913    if (info->indirect) {
3914       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3915
3916       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3917                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3918
3919       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3920       tu_cs_emit(cs, 0x00000000);
3921       tu_cs_emit_qw(cs, iova);
3922       tu_cs_emit(cs,
3923                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3924                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3925                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3926    } else {
3927       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3928       tu_cs_emit(cs, 0x00000000);
3929       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3930       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3931       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3932    }
3933
3934    tu_cs_emit_wfi(cs);
3935
3936    tu6_emit_cache_flush(cmd, cs);
3937 }
3938
3939 void
3940 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3941                    uint32_t base_x,
3942                    uint32_t base_y,
3943                    uint32_t base_z,
3944                    uint32_t x,
3945                    uint32_t y,
3946                    uint32_t z)
3947 {
3948    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3949    struct tu_dispatch_info info = {};
3950
3951    info.blocks[0] = x;
3952    info.blocks[1] = y;
3953    info.blocks[2] = z;
3954
3955    info.offsets[0] = base_x;
3956    info.offsets[1] = base_y;
3957    info.offsets[2] = base_z;
3958    tu_dispatch(cmd_buffer, &info);
3959 }
3960
3961 void
3962 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3963                uint32_t x,
3964                uint32_t y,
3965                uint32_t z)
3966 {
3967    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3968 }
3969
3970 void
3971 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3972                        VkBuffer _buffer,
3973                        VkDeviceSize offset)
3974 {
3975    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3976    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3977    struct tu_dispatch_info info = {};
3978
3979    info.indirect = buffer;
3980    info.indirect_offset = offset;
3981
3982    tu_dispatch(cmd_buffer, &info);
3983 }
3984
3985 void
3986 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3987 {
3988    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3989
3990    tu_cs_end(&cmd_buffer->draw_cs);
3991    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3992
3993    if (use_sysmem_rendering(cmd_buffer))
3994       tu_cmd_render_sysmem(cmd_buffer);
3995    else
3996       tu_cmd_render_tiles(cmd_buffer);
3997
3998    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3999       rendered */
4000    tu_cs_discard_entries(&cmd_buffer->draw_cs);
4001    tu_cs_begin(&cmd_buffer->draw_cs);
4002    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
4003    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
4004
4005    cmd_buffer->state.pass = NULL;
4006    cmd_buffer->state.subpass = NULL;
4007    cmd_buffer->state.framebuffer = NULL;
4008 }
4009
4010 void
4011 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
4012                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
4013 {
4014    tu_CmdEndRenderPass(commandBuffer);
4015 }
4016
4017 struct tu_barrier_info
4018 {
4019    uint32_t eventCount;
4020    const VkEvent *pEvents;
4021    VkPipelineStageFlags srcStageMask;
4022 };
4023
4024 static void
4025 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
4026            uint32_t memoryBarrierCount,
4027            const VkMemoryBarrier *pMemoryBarriers,
4028            uint32_t bufferMemoryBarrierCount,
4029            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4030            uint32_t imageMemoryBarrierCount,
4031            const VkImageMemoryBarrier *pImageMemoryBarriers,
4032            const struct tu_barrier_info *info)
4033 {
4034 }
4035
4036 void
4037 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
4038                       VkPipelineStageFlags srcStageMask,
4039                       VkPipelineStageFlags destStageMask,
4040                       VkBool32 byRegion,
4041                       uint32_t memoryBarrierCount,
4042                       const VkMemoryBarrier *pMemoryBarriers,
4043                       uint32_t bufferMemoryBarrierCount,
4044                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4045                       uint32_t imageMemoryBarrierCount,
4046                       const VkImageMemoryBarrier *pImageMemoryBarriers)
4047 {
4048    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4049    struct tu_barrier_info info;
4050
4051    info.eventCount = 0;
4052    info.pEvents = NULL;
4053    info.srcStageMask = srcStageMask;
4054
4055    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4056               bufferMemoryBarrierCount, pBufferMemoryBarriers,
4057               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4058 }
4059
4060 static void
4061 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
4062 {
4063    struct tu_cs *cs = &cmd->cs;
4064
4065    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
4066
4067    /* TODO: any flush required before/after ? */
4068
4069    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
4070    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
4071    tu_cs_emit(cs, value);
4072 }
4073
4074 void
4075 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
4076                VkEvent _event,
4077                VkPipelineStageFlags stageMask)
4078 {
4079    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4080    TU_FROM_HANDLE(tu_event, event, _event);
4081
4082    write_event(cmd, event, 1);
4083 }
4084
4085 void
4086 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
4087                  VkEvent _event,
4088                  VkPipelineStageFlags stageMask)
4089 {
4090    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4091    TU_FROM_HANDLE(tu_event, event, _event);
4092
4093    write_event(cmd, event, 0);
4094 }
4095
4096 void
4097 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
4098                  uint32_t eventCount,
4099                  const VkEvent *pEvents,
4100                  VkPipelineStageFlags srcStageMask,
4101                  VkPipelineStageFlags dstStageMask,
4102                  uint32_t memoryBarrierCount,
4103                  const VkMemoryBarrier *pMemoryBarriers,
4104                  uint32_t bufferMemoryBarrierCount,
4105                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4106                  uint32_t imageMemoryBarrierCount,
4107                  const VkImageMemoryBarrier *pImageMemoryBarriers)
4108 {
4109    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4110    struct tu_cs *cs = &cmd->cs;
4111
4112    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
4113
4114    for (uint32_t i = 0; i < eventCount; i++) {
4115       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
4116
4117       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
4118
4119       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
4120       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
4121                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
4122       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
4123       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
4124       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
4125       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
4126    }
4127 }
4128
4129 void
4130 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
4131 {
4132    /* No-op */
4133 }