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freedreno: Document CP_COND_REG_EXEC more
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32
33 #include "vk_format.h"
34
35 #include "tu_cs.h"
36 #include "tu_blit.h"
37
38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
39
40 void
41 tu_bo_list_init(struct tu_bo_list *list)
42 {
43 list->count = list->capacity = 0;
44 list->bo_infos = NULL;
45 }
46
47 void
48 tu_bo_list_destroy(struct tu_bo_list *list)
49 {
50 free(list->bo_infos);
51 }
52
53 void
54 tu_bo_list_reset(struct tu_bo_list *list)
55 {
56 list->count = 0;
57 }
58
59 /**
60 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
61 */
62 static uint32_t
63 tu_bo_list_add_info(struct tu_bo_list *list,
64 const struct drm_msm_gem_submit_bo *bo_info)
65 {
66 assert(bo_info->handle != 0);
67
68 for (uint32_t i = 0; i < list->count; ++i) {
69 if (list->bo_infos[i].handle == bo_info->handle) {
70 assert(list->bo_infos[i].presumed == bo_info->presumed);
71 list->bo_infos[i].flags |= bo_info->flags;
72 return i;
73 }
74 }
75
76 /* grow list->bo_infos if needed */
77 if (list->count == list->capacity) {
78 uint32_t new_capacity = MAX2(2 * list->count, 16);
79 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
80 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
81 if (!new_bo_infos)
82 return TU_BO_LIST_FAILED;
83 list->bo_infos = new_bo_infos;
84 list->capacity = new_capacity;
85 }
86
87 list->bo_infos[list->count] = *bo_info;
88 return list->count++;
89 }
90
91 uint32_t
92 tu_bo_list_add(struct tu_bo_list *list,
93 const struct tu_bo *bo,
94 uint32_t flags)
95 {
96 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
97 .flags = flags,
98 .handle = bo->gem_handle,
99 .presumed = bo->iova,
100 });
101 }
102
103 VkResult
104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
105 {
106 for (uint32_t i = 0; i < other->count; i++) {
107 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
108 return VK_ERROR_OUT_OF_HOST_MEMORY;
109 }
110
111 return VK_SUCCESS;
112 }
113
114 static void
115 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
116 const struct tu_device *dev,
117 uint32_t pixels)
118 {
119 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
120 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
121 const uint32_t max_tile_width = 1024; /* A6xx */
122
123 tiling->tile0.offset = (VkOffset2D) {
124 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
125 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
126 };
127
128 const uint32_t ra_width =
129 tiling->render_area.extent.width +
130 (tiling->render_area.offset.x - tiling->tile0.offset.x);
131 const uint32_t ra_height =
132 tiling->render_area.extent.height +
133 (tiling->render_area.offset.y - tiling->tile0.offset.y);
134
135 /* start from 1 tile */
136 tiling->tile_count = (VkExtent2D) {
137 .width = 1,
138 .height = 1,
139 };
140 tiling->tile0.extent = (VkExtent2D) {
141 .width = align(ra_width, tile_align_w),
142 .height = align(ra_height, tile_align_h),
143 };
144
145 /* do not exceed max tile width */
146 while (tiling->tile0.extent.width > max_tile_width) {
147 tiling->tile_count.width++;
148 tiling->tile0.extent.width =
149 align(ra_width / tiling->tile_count.width, tile_align_w);
150 }
151
152 /* do not exceed gmem size */
153 while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
154 if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
155 tiling->tile_count.width++;
156 tiling->tile0.extent.width =
157 align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
158 } else {
159 /* if this assert fails then layout is impossible.. */
160 assert(tiling->tile0.extent.height > tile_align_h);
161 tiling->tile_count.height++;
162 tiling->tile0.extent.height =
163 align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
164 }
165 }
166 }
167
168 static void
169 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
170 const struct tu_device *dev)
171 {
172 const uint32_t max_pipe_count = 32; /* A6xx */
173
174 /* start from 1 tile per pipe */
175 tiling->pipe0 = (VkExtent2D) {
176 .width = 1,
177 .height = 1,
178 };
179 tiling->pipe_count = tiling->tile_count;
180
181 /* do not exceed max pipe count vertically */
182 while (tiling->pipe_count.height > max_pipe_count) {
183 tiling->pipe0.height += 2;
184 tiling->pipe_count.height =
185 (tiling->tile_count.height + tiling->pipe0.height - 1) /
186 tiling->pipe0.height;
187 }
188
189 /* do not exceed max pipe count */
190 while (tiling->pipe_count.width * tiling->pipe_count.height >
191 max_pipe_count) {
192 tiling->pipe0.width += 1;
193 tiling->pipe_count.width =
194 (tiling->tile_count.width + tiling->pipe0.width - 1) /
195 tiling->pipe0.width;
196 }
197 }
198
199 static void
200 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
201 const struct tu_device *dev)
202 {
203 const uint32_t max_pipe_count = 32; /* A6xx */
204 const uint32_t used_pipe_count =
205 tiling->pipe_count.width * tiling->pipe_count.height;
206 const VkExtent2D last_pipe = {
207 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
208 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
209 };
210
211 assert(used_pipe_count <= max_pipe_count);
212 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
213
214 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
215 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
216 const uint32_t pipe_x = tiling->pipe0.width * x;
217 const uint32_t pipe_y = tiling->pipe0.height * y;
218 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
219 ? last_pipe.width
220 : tiling->pipe0.width;
221 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
222 ? last_pipe.height
223 : tiling->pipe0.height;
224 const uint32_t n = tiling->pipe_count.width * y + x;
225
226 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
227 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
228 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
229 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
230 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
231 }
232 }
233
234 memset(tiling->pipe_config + used_pipe_count, 0,
235 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
236 }
237
238 static void
239 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
240 const struct tu_device *dev,
241 uint32_t tx,
242 uint32_t ty,
243 struct tu_tile *tile)
244 {
245 /* find the pipe and the slot for tile (tx, ty) */
246 const uint32_t px = tx / tiling->pipe0.width;
247 const uint32_t py = ty / tiling->pipe0.height;
248 const uint32_t sx = tx - tiling->pipe0.width * px;
249 const uint32_t sy = ty - tiling->pipe0.height * py;
250
251 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
252 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
253 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
254
255 /* convert to 1D indices */
256 tile->pipe = tiling->pipe_count.width * py + px;
257 tile->slot = tiling->pipe0.width * sy + sx;
258
259 /* get the blit area for the tile */
260 tile->begin = (VkOffset2D) {
261 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
262 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
263 };
264 tile->end.x =
265 (tx == tiling->tile_count.width - 1)
266 ? tiling->render_area.offset.x + tiling->render_area.extent.width
267 : tile->begin.x + tiling->tile0.extent.width;
268 tile->end.y =
269 (ty == tiling->tile_count.height - 1)
270 ? tiling->render_area.offset.y + tiling->render_area.extent.height
271 : tile->begin.y + tiling->tile0.extent.height;
272 }
273
274 enum a3xx_msaa_samples
275 tu_msaa_samples(uint32_t samples)
276 {
277 switch (samples) {
278 case 1:
279 return MSAA_ONE;
280 case 2:
281 return MSAA_TWO;
282 case 4:
283 return MSAA_FOUR;
284 case 8:
285 return MSAA_EIGHT;
286 default:
287 assert(!"invalid sample count");
288 return MSAA_ONE;
289 }
290 }
291
292 static enum a4xx_index_size
293 tu6_index_size(VkIndexType type)
294 {
295 switch (type) {
296 case VK_INDEX_TYPE_UINT16:
297 return INDEX4_SIZE_16_BIT;
298 case VK_INDEX_TYPE_UINT32:
299 return INDEX4_SIZE_32_BIT;
300 default:
301 unreachable("invalid VkIndexType");
302 return INDEX4_SIZE_8_BIT;
303 }
304 }
305
306 static void
307 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
308 {
309 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
310 }
311
312 unsigned
313 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
314 struct tu_cs *cs,
315 enum vgt_event_type event,
316 bool need_seqno)
317 {
318 unsigned seqno = 0;
319
320 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
321 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
322 if (need_seqno) {
323 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
324 seqno = ++cmd->scratch_seqno;
325 tu_cs_emit(cs, seqno);
326 }
327
328 return seqno;
329 }
330
331 static void
332 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
333 {
334 tu6_emit_event_write(cmd, cs, 0x31, false);
335 }
336
337 static void
338 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
339 {
340 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
341 }
342
343 static void
344 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
345 {
346 if (cmd->wait_for_idle) {
347 tu_cs_emit_wfi(cs);
348 cmd->wait_for_idle = false;
349 }
350 }
351
352 #define tu_image_view_ubwc_pitches(iview) \
353 .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
354 .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
355
356 static void
357 tu6_emit_zs(struct tu_cmd_buffer *cmd,
358 const struct tu_subpass *subpass,
359 struct tu_cs *cs)
360 {
361 const struct tu_framebuffer *fb = cmd->state.framebuffer;
362
363 const uint32_t a = subpass->depth_stencil_attachment.attachment;
364 if (a == VK_ATTACHMENT_UNUSED) {
365 tu_cs_emit_regs(cs,
366 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
367 A6XX_RB_DEPTH_BUFFER_PITCH(0),
368 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
369 A6XX_RB_DEPTH_BUFFER_BASE(0),
370 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
371
372 tu_cs_emit_regs(cs,
373 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
374
375 tu_cs_emit_regs(cs,
376 A6XX_GRAS_LRZ_BUFFER_BASE(0),
377 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
378 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
379
380 tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
381
382 return;
383 }
384
385 const struct tu_image_view *iview = fb->attachments[a].attachment;
386 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
387
388 tu_cs_emit_regs(cs,
389 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
390 A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
391 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
392 A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
393 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
394
395 tu_cs_emit_regs(cs,
396 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
397
398 tu_cs_emit_regs(cs,
399 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
401
402 tu_cs_emit_regs(cs,
403 A6XX_GRAS_LRZ_BUFFER_BASE(0),
404 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
405 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
406
407 tu_cs_emit_regs(cs,
408 A6XX_RB_STENCIL_INFO(0));
409
410 /* enable zs? */
411 }
412
413 static void
414 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
415 const struct tu_subpass *subpass,
416 struct tu_cs *cs)
417 {
418 const struct tu_framebuffer *fb = cmd->state.framebuffer;
419 unsigned char mrt_comp[MAX_RTS] = { 0 };
420 unsigned srgb_cntl = 0;
421
422 for (uint32_t i = 0; i < subpass->color_count; ++i) {
423 uint32_t a = subpass->color_attachments[i].attachment;
424 if (a == VK_ATTACHMENT_UNUSED)
425 continue;
426
427 const struct tu_image_view *iview = fb->attachments[a].attachment;
428 const enum a6xx_tile_mode tile_mode =
429 tu6_get_image_tile_mode(iview->image, iview->base_mip);
430
431 mrt_comp[i] = 0xf;
432
433 if (vk_format_is_srgb(iview->vk_format))
434 srgb_cntl |= (1 << i);
435
436 const struct tu_native_format *format =
437 tu6_get_native_format(iview->vk_format);
438 assert(format && format->rb >= 0);
439
440 tu_cs_emit_regs(cs,
441 A6XX_RB_MRT_BUF_INFO(i,
442 .color_tile_mode = tile_mode,
443 .color_format = format->rb,
444 .color_swap = format->swap),
445 A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
446 A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
447 A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
448 A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
449
450 tu_cs_emit_regs(cs,
451 A6XX_SP_FS_MRT_REG(i,
452 .color_format = format->rb,
453 .color_sint = vk_format_is_sint(iview->vk_format),
454 .color_uint = vk_format_is_uint(iview->vk_format)));
455
456 tu_cs_emit_regs(cs,
457 A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
458 A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
459 }
460
461 tu_cs_emit_regs(cs,
462 A6XX_RB_SRGB_CNTL(srgb_cntl));
463
464 tu_cs_emit_regs(cs,
465 A6XX_SP_SRGB_CNTL(srgb_cntl));
466
467 tu_cs_emit_regs(cs,
468 A6XX_RB_RENDER_COMPONENTS(
469 .rt0 = mrt_comp[0],
470 .rt1 = mrt_comp[1],
471 .rt2 = mrt_comp[2],
472 .rt3 = mrt_comp[3],
473 .rt4 = mrt_comp[4],
474 .rt5 = mrt_comp[5],
475 .rt6 = mrt_comp[6],
476 .rt7 = mrt_comp[7]));
477
478 tu_cs_emit_regs(cs,
479 A6XX_SP_FS_RENDER_COMPONENTS(
480 .rt0 = mrt_comp[0],
481 .rt1 = mrt_comp[1],
482 .rt2 = mrt_comp[2],
483 .rt3 = mrt_comp[3],
484 .rt4 = mrt_comp[4],
485 .rt5 = mrt_comp[5],
486 .rt6 = mrt_comp[6],
487 .rt7 = mrt_comp[7]));
488 }
489
490 static void
491 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
492 const struct tu_subpass *subpass,
493 struct tu_cs *cs)
494 {
495 const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
496 bool msaa_disable = samples == MSAA_ONE;
497
498 tu_cs_emit_regs(cs,
499 A6XX_SP_TP_RAS_MSAA_CNTL(samples),
500 A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
501 .msaa_disable = msaa_disable));
502
503 tu_cs_emit_regs(cs,
504 A6XX_GRAS_RAS_MSAA_CNTL(samples),
505 A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
506 .msaa_disable = msaa_disable));
507
508 tu_cs_emit_regs(cs,
509 A6XX_RB_RAS_MSAA_CNTL(samples),
510 A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
511 .msaa_disable = msaa_disable));
512
513 tu_cs_emit_regs(cs,
514 A6XX_RB_MSAA_CNTL(samples));
515 }
516
517 static void
518 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
519 {
520 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
521 const uint32_t bin_w = tiling->tile0.extent.width;
522 const uint32_t bin_h = tiling->tile0.extent.height;
523
524 tu_cs_emit_regs(cs,
525 A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
526 .binh = bin_h,
527 .dword = flags));
528
529 tu_cs_emit_regs(cs,
530 A6XX_RB_BIN_CONTROL(.binw = bin_w,
531 .binh = bin_h,
532 .dword = flags));
533
534 /* no flag for RB_BIN_CONTROL2... */
535 tu_cs_emit_regs(cs,
536 A6XX_RB_BIN_CONTROL2(.binw = bin_w,
537 .binh = bin_h));
538 }
539
540 static void
541 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
542 struct tu_cs *cs,
543 bool binning)
544 {
545 uint32_t cntl = 0;
546 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
547 if (binning)
548 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
549
550 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
551 tu_cs_emit(cs, 0x2);
552 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
553 tu_cs_emit(cs, cntl);
554 }
555
556 static void
557 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
558 {
559 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
560 uint32_t x1 = render_area->offset.x;
561 uint32_t y1 = render_area->offset.y;
562 uint32_t x2 = x1 + render_area->extent.width - 1;
563 uint32_t y2 = y1 + render_area->extent.height - 1;
564
565 /* TODO: alignment requirement seems to be less than tile_align_w/h */
566 if (align) {
567 x1 = x1 & ~cmd->device->physical_device->tile_align_w;
568 y1 = y1 & ~cmd->device->physical_device->tile_align_h;
569 x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
570 y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
571 }
572
573 tu_cs_emit_regs(cs,
574 A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
575 A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
576 }
577
578 static void
579 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
580 struct tu_cs *cs,
581 const struct tu_image_view *iview,
582 uint32_t gmem_offset,
583 bool resolve)
584 {
585 tu_cs_emit_regs(cs,
586 A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
587
588 const struct tu_native_format *format =
589 tu6_get_native_format(iview->vk_format);
590 assert(format && format->rb >= 0);
591
592 enum a6xx_tile_mode tile_mode =
593 tu6_get_image_tile_mode(iview->image, iview->base_mip);
594 tu_cs_emit_regs(cs,
595 A6XX_RB_BLIT_DST_INFO(
596 .tile_mode = tile_mode,
597 .samples = tu_msaa_samples(iview->image->samples),
598 .color_format = format->rb,
599 .color_swap = format->swap,
600 .flags = iview->image->layout.ubwc_size != 0),
601 A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
602 A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
603 A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
604
605 if (iview->image->layout.ubwc_size) {
606 tu_cs_emit_regs(cs,
607 A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
608 A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
609 }
610
611 tu_cs_emit_regs(cs,
612 A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
613 }
614
615 static void
616 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
617 {
618 tu6_emit_marker(cmd, cs);
619 tu6_emit_event_write(cmd, cs, BLIT, false);
620 tu6_emit_marker(cmd, cs);
621 }
622
623 static void
624 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
625 struct tu_cs *cs,
626 uint32_t x1,
627 uint32_t y1,
628 uint32_t x2,
629 uint32_t y2)
630 {
631 tu_cs_emit_regs(cs,
632 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
633 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
634
635 tu_cs_emit_regs(cs,
636 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
637 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
638 }
639
640 static void
641 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
642 struct tu_cs *cs,
643 uint32_t x1,
644 uint32_t y1)
645 {
646 tu_cs_emit_regs(cs,
647 A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
648
649 tu_cs_emit_regs(cs,
650 A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
651
652 tu_cs_emit_regs(cs,
653 A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
654
655 tu_cs_emit_regs(cs,
656 A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
657 }
658
659 static bool
660 use_hw_binning(struct tu_cmd_buffer *cmd)
661 {
662 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
663
664 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
665 return false;
666
667 return (tiling->tile_count.width * tiling->tile_count.height) > 2;
668 }
669
670 static void
671 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
672 struct tu_cs *cs,
673 const struct tu_tile *tile)
674 {
675 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
676 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
677
678 tu6_emit_marker(cmd, cs);
679 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
680 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
681 tu6_emit_marker(cmd, cs);
682
683 const uint32_t x1 = tile->begin.x;
684 const uint32_t y1 = tile->begin.y;
685 const uint32_t x2 = tile->end.x - 1;
686 const uint32_t y2 = tile->end.y - 1;
687 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
688 tu6_emit_window_offset(cmd, cs, x1, y1);
689
690 tu_cs_emit_regs(cs,
691 A6XX_VPC_SO_OVERRIDE(.so_disable = true));
692
693 if (use_hw_binning(cmd)) {
694 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
695
696 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
697 tu_cs_emit(cs, 0x0);
698
699 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
700 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
701 A6XX_CP_REG_TEST_0_BIT(0) |
702 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
703
704 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
705 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
706 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
707
708 /* if (no overflow) */ {
709 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
710 tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
711 CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
712 tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
713 tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
714 tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
715
716 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
717 tu_cs_emit(cs, 0x0);
718
719 /* use a NOP packet to skip over the 'else' side: */
720 tu_cs_emit_pkt7(cs, CP_NOP, 2);
721 } /* else */ {
722 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
723 tu_cs_emit(cs, 0x1);
724 }
725
726 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
727 tu_cs_emit(cs, 0x0);
728
729 tu_cs_emit_regs(cs,
730 A6XX_RB_UNKNOWN_8804(0));
731
732 tu_cs_emit_regs(cs,
733 A6XX_SP_TP_UNKNOWN_B304(0));
734
735 tu_cs_emit_regs(cs,
736 A6XX_GRAS_UNKNOWN_80A4(0));
737 } else {
738 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
739 tu_cs_emit(cs, 0x1);
740
741 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
742 tu_cs_emit(cs, 0x0);
743 }
744 }
745
746 static void
747 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
748 {
749 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
750 const struct tu_framebuffer *fb = cmd->state.framebuffer;
751 const struct tu_image_view *iview = fb->attachments[a].attachment;
752 const struct tu_render_pass_attachment *attachment =
753 &cmd->state.pass->attachments[a];
754
755 if (attachment->gmem_offset < 0)
756 return;
757
758 const uint32_t x1 = tiling->render_area.offset.x;
759 const uint32_t y1 = tiling->render_area.offset.y;
760 const uint32_t x2 = x1 + tiling->render_area.extent.width;
761 const uint32_t y2 = y1 + tiling->render_area.extent.height;
762 const uint32_t tile_x2 =
763 tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
764 const uint32_t tile_y2 =
765 tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
766 bool need_load =
767 x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
768 y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
769
770 if (need_load)
771 tu_finishme("improve handling of unaligned render area");
772
773 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
774 need_load = true;
775
776 if (vk_format_has_stencil(iview->vk_format) &&
777 attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
778 need_load = true;
779
780 if (need_load) {
781 tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
782 tu6_emit_blit(cmd, cs);
783 }
784 }
785
786 static void
787 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
788 uint32_t a,
789 const VkRenderPassBeginInfo *info)
790 {
791 const struct tu_framebuffer *fb = cmd->state.framebuffer;
792 const struct tu_image_view *iview = fb->attachments[a].attachment;
793 const struct tu_render_pass_attachment *attachment =
794 &cmd->state.pass->attachments[a];
795 unsigned clear_mask = 0;
796
797 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
798 if (attachment->gmem_offset < 0)
799 return;
800
801 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
802 clear_mask = 0xf;
803
804 if (vk_format_has_stencil(iview->vk_format)) {
805 clear_mask &= 0x1;
806 if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
807 clear_mask |= 0x2;
808 }
809 if (!clear_mask)
810 return;
811
812 const struct tu_native_format *format =
813 tu6_get_native_format(iview->vk_format);
814 assert(format && format->rb >= 0);
815
816 tu_cs_emit_regs(cs,
817 A6XX_RB_BLIT_DST_INFO(.color_format = format->rb));
818
819 tu_cs_emit_regs(cs,
820 A6XX_RB_BLIT_INFO(.gmem = true,
821 .clear_mask = clear_mask));
822
823 tu_cs_emit_regs(cs,
824 A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
825
826 tu_cs_emit_regs(cs,
827 A6XX_RB_UNKNOWN_88D0(0));
828
829 uint32_t clear_vals[4] = { 0 };
830 tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
831
832 tu_cs_emit_regs(cs,
833 A6XX_RB_BLIT_CLEAR_COLOR_DW0(clear_vals[0]),
834 A6XX_RB_BLIT_CLEAR_COLOR_DW1(clear_vals[1]),
835 A6XX_RB_BLIT_CLEAR_COLOR_DW2(clear_vals[2]),
836 A6XX_RB_BLIT_CLEAR_COLOR_DW3(clear_vals[3]));
837
838 tu6_emit_blit(cmd, cs);
839 }
840
841 static void
842 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
843 struct tu_cs *cs,
844 uint32_t a,
845 uint32_t gmem_a)
846 {
847 if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
848 return;
849
850 tu6_emit_blit_info(cmd, cs,
851 cmd->state.framebuffer->attachments[a].attachment,
852 cmd->state.pass->attachments[gmem_a].gmem_offset, true);
853 tu6_emit_blit(cmd, cs);
854 }
855
856 static void
857 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
858 {
859 const struct tu_render_pass *pass = cmd->state.pass;
860 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
861
862 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
863 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
864 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
865 CP_SET_DRAW_STATE__0_GROUP_ID(0));
866 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
867 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
868
869 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
870 tu_cs_emit(cs, 0x0);
871
872 tu6_emit_marker(cmd, cs);
873 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
874 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
875 tu6_emit_marker(cmd, cs);
876
877 tu6_emit_blit_scissor(cmd, cs, true);
878
879 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
880 if (pass->attachments[a].gmem_offset >= 0)
881 tu6_emit_store_attachment(cmd, cs, a, a);
882 }
883
884 if (subpass->resolve_attachments) {
885 for (unsigned i = 0; i < subpass->color_count; i++) {
886 uint32_t a = subpass->resolve_attachments[i].attachment;
887 if (a != VK_ATTACHMENT_UNUSED)
888 tu6_emit_store_attachment(cmd, cs, a,
889 subpass->color_attachments[i].attachment);
890 }
891 }
892 }
893
894 static void
895 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
896 {
897 tu_cs_emit_regs(cs,
898 A6XX_PC_RESTART_INDEX(restart_index));
899 }
900
901 static void
902 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
903 {
904 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
905 if (result != VK_SUCCESS) {
906 cmd->record_result = result;
907 return;
908 }
909
910 tu6_emit_cache_flush(cmd, cs);
911
912 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
913
914 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
915 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
916 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
917 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
918 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
919 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
920 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
921 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
922 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
923
924 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
926 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
928 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
930 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
932 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
935 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
937 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
938
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
940
941 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
942 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
943 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
944
945 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
946 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
947 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
948 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
949 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
950 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
951 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
952 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
953 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
954 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
955 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
956 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
957
958 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
959 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
960
961 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
962 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
963
964 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
965 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
966
967 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
970
971 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
972 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
973
974 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
975
976 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
981 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
983 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
984 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
985 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
986 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
987 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
988 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
989 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
990 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
991 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
992 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
993 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
994 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
995 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
996 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
997 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
998 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
999
1000 tu6_emit_marker(cmd, cs);
1001
1002 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1003
1004 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1005
1006 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1007
1008 /* we don't use this yet.. probably best to disable.. */
1009 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1010 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1011 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1012 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1013 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1014 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1015
1016 tu_cs_emit_regs(cs,
1017 A6XX_VPC_SO_BUFFER_BASE(0),
1018 A6XX_VPC_SO_BUFFER_SIZE(0));
1019
1020 tu_cs_emit_regs(cs,
1021 A6XX_VPC_SO_FLUSH_BASE(0));
1022
1023 tu_cs_emit_regs(cs,
1024 A6XX_VPC_SO_BUF_CNTL(0));
1025
1026 tu_cs_emit_regs(cs,
1027 A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1028
1029 tu_cs_emit_regs(cs,
1030 A6XX_VPC_SO_BUFFER_BASE(1, 0),
1031 A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1032
1033 tu_cs_emit_regs(cs,
1034 A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1035 A6XX_VPC_SO_FLUSH_BASE(1, 0),
1036 A6XX_VPC_SO_BUFFER_BASE(2, 0),
1037 A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1038
1039 tu_cs_emit_regs(cs,
1040 A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1041 A6XX_VPC_SO_FLUSH_BASE(2, 0),
1042 A6XX_VPC_SO_BUFFER_BASE(3, 0),
1043 A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1044
1045 tu_cs_emit_regs(cs,
1046 A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1047 A6XX_VPC_SO_FLUSH_BASE(3, 0));
1048
1049 tu_cs_emit_regs(cs,
1050 A6XX_SP_HS_CTRL_REG0(0));
1051
1052 tu_cs_emit_regs(cs,
1053 A6XX_SP_GS_CTRL_REG0(0));
1054
1055 tu_cs_emit_regs(cs,
1056 A6XX_GRAS_LRZ_CNTL(0));
1057
1058 tu_cs_emit_regs(cs,
1059 A6XX_RB_LRZ_CNTL(0));
1060
1061 tu_cs_sanity_check(cs);
1062 }
1063
1064 static void
1065 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1066 {
1067 unsigned seqno;
1068
1069 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1070
1071 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1072 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1073 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1074 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1075 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1076 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1077 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1078
1079 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1080
1081 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1082 tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1083 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1084 tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1085 }
1086
1087 static void
1088 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1089 {
1090 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1091
1092 tu_cs_emit_regs(cs,
1093 A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1094 .height = tiling->tile0.extent.height),
1095 A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data, .bo_offset = cmd->vsc_data_pitch));
1096
1097 tu_cs_emit_regs(cs,
1098 A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1099 .ny = tiling->tile_count.height));
1100
1101 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1102 for (unsigned i = 0; i < 32; i++)
1103 tu_cs_emit(cs, tiling->pipe_config[i]);
1104
1105 tu_cs_emit_regs(cs,
1106 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1107 A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1108 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1109
1110 tu_cs_emit_regs(cs,
1111 A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1112 A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1113 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1114 }
1115
1116 static void
1117 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1118 {
1119 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1120 const uint32_t used_pipe_count =
1121 tiling->pipe_count.width * tiling->pipe_count.height;
1122
1123 /* Clear vsc_scratch: */
1124 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1125 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1126 tu_cs_emit(cs, 0x0);
1127
1128 /* Check for overflow, write vsc_scratch if detected: */
1129 for (int i = 0; i < used_pipe_count; i++) {
1130 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1131 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1132 CP_COND_WRITE5_0_WRITE_MEMORY);
1133 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1134 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1135 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1136 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1137 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1138 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1139
1140 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1141 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1142 CP_COND_WRITE5_0_WRITE_MEMORY);
1143 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1144 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1145 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1146 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1147 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1148 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1149 }
1150
1151 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1152
1153 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1154
1155 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1156 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1157 CP_MEM_TO_REG_0_CNT(1 - 1));
1158 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1159
1160 /*
1161 * This is a bit awkward, we really want a way to invert the
1162 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1163 * execute cmds to use hwbinning when a bit is *not* set. This
1164 * dance is to invert OVERFLOW_FLAG_REG
1165 *
1166 * A CP_NOP packet is used to skip executing the 'else' clause
1167 * if (b0 set)..
1168 */
1169
1170 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1171 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1172 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1173 A6XX_CP_REG_TEST_0_BIT(0) |
1174 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1175
1176 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1177 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1178 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1179
1180 /* if (b0 set) */ {
1181 /*
1182 * On overflow, mirror the value to control->vsc_overflow
1183 * which CPU is checking to detect overflow (see
1184 * check_vsc_overflow())
1185 */
1186 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1187 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1188 CP_REG_TO_MEM_0_CNT(0));
1189 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1190
1191 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1192 tu_cs_emit(cs, 0x0);
1193
1194 tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
1195 } /* else */ {
1196 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1197 tu_cs_emit(cs, 0x1);
1198 }
1199 }
1200
1201 static void
1202 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1203 {
1204 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1205
1206 uint32_t x1 = tiling->tile0.offset.x;
1207 uint32_t y1 = tiling->tile0.offset.y;
1208 uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1209 uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1210
1211 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1212
1213 tu6_emit_marker(cmd, cs);
1214 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1215 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1216 tu6_emit_marker(cmd, cs);
1217
1218 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1219 tu_cs_emit(cs, 0x1);
1220
1221 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1222 tu_cs_emit(cs, 0x1);
1223
1224 tu_cs_emit_wfi(cs);
1225
1226 tu_cs_emit_regs(cs,
1227 A6XX_VFD_MODE_CNTL(.binning_pass = true));
1228
1229 update_vsc_pipe(cmd, cs);
1230
1231 tu_cs_emit_regs(cs,
1232 A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
1233
1234 tu_cs_emit_regs(cs,
1235 A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
1236
1237 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1238 tu_cs_emit(cs, UNK_2C);
1239
1240 tu_cs_emit_regs(cs,
1241 A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1242
1243 tu_cs_emit_regs(cs,
1244 A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1245
1246 /* emit IB to binning drawcmds: */
1247 tu_cs_emit_call(cs, &cmd->draw_cs);
1248
1249 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1250 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1251 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1252 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1253 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1254 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1255
1256 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1257 tu_cs_emit(cs, UNK_2D);
1258
1259 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1260 tu6_cache_flush(cmd, cs);
1261
1262 tu_cs_emit_wfi(cs);
1263
1264 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1265
1266 emit_vsc_overflow_test(cmd, cs);
1267
1268 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1269 tu_cs_emit(cs, 0x0);
1270
1271 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1272 tu_cs_emit(cs, 0x0);
1273
1274 tu_cs_emit_wfi(cs);
1275
1276 tu_cs_emit_regs(cs,
1277 A6XX_RB_CCU_CNTL(.unknown = 0x7c400004));
1278
1279 cmd->wait_for_idle = false;
1280 }
1281
1282 static void
1283 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1284 {
1285 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1286 if (result != VK_SUCCESS) {
1287 cmd->record_result = result;
1288 return;
1289 }
1290
1291 tu6_emit_lrz_flush(cmd, cs);
1292
1293 /* lrz clear? */
1294
1295 tu6_emit_cache_flush(cmd, cs);
1296
1297 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1298 tu_cs_emit(cs, 0x0);
1299
1300 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1301 tu6_emit_wfi(cmd, cs);
1302 tu_cs_emit_regs(cs,
1303 A6XX_RB_CCU_CNTL(0x7c400004));
1304
1305 if (use_hw_binning(cmd)) {
1306 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1307
1308 tu6_emit_render_cntl(cmd, cs, true);
1309
1310 tu6_emit_binning_pass(cmd, cs);
1311
1312 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1313
1314 tu_cs_emit_regs(cs,
1315 A6XX_VFD_MODE_CNTL(0));
1316
1317 tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
1318
1319 tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
1320
1321 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1322 tu_cs_emit(cs, 0x1);
1323 } else {
1324 tu6_emit_bin_size(cmd, cs, 0x6000000);
1325 }
1326
1327 tu6_emit_render_cntl(cmd, cs, false);
1328
1329 tu_cs_sanity_check(cs);
1330 }
1331
1332 static void
1333 tu6_render_tile(struct tu_cmd_buffer *cmd,
1334 struct tu_cs *cs,
1335 const struct tu_tile *tile)
1336 {
1337 const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1338 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1339 if (result != VK_SUCCESS) {
1340 cmd->record_result = result;
1341 return;
1342 }
1343
1344 tu6_emit_tile_select(cmd, cs, tile);
1345 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1346
1347 tu_cs_emit_call(cs, &cmd->draw_cs);
1348 cmd->wait_for_idle = true;
1349
1350 if (use_hw_binning(cmd)) {
1351 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1352 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1353 A6XX_CP_REG_TEST_0_BIT(0) |
1354 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1355
1356 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1357 tu_cs_emit(cs, 0x10000000);
1358 tu_cs_emit(cs, 2); /* conditionally execute next 2 dwords */
1359
1360 /* if (no overflow) */ {
1361 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1362 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1363 }
1364 }
1365
1366 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1367
1368 tu_cs_sanity_check(cs);
1369 }
1370
1371 static void
1372 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1373 {
1374 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1375 if (result != VK_SUCCESS) {
1376 cmd->record_result = result;
1377 return;
1378 }
1379
1380 tu_cs_emit_regs(cs,
1381 A6XX_GRAS_LRZ_CNTL(0));
1382
1383 tu6_emit_lrz_flush(cmd, cs);
1384
1385 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1386
1387 tu_cs_sanity_check(cs);
1388 }
1389
1390 static void
1391 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1392 {
1393 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1394
1395 tu6_render_begin(cmd, &cmd->cs);
1396
1397 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1398 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1399 struct tu_tile tile;
1400 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1401 tu6_render_tile(cmd, &cmd->cs, &tile);
1402 }
1403 }
1404
1405 tu6_render_end(cmd, &cmd->cs);
1406 }
1407
1408 static void
1409 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1410 const VkRenderPassBeginInfo *info)
1411 {
1412 const uint32_t tile_load_space =
1413 8 + (23+19) * cmd->state.pass->attachment_count +
1414 21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1415
1416 struct tu_cs sub_cs;
1417
1418 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1419 tile_load_space, &sub_cs);
1420 if (result != VK_SUCCESS) {
1421 cmd->record_result = result;
1422 return;
1423 }
1424
1425 tu6_emit_blit_scissor(cmd, &sub_cs, true);
1426
1427 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1428 tu6_emit_load_attachment(cmd, &sub_cs, i);
1429
1430 tu6_emit_blit_scissor(cmd, &sub_cs, false);
1431
1432 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1433 tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1434
1435 /* invalidate because reading input attachments will cache GMEM and
1436 * the cache isn''t updated when GMEM is written
1437 * TODO: is there a no-cache bit for textures?
1438 */
1439 if (cmd->state.subpass->input_count)
1440 tu6_emit_event_write(cmd, &sub_cs, CACHE_INVALIDATE, false);
1441
1442 tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1443 tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1444 tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1445
1446 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1447 }
1448
1449 static void
1450 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1451 {
1452 const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1453 struct tu_cs sub_cs;
1454
1455 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1456 tile_store_space, &sub_cs);
1457 if (result != VK_SUCCESS) {
1458 cmd->record_result = result;
1459 return;
1460 }
1461
1462 /* emit to tile-store sub_cs */
1463 tu6_emit_tile_store(cmd, &sub_cs);
1464
1465 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1466 }
1467
1468 static void
1469 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1470 const VkRect2D *render_area)
1471 {
1472 const struct tu_device *dev = cmd->device;
1473 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1474
1475 tiling->render_area = *render_area;
1476
1477 tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1478 tu_tiling_config_update_pipe_layout(tiling, dev);
1479 tu_tiling_config_update_pipes(tiling, dev);
1480 }
1481
1482 const struct tu_dynamic_state default_dynamic_state = {
1483 .viewport =
1484 {
1485 .count = 0,
1486 },
1487 .scissor =
1488 {
1489 .count = 0,
1490 },
1491 .line_width = 1.0f,
1492 .depth_bias =
1493 {
1494 .bias = 0.0f,
1495 .clamp = 0.0f,
1496 .slope = 0.0f,
1497 },
1498 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1499 .depth_bounds =
1500 {
1501 .min = 0.0f,
1502 .max = 1.0f,
1503 },
1504 .stencil_compare_mask =
1505 {
1506 .front = ~0u,
1507 .back = ~0u,
1508 },
1509 .stencil_write_mask =
1510 {
1511 .front = ~0u,
1512 .back = ~0u,
1513 },
1514 .stencil_reference =
1515 {
1516 .front = 0u,
1517 .back = 0u,
1518 },
1519 };
1520
1521 static void UNUSED /* FINISHME */
1522 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1523 const struct tu_dynamic_state *src)
1524 {
1525 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1526 uint32_t copy_mask = src->mask;
1527 uint32_t dest_mask = 0;
1528
1529 tu_use_args(cmd_buffer); /* FINISHME */
1530
1531 /* Make sure to copy the number of viewports/scissors because they can
1532 * only be specified at pipeline creation time.
1533 */
1534 dest->viewport.count = src->viewport.count;
1535 dest->scissor.count = src->scissor.count;
1536 dest->discard_rectangle.count = src->discard_rectangle.count;
1537
1538 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1539 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1540 src->viewport.count * sizeof(VkViewport))) {
1541 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1542 src->viewport.count);
1543 dest_mask |= TU_DYNAMIC_VIEWPORT;
1544 }
1545 }
1546
1547 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1548 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1549 src->scissor.count * sizeof(VkRect2D))) {
1550 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1551 src->scissor.count);
1552 dest_mask |= TU_DYNAMIC_SCISSOR;
1553 }
1554 }
1555
1556 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1557 if (dest->line_width != src->line_width) {
1558 dest->line_width = src->line_width;
1559 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1560 }
1561 }
1562
1563 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1564 if (memcmp(&dest->depth_bias, &src->depth_bias,
1565 sizeof(src->depth_bias))) {
1566 dest->depth_bias = src->depth_bias;
1567 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1568 }
1569 }
1570
1571 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1572 if (memcmp(&dest->blend_constants, &src->blend_constants,
1573 sizeof(src->blend_constants))) {
1574 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1575 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1576 }
1577 }
1578
1579 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1580 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1581 sizeof(src->depth_bounds))) {
1582 dest->depth_bounds = src->depth_bounds;
1583 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1584 }
1585 }
1586
1587 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1588 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1589 sizeof(src->stencil_compare_mask))) {
1590 dest->stencil_compare_mask = src->stencil_compare_mask;
1591 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1592 }
1593 }
1594
1595 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1596 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1597 sizeof(src->stencil_write_mask))) {
1598 dest->stencil_write_mask = src->stencil_write_mask;
1599 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1600 }
1601 }
1602
1603 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1604 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1605 sizeof(src->stencil_reference))) {
1606 dest->stencil_reference = src->stencil_reference;
1607 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1608 }
1609 }
1610
1611 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1612 if (memcmp(&dest->discard_rectangle.rectangles,
1613 &src->discard_rectangle.rectangles,
1614 src->discard_rectangle.count * sizeof(VkRect2D))) {
1615 typed_memcpy(dest->discard_rectangle.rectangles,
1616 src->discard_rectangle.rectangles,
1617 src->discard_rectangle.count);
1618 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1619 }
1620 }
1621 }
1622
1623 static VkResult
1624 tu_create_cmd_buffer(struct tu_device *device,
1625 struct tu_cmd_pool *pool,
1626 VkCommandBufferLevel level,
1627 VkCommandBuffer *pCommandBuffer)
1628 {
1629 struct tu_cmd_buffer *cmd_buffer;
1630 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1631 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1632 if (cmd_buffer == NULL)
1633 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1634
1635 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1636 cmd_buffer->device = device;
1637 cmd_buffer->pool = pool;
1638 cmd_buffer->level = level;
1639
1640 if (pool) {
1641 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1642 cmd_buffer->queue_family_index = pool->queue_family_index;
1643
1644 } else {
1645 /* Init the pool_link so we can safely call list_del when we destroy
1646 * the command buffer
1647 */
1648 list_inithead(&cmd_buffer->pool_link);
1649 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1650 }
1651
1652 tu_bo_list_init(&cmd_buffer->bo_list);
1653 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1654 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1655 tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1656
1657 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1658
1659 list_inithead(&cmd_buffer->upload.list);
1660
1661 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1662 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1663
1664 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1665 if (result != VK_SUCCESS)
1666 return result;
1667
1668 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1669 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1670
1671 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1672 cmd_buffer->vsc_data_pitch = 0x440 * 4;
1673 cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
1674
1675 result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
1676 if (result != VK_SUCCESS)
1677 goto fail_vsc_data;
1678
1679 result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
1680 if (result != VK_SUCCESS)
1681 goto fail_vsc_data2;
1682
1683 return VK_SUCCESS;
1684
1685 fail_vsc_data2:
1686 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1687 fail_vsc_data:
1688 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1689 return result;
1690 }
1691
1692 static void
1693 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1694 {
1695 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1696 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1697 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
1698
1699 list_del(&cmd_buffer->pool_link);
1700
1701 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1702 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1703
1704 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1705 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1706 tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1707
1708 tu_bo_list_destroy(&cmd_buffer->bo_list);
1709 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1710 }
1711
1712 static VkResult
1713 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1714 {
1715 cmd_buffer->wait_for_idle = true;
1716
1717 cmd_buffer->record_result = VK_SUCCESS;
1718
1719 tu_bo_list_reset(&cmd_buffer->bo_list);
1720 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1721 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1722 tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1723
1724 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1725 cmd_buffer->descriptors[i].dirty = 0;
1726 cmd_buffer->descriptors[i].valid = 0;
1727 cmd_buffer->descriptors[i].push_dirty = false;
1728 }
1729
1730 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1731
1732 return cmd_buffer->record_result;
1733 }
1734
1735 VkResult
1736 tu_AllocateCommandBuffers(VkDevice _device,
1737 const VkCommandBufferAllocateInfo *pAllocateInfo,
1738 VkCommandBuffer *pCommandBuffers)
1739 {
1740 TU_FROM_HANDLE(tu_device, device, _device);
1741 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1742
1743 VkResult result = VK_SUCCESS;
1744 uint32_t i;
1745
1746 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1747
1748 if (!list_is_empty(&pool->free_cmd_buffers)) {
1749 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1750 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1751
1752 list_del(&cmd_buffer->pool_link);
1753 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1754
1755 result = tu_reset_cmd_buffer(cmd_buffer);
1756 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1757 cmd_buffer->level = pAllocateInfo->level;
1758
1759 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1760 } else {
1761 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1762 &pCommandBuffers[i]);
1763 }
1764 if (result != VK_SUCCESS)
1765 break;
1766 }
1767
1768 if (result != VK_SUCCESS) {
1769 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1770 pCommandBuffers);
1771
1772 /* From the Vulkan 1.0.66 spec:
1773 *
1774 * "vkAllocateCommandBuffers can be used to create multiple
1775 * command buffers. If the creation of any of those command
1776 * buffers fails, the implementation must destroy all
1777 * successfully created command buffer objects from this
1778 * command, set all entries of the pCommandBuffers array to
1779 * NULL and return the error."
1780 */
1781 memset(pCommandBuffers, 0,
1782 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1783 }
1784
1785 return result;
1786 }
1787
1788 void
1789 tu_FreeCommandBuffers(VkDevice device,
1790 VkCommandPool commandPool,
1791 uint32_t commandBufferCount,
1792 const VkCommandBuffer *pCommandBuffers)
1793 {
1794 for (uint32_t i = 0; i < commandBufferCount; i++) {
1795 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1796
1797 if (cmd_buffer) {
1798 if (cmd_buffer->pool) {
1799 list_del(&cmd_buffer->pool_link);
1800 list_addtail(&cmd_buffer->pool_link,
1801 &cmd_buffer->pool->free_cmd_buffers);
1802 } else
1803 tu_cmd_buffer_destroy(cmd_buffer);
1804 }
1805 }
1806 }
1807
1808 VkResult
1809 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1810 VkCommandBufferResetFlags flags)
1811 {
1812 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1813 return tu_reset_cmd_buffer(cmd_buffer);
1814 }
1815
1816 VkResult
1817 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1818 const VkCommandBufferBeginInfo *pBeginInfo)
1819 {
1820 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1821 VkResult result = VK_SUCCESS;
1822
1823 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1824 /* If the command buffer has already been resetted with
1825 * vkResetCommandBuffer, no need to do it again.
1826 */
1827 result = tu_reset_cmd_buffer(cmd_buffer);
1828 if (result != VK_SUCCESS)
1829 return result;
1830 }
1831
1832 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1833 cmd_buffer->usage_flags = pBeginInfo->flags;
1834
1835 tu_cs_begin(&cmd_buffer->cs);
1836 tu_cs_begin(&cmd_buffer->draw_cs);
1837
1838 cmd_buffer->marker_seqno = 0;
1839 cmd_buffer->scratch_seqno = 0;
1840
1841 /* setup initial configuration into command buffer */
1842 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1843 switch (cmd_buffer->queue_family_index) {
1844 case TU_QUEUE_GENERAL:
1845 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1846 break;
1847 default:
1848 break;
1849 }
1850 } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1851 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1852 assert(pBeginInfo->pInheritanceInfo);
1853 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1854 cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1855 }
1856
1857 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1858
1859 return VK_SUCCESS;
1860 }
1861
1862 void
1863 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1864 uint32_t firstBinding,
1865 uint32_t bindingCount,
1866 const VkBuffer *pBuffers,
1867 const VkDeviceSize *pOffsets)
1868 {
1869 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1870
1871 assert(firstBinding + bindingCount <= MAX_VBS);
1872
1873 for (uint32_t i = 0; i < bindingCount; i++) {
1874 cmd->state.vb.buffers[firstBinding + i] =
1875 tu_buffer_from_handle(pBuffers[i]);
1876 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1877 }
1878
1879 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1880 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1881 }
1882
1883 void
1884 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1885 VkBuffer buffer,
1886 VkDeviceSize offset,
1887 VkIndexType indexType)
1888 {
1889 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1890 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1891
1892 /* initialize/update the restart index */
1893 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1894 struct tu_cs *draw_cs = &cmd->draw_cs;
1895 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1896 if (result != VK_SUCCESS) {
1897 cmd->record_result = result;
1898 return;
1899 }
1900
1901 tu6_emit_restart_index(
1902 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1903
1904 tu_cs_sanity_check(draw_cs);
1905 }
1906
1907 /* track the BO */
1908 if (cmd->state.index_buffer != buf)
1909 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1910
1911 cmd->state.index_buffer = buf;
1912 cmd->state.index_offset = offset;
1913 cmd->state.index_type = indexType;
1914 }
1915
1916 void
1917 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1918 VkPipelineBindPoint pipelineBindPoint,
1919 VkPipelineLayout _layout,
1920 uint32_t firstSet,
1921 uint32_t descriptorSetCount,
1922 const VkDescriptorSet *pDescriptorSets,
1923 uint32_t dynamicOffsetCount,
1924 const uint32_t *pDynamicOffsets)
1925 {
1926 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1927 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1928 unsigned dyn_idx = 0;
1929
1930 struct tu_descriptor_state *descriptors_state =
1931 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1932
1933 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1934 unsigned idx = i + firstSet;
1935 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1936
1937 descriptors_state->sets[idx] = set;
1938 descriptors_state->valid |= (1u << idx);
1939
1940 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1941 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1942 assert(dyn_idx < dynamicOffsetCount);
1943
1944 descriptors_state->dynamic_buffers[idx] =
1945 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1946 }
1947 }
1948
1949 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1950 }
1951
1952 void
1953 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1954 VkPipelineLayout layout,
1955 VkShaderStageFlags stageFlags,
1956 uint32_t offset,
1957 uint32_t size,
1958 const void *pValues)
1959 {
1960 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1961 memcpy((void*) cmd->push_constants + offset, pValues, size);
1962 cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1963 }
1964
1965 VkResult
1966 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1967 {
1968 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1969
1970 if (cmd_buffer->scratch_seqno) {
1971 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1972 MSM_SUBMIT_BO_WRITE);
1973 }
1974
1975 if (cmd_buffer->use_vsc_data) {
1976 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
1977 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1978 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
1979 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1980 }
1981
1982 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1983 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1984 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1985 }
1986
1987 for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
1988 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
1989 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1990 }
1991
1992 tu_cs_end(&cmd_buffer->cs);
1993 tu_cs_end(&cmd_buffer->draw_cs);
1994
1995 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1996
1997 return cmd_buffer->record_result;
1998 }
1999
2000 void
2001 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2002 VkPipelineBindPoint pipelineBindPoint,
2003 VkPipeline _pipeline)
2004 {
2005 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2006 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2007
2008 switch (pipelineBindPoint) {
2009 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2010 cmd->state.pipeline = pipeline;
2011 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2012 break;
2013 case VK_PIPELINE_BIND_POINT_COMPUTE:
2014 cmd->state.compute_pipeline = pipeline;
2015 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2016 break;
2017 default:
2018 unreachable("unrecognized pipeline bind point");
2019 break;
2020 }
2021
2022 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2023 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2024 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2025 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2026 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2027 }
2028 }
2029
2030 void
2031 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2032 uint32_t firstViewport,
2033 uint32_t viewportCount,
2034 const VkViewport *pViewports)
2035 {
2036 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2037 struct tu_cs *draw_cs = &cmd->draw_cs;
2038
2039 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2040 if (result != VK_SUCCESS) {
2041 cmd->record_result = result;
2042 return;
2043 }
2044
2045 assert(firstViewport == 0 && viewportCount == 1);
2046 tu6_emit_viewport(draw_cs, pViewports);
2047
2048 tu_cs_sanity_check(draw_cs);
2049 }
2050
2051 void
2052 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2053 uint32_t firstScissor,
2054 uint32_t scissorCount,
2055 const VkRect2D *pScissors)
2056 {
2057 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2058 struct tu_cs *draw_cs = &cmd->draw_cs;
2059
2060 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2061 if (result != VK_SUCCESS) {
2062 cmd->record_result = result;
2063 return;
2064 }
2065
2066 assert(firstScissor == 0 && scissorCount == 1);
2067 tu6_emit_scissor(draw_cs, pScissors);
2068
2069 tu_cs_sanity_check(draw_cs);
2070 }
2071
2072 void
2073 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2074 {
2075 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2076
2077 cmd->state.dynamic.line_width = lineWidth;
2078
2079 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2080 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2081 }
2082
2083 void
2084 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2085 float depthBiasConstantFactor,
2086 float depthBiasClamp,
2087 float depthBiasSlopeFactor)
2088 {
2089 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2090 struct tu_cs *draw_cs = &cmd->draw_cs;
2091
2092 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2093 if (result != VK_SUCCESS) {
2094 cmd->record_result = result;
2095 return;
2096 }
2097
2098 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2099 depthBiasSlopeFactor);
2100
2101 tu_cs_sanity_check(draw_cs);
2102 }
2103
2104 void
2105 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2106 const float blendConstants[4])
2107 {
2108 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2109 struct tu_cs *draw_cs = &cmd->draw_cs;
2110
2111 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2112 if (result != VK_SUCCESS) {
2113 cmd->record_result = result;
2114 return;
2115 }
2116
2117 tu6_emit_blend_constants(draw_cs, blendConstants);
2118
2119 tu_cs_sanity_check(draw_cs);
2120 }
2121
2122 void
2123 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2124 float minDepthBounds,
2125 float maxDepthBounds)
2126 {
2127 }
2128
2129 void
2130 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2131 VkStencilFaceFlags faceMask,
2132 uint32_t compareMask)
2133 {
2134 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2135
2136 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2137 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2138 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2139 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2140
2141 /* the front/back compare masks must be updated together */
2142 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2143 }
2144
2145 void
2146 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2147 VkStencilFaceFlags faceMask,
2148 uint32_t writeMask)
2149 {
2150 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2151
2152 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2153 cmd->state.dynamic.stencil_write_mask.front = writeMask;
2154 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2155 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2156
2157 /* the front/back write masks must be updated together */
2158 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2159 }
2160
2161 void
2162 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2163 VkStencilFaceFlags faceMask,
2164 uint32_t reference)
2165 {
2166 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2167
2168 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2169 cmd->state.dynamic.stencil_reference.front = reference;
2170 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2171 cmd->state.dynamic.stencil_reference.back = reference;
2172
2173 /* the front/back references must be updated together */
2174 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2175 }
2176
2177 void
2178 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2179 uint32_t commandBufferCount,
2180 const VkCommandBuffer *pCmdBuffers)
2181 {
2182 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2183 VkResult result;
2184
2185 assert(commandBufferCount > 0);
2186
2187 for (uint32_t i = 0; i < commandBufferCount; i++) {
2188 TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2189
2190 result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2191 if (result != VK_SUCCESS) {
2192 cmd->record_result = result;
2193 break;
2194 }
2195
2196 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2197 if (result != VK_SUCCESS) {
2198 cmd->record_result = result;
2199 break;
2200 }
2201 }
2202 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2203 }
2204
2205 VkResult
2206 tu_CreateCommandPool(VkDevice _device,
2207 const VkCommandPoolCreateInfo *pCreateInfo,
2208 const VkAllocationCallbacks *pAllocator,
2209 VkCommandPool *pCmdPool)
2210 {
2211 TU_FROM_HANDLE(tu_device, device, _device);
2212 struct tu_cmd_pool *pool;
2213
2214 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2215 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2216 if (pool == NULL)
2217 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2218
2219 if (pAllocator)
2220 pool->alloc = *pAllocator;
2221 else
2222 pool->alloc = device->alloc;
2223
2224 list_inithead(&pool->cmd_buffers);
2225 list_inithead(&pool->free_cmd_buffers);
2226
2227 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2228
2229 *pCmdPool = tu_cmd_pool_to_handle(pool);
2230
2231 return VK_SUCCESS;
2232 }
2233
2234 void
2235 tu_DestroyCommandPool(VkDevice _device,
2236 VkCommandPool commandPool,
2237 const VkAllocationCallbacks *pAllocator)
2238 {
2239 TU_FROM_HANDLE(tu_device, device, _device);
2240 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2241
2242 if (!pool)
2243 return;
2244
2245 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2246 &pool->cmd_buffers, pool_link)
2247 {
2248 tu_cmd_buffer_destroy(cmd_buffer);
2249 }
2250
2251 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2252 &pool->free_cmd_buffers, pool_link)
2253 {
2254 tu_cmd_buffer_destroy(cmd_buffer);
2255 }
2256
2257 vk_free2(&device->alloc, pAllocator, pool);
2258 }
2259
2260 VkResult
2261 tu_ResetCommandPool(VkDevice device,
2262 VkCommandPool commandPool,
2263 VkCommandPoolResetFlags flags)
2264 {
2265 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2266 VkResult result;
2267
2268 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2269 pool_link)
2270 {
2271 result = tu_reset_cmd_buffer(cmd_buffer);
2272 if (result != VK_SUCCESS)
2273 return result;
2274 }
2275
2276 return VK_SUCCESS;
2277 }
2278
2279 void
2280 tu_TrimCommandPool(VkDevice device,
2281 VkCommandPool commandPool,
2282 VkCommandPoolTrimFlags flags)
2283 {
2284 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2285
2286 if (!pool)
2287 return;
2288
2289 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2290 &pool->free_cmd_buffers, pool_link)
2291 {
2292 tu_cmd_buffer_destroy(cmd_buffer);
2293 }
2294 }
2295
2296 void
2297 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2298 const VkRenderPassBeginInfo *pRenderPassBegin,
2299 VkSubpassContents contents)
2300 {
2301 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2302 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2303 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2304
2305 cmd->state.pass = pass;
2306 cmd->state.subpass = pass->subpasses;
2307 cmd->state.framebuffer = fb;
2308
2309 tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2310 tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2311 tu_cmd_prepare_tile_store_ib(cmd);
2312
2313 /* note: use_hw_binning only checks tiling config */
2314 if (use_hw_binning(cmd))
2315 cmd->use_vsc_data = true;
2316
2317 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2318 const struct tu_image_view *iview = fb->attachments[i].attachment;
2319 tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2320 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2321 }
2322 }
2323
2324 void
2325 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2326 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2327 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2328 {
2329 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2330 pSubpassBeginInfo->contents);
2331 }
2332
2333 void
2334 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2335 {
2336 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2337 const struct tu_render_pass *pass = cmd->state.pass;
2338 struct tu_cs *cs = &cmd->draw_cs;
2339
2340 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2341 if (result != VK_SUCCESS) {
2342 cmd->record_result = result;
2343 return;
2344 }
2345
2346 const struct tu_subpass *subpass = cmd->state.subpass++;
2347 /* TODO:
2348 * if msaa samples change between subpasses,
2349 * attachment store is broken for some attachments
2350 */
2351 if (subpass->resolve_attachments) {
2352 tu6_emit_blit_scissor(cmd, cs, true);
2353 for (unsigned i = 0; i < subpass->color_count; i++) {
2354 uint32_t a = subpass->resolve_attachments[i].attachment;
2355 if (a != VK_ATTACHMENT_UNUSED) {
2356 tu6_emit_store_attachment(cmd, cs, a,
2357 subpass->color_attachments[i].attachment);
2358 }
2359 }
2360 }
2361
2362 /* invalidate because reading input attachments will cache GMEM and
2363 * the cache isn''t updated when GMEM is written
2364 * TODO: is there a no-cache bit for textures?
2365 */
2366 if (cmd->state.subpass->input_count)
2367 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2368
2369 /* emit mrt/zs/msaa state for the subpass that is starting */
2370 tu6_emit_zs(cmd, cmd->state.subpass, cs);
2371 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2372 tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2373
2374 /* TODO:
2375 * since we don't know how to do GMEM->GMEM resolve,
2376 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2377 */
2378 if (subpass->resolve_attachments) {
2379 for (unsigned i = 0; i < subpass->color_count; i++) {
2380 uint32_t a = subpass->resolve_attachments[i].attachment;
2381 const struct tu_image_view *iview =
2382 cmd->state.framebuffer->attachments[a].attachment;
2383 if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2384 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2385 tu6_emit_blit_info(cmd, cs, iview, pass->attachments[a].gmem_offset, false);
2386 tu6_emit_blit(cmd, cs);
2387 }
2388 }
2389 }
2390 }
2391
2392 void
2393 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2394 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2395 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2396 {
2397 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2398 }
2399
2400 struct tu_draw_info
2401 {
2402 /**
2403 * Number of vertices.
2404 */
2405 uint32_t count;
2406
2407 /**
2408 * Index of the first vertex.
2409 */
2410 int32_t vertex_offset;
2411
2412 /**
2413 * First instance id.
2414 */
2415 uint32_t first_instance;
2416
2417 /**
2418 * Number of instances.
2419 */
2420 uint32_t instance_count;
2421
2422 /**
2423 * First index (indexed draws only).
2424 */
2425 uint32_t first_index;
2426
2427 /**
2428 * Whether it's an indexed draw.
2429 */
2430 bool indexed;
2431
2432 /**
2433 * Indirect draw parameters resource.
2434 */
2435 struct tu_buffer *indirect;
2436 uint64_t indirect_offset;
2437 uint32_t stride;
2438
2439 /**
2440 * Draw count parameters resource.
2441 */
2442 struct tu_buffer *count_buffer;
2443 uint64_t count_buffer_offset;
2444 };
2445
2446 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2447 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2448
2449 enum tu_draw_state_group_id
2450 {
2451 TU_DRAW_STATE_PROGRAM,
2452 TU_DRAW_STATE_PROGRAM_BINNING,
2453 TU_DRAW_STATE_VI,
2454 TU_DRAW_STATE_VI_BINNING,
2455 TU_DRAW_STATE_VP,
2456 TU_DRAW_STATE_RAST,
2457 TU_DRAW_STATE_DS,
2458 TU_DRAW_STATE_BLEND,
2459 TU_DRAW_STATE_VS_CONST,
2460 TU_DRAW_STATE_FS_CONST,
2461 TU_DRAW_STATE_VS_TEX,
2462 TU_DRAW_STATE_FS_TEX,
2463 TU_DRAW_STATE_FS_IBO,
2464 TU_DRAW_STATE_VS_PARAMS,
2465
2466 TU_DRAW_STATE_COUNT,
2467 };
2468
2469 struct tu_draw_state_group
2470 {
2471 enum tu_draw_state_group_id id;
2472 uint32_t enable_mask;
2473 struct tu_cs_entry ib;
2474 };
2475
2476 const static struct tu_sampler*
2477 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2478 const struct tu_descriptor_map *map, unsigned i,
2479 unsigned array_index)
2480 {
2481 assert(descriptors_state->valid & (1 << map->set[i]));
2482
2483 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2484 assert(map->binding[i] < set->layout->binding_count);
2485
2486 const struct tu_descriptor_set_binding_layout *layout =
2487 &set->layout->binding[map->binding[i]];
2488
2489 if (layout->immutable_samplers_offset) {
2490 const struct tu_sampler *immutable_samplers =
2491 tu_immutable_samplers(set->layout, layout);
2492
2493 return &immutable_samplers[array_index];
2494 }
2495
2496 switch (layout->type) {
2497 case VK_DESCRIPTOR_TYPE_SAMPLER:
2498 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2499 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2500 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2501 array_index *
2502 (A6XX_TEX_CONST_DWORDS +
2503 sizeof(struct tu_sampler) / 4)];
2504 default:
2505 unreachable("unimplemented descriptor type");
2506 break;
2507 }
2508 }
2509
2510 static void
2511 write_tex_const(struct tu_cmd_buffer *cmd,
2512 uint32_t *dst,
2513 struct tu_descriptor_state *descriptors_state,
2514 const struct tu_descriptor_map *map,
2515 unsigned i, unsigned array_index)
2516 {
2517 assert(descriptors_state->valid & (1 << map->set[i]));
2518
2519 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2520 assert(map->binding[i] < set->layout->binding_count);
2521
2522 const struct tu_descriptor_set_binding_layout *layout =
2523 &set->layout->binding[map->binding[i]];
2524
2525 switch (layout->type) {
2526 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2527 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2528 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2529 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2530 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2531 array_index * A6XX_TEX_CONST_DWORDS],
2532 A6XX_TEX_CONST_DWORDS * 4);
2533 break;
2534 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2535 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2536 array_index *
2537 (A6XX_TEX_CONST_DWORDS +
2538 sizeof(struct tu_sampler) / 4)],
2539 A6XX_TEX_CONST_DWORDS * 4);
2540 break;
2541 default:
2542 unreachable("unimplemented descriptor type");
2543 break;
2544 }
2545
2546 if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2547 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2548 uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2549 array_index].attachment;
2550 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2551
2552 assert(att->gmem_offset >= 0);
2553
2554 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2555 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2556 dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2557 dst[2] |=
2558 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2559 A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2560 dst[3] = 0;
2561 dst[4] = 0x100000 + att->gmem_offset;
2562 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2563 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2564 dst[i] = 0;
2565
2566 if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2567 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2568 }
2569 }
2570
2571 static void
2572 write_image_ibo(struct tu_cmd_buffer *cmd,
2573 uint32_t *dst,
2574 struct tu_descriptor_state *descriptors_state,
2575 const struct tu_descriptor_map *map,
2576 unsigned i, unsigned array_index)
2577 {
2578 assert(descriptors_state->valid & (1 << map->set[i]));
2579
2580 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2581 assert(map->binding[i] < set->layout->binding_count);
2582
2583 const struct tu_descriptor_set_binding_layout *layout =
2584 &set->layout->binding[map->binding[i]];
2585
2586 assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2587
2588 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2589 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2590 A6XX_TEX_CONST_DWORDS * 4);
2591 }
2592
2593 static uint64_t
2594 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2595 const struct tu_descriptor_map *map,
2596 unsigned i, unsigned array_index)
2597 {
2598 assert(descriptors_state->valid & (1 << map->set[i]));
2599
2600 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2601 assert(map->binding[i] < set->layout->binding_count);
2602
2603 const struct tu_descriptor_set_binding_layout *layout =
2604 &set->layout->binding[map->binding[i]];
2605
2606 switch (layout->type) {
2607 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2608 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2609 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2610 array_index];
2611 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2612 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2613 return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2614 set->mapped_ptr[layout->offset / 4 + array_index * 2];
2615 default:
2616 unreachable("unimplemented descriptor type");
2617 break;
2618 }
2619 }
2620
2621 static inline uint32_t
2622 tu6_stage2opcode(gl_shader_stage type)
2623 {
2624 switch (type) {
2625 case MESA_SHADER_VERTEX:
2626 case MESA_SHADER_TESS_CTRL:
2627 case MESA_SHADER_TESS_EVAL:
2628 case MESA_SHADER_GEOMETRY:
2629 return CP_LOAD_STATE6_GEOM;
2630 case MESA_SHADER_FRAGMENT:
2631 case MESA_SHADER_COMPUTE:
2632 case MESA_SHADER_KERNEL:
2633 return CP_LOAD_STATE6_FRAG;
2634 default:
2635 unreachable("bad shader type");
2636 }
2637 }
2638
2639 static inline enum a6xx_state_block
2640 tu6_stage2shadersb(gl_shader_stage type)
2641 {
2642 switch (type) {
2643 case MESA_SHADER_VERTEX:
2644 return SB6_VS_SHADER;
2645 case MESA_SHADER_FRAGMENT:
2646 return SB6_FS_SHADER;
2647 case MESA_SHADER_COMPUTE:
2648 case MESA_SHADER_KERNEL:
2649 return SB6_CS_SHADER;
2650 default:
2651 unreachable("bad shader type");
2652 return ~0;
2653 }
2654 }
2655
2656 static void
2657 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2658 struct tu_descriptor_state *descriptors_state,
2659 gl_shader_stage type,
2660 uint32_t *push_constants)
2661 {
2662 const struct tu_program_descriptor_linkage *link =
2663 &pipeline->program.link[type];
2664 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2665
2666 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2667 if (state->range[i].start < state->range[i].end) {
2668 uint32_t size = state->range[i].end - state->range[i].start;
2669 uint32_t offset = state->range[i].start;
2670
2671 /* and even if the start of the const buffer is before
2672 * first_immediate, the end may not be:
2673 */
2674 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2675
2676 if (size == 0)
2677 continue;
2678
2679 /* things should be aligned to vec4: */
2680 debug_assert((state->range[i].offset % 16) == 0);
2681 debug_assert((size % 16) == 0);
2682 debug_assert((offset % 16) == 0);
2683
2684 if (i == 0) {
2685 /* push constants */
2686 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2687 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2688 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2689 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2690 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2691 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2692 tu_cs_emit(cs, 0);
2693 tu_cs_emit(cs, 0);
2694 for (unsigned i = 0; i < size / 4; i++)
2695 tu_cs_emit(cs, push_constants[i + offset / 4]);
2696 continue;
2697 }
2698
2699 /* Look through the UBO map to find our UBO index, and get the VA for
2700 * that UBO.
2701 */
2702 uint64_t va = 0;
2703 uint32_t ubo_idx = i - 1;
2704 uint32_t ubo_map_base = 0;
2705 for (int j = 0; j < link->ubo_map.num; j++) {
2706 if (ubo_idx >= ubo_map_base &&
2707 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2708 va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2709 ubo_idx - ubo_map_base);
2710 break;
2711 }
2712 ubo_map_base += link->ubo_map.array_size[j];
2713 }
2714 assert(va);
2715
2716 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2717 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2718 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2719 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2720 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2721 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2722 tu_cs_emit_qw(cs, va + offset);
2723 }
2724 }
2725 }
2726
2727 static void
2728 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2729 struct tu_descriptor_state *descriptors_state,
2730 gl_shader_stage type)
2731 {
2732 const struct tu_program_descriptor_linkage *link =
2733 &pipeline->program.link[type];
2734
2735 uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2736 uint32_t anum = align(num, 2);
2737
2738 if (!num)
2739 return;
2740
2741 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2742 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2743 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2744 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2745 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2746 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2747 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2748 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2749
2750 unsigned emitted = 0;
2751 for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2752 for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2753 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2754 emitted++;
2755 }
2756 }
2757
2758 for (; emitted < anum; emitted++) {
2759 tu_cs_emit(cs, 0xffffffff);
2760 tu_cs_emit(cs, 0xffffffff);
2761 }
2762 }
2763
2764 static struct tu_cs_entry
2765 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2766 const struct tu_pipeline *pipeline,
2767 struct tu_descriptor_state *descriptors_state,
2768 gl_shader_stage type)
2769 {
2770 struct tu_cs cs;
2771 tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2772
2773 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2774 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2775
2776 return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2777 }
2778
2779 static VkResult
2780 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2781 const struct tu_draw_info *draw,
2782 struct tu_cs_entry *entry)
2783 {
2784 /* TODO: fill out more than just base instance */
2785 const struct tu_program_descriptor_linkage *link =
2786 &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2787 const struct ir3_const_state *const_state = &link->const_state;
2788 struct tu_cs cs;
2789
2790 if (const_state->offsets.driver_param >= link->constlen) {
2791 *entry = (struct tu_cs_entry) {};
2792 return VK_SUCCESS;
2793 }
2794
2795 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 8, &cs);
2796 if (result != VK_SUCCESS)
2797 return result;
2798
2799 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2800 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2801 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2802 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2803 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2804 CP_LOAD_STATE6_0_NUM_UNIT(1));
2805 tu_cs_emit(&cs, 0);
2806 tu_cs_emit(&cs, 0);
2807
2808 STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2809
2810 tu_cs_emit(&cs, 0);
2811 tu_cs_emit(&cs, 0);
2812 tu_cs_emit(&cs, draw->first_instance);
2813 tu_cs_emit(&cs, 0);
2814
2815 *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2816 return VK_SUCCESS;
2817 }
2818
2819 static VkResult
2820 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2821 const struct tu_pipeline *pipeline,
2822 struct tu_descriptor_state *descriptors_state,
2823 gl_shader_stage type,
2824 struct tu_cs_entry *entry,
2825 bool *needs_border)
2826 {
2827 struct tu_device *device = cmd->device;
2828 struct tu_cs *draw_state = &cmd->sub_cs;
2829 const struct tu_program_descriptor_linkage *link =
2830 &pipeline->program.link[type];
2831 VkResult result;
2832
2833 if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
2834 *entry = (struct tu_cs_entry) {};
2835 return VK_SUCCESS;
2836 }
2837
2838 /* allocate and fill texture state */
2839 struct ts_cs_memory tex_const;
2840 result = tu_cs_alloc(device, draw_state, link->texture_map.num_desc,
2841 A6XX_TEX_CONST_DWORDS, &tex_const);
2842 if (result != VK_SUCCESS)
2843 return result;
2844
2845 int tex_index = 0;
2846 for (unsigned i = 0; i < link->texture_map.num; i++) {
2847 for (int j = 0; j < link->texture_map.array_size[i]; j++) {
2848 write_tex_const(cmd,
2849 &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
2850 descriptors_state, &link->texture_map, i, j);
2851 }
2852 }
2853
2854 /* allocate and fill sampler state */
2855 struct ts_cs_memory tex_samp = { 0 };
2856 if (link->sampler_map.num_desc) {
2857 result = tu_cs_alloc(device, draw_state, link->sampler_map.num_desc,
2858 A6XX_TEX_SAMP_DWORDS, &tex_samp);
2859 if (result != VK_SUCCESS)
2860 return result;
2861
2862 int sampler_index = 0;
2863 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2864 for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
2865 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
2866 &link->sampler_map,
2867 i, j);
2868 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
2869 sampler->state, sizeof(sampler->state));
2870 *needs_border |= sampler->needs_border;
2871 }
2872 }
2873 }
2874
2875 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2876 enum a6xx_state_block sb;
2877
2878 switch (type) {
2879 case MESA_SHADER_VERTEX:
2880 sb = SB6_VS_TEX;
2881 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2882 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2883 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2884 break;
2885 case MESA_SHADER_FRAGMENT:
2886 sb = SB6_FS_TEX;
2887 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2888 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2889 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2890 break;
2891 case MESA_SHADER_COMPUTE:
2892 sb = SB6_CS_TEX;
2893 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2894 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2895 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2896 break;
2897 default:
2898 unreachable("bad state block");
2899 }
2900
2901 struct tu_cs cs;
2902 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2903 if (result != VK_SUCCESS)
2904 return result;
2905
2906 if (link->sampler_map.num_desc) {
2907 /* output sampler state: */
2908 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2909 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2910 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2911 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2912 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2913 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
2914 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2915
2916 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2917 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2918 }
2919
2920 /* emit texture state: */
2921 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2922 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2923 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2924 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2925 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2926 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
2927 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2928
2929 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2930 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2931
2932 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2933 tu_cs_emit(&cs, link->texture_map.num_desc);
2934
2935 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2936 return VK_SUCCESS;
2937 }
2938
2939 static VkResult
2940 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
2941 const struct tu_pipeline *pipeline,
2942 struct tu_descriptor_state *descriptors_state,
2943 gl_shader_stage type,
2944 struct tu_cs_entry *entry)
2945 {
2946 struct tu_device *device = cmd->device;
2947 struct tu_cs *draw_state = &cmd->sub_cs;
2948 const struct tu_program_descriptor_linkage *link =
2949 &pipeline->program.link[type];
2950 VkResult result;
2951
2952 unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
2953
2954 if (num_desc == 0) {
2955 *entry = (struct tu_cs_entry) {};
2956 return VK_SUCCESS;
2957 }
2958
2959 struct ts_cs_memory ibo_const;
2960 result = tu_cs_alloc(device, draw_state, num_desc,
2961 A6XX_TEX_CONST_DWORDS, &ibo_const);
2962 if (result != VK_SUCCESS)
2963 return result;
2964
2965 int ssbo_index = 0;
2966 for (unsigned i = 0; i < link->ssbo_map.num; i++) {
2967 for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
2968 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
2969
2970 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
2971 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2972 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2973
2974 dst[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT);
2975 dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2976 A6XX_IBO_1_HEIGHT(sz >> 15);
2977 dst[2] = A6XX_IBO_2_UNK4 |
2978 A6XX_IBO_2_UNK31 |
2979 A6XX_IBO_2_TYPE(A6XX_TEX_1D);
2980 dst[3] = 0;
2981 dst[4] = va;
2982 dst[5] = va >> 32;
2983 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2984 dst[i] = 0;
2985
2986 ssbo_index++;
2987 }
2988 }
2989
2990 for (unsigned i = 0; i < link->image_map.num; i++) {
2991 for (int j = 0; j < link->image_map.array_size[i]; j++) {
2992 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
2993
2994 write_image_ibo(cmd, dst,
2995 descriptors_state, &link->image_map, i, j);
2996
2997 ssbo_index++;
2998 }
2999 }
3000
3001 assert(ssbo_index == num_desc);
3002
3003 struct tu_cs cs;
3004 result = tu_cs_begin_sub_stream(device, draw_state, 7, &cs);
3005 if (result != VK_SUCCESS)
3006 return result;
3007
3008 uint32_t opcode, ibo_addr_reg;
3009 enum a6xx_state_block sb;
3010 enum a6xx_state_type st;
3011
3012 switch (type) {
3013 case MESA_SHADER_FRAGMENT:
3014 opcode = CP_LOAD_STATE6;
3015 st = ST6_SHADER;
3016 sb = SB6_IBO;
3017 ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3018 break;
3019 case MESA_SHADER_COMPUTE:
3020 opcode = CP_LOAD_STATE6_FRAG;
3021 st = ST6_IBO;
3022 sb = SB6_CS_SHADER;
3023 ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3024 break;
3025 default:
3026 unreachable("unsupported stage for ibos");
3027 }
3028
3029 /* emit texture state: */
3030 tu_cs_emit_pkt7(&cs, opcode, 3);
3031 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3032 CP_LOAD_STATE6_0_STATE_TYPE(st) |
3033 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3034 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3035 CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3036 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3037
3038 tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3039 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3040
3041 *entry = tu_cs_end_sub_stream(draw_state, &cs);
3042 return VK_SUCCESS;
3043 }
3044
3045 struct PACKED bcolor_entry {
3046 uint32_t fp32[4];
3047 uint16_t ui16[4];
3048 int16_t si16[4];
3049 uint16_t fp16[4];
3050 uint16_t rgb565;
3051 uint16_t rgb5a1;
3052 uint16_t rgba4;
3053 uint8_t __pad0[2];
3054 uint8_t ui8[4];
3055 int8_t si8[4];
3056 uint32_t rgb10a2;
3057 uint32_t z24; /* also s8? */
3058 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
3059 uint8_t __pad1[56];
3060 } border_color[] = {
3061 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3062 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3063 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3064 .fp32[3] = 0x3f800000,
3065 .ui16[3] = 0xffff,
3066 .si16[3] = 0x7fff,
3067 .fp16[3] = 0x3c00,
3068 .rgb5a1 = 0x8000,
3069 .rgba4 = 0xf000,
3070 .ui8[3] = 0xff,
3071 .si8[3] = 0x7f,
3072 .rgb10a2 = 0xc0000000,
3073 .srgb[3] = 0x3c00,
3074 },
3075 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3076 .fp32[3] = 1,
3077 .fp16[3] = 1,
3078 },
3079 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3080 .fp32[0 ... 3] = 0x3f800000,
3081 .ui16[0 ... 3] = 0xffff,
3082 .si16[0 ... 3] = 0x7fff,
3083 .fp16[0 ... 3] = 0x3c00,
3084 .rgb565 = 0xffff,
3085 .rgb5a1 = 0xffff,
3086 .rgba4 = 0xffff,
3087 .ui8[0 ... 3] = 0xff,
3088 .si8[0 ... 3] = 0x7f,
3089 .rgb10a2 = 0xffffffff,
3090 .z24 = 0xffffff,
3091 .srgb[0 ... 3] = 0x3c00,
3092 },
3093 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3094 .fp32[0 ... 3] = 1,
3095 .fp16[0 ... 3] = 1,
3096 },
3097 };
3098
3099 static VkResult
3100 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3101 struct tu_cs *cs)
3102 {
3103 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3104
3105 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3106 struct tu_descriptor_state *descriptors_state =
3107 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3108 const struct tu_descriptor_map *vs_sampler =
3109 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3110 const struct tu_descriptor_map *fs_sampler =
3111 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3112 struct ts_cs_memory ptr;
3113
3114 VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
3115 vs_sampler->num_desc + fs_sampler->num_desc,
3116 128 / 4,
3117 &ptr);
3118 if (result != VK_SUCCESS)
3119 return result;
3120
3121 for (unsigned i = 0; i < vs_sampler->num; i++) {
3122 for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3123 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3124 vs_sampler, i, j);
3125 memcpy(ptr.map, &border_color[sampler->border], 128);
3126 ptr.map += 128 / 4;
3127 }
3128 }
3129
3130 for (unsigned i = 0; i < fs_sampler->num; i++) {
3131 for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3132 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3133 fs_sampler, i, j);
3134 memcpy(ptr.map, &border_color[sampler->border], 128);
3135 ptr.map += 128 / 4;
3136 }
3137 }
3138
3139 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3140 tu_cs_emit_qw(cs, ptr.iova);
3141 return VK_SUCCESS;
3142 }
3143
3144 static VkResult
3145 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3146 struct tu_cs *cs,
3147 const struct tu_draw_info *draw)
3148 {
3149 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3150 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3151 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3152 uint32_t draw_state_group_count = 0;
3153
3154 struct tu_descriptor_state *descriptors_state =
3155 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3156
3157 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3158 if (result != VK_SUCCESS)
3159 return result;
3160
3161 /* TODO lrz */
3162
3163 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3164 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3165 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3166
3167 tu_cs_emit_regs(cs,
3168 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3169 pipeline->ia.primitive_restart && draw->indexed));
3170
3171 if (cmd->state.dirty &
3172 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3173 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3174 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3175 dynamic->line_width);
3176 }
3177
3178 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3179 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3180 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3181 dynamic->stencil_compare_mask.back);
3182 }
3183
3184 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3185 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3186 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3187 dynamic->stencil_write_mask.back);
3188 }
3189
3190 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3191 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3192 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3193 dynamic->stencil_reference.back);
3194 }
3195
3196 if (cmd->state.dirty &
3197 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3198 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3199 const uint32_t binding = pipeline->vi.bindings[i];
3200 const uint32_t stride = pipeline->vi.strides[i];
3201 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3202 const VkDeviceSize offset = buf->bo_offset +
3203 cmd->state.vb.offsets[binding] +
3204 pipeline->vi.offsets[i];
3205 const VkDeviceSize size =
3206 offset < buf->bo->size ? buf->bo->size - offset : 0;
3207
3208 tu_cs_emit_regs(cs,
3209 A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3210 A6XX_VFD_FETCH_SIZE(i, size),
3211 A6XX_VFD_FETCH_STRIDE(i, stride));
3212 }
3213 }
3214
3215 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3216 draw_state_groups[draw_state_group_count++] =
3217 (struct tu_draw_state_group) {
3218 .id = TU_DRAW_STATE_PROGRAM,
3219 .enable_mask = ENABLE_DRAW,
3220 .ib = pipeline->program.state_ib,
3221 };
3222 draw_state_groups[draw_state_group_count++] =
3223 (struct tu_draw_state_group) {
3224 .id = TU_DRAW_STATE_PROGRAM_BINNING,
3225 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3226 .ib = pipeline->program.binning_state_ib,
3227 };
3228 draw_state_groups[draw_state_group_count++] =
3229 (struct tu_draw_state_group) {
3230 .id = TU_DRAW_STATE_VI,
3231 .enable_mask = ENABLE_DRAW,
3232 .ib = pipeline->vi.state_ib,
3233 };
3234 draw_state_groups[draw_state_group_count++] =
3235 (struct tu_draw_state_group) {
3236 .id = TU_DRAW_STATE_VI_BINNING,
3237 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3238 .ib = pipeline->vi.binning_state_ib,
3239 };
3240 draw_state_groups[draw_state_group_count++] =
3241 (struct tu_draw_state_group) {
3242 .id = TU_DRAW_STATE_VP,
3243 .enable_mask = ENABLE_ALL,
3244 .ib = pipeline->vp.state_ib,
3245 };
3246 draw_state_groups[draw_state_group_count++] =
3247 (struct tu_draw_state_group) {
3248 .id = TU_DRAW_STATE_RAST,
3249 .enable_mask = ENABLE_ALL,
3250 .ib = pipeline->rast.state_ib,
3251 };
3252 draw_state_groups[draw_state_group_count++] =
3253 (struct tu_draw_state_group) {
3254 .id = TU_DRAW_STATE_DS,
3255 .enable_mask = ENABLE_ALL,
3256 .ib = pipeline->ds.state_ib,
3257 };
3258 draw_state_groups[draw_state_group_count++] =
3259 (struct tu_draw_state_group) {
3260 .id = TU_DRAW_STATE_BLEND,
3261 .enable_mask = ENABLE_ALL,
3262 .ib = pipeline->blend.state_ib,
3263 };
3264 }
3265
3266 if (cmd->state.dirty &
3267 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3268 draw_state_groups[draw_state_group_count++] =
3269 (struct tu_draw_state_group) {
3270 .id = TU_DRAW_STATE_VS_CONST,
3271 .enable_mask = ENABLE_ALL,
3272 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3273 };
3274 draw_state_groups[draw_state_group_count++] =
3275 (struct tu_draw_state_group) {
3276 .id = TU_DRAW_STATE_FS_CONST,
3277 .enable_mask = ENABLE_DRAW,
3278 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3279 };
3280 }
3281
3282 if (cmd->state.dirty &
3283 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3284 bool needs_border = false;
3285 struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
3286
3287 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3288 MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3289 if (result != VK_SUCCESS)
3290 return result;
3291
3292 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3293 MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3294 if (result != VK_SUCCESS)
3295 return result;
3296
3297 result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3298 MESA_SHADER_FRAGMENT, &fs_ibo);
3299 if (result != VK_SUCCESS)
3300 return result;
3301
3302 draw_state_groups[draw_state_group_count++] =
3303 (struct tu_draw_state_group) {
3304 .id = TU_DRAW_STATE_VS_TEX,
3305 .enable_mask = ENABLE_ALL,
3306 .ib = vs_tex,
3307 };
3308 draw_state_groups[draw_state_group_count++] =
3309 (struct tu_draw_state_group) {
3310 .id = TU_DRAW_STATE_FS_TEX,
3311 .enable_mask = ENABLE_DRAW,
3312 .ib = fs_tex,
3313 };
3314 draw_state_groups[draw_state_group_count++] =
3315 (struct tu_draw_state_group) {
3316 .id = TU_DRAW_STATE_FS_IBO,
3317 .enable_mask = ENABLE_DRAW,
3318 .ib = fs_ibo,
3319 };
3320
3321 if (needs_border) {
3322 result = tu6_emit_border_color(cmd, cs);
3323 if (result != VK_SUCCESS)
3324 return result;
3325 }
3326 }
3327
3328 struct tu_cs_entry vs_params;
3329 result = tu6_emit_vs_params(cmd, draw, &vs_params);
3330 if (result != VK_SUCCESS)
3331 return result;
3332
3333 draw_state_groups[draw_state_group_count++] =
3334 (struct tu_draw_state_group) {
3335 .id = TU_DRAW_STATE_VS_PARAMS,
3336 .enable_mask = ENABLE_ALL,
3337 .ib = vs_params,
3338 };
3339
3340 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3341 for (uint32_t i = 0; i < draw_state_group_count; i++) {
3342 const struct tu_draw_state_group *group = &draw_state_groups[i];
3343 debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3344 uint32_t cp_set_draw_state =
3345 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3346 group->enable_mask |
3347 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3348 uint64_t iova;
3349 if (group->ib.size) {
3350 iova = group->ib.bo->iova + group->ib.offset;
3351 } else {
3352 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3353 iova = 0;
3354 }
3355
3356 tu_cs_emit(cs, cp_set_draw_state);
3357 tu_cs_emit_qw(cs, iova);
3358 }
3359
3360 tu_cs_sanity_check(cs);
3361
3362 /* track BOs */
3363 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3364 for (uint32_t i = 0; i < MAX_VBS; i++) {
3365 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3366 if (buf)
3367 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3368 }
3369 }
3370 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3371 unsigned i;
3372 for_each_bit(i, descriptors_state->valid) {
3373 struct tu_descriptor_set *set = descriptors_state->sets[i];
3374 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3375 if (set->descriptors[j]) {
3376 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3377 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3378 }
3379 }
3380 }
3381
3382 /* Fragment shader state overwrites compute shader state, so flag the
3383 * compute pipeline for re-emit.
3384 */
3385 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3386 return VK_SUCCESS;
3387 }
3388
3389 static void
3390 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3391 struct tu_cs *cs,
3392 const struct tu_draw_info *draw)
3393 {
3394
3395 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3396
3397 tu_cs_emit_regs(cs,
3398 A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3399 A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3400
3401 /* TODO hw binning */
3402 if (draw->indexed) {
3403 const enum a4xx_index_size index_size =
3404 tu6_index_size(cmd->state.index_type);
3405 const uint32_t index_bytes =
3406 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3407 const struct tu_buffer *buf = cmd->state.index_buffer;
3408 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3409 index_bytes * draw->first_index;
3410 const uint32_t size = index_bytes * draw->count;
3411
3412 const uint32_t cp_draw_indx =
3413 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3414 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3415 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3416 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3417
3418 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3419 tu_cs_emit(cs, cp_draw_indx);
3420 tu_cs_emit(cs, draw->instance_count);
3421 tu_cs_emit(cs, draw->count);
3422 tu_cs_emit(cs, 0x0); /* XXX */
3423 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3424 tu_cs_emit(cs, size);
3425 } else {
3426 const uint32_t cp_draw_indx =
3427 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3428 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3429 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3430
3431 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3432 tu_cs_emit(cs, cp_draw_indx);
3433 tu_cs_emit(cs, draw->instance_count);
3434 tu_cs_emit(cs, draw->count);
3435 }
3436 }
3437
3438 static void
3439 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3440 {
3441 struct tu_cs *cs = &cmd->draw_cs;
3442 VkResult result;
3443
3444 result = tu6_bind_draw_states(cmd, cs, draw);
3445 if (result != VK_SUCCESS) {
3446 cmd->record_result = result;
3447 return;
3448 }
3449
3450 result = tu_cs_reserve_space(cmd->device, cs, 32);
3451 if (result != VK_SUCCESS) {
3452 cmd->record_result = result;
3453 return;
3454 }
3455
3456 if (draw->indirect) {
3457 tu_finishme("indirect draw");
3458 return;
3459 }
3460
3461 /* TODO tu6_emit_marker should pick different regs depending on cs */
3462
3463 tu6_emit_marker(cmd, cs);
3464 tu6_emit_draw_direct(cmd, cs, draw);
3465 tu6_emit_marker(cmd, cs);
3466
3467 cmd->wait_for_idle = true;
3468
3469 tu_cs_sanity_check(cs);
3470 }
3471
3472 void
3473 tu_CmdDraw(VkCommandBuffer commandBuffer,
3474 uint32_t vertexCount,
3475 uint32_t instanceCount,
3476 uint32_t firstVertex,
3477 uint32_t firstInstance)
3478 {
3479 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3480 struct tu_draw_info info = {};
3481
3482 info.count = vertexCount;
3483 info.instance_count = instanceCount;
3484 info.first_instance = firstInstance;
3485 info.vertex_offset = firstVertex;
3486
3487 tu_draw(cmd_buffer, &info);
3488 }
3489
3490 void
3491 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3492 uint32_t indexCount,
3493 uint32_t instanceCount,
3494 uint32_t firstIndex,
3495 int32_t vertexOffset,
3496 uint32_t firstInstance)
3497 {
3498 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3499 struct tu_draw_info info = {};
3500
3501 info.indexed = true;
3502 info.count = indexCount;
3503 info.instance_count = instanceCount;
3504 info.first_index = firstIndex;
3505 info.vertex_offset = vertexOffset;
3506 info.first_instance = firstInstance;
3507
3508 tu_draw(cmd_buffer, &info);
3509 }
3510
3511 void
3512 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3513 VkBuffer _buffer,
3514 VkDeviceSize offset,
3515 uint32_t drawCount,
3516 uint32_t stride)
3517 {
3518 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3519 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3520 struct tu_draw_info info = {};
3521
3522 info.count = drawCount;
3523 info.indirect = buffer;
3524 info.indirect_offset = offset;
3525 info.stride = stride;
3526
3527 tu_draw(cmd_buffer, &info);
3528 }
3529
3530 void
3531 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3532 VkBuffer _buffer,
3533 VkDeviceSize offset,
3534 uint32_t drawCount,
3535 uint32_t stride)
3536 {
3537 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3538 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3539 struct tu_draw_info info = {};
3540
3541 info.indexed = true;
3542 info.count = drawCount;
3543 info.indirect = buffer;
3544 info.indirect_offset = offset;
3545 info.stride = stride;
3546
3547 tu_draw(cmd_buffer, &info);
3548 }
3549
3550 struct tu_dispatch_info
3551 {
3552 /**
3553 * Determine the layout of the grid (in block units) to be used.
3554 */
3555 uint32_t blocks[3];
3556
3557 /**
3558 * A starting offset for the grid. If unaligned is set, the offset
3559 * must still be aligned.
3560 */
3561 uint32_t offsets[3];
3562 /**
3563 * Whether it's an unaligned compute dispatch.
3564 */
3565 bool unaligned;
3566
3567 /**
3568 * Indirect compute parameters resource.
3569 */
3570 struct tu_buffer *indirect;
3571 uint64_t indirect_offset;
3572 };
3573
3574 static void
3575 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3576 const struct tu_dispatch_info *info)
3577 {
3578 gl_shader_stage type = MESA_SHADER_COMPUTE;
3579 const struct tu_program_descriptor_linkage *link =
3580 &pipeline->program.link[type];
3581 const struct ir3_const_state *const_state = &link->const_state;
3582 uint32_t offset = const_state->offsets.driver_param;
3583
3584 if (link->constlen <= offset)
3585 return;
3586
3587 if (!info->indirect) {
3588 uint32_t driver_params[IR3_DP_CS_COUNT] = {
3589 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3590 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3591 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3592 [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3593 [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3594 [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3595 };
3596
3597 uint32_t num_consts = MIN2(const_state->num_driver_params,
3598 (link->constlen - offset) * 4);
3599 /* push constants */
3600 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3601 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3602 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3603 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3604 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3605 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3606 tu_cs_emit(cs, 0);
3607 tu_cs_emit(cs, 0);
3608 uint32_t i;
3609 for (i = 0; i < num_consts; i++)
3610 tu_cs_emit(cs, driver_params[i]);
3611 } else {
3612 tu_finishme("Indirect driver params");
3613 }
3614 }
3615
3616 static void
3617 tu_dispatch(struct tu_cmd_buffer *cmd,
3618 const struct tu_dispatch_info *info)
3619 {
3620 struct tu_cs *cs = &cmd->cs;
3621 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3622 struct tu_descriptor_state *descriptors_state =
3623 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3624
3625 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3626 if (result != VK_SUCCESS) {
3627 cmd->record_result = result;
3628 return;
3629 }
3630
3631 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3632 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3633
3634 struct tu_cs_entry ib;
3635
3636 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3637 if (ib.size)
3638 tu_cs_emit_ib(cs, &ib);
3639
3640 tu_emit_compute_driver_params(cs, pipeline, info);
3641
3642 bool needs_border;
3643 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3644 MESA_SHADER_COMPUTE, &ib, &needs_border);
3645 if (result != VK_SUCCESS) {
3646 cmd->record_result = result;
3647 return;
3648 }
3649
3650 if (ib.size)
3651 tu_cs_emit_ib(cs, &ib);
3652
3653 if (needs_border)
3654 tu_finishme("compute border color");
3655
3656 result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3657 if (result != VK_SUCCESS) {
3658 cmd->record_result = result;
3659 return;
3660 }
3661
3662 if (ib.size)
3663 tu_cs_emit_ib(cs, &ib);
3664
3665 /* track BOs */
3666 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3667 unsigned i;
3668 for_each_bit(i, descriptors_state->valid) {
3669 struct tu_descriptor_set *set = descriptors_state->sets[i];
3670 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3671 if (set->descriptors[j]) {
3672 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3673 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3674 }
3675 }
3676 }
3677
3678 /* Compute shader state overwrites fragment shader state, so we flag the
3679 * graphics pipeline for re-emit.
3680 */
3681 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3682
3683 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3684 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3685
3686 const uint32_t *local_size = pipeline->compute.local_size;
3687 const uint32_t *num_groups = info->blocks;
3688 tu_cs_emit_regs(cs,
3689 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3690 .localsizex = local_size[0] - 1,
3691 .localsizey = local_size[1] - 1,
3692 .localsizez = local_size[2] - 1),
3693 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3694 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3695 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3696 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3697 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3698 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3699
3700 tu_cs_emit_regs(cs,
3701 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3702 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3703 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3704
3705 if (info->indirect) {
3706 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3707
3708 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3709 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3710
3711 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3712 tu_cs_emit(cs, 0x00000000);
3713 tu_cs_emit_qw(cs, iova);
3714 tu_cs_emit(cs,
3715 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3716 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3717 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3718 } else {
3719 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3720 tu_cs_emit(cs, 0x00000000);
3721 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3722 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3723 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3724 }
3725
3726 tu_cs_emit_wfi(cs);
3727
3728 tu6_emit_cache_flush(cmd, cs);
3729 }
3730
3731 void
3732 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3733 uint32_t base_x,
3734 uint32_t base_y,
3735 uint32_t base_z,
3736 uint32_t x,
3737 uint32_t y,
3738 uint32_t z)
3739 {
3740 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3741 struct tu_dispatch_info info = {};
3742
3743 info.blocks[0] = x;
3744 info.blocks[1] = y;
3745 info.blocks[2] = z;
3746
3747 info.offsets[0] = base_x;
3748 info.offsets[1] = base_y;
3749 info.offsets[2] = base_z;
3750 tu_dispatch(cmd_buffer, &info);
3751 }
3752
3753 void
3754 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3755 uint32_t x,
3756 uint32_t y,
3757 uint32_t z)
3758 {
3759 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3760 }
3761
3762 void
3763 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3764 VkBuffer _buffer,
3765 VkDeviceSize offset)
3766 {
3767 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3768 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3769 struct tu_dispatch_info info = {};
3770
3771 info.indirect = buffer;
3772 info.indirect_offset = offset;
3773
3774 tu_dispatch(cmd_buffer, &info);
3775 }
3776
3777 void
3778 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3779 {
3780 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3781
3782 tu_cs_end(&cmd_buffer->draw_cs);
3783
3784 tu_cmd_render_tiles(cmd_buffer);
3785
3786 /* discard draw_cs entries now that the tiles are rendered */
3787 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3788 tu_cs_begin(&cmd_buffer->draw_cs);
3789
3790 cmd_buffer->state.pass = NULL;
3791 cmd_buffer->state.subpass = NULL;
3792 cmd_buffer->state.framebuffer = NULL;
3793 }
3794
3795 void
3796 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3797 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3798 {
3799 tu_CmdEndRenderPass(commandBuffer);
3800 }
3801
3802 struct tu_barrier_info
3803 {
3804 uint32_t eventCount;
3805 const VkEvent *pEvents;
3806 VkPipelineStageFlags srcStageMask;
3807 };
3808
3809 static void
3810 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3811 uint32_t memoryBarrierCount,
3812 const VkMemoryBarrier *pMemoryBarriers,
3813 uint32_t bufferMemoryBarrierCount,
3814 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3815 uint32_t imageMemoryBarrierCount,
3816 const VkImageMemoryBarrier *pImageMemoryBarriers,
3817 const struct tu_barrier_info *info)
3818 {
3819 }
3820
3821 void
3822 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3823 VkPipelineStageFlags srcStageMask,
3824 VkPipelineStageFlags destStageMask,
3825 VkBool32 byRegion,
3826 uint32_t memoryBarrierCount,
3827 const VkMemoryBarrier *pMemoryBarriers,
3828 uint32_t bufferMemoryBarrierCount,
3829 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3830 uint32_t imageMemoryBarrierCount,
3831 const VkImageMemoryBarrier *pImageMemoryBarriers)
3832 {
3833 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3834 struct tu_barrier_info info;
3835
3836 info.eventCount = 0;
3837 info.pEvents = NULL;
3838 info.srcStageMask = srcStageMask;
3839
3840 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3841 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3842 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3843 }
3844
3845 static void
3846 write_event(struct tu_cmd_buffer *cmd_buffer,
3847 struct tu_event *event,
3848 VkPipelineStageFlags stageMask,
3849 unsigned value)
3850 {
3851 }
3852
3853 void
3854 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3855 VkEvent _event,
3856 VkPipelineStageFlags stageMask)
3857 {
3858 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3859 TU_FROM_HANDLE(tu_event, event, _event);
3860
3861 write_event(cmd_buffer, event, stageMask, 1);
3862 }
3863
3864 void
3865 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3866 VkEvent _event,
3867 VkPipelineStageFlags stageMask)
3868 {
3869 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3870 TU_FROM_HANDLE(tu_event, event, _event);
3871
3872 write_event(cmd_buffer, event, stageMask, 0);
3873 }
3874
3875 void
3876 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3877 uint32_t eventCount,
3878 const VkEvent *pEvents,
3879 VkPipelineStageFlags srcStageMask,
3880 VkPipelineStageFlags dstStageMask,
3881 uint32_t memoryBarrierCount,
3882 const VkMemoryBarrier *pMemoryBarriers,
3883 uint32_t bufferMemoryBarrierCount,
3884 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3885 uint32_t imageMemoryBarrierCount,
3886 const VkImageMemoryBarrier *pImageMemoryBarriers)
3887 {
3888 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3889 struct tu_barrier_info info;
3890
3891 info.eventCount = eventCount;
3892 info.pEvents = pEvents;
3893 info.srcStageMask = 0;
3894
3895 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3896 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3897 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3898 }
3899
3900 void
3901 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3902 {
3903 /* No-op */
3904 }