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freedreno: Use new macros for CP_WAIT_REG_MEM and CP_WAIT_MEM_GTE
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40
41 void
42 tu_bo_list_init(struct tu_bo_list *list)
43 {
44 list->count = list->capacity = 0;
45 list->bo_infos = NULL;
46 }
47
48 void
49 tu_bo_list_destroy(struct tu_bo_list *list)
50 {
51 free(list->bo_infos);
52 }
53
54 void
55 tu_bo_list_reset(struct tu_bo_list *list)
56 {
57 list->count = 0;
58 }
59
60 /**
61 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 */
63 static uint32_t
64 tu_bo_list_add_info(struct tu_bo_list *list,
65 const struct drm_msm_gem_submit_bo *bo_info)
66 {
67 assert(bo_info->handle != 0);
68
69 for (uint32_t i = 0; i < list->count; ++i) {
70 if (list->bo_infos[i].handle == bo_info->handle) {
71 assert(list->bo_infos[i].presumed == bo_info->presumed);
72 list->bo_infos[i].flags |= bo_info->flags;
73 return i;
74 }
75 }
76
77 /* grow list->bo_infos if needed */
78 if (list->count == list->capacity) {
79 uint32_t new_capacity = MAX2(2 * list->count, 16);
80 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
81 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
82 if (!new_bo_infos)
83 return TU_BO_LIST_FAILED;
84 list->bo_infos = new_bo_infos;
85 list->capacity = new_capacity;
86 }
87
88 list->bo_infos[list->count] = *bo_info;
89 return list->count++;
90 }
91
92 uint32_t
93 tu_bo_list_add(struct tu_bo_list *list,
94 const struct tu_bo *bo,
95 uint32_t flags)
96 {
97 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
98 .flags = flags,
99 .handle = bo->gem_handle,
100 .presumed = bo->iova,
101 });
102 }
103
104 VkResult
105 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
106 {
107 for (uint32_t i = 0; i < other->count; i++) {
108 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
109 return VK_ERROR_OUT_OF_HOST_MEMORY;
110 }
111
112 return VK_SUCCESS;
113 }
114
115 static VkResult
116 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
117 const struct tu_device *dev)
118 {
119 const uint32_t gmem_size = dev->physical_device->gmem_size;
120 uint32_t offset = 0;
121
122 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
123 /* 16KB-aligned */
124 offset = align(offset, 0x4000);
125
126 tiling->gmem_offsets[i] = offset;
127 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
128 tiling->buffer_cpp[i];
129 }
130
131 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
132 }
133
134 static void
135 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
136 const struct tu_device *dev)
137 {
138 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
139 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
140 const uint32_t max_tile_width = 1024; /* A6xx */
141
142 tiling->tile0.offset = (VkOffset2D) {
143 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
144 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
145 };
146
147 const uint32_t ra_width =
148 tiling->render_area.extent.width +
149 (tiling->render_area.offset.x - tiling->tile0.offset.x);
150 const uint32_t ra_height =
151 tiling->render_area.extent.height +
152 (tiling->render_area.offset.y - tiling->tile0.offset.y);
153
154 /* start from 1 tile */
155 tiling->tile_count = (VkExtent2D) {
156 .width = 1,
157 .height = 1,
158 };
159 tiling->tile0.extent = (VkExtent2D) {
160 .width = align(ra_width, tile_align_w),
161 .height = align(ra_height, tile_align_h),
162 };
163
164 /* do not exceed max tile width */
165 while (tiling->tile0.extent.width > max_tile_width) {
166 tiling->tile_count.width++;
167 tiling->tile0.extent.width =
168 align(ra_width / tiling->tile_count.width, tile_align_w);
169 }
170
171 /* do not exceed gmem size */
172 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
173 if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
174 tiling->tile_count.width++;
175 tiling->tile0.extent.width =
176 align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
177 } else {
178 /* if this assert fails then layout is impossible.. */
179 assert(tiling->tile0.extent.height > tile_align_h);
180 tiling->tile_count.height++;
181 tiling->tile0.extent.height =
182 align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
183 }
184 }
185 }
186
187 static void
188 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
189 const struct tu_device *dev)
190 {
191 const uint32_t max_pipe_count = 32; /* A6xx */
192
193 /* start from 1 tile per pipe */
194 tiling->pipe0 = (VkExtent2D) {
195 .width = 1,
196 .height = 1,
197 };
198 tiling->pipe_count = tiling->tile_count;
199
200 /* do not exceed max pipe count vertically */
201 while (tiling->pipe_count.height > max_pipe_count) {
202 tiling->pipe0.height += 2;
203 tiling->pipe_count.height =
204 (tiling->tile_count.height + tiling->pipe0.height - 1) /
205 tiling->pipe0.height;
206 }
207
208 /* do not exceed max pipe count */
209 while (tiling->pipe_count.width * tiling->pipe_count.height >
210 max_pipe_count) {
211 tiling->pipe0.width += 1;
212 tiling->pipe_count.width =
213 (tiling->tile_count.width + tiling->pipe0.width - 1) /
214 tiling->pipe0.width;
215 }
216 }
217
218 static void
219 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
220 const struct tu_device *dev)
221 {
222 const uint32_t max_pipe_count = 32; /* A6xx */
223 const uint32_t used_pipe_count =
224 tiling->pipe_count.width * tiling->pipe_count.height;
225 const VkExtent2D last_pipe = {
226 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
227 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
228 };
229
230 assert(used_pipe_count <= max_pipe_count);
231 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
232
233 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
234 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
235 const uint32_t pipe_x = tiling->pipe0.width * x;
236 const uint32_t pipe_y = tiling->pipe0.height * y;
237 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
238 ? last_pipe.width
239 : tiling->pipe0.width;
240 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
241 ? last_pipe.height
242 : tiling->pipe0.height;
243 const uint32_t n = tiling->pipe_count.width * y + x;
244
245 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
246 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
247 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
248 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
249 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
250 }
251 }
252
253 memset(tiling->pipe_config + used_pipe_count, 0,
254 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
255 }
256
257 static void
258 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
259 const struct tu_device *dev,
260 uint32_t tx,
261 uint32_t ty,
262 struct tu_tile *tile)
263 {
264 /* find the pipe and the slot for tile (tx, ty) */
265 const uint32_t px = tx / tiling->pipe0.width;
266 const uint32_t py = ty / tiling->pipe0.height;
267 const uint32_t sx = tx - tiling->pipe0.width * px;
268 const uint32_t sy = ty - tiling->pipe0.height * py;
269
270 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
271 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
272 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
273
274 /* convert to 1D indices */
275 tile->pipe = tiling->pipe_count.width * py + px;
276 tile->slot = tiling->pipe0.width * sy + sx;
277
278 /* get the blit area for the tile */
279 tile->begin = (VkOffset2D) {
280 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
281 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
282 };
283 tile->end.x =
284 (tx == tiling->tile_count.width - 1)
285 ? tiling->render_area.offset.x + tiling->render_area.extent.width
286 : tile->begin.x + tiling->tile0.extent.width;
287 tile->end.y =
288 (ty == tiling->tile_count.height - 1)
289 ? tiling->render_area.offset.y + tiling->render_area.extent.height
290 : tile->begin.y + tiling->tile0.extent.height;
291 }
292
293 enum a3xx_msaa_samples
294 tu_msaa_samples(uint32_t samples)
295 {
296 switch (samples) {
297 case 1:
298 return MSAA_ONE;
299 case 2:
300 return MSAA_TWO;
301 case 4:
302 return MSAA_FOUR;
303 case 8:
304 return MSAA_EIGHT;
305 default:
306 assert(!"invalid sample count");
307 return MSAA_ONE;
308 }
309 }
310
311 static enum a4xx_index_size
312 tu6_index_size(VkIndexType type)
313 {
314 switch (type) {
315 case VK_INDEX_TYPE_UINT16:
316 return INDEX4_SIZE_16_BIT;
317 case VK_INDEX_TYPE_UINT32:
318 return INDEX4_SIZE_32_BIT;
319 default:
320 unreachable("invalid VkIndexType");
321 return INDEX4_SIZE_8_BIT;
322 }
323 }
324
325 static void
326 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
327 {
328 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
329 }
330
331 unsigned
332 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
333 struct tu_cs *cs,
334 enum vgt_event_type event,
335 bool need_seqno)
336 {
337 unsigned seqno = 0;
338
339 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
340 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
341 if (need_seqno) {
342 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
343 seqno = ++cmd->scratch_seqno;
344 tu_cs_emit(cs, seqno);
345 }
346
347 return seqno;
348 }
349
350 static void
351 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu6_emit_event_write(cmd, cs, 0x31, false);
354 }
355
356 static void
357 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
358 {
359 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
360 }
361
362 static void
363 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
364 {
365 if (cmd->wait_for_idle) {
366 tu_cs_emit_wfi(cs);
367 cmd->wait_for_idle = false;
368 }
369 }
370
371 static void
372 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
373 {
374 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
375 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
376 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
377 if (iview->image->layout.ubwc_size) {
378 tu_cs_emit_qw(cs, va);
379 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
380 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
381 } else {
382 tu_cs_emit_qw(cs, 0);
383 tu_cs_emit(cs, 0);
384 }
385 }
386
387 static void
388 tu6_emit_zs(struct tu_cmd_buffer *cmd,
389 const struct tu_subpass *subpass,
390 struct tu_cs *cs)
391 {
392 const struct tu_framebuffer *fb = cmd->state.framebuffer;
393 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
394
395 const uint32_t a = subpass->depth_stencil_attachment.attachment;
396 if (a == VK_ATTACHMENT_UNUSED) {
397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
398 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
399 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
400 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
401 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
402 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
403 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
404
405 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
406 tu_cs_emit(cs,
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
410 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
411 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
412 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
413 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
414 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
417 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
418
419 return;
420 }
421
422 const struct tu_image_view *iview = fb->attachments[a].attachment;
423 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
424
425 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
426 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
427 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
428 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size));
429 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
430 tu_cs_emit(cs, tiling->gmem_offsets[a]);
431
432 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
433 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
436 tu6_emit_flag_buffer(cs, iview);
437
438 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
439 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
440 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
441 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
442 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
443 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
444
445 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
446 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
447
448 /* enable zs? */
449 }
450
451 static void
452 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
453 const struct tu_subpass *subpass,
454 struct tu_cs *cs)
455 {
456 const struct tu_framebuffer *fb = cmd->state.framebuffer;
457 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
458 unsigned char mrt_comp[MAX_RTS] = { 0 };
459 unsigned srgb_cntl = 0;
460
461 for (uint32_t i = 0; i < subpass->color_count; ++i) {
462 uint32_t a = subpass->color_attachments[i].attachment;
463 if (a == VK_ATTACHMENT_UNUSED)
464 continue;
465
466 const struct tu_image_view *iview = fb->attachments[a].attachment;
467 const enum a6xx_tile_mode tile_mode =
468 tu6_get_image_tile_mode(iview->image, iview->base_mip);
469
470 mrt_comp[i] = 0xf;
471
472 if (vk_format_is_srgb(iview->vk_format))
473 srgb_cntl |= (1 << i);
474
475 const struct tu_native_format *format =
476 tu6_get_native_format(iview->vk_format);
477 assert(format && format->rb >= 0);
478
479 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
480 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
481 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
482 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
483 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
484 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layout.layer_size));
485 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
486 tu_cs_emit(
487 cs, tiling->gmem_offsets[a]); /* RB_MRT[i].BASE_GMEM */
488
489 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
490 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
491 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
492 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
493
494 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
495 tu6_emit_flag_buffer(cs, iview);
496 }
497
498 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
499 tu_cs_emit(cs, srgb_cntl);
500
501 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
502 tu_cs_emit(cs, srgb_cntl);
503
504 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
505 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
506 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
507 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
508 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
509 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
510 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
511 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
512 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
513
514 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
515 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
516 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
517 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
518 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
519 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
520 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
521 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
522 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
523 }
524
525 static void
526 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
527 const struct tu_subpass *subpass,
528 struct tu_cs *cs)
529 {
530 const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
533 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
534 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
535 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
536
537 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
538 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
539 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
540 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
541
542 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
543 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
544 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
545 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
546
547 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
548 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
549 }
550
551 static void
552 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
553 {
554 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
555 const uint32_t bin_w = tiling->tile0.extent.width;
556 const uint32_t bin_h = tiling->tile0.extent.height;
557
558 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
559 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
560 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
561
562 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
563 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
564 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
565
566 /* no flag for RB_BIN_CONTROL2... */
567 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
568 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
569 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
570 }
571
572 static void
573 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
574 struct tu_cs *cs,
575 bool binning)
576 {
577 uint32_t cntl = 0;
578 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
579 if (binning)
580 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
581
582 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
583 tu_cs_emit(cs, 0x2);
584 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
585 tu_cs_emit(cs, cntl);
586 }
587
588 static void
589 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
590 {
591 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
592 uint32_t x1 = render_area->offset.x;
593 uint32_t y1 = render_area->offset.y;
594 uint32_t x2 = x1 + render_area->extent.width - 1;
595 uint32_t y2 = y1 + render_area->extent.height - 1;
596
597 /* TODO: alignment requirement seems to be less than tile_align_w/h */
598 if (align) {
599 x1 = x1 & ~cmd->device->physical_device->tile_align_w;
600 y1 = y1 & ~cmd->device->physical_device->tile_align_h;
601 x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
602 y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
603 }
604
605 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
606 tu_cs_emit(cs,
607 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
608 tu_cs_emit(cs,
609 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
610 }
611
612 static void
613 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
614 struct tu_cs *cs,
615 const struct tu_image_view *iview,
616 uint32_t gmem_offset,
617 bool resolve)
618 {
619 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
620 tu_cs_emit(cs, resolve ? 0 : (A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM));
621
622 const struct tu_native_format *format =
623 tu6_get_native_format(iview->vk_format);
624 assert(format && format->rb >= 0);
625
626 enum a6xx_tile_mode tile_mode =
627 tu6_get_image_tile_mode(iview->image, iview->base_mip);
628 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
629 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
630 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
631 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
632 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
633 COND(iview->image->layout.ubwc_size,
634 A6XX_RB_BLIT_DST_INFO_FLAGS));
635 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
636 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
637 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
638
639 if (iview->image->layout.ubwc_size) {
640 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
641 tu6_emit_flag_buffer(cs, iview);
642 }
643
644 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
645 tu_cs_emit(cs, gmem_offset);
646 }
647
648 static void
649 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
650 {
651 tu6_emit_marker(cmd, cs);
652 tu6_emit_event_write(cmd, cs, BLIT, false);
653 tu6_emit_marker(cmd, cs);
654 }
655
656 static void
657 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
658 struct tu_cs *cs,
659 uint32_t x1,
660 uint32_t y1,
661 uint32_t x2,
662 uint32_t y2)
663 {
664 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
665 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
666 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
667 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
668 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
669
670 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
671 tu_cs_emit(
672 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
673 tu_cs_emit(
674 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
675 }
676
677 static void
678 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
679 struct tu_cs *cs,
680 uint32_t x1,
681 uint32_t y1)
682 {
683 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
684 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
687 tu_cs_emit(cs,
688 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
689
690 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
691 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
692
693 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
694 tu_cs_emit(
695 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
696 }
697
698 static bool
699 use_hw_binning(struct tu_cmd_buffer *cmd)
700 {
701 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
702
703 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
704 return false;
705
706 return (tiling->tile_count.width * tiling->tile_count.height) > 2;
707 }
708
709 static void
710 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
711 struct tu_cs *cs,
712 const struct tu_tile *tile)
713 {
714 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
715 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
716
717 tu6_emit_marker(cmd, cs);
718 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
719 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
720 tu6_emit_marker(cmd, cs);
721
722 const uint32_t x1 = tile->begin.x;
723 const uint32_t y1 = tile->begin.y;
724 const uint32_t x2 = tile->end.x - 1;
725 const uint32_t y2 = tile->end.y - 1;
726 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
727 tu6_emit_window_offset(cmd, cs, x1, y1);
728
729 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
730 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
731
732 if (use_hw_binning(cmd)) {
733 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
734
735 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
736 tu_cs_emit(cs, 0x0);
737
738 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
739 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
740 A6XX_CP_REG_TEST_0_BIT(0) |
741 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
742
743 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
744 tu_cs_emit(cs, 0x10000000);
745 tu_cs_emit(cs, 11); /* conditionally execute next 11 dwords */
746
747 /* if (no overflow) */ {
748 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
749 tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
750 CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
751 tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
752 tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
753 tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
754
755 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
756 tu_cs_emit(cs, 0x0);
757
758 /* use a NOP packet to skip over the 'else' side: */
759 tu_cs_emit_pkt7(cs, CP_NOP, 2);
760 } /* else */ {
761 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
762 tu_cs_emit(cs, 0x1);
763 }
764
765 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
766 tu_cs_emit(cs, 0x0);
767
768 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8804, 1);
769 tu_cs_emit(cs, 0x0);
770
771 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
772 tu_cs_emit(cs, 0x0);
773
774 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
775 tu_cs_emit(cs, 0x0);
776 } else {
777 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
778 tu_cs_emit(cs, 0x1);
779
780 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
781 tu_cs_emit(cs, 0x0);
782 }
783 }
784
785 static void
786 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
787 {
788 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
789 const struct tu_framebuffer *fb = cmd->state.framebuffer;
790 const struct tu_image_view *iview = fb->attachments[a].attachment;
791 const struct tu_render_pass_attachment *attachment =
792 &cmd->state.pass->attachments[a];
793
794 if (!attachment->needs_gmem)
795 return;
796
797 const uint32_t x1 = tiling->render_area.offset.x;
798 const uint32_t y1 = tiling->render_area.offset.y;
799 const uint32_t x2 = x1 + tiling->render_area.extent.width;
800 const uint32_t y2 = y1 + tiling->render_area.extent.height;
801 const uint32_t tile_x2 =
802 tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
803 const uint32_t tile_y2 =
804 tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
805 bool need_load =
806 x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
807 y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
808
809 if (need_load)
810 tu_finishme("improve handling of unaligned render area");
811
812 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
813 need_load = true;
814
815 if (vk_format_has_stencil(iview->vk_format) &&
816 attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
817 need_load = true;
818
819 if (need_load) {
820 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
821 tu6_emit_blit(cmd, cs);
822 }
823 }
824
825 static void
826 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
827 uint32_t a,
828 const VkRenderPassBeginInfo *info)
829 {
830 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
831 const struct tu_framebuffer *fb = cmd->state.framebuffer;
832 const struct tu_image_view *iview = fb->attachments[a].attachment;
833 const struct tu_render_pass_attachment *attachment =
834 &cmd->state.pass->attachments[a];
835 unsigned clear_mask = 0;
836
837 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
838 if (!attachment->needs_gmem)
839 return;
840
841 if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
842 clear_mask = 0xf;
843
844 if (vk_format_has_stencil(iview->vk_format)) {
845 clear_mask &= 0x1;
846 if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
847 clear_mask |= 0x2;
848 }
849 if (!clear_mask)
850 return;
851
852 const struct tu_native_format *format =
853 tu6_get_native_format(iview->vk_format);
854 assert(format && format->rb >= 0);
855
856 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
857 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
858
859 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
860 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(clear_mask));
861
862 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
863 tu_cs_emit(cs, tiling->gmem_offsets[a]);
864
865 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
866 tu_cs_emit(cs, 0);
867
868 uint32_t clear_vals[4] = { 0 };
869 tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
870
871 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
872 tu_cs_emit(cs, clear_vals[0]);
873 tu_cs_emit(cs, clear_vals[1]);
874 tu_cs_emit(cs, clear_vals[2]);
875 tu_cs_emit(cs, clear_vals[3]);
876
877 tu6_emit_blit(cmd, cs);
878 }
879
880 static void
881 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
882 struct tu_cs *cs,
883 uint32_t a,
884 uint32_t gmem_a)
885 {
886 if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
887 return;
888
889 tu6_emit_blit_info(cmd, cs,
890 cmd->state.framebuffer->attachments[a].attachment,
891 cmd->state.tiling_config.gmem_offsets[gmem_a], true);
892 tu6_emit_blit(cmd, cs);
893 }
894
895 static void
896 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
897 {
898 const struct tu_render_pass *pass = cmd->state.pass;
899 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
900
901 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
902 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
903 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
904 CP_SET_DRAW_STATE__0_GROUP_ID(0));
905 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
906 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
907
908 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
909 tu_cs_emit(cs, 0x0);
910
911 tu6_emit_marker(cmd, cs);
912 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
913 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
914 tu6_emit_marker(cmd, cs);
915
916 tu6_emit_blit_scissor(cmd, cs, true);
917
918 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
919 if (pass->attachments[a].needs_gmem)
920 tu6_emit_store_attachment(cmd, cs, a, a);
921 }
922
923 if (subpass->resolve_attachments) {
924 for (unsigned i = 0; i < subpass->color_count; i++) {
925 uint32_t a = subpass->resolve_attachments[i].attachment;
926 if (a != VK_ATTACHMENT_UNUSED)
927 tu6_emit_store_attachment(cmd, cs, a,
928 subpass->color_attachments[i].attachment);
929 }
930 }
931 }
932
933 static void
934 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
935 {
936 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
937 tu_cs_emit(cs, restart_index);
938 }
939
940 static void
941 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
942 {
943 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
944 if (result != VK_SUCCESS) {
945 cmd->record_result = result;
946 return;
947 }
948
949 tu6_emit_cache_flush(cmd, cs);
950
951 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
952
953 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
954 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
955 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
956 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
957 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
958 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
959 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
960 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
961 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
962
963 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
965 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
967 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
971 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
972 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
974 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
975 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
976 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
977
978 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
979
980 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
983
984 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
985 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
986 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
987 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
988 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
989 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
990 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
991 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
992 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
993 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
994 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
995 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
996
997 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
998 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
999
1000 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1001 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1002
1003 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1004 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1005
1006 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1007 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1008 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1009
1010 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1011 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1012
1013 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1014
1015 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1016
1017 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1018 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1019 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1020 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1021 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1022 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1023 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1024 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1025 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1026 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1027 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1028 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1029 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1030 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1031 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1032 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1033 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1034 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1035 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1036 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1037 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1038
1039 tu6_emit_marker(cmd, cs);
1040
1041 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1042
1043 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1044
1045 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1046
1047 /* we don't use this yet.. probably best to disable.. */
1048 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1049 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1050 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1051 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1052 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1053 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1054
1055 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1056 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1057 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1058 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1059
1060 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1061 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1062 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1063
1064 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1065 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1066
1067 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1068 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1069
1070 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1071 tu_cs_emit(cs, 0x00000000);
1072 tu_cs_emit(cs, 0x00000000);
1073 tu_cs_emit(cs, 0x00000000);
1074
1075 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1076 tu_cs_emit(cs, 0x00000000);
1077 tu_cs_emit(cs, 0x00000000);
1078 tu_cs_emit(cs, 0x00000000);
1079 tu_cs_emit(cs, 0x00000000);
1080 tu_cs_emit(cs, 0x00000000);
1081 tu_cs_emit(cs, 0x00000000);
1082
1083 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1084 tu_cs_emit(cs, 0x00000000);
1085 tu_cs_emit(cs, 0x00000000);
1086 tu_cs_emit(cs, 0x00000000);
1087 tu_cs_emit(cs, 0x00000000);
1088 tu_cs_emit(cs, 0x00000000);
1089 tu_cs_emit(cs, 0x00000000);
1090
1091 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1092 tu_cs_emit(cs, 0x00000000);
1093 tu_cs_emit(cs, 0x00000000);
1094 tu_cs_emit(cs, 0x00000000);
1095
1096 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1097 tu_cs_emit(cs, 0x00000000);
1098
1099 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1100 tu_cs_emit(cs, 0x00000000);
1101
1102 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1103 tu_cs_emit(cs, 0x00000000);
1104
1105 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1106 tu_cs_emit(cs, 0x00000000);
1107
1108 tu_cs_sanity_check(cs);
1109 }
1110
1111 static void
1112 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1113 {
1114 unsigned seqno;
1115
1116 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1117
1118 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1119 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1120 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1121 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1122 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1123 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1124 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1125
1126 seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1127
1128 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1129 tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1130 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1131 tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1132 }
1133
1134 static void
1135 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1136 {
1137 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1138
1139 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_SIZE, 3);
1140 tu_cs_emit(cs, A6XX_VSC_BIN_SIZE_WIDTH(tiling->tile0.extent.width) |
1141 A6XX_VSC_BIN_SIZE_HEIGHT(tiling->tile0.extent.height));
1142 tu_cs_emit_qw(cs, cmd->vsc_data.iova + 32 * cmd->vsc_data_pitch); /* VSC_SIZE_ADDRESS_LO/HI */
1143
1144 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_COUNT, 1);
1145 tu_cs_emit(cs, A6XX_VSC_BIN_COUNT_NX(tiling->tile_count.width) |
1146 A6XX_VSC_BIN_COUNT_NY(tiling->tile_count.height));
1147
1148 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1149 for (unsigned i = 0; i < 32; i++)
1150 tu_cs_emit(cs, tiling->pipe_config[i]);
1151
1152 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
1153 tu_cs_emit_qw(cs, cmd->vsc_data2.iova);
1154 tu_cs_emit(cs, cmd->vsc_data2_pitch);
1155 tu_cs_emit(cs, cmd->vsc_data2.size);
1156
1157 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
1158 tu_cs_emit_qw(cs, cmd->vsc_data.iova);
1159 tu_cs_emit(cs, cmd->vsc_data_pitch);
1160 tu_cs_emit(cs, cmd->vsc_data.size);
1161 }
1162
1163 static void
1164 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1165 {
1166 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1167 const uint32_t used_pipe_count =
1168 tiling->pipe_count.width * tiling->pipe_count.height;
1169
1170 /* Clear vsc_scratch: */
1171 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1172 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1173 tu_cs_emit(cs, 0x0);
1174
1175 /* Check for overflow, write vsc_scratch if detected: */
1176 for (int i = 0; i < used_pipe_count; i++) {
1177 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1178 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1179 CP_COND_WRITE5_0_WRITE_MEMORY);
1180 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1181 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1182 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1183 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1184 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1185 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1186
1187 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1188 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1189 CP_COND_WRITE5_0_WRITE_MEMORY);
1190 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1191 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1192 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1193 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1194 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1195 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1196 }
1197
1198 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1199
1200 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1201
1202 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1203 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1204 CP_MEM_TO_REG_0_CNT(1 - 1));
1205 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1206
1207 /*
1208 * This is a bit awkward, we really want a way to invert the
1209 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1210 * execute cmds to use hwbinning when a bit is *not* set. This
1211 * dance is to invert OVERFLOW_FLAG_REG
1212 *
1213 * A CP_NOP packet is used to skip executing the 'else' clause
1214 * if (b0 set)..
1215 */
1216
1217 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1218 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1219 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1220 A6XX_CP_REG_TEST_0_BIT(0) |
1221 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1222
1223 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1224 tu_cs_emit(cs, 0x10000000);
1225 tu_cs_emit(cs, 7); /* conditionally execute next 7 dwords */
1226
1227 /* if (b0 set) */ {
1228 /*
1229 * On overflow, mirror the value to control->vsc_overflow
1230 * which CPU is checking to detect overflow (see
1231 * check_vsc_overflow())
1232 */
1233 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1234 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1235 CP_REG_TO_MEM_0_CNT(0));
1236 tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1237
1238 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1239 tu_cs_emit(cs, 0x0);
1240
1241 tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
1242 } /* else */ {
1243 tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1244 tu_cs_emit(cs, 0x1);
1245 }
1246 }
1247
1248 static void
1249 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1250 {
1251 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1252
1253 uint32_t x1 = tiling->tile0.offset.x;
1254 uint32_t y1 = tiling->tile0.offset.y;
1255 uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1256 uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1257
1258 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1259
1260 tu6_emit_marker(cmd, cs);
1261 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1262 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1263 tu6_emit_marker(cmd, cs);
1264
1265 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1266 tu_cs_emit(cs, 0x1);
1267
1268 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1269 tu_cs_emit(cs, 0x1);
1270
1271 tu_cs_emit_wfi(cs);
1272
1273 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1274 tu_cs_emit(cs, A6XX_VFD_MODE_CNTL_BINNING_PASS);
1275
1276 update_vsc_pipe(cmd, cs);
1277
1278 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1279 tu_cs_emit(cs, 0x1);
1280
1281 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1282 tu_cs_emit(cs, 0x1);
1283
1284 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1285 tu_cs_emit(cs, UNK_2C);
1286
1287 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
1288 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(0) |
1289 A6XX_RB_WINDOW_OFFSET_Y(0));
1290
1291 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
1292 tu_cs_emit(cs, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
1293 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
1294
1295 /* emit IB to binning drawcmds: */
1296 tu_cs_emit_call(cs, &cmd->draw_cs);
1297
1298 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1299 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1300 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1301 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1302 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1303 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1304
1305 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1306 tu_cs_emit(cs, UNK_2D);
1307
1308 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1309 tu6_cache_flush(cmd, cs);
1310
1311 tu_cs_emit_wfi(cs);
1312
1313 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1314
1315 emit_vsc_overflow_test(cmd, cs);
1316
1317 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1318 tu_cs_emit(cs, 0x0);
1319
1320 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1321 tu_cs_emit(cs, 0x0);
1322
1323 tu_cs_emit_wfi(cs);
1324
1325 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1326 tu_cs_emit(cs, 0x7c400004);
1327
1328 cmd->wait_for_idle = false;
1329 }
1330
1331 static void
1332 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1333 {
1334 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1335 if (result != VK_SUCCESS) {
1336 cmd->record_result = result;
1337 return;
1338 }
1339
1340 tu6_emit_lrz_flush(cmd, cs);
1341
1342 /* lrz clear? */
1343
1344 tu6_emit_cache_flush(cmd, cs);
1345
1346 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1347 tu_cs_emit(cs, 0x0);
1348
1349 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1350 tu6_emit_wfi(cmd, cs);
1351 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1352 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1353
1354 if (use_hw_binning(cmd)) {
1355 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1356
1357 tu6_emit_render_cntl(cmd, cs, true);
1358
1359 tu6_emit_binning_pass(cmd, cs);
1360
1361 tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1362
1363 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1364 tu_cs_emit(cs, 0x0);
1365
1366 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1367 tu_cs_emit(cs, 0x1);
1368
1369 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1370 tu_cs_emit(cs, 0x1);
1371
1372 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1373 tu_cs_emit(cs, 0x1);
1374 } else {
1375 tu6_emit_bin_size(cmd, cs, 0x6000000);
1376 }
1377
1378 tu6_emit_render_cntl(cmd, cs, false);
1379
1380 tu_cs_sanity_check(cs);
1381 }
1382
1383 static void
1384 tu6_render_tile(struct tu_cmd_buffer *cmd,
1385 struct tu_cs *cs,
1386 const struct tu_tile *tile)
1387 {
1388 const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1389 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1390 if (result != VK_SUCCESS) {
1391 cmd->record_result = result;
1392 return;
1393 }
1394
1395 tu6_emit_tile_select(cmd, cs, tile);
1396 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1397
1398 tu_cs_emit_call(cs, &cmd->draw_cs);
1399 cmd->wait_for_idle = true;
1400
1401 if (use_hw_binning(cmd)) {
1402 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1403 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1404 A6XX_CP_REG_TEST_0_BIT(0) |
1405 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1406
1407 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1408 tu_cs_emit(cs, 0x10000000);
1409 tu_cs_emit(cs, 2); /* conditionally execute next 2 dwords */
1410
1411 /* if (no overflow) */ {
1412 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1413 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1414 }
1415 }
1416
1417 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1418
1419 tu_cs_sanity_check(cs);
1420 }
1421
1422 static void
1423 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1424 {
1425 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1426 if (result != VK_SUCCESS) {
1427 cmd->record_result = result;
1428 return;
1429 }
1430
1431 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1432 tu_cs_emit(cs, 0);
1433
1434 tu6_emit_lrz_flush(cmd, cs);
1435
1436 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1437
1438 tu_cs_sanity_check(cs);
1439 }
1440
1441 static void
1442 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1443 {
1444 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1445
1446 tu6_render_begin(cmd, &cmd->cs);
1447
1448 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1449 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1450 struct tu_tile tile;
1451 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1452 tu6_render_tile(cmd, &cmd->cs, &tile);
1453 }
1454 }
1455
1456 tu6_render_end(cmd, &cmd->cs);
1457 }
1458
1459 static void
1460 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1461 const VkRenderPassBeginInfo *info)
1462 {
1463 const uint32_t tile_load_space =
1464 6 + (23+19) * cmd->state.pass->attachment_count +
1465 21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1466
1467 struct tu_cs sub_cs;
1468
1469 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1470 tile_load_space, &sub_cs);
1471 if (result != VK_SUCCESS) {
1472 cmd->record_result = result;
1473 return;
1474 }
1475
1476 tu6_emit_blit_scissor(cmd, &sub_cs, true);
1477
1478 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1479 tu6_emit_load_attachment(cmd, &sub_cs, i);
1480
1481 tu6_emit_blit_scissor(cmd, &sub_cs, false);
1482
1483 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1484 tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1485
1486 tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1487 tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1488 tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1489
1490 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1491 }
1492
1493 static void
1494 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1495 {
1496 const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1497 struct tu_cs sub_cs;
1498
1499 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1500 tile_store_space, &sub_cs);
1501 if (result != VK_SUCCESS) {
1502 cmd->record_result = result;
1503 return;
1504 }
1505
1506 /* emit to tile-store sub_cs */
1507 tu6_emit_tile_store(cmd, &sub_cs);
1508
1509 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1510 }
1511
1512 static void
1513 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1514 const VkRect2D *render_area)
1515 {
1516 const struct tu_device *dev = cmd->device;
1517 const struct tu_render_pass *pass = cmd->state.pass;
1518 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1519
1520 tiling->render_area = *render_area;
1521 for (uint32_t a = 0; a < pass->attachment_count; a++) {
1522 if (pass->attachments[a].needs_gmem)
1523 tiling->buffer_cpp[a] = pass->attachments[a].cpp;
1524 else
1525 tiling->buffer_cpp[a] = 0;
1526 }
1527 tiling->buffer_count = pass->attachment_count;
1528
1529 tu_tiling_config_update_tile_layout(tiling, dev);
1530 tu_tiling_config_update_pipe_layout(tiling, dev);
1531 tu_tiling_config_update_pipes(tiling, dev);
1532 }
1533
1534 const struct tu_dynamic_state default_dynamic_state = {
1535 .viewport =
1536 {
1537 .count = 0,
1538 },
1539 .scissor =
1540 {
1541 .count = 0,
1542 },
1543 .line_width = 1.0f,
1544 .depth_bias =
1545 {
1546 .bias = 0.0f,
1547 .clamp = 0.0f,
1548 .slope = 0.0f,
1549 },
1550 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1551 .depth_bounds =
1552 {
1553 .min = 0.0f,
1554 .max = 1.0f,
1555 },
1556 .stencil_compare_mask =
1557 {
1558 .front = ~0u,
1559 .back = ~0u,
1560 },
1561 .stencil_write_mask =
1562 {
1563 .front = ~0u,
1564 .back = ~0u,
1565 },
1566 .stencil_reference =
1567 {
1568 .front = 0u,
1569 .back = 0u,
1570 },
1571 };
1572
1573 static void UNUSED /* FINISHME */
1574 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1575 const struct tu_dynamic_state *src)
1576 {
1577 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1578 uint32_t copy_mask = src->mask;
1579 uint32_t dest_mask = 0;
1580
1581 tu_use_args(cmd_buffer); /* FINISHME */
1582
1583 /* Make sure to copy the number of viewports/scissors because they can
1584 * only be specified at pipeline creation time.
1585 */
1586 dest->viewport.count = src->viewport.count;
1587 dest->scissor.count = src->scissor.count;
1588 dest->discard_rectangle.count = src->discard_rectangle.count;
1589
1590 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1591 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1592 src->viewport.count * sizeof(VkViewport))) {
1593 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1594 src->viewport.count);
1595 dest_mask |= TU_DYNAMIC_VIEWPORT;
1596 }
1597 }
1598
1599 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1600 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1601 src->scissor.count * sizeof(VkRect2D))) {
1602 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1603 src->scissor.count);
1604 dest_mask |= TU_DYNAMIC_SCISSOR;
1605 }
1606 }
1607
1608 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1609 if (dest->line_width != src->line_width) {
1610 dest->line_width = src->line_width;
1611 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1612 }
1613 }
1614
1615 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1616 if (memcmp(&dest->depth_bias, &src->depth_bias,
1617 sizeof(src->depth_bias))) {
1618 dest->depth_bias = src->depth_bias;
1619 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1620 }
1621 }
1622
1623 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1624 if (memcmp(&dest->blend_constants, &src->blend_constants,
1625 sizeof(src->blend_constants))) {
1626 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1627 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1628 }
1629 }
1630
1631 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1632 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1633 sizeof(src->depth_bounds))) {
1634 dest->depth_bounds = src->depth_bounds;
1635 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1636 }
1637 }
1638
1639 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1640 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1641 sizeof(src->stencil_compare_mask))) {
1642 dest->stencil_compare_mask = src->stencil_compare_mask;
1643 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1644 }
1645 }
1646
1647 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1648 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1649 sizeof(src->stencil_write_mask))) {
1650 dest->stencil_write_mask = src->stencil_write_mask;
1651 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1652 }
1653 }
1654
1655 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1656 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1657 sizeof(src->stencil_reference))) {
1658 dest->stencil_reference = src->stencil_reference;
1659 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1660 }
1661 }
1662
1663 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1664 if (memcmp(&dest->discard_rectangle.rectangles,
1665 &src->discard_rectangle.rectangles,
1666 src->discard_rectangle.count * sizeof(VkRect2D))) {
1667 typed_memcpy(dest->discard_rectangle.rectangles,
1668 src->discard_rectangle.rectangles,
1669 src->discard_rectangle.count);
1670 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1671 }
1672 }
1673 }
1674
1675 static VkResult
1676 tu_create_cmd_buffer(struct tu_device *device,
1677 struct tu_cmd_pool *pool,
1678 VkCommandBufferLevel level,
1679 VkCommandBuffer *pCommandBuffer)
1680 {
1681 struct tu_cmd_buffer *cmd_buffer;
1682 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1683 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1684 if (cmd_buffer == NULL)
1685 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1686
1687 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1688 cmd_buffer->device = device;
1689 cmd_buffer->pool = pool;
1690 cmd_buffer->level = level;
1691
1692 if (pool) {
1693 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1694 cmd_buffer->queue_family_index = pool->queue_family_index;
1695
1696 } else {
1697 /* Init the pool_link so we can safely call list_del when we destroy
1698 * the command buffer
1699 */
1700 list_inithead(&cmd_buffer->pool_link);
1701 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1702 }
1703
1704 tu_bo_list_init(&cmd_buffer->bo_list);
1705 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1706 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1707 tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1708
1709 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1710
1711 list_inithead(&cmd_buffer->upload.list);
1712
1713 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1714 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1715
1716 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1717 if (result != VK_SUCCESS)
1718 return result;
1719
1720 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1721 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1722
1723 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1724 cmd_buffer->vsc_data_pitch = 0x440 * 4;
1725 cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
1726
1727 result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
1728 if (result != VK_SUCCESS)
1729 goto fail_vsc_data;
1730
1731 result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
1732 if (result != VK_SUCCESS)
1733 goto fail_vsc_data2;
1734
1735 return VK_SUCCESS;
1736
1737 fail_vsc_data2:
1738 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1739 fail_vsc_data:
1740 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1741 return result;
1742 }
1743
1744 static void
1745 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1746 {
1747 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1748 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1749 tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
1750
1751 list_del(&cmd_buffer->pool_link);
1752
1753 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1754 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1755
1756 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1757 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1758 tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1759
1760 tu_bo_list_destroy(&cmd_buffer->bo_list);
1761 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1762 }
1763
1764 static VkResult
1765 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1766 {
1767 cmd_buffer->wait_for_idle = true;
1768
1769 cmd_buffer->record_result = VK_SUCCESS;
1770
1771 tu_bo_list_reset(&cmd_buffer->bo_list);
1772 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1773 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1774 tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1775
1776 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1777 cmd_buffer->descriptors[i].dirty = 0;
1778 cmd_buffer->descriptors[i].valid = 0;
1779 cmd_buffer->descriptors[i].push_dirty = false;
1780 }
1781
1782 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1783
1784 return cmd_buffer->record_result;
1785 }
1786
1787 VkResult
1788 tu_AllocateCommandBuffers(VkDevice _device,
1789 const VkCommandBufferAllocateInfo *pAllocateInfo,
1790 VkCommandBuffer *pCommandBuffers)
1791 {
1792 TU_FROM_HANDLE(tu_device, device, _device);
1793 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1794
1795 VkResult result = VK_SUCCESS;
1796 uint32_t i;
1797
1798 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1799
1800 if (!list_is_empty(&pool->free_cmd_buffers)) {
1801 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1802 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1803
1804 list_del(&cmd_buffer->pool_link);
1805 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1806
1807 result = tu_reset_cmd_buffer(cmd_buffer);
1808 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1809 cmd_buffer->level = pAllocateInfo->level;
1810
1811 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1812 } else {
1813 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1814 &pCommandBuffers[i]);
1815 }
1816 if (result != VK_SUCCESS)
1817 break;
1818 }
1819
1820 if (result != VK_SUCCESS) {
1821 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1822 pCommandBuffers);
1823
1824 /* From the Vulkan 1.0.66 spec:
1825 *
1826 * "vkAllocateCommandBuffers can be used to create multiple
1827 * command buffers. If the creation of any of those command
1828 * buffers fails, the implementation must destroy all
1829 * successfully created command buffer objects from this
1830 * command, set all entries of the pCommandBuffers array to
1831 * NULL and return the error."
1832 */
1833 memset(pCommandBuffers, 0,
1834 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1835 }
1836
1837 return result;
1838 }
1839
1840 void
1841 tu_FreeCommandBuffers(VkDevice device,
1842 VkCommandPool commandPool,
1843 uint32_t commandBufferCount,
1844 const VkCommandBuffer *pCommandBuffers)
1845 {
1846 for (uint32_t i = 0; i < commandBufferCount; i++) {
1847 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1848
1849 if (cmd_buffer) {
1850 if (cmd_buffer->pool) {
1851 list_del(&cmd_buffer->pool_link);
1852 list_addtail(&cmd_buffer->pool_link,
1853 &cmd_buffer->pool->free_cmd_buffers);
1854 } else
1855 tu_cmd_buffer_destroy(cmd_buffer);
1856 }
1857 }
1858 }
1859
1860 VkResult
1861 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1862 VkCommandBufferResetFlags flags)
1863 {
1864 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1865 return tu_reset_cmd_buffer(cmd_buffer);
1866 }
1867
1868 VkResult
1869 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1870 const VkCommandBufferBeginInfo *pBeginInfo)
1871 {
1872 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1873 VkResult result = VK_SUCCESS;
1874
1875 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1876 /* If the command buffer has already been resetted with
1877 * vkResetCommandBuffer, no need to do it again.
1878 */
1879 result = tu_reset_cmd_buffer(cmd_buffer);
1880 if (result != VK_SUCCESS)
1881 return result;
1882 }
1883
1884 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1885 cmd_buffer->usage_flags = pBeginInfo->flags;
1886
1887 tu_cs_begin(&cmd_buffer->cs);
1888 tu_cs_begin(&cmd_buffer->draw_cs);
1889
1890 cmd_buffer->marker_seqno = 0;
1891 cmd_buffer->scratch_seqno = 0;
1892
1893 /* setup initial configuration into command buffer */
1894 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1895 switch (cmd_buffer->queue_family_index) {
1896 case TU_QUEUE_GENERAL:
1897 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1898 break;
1899 default:
1900 break;
1901 }
1902 }
1903
1904 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1905
1906 return VK_SUCCESS;
1907 }
1908
1909 void
1910 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1911 uint32_t firstBinding,
1912 uint32_t bindingCount,
1913 const VkBuffer *pBuffers,
1914 const VkDeviceSize *pOffsets)
1915 {
1916 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1917
1918 assert(firstBinding + bindingCount <= MAX_VBS);
1919
1920 for (uint32_t i = 0; i < bindingCount; i++) {
1921 cmd->state.vb.buffers[firstBinding + i] =
1922 tu_buffer_from_handle(pBuffers[i]);
1923 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1924 }
1925
1926 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1927 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1928 }
1929
1930 void
1931 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1932 VkBuffer buffer,
1933 VkDeviceSize offset,
1934 VkIndexType indexType)
1935 {
1936 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1937 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1938
1939 /* initialize/update the restart index */
1940 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1941 struct tu_cs *draw_cs = &cmd->draw_cs;
1942 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1943 if (result != VK_SUCCESS) {
1944 cmd->record_result = result;
1945 return;
1946 }
1947
1948 tu6_emit_restart_index(
1949 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1950
1951 tu_cs_sanity_check(draw_cs);
1952 }
1953
1954 /* track the BO */
1955 if (cmd->state.index_buffer != buf)
1956 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1957
1958 cmd->state.index_buffer = buf;
1959 cmd->state.index_offset = offset;
1960 cmd->state.index_type = indexType;
1961 }
1962
1963 void
1964 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1965 VkPipelineBindPoint pipelineBindPoint,
1966 VkPipelineLayout _layout,
1967 uint32_t firstSet,
1968 uint32_t descriptorSetCount,
1969 const VkDescriptorSet *pDescriptorSets,
1970 uint32_t dynamicOffsetCount,
1971 const uint32_t *pDynamicOffsets)
1972 {
1973 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1974 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1975 unsigned dyn_idx = 0;
1976
1977 struct tu_descriptor_state *descriptors_state =
1978 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1979
1980 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1981 unsigned idx = i + firstSet;
1982 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1983
1984 descriptors_state->sets[idx] = set;
1985 descriptors_state->valid |= (1u << idx);
1986
1987 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1988 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1989 assert(dyn_idx < dynamicOffsetCount);
1990
1991 descriptors_state->dynamic_buffers[idx] =
1992 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1993 }
1994 }
1995
1996 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1997 }
1998
1999 void
2000 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2001 VkPipelineLayout layout,
2002 VkShaderStageFlags stageFlags,
2003 uint32_t offset,
2004 uint32_t size,
2005 const void *pValues)
2006 {
2007 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2008 memcpy((void*) cmd->push_constants + offset, pValues, size);
2009 cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2010 }
2011
2012 VkResult
2013 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2014 {
2015 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2016
2017 if (cmd_buffer->scratch_seqno) {
2018 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2019 MSM_SUBMIT_BO_WRITE);
2020 }
2021
2022 if (cmd_buffer->use_vsc_data) {
2023 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2024 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2025 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2026 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2027 }
2028
2029 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2030 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2031 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2032 }
2033
2034 for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2035 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2036 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2037 }
2038
2039 tu_cs_end(&cmd_buffer->cs);
2040 tu_cs_end(&cmd_buffer->draw_cs);
2041
2042 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2043
2044 return cmd_buffer->record_result;
2045 }
2046
2047 void
2048 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2049 VkPipelineBindPoint pipelineBindPoint,
2050 VkPipeline _pipeline)
2051 {
2052 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2053 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2054
2055 switch (pipelineBindPoint) {
2056 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2057 cmd->state.pipeline = pipeline;
2058 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2059 break;
2060 case VK_PIPELINE_BIND_POINT_COMPUTE:
2061 cmd->state.compute_pipeline = pipeline;
2062 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2063 break;
2064 default:
2065 unreachable("unrecognized pipeline bind point");
2066 break;
2067 }
2068
2069 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2070 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2071 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2072 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2073 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2074 }
2075 }
2076
2077 void
2078 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2079 uint32_t firstViewport,
2080 uint32_t viewportCount,
2081 const VkViewport *pViewports)
2082 {
2083 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2084 struct tu_cs *draw_cs = &cmd->draw_cs;
2085
2086 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2087 if (result != VK_SUCCESS) {
2088 cmd->record_result = result;
2089 return;
2090 }
2091
2092 assert(firstViewport == 0 && viewportCount == 1);
2093 tu6_emit_viewport(draw_cs, pViewports);
2094
2095 tu_cs_sanity_check(draw_cs);
2096 }
2097
2098 void
2099 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2100 uint32_t firstScissor,
2101 uint32_t scissorCount,
2102 const VkRect2D *pScissors)
2103 {
2104 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2105 struct tu_cs *draw_cs = &cmd->draw_cs;
2106
2107 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2108 if (result != VK_SUCCESS) {
2109 cmd->record_result = result;
2110 return;
2111 }
2112
2113 assert(firstScissor == 0 && scissorCount == 1);
2114 tu6_emit_scissor(draw_cs, pScissors);
2115
2116 tu_cs_sanity_check(draw_cs);
2117 }
2118
2119 void
2120 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2121 {
2122 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2123
2124 cmd->state.dynamic.line_width = lineWidth;
2125
2126 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2127 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2128 }
2129
2130 void
2131 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2132 float depthBiasConstantFactor,
2133 float depthBiasClamp,
2134 float depthBiasSlopeFactor)
2135 {
2136 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2137 struct tu_cs *draw_cs = &cmd->draw_cs;
2138
2139 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2140 if (result != VK_SUCCESS) {
2141 cmd->record_result = result;
2142 return;
2143 }
2144
2145 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2146 depthBiasSlopeFactor);
2147
2148 tu_cs_sanity_check(draw_cs);
2149 }
2150
2151 void
2152 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2153 const float blendConstants[4])
2154 {
2155 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2156 struct tu_cs *draw_cs = &cmd->draw_cs;
2157
2158 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2159 if (result != VK_SUCCESS) {
2160 cmd->record_result = result;
2161 return;
2162 }
2163
2164 tu6_emit_blend_constants(draw_cs, blendConstants);
2165
2166 tu_cs_sanity_check(draw_cs);
2167 }
2168
2169 void
2170 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2171 float minDepthBounds,
2172 float maxDepthBounds)
2173 {
2174 }
2175
2176 void
2177 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2178 VkStencilFaceFlags faceMask,
2179 uint32_t compareMask)
2180 {
2181 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2182
2183 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2184 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2185 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2186 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2187
2188 /* the front/back compare masks must be updated together */
2189 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2190 }
2191
2192 void
2193 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2194 VkStencilFaceFlags faceMask,
2195 uint32_t writeMask)
2196 {
2197 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2198
2199 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2200 cmd->state.dynamic.stencil_write_mask.front = writeMask;
2201 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2202 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2203
2204 /* the front/back write masks must be updated together */
2205 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2206 }
2207
2208 void
2209 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2210 VkStencilFaceFlags faceMask,
2211 uint32_t reference)
2212 {
2213 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2214
2215 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2216 cmd->state.dynamic.stencil_reference.front = reference;
2217 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2218 cmd->state.dynamic.stencil_reference.back = reference;
2219
2220 /* the front/back references must be updated together */
2221 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2222 }
2223
2224 void
2225 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2226 uint32_t commandBufferCount,
2227 const VkCommandBuffer *pCmdBuffers)
2228 {
2229 }
2230
2231 VkResult
2232 tu_CreateCommandPool(VkDevice _device,
2233 const VkCommandPoolCreateInfo *pCreateInfo,
2234 const VkAllocationCallbacks *pAllocator,
2235 VkCommandPool *pCmdPool)
2236 {
2237 TU_FROM_HANDLE(tu_device, device, _device);
2238 struct tu_cmd_pool *pool;
2239
2240 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2241 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2242 if (pool == NULL)
2243 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2244
2245 if (pAllocator)
2246 pool->alloc = *pAllocator;
2247 else
2248 pool->alloc = device->alloc;
2249
2250 list_inithead(&pool->cmd_buffers);
2251 list_inithead(&pool->free_cmd_buffers);
2252
2253 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2254
2255 *pCmdPool = tu_cmd_pool_to_handle(pool);
2256
2257 return VK_SUCCESS;
2258 }
2259
2260 void
2261 tu_DestroyCommandPool(VkDevice _device,
2262 VkCommandPool commandPool,
2263 const VkAllocationCallbacks *pAllocator)
2264 {
2265 TU_FROM_HANDLE(tu_device, device, _device);
2266 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2267
2268 if (!pool)
2269 return;
2270
2271 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2272 &pool->cmd_buffers, pool_link)
2273 {
2274 tu_cmd_buffer_destroy(cmd_buffer);
2275 }
2276
2277 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2278 &pool->free_cmd_buffers, pool_link)
2279 {
2280 tu_cmd_buffer_destroy(cmd_buffer);
2281 }
2282
2283 vk_free2(&device->alloc, pAllocator, pool);
2284 }
2285
2286 VkResult
2287 tu_ResetCommandPool(VkDevice device,
2288 VkCommandPool commandPool,
2289 VkCommandPoolResetFlags flags)
2290 {
2291 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2292 VkResult result;
2293
2294 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2295 pool_link)
2296 {
2297 result = tu_reset_cmd_buffer(cmd_buffer);
2298 if (result != VK_SUCCESS)
2299 return result;
2300 }
2301
2302 return VK_SUCCESS;
2303 }
2304
2305 void
2306 tu_TrimCommandPool(VkDevice device,
2307 VkCommandPool commandPool,
2308 VkCommandPoolTrimFlags flags)
2309 {
2310 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2311
2312 if (!pool)
2313 return;
2314
2315 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2316 &pool->free_cmd_buffers, pool_link)
2317 {
2318 tu_cmd_buffer_destroy(cmd_buffer);
2319 }
2320 }
2321
2322 void
2323 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2324 const VkRenderPassBeginInfo *pRenderPassBegin,
2325 VkSubpassContents contents)
2326 {
2327 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2328 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2329 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2330
2331 cmd->state.pass = pass;
2332 cmd->state.subpass = pass->subpasses;
2333 cmd->state.framebuffer = fb;
2334
2335 tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2336 tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2337 tu_cmd_prepare_tile_store_ib(cmd);
2338
2339 /* note: use_hw_binning only checks tiling config */
2340 if (use_hw_binning(cmd))
2341 cmd->use_vsc_data = true;
2342
2343 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2344 const struct tu_image_view *iview = fb->attachments[i].attachment;
2345 tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2346 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2347 }
2348 }
2349
2350 void
2351 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2352 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2353 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2354 {
2355 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2356 pSubpassBeginInfo->contents);
2357 }
2358
2359 void
2360 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2361 {
2362 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2363 const struct tu_render_pass *pass = cmd->state.pass;
2364 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2365 struct tu_cs *cs = &cmd->draw_cs;
2366
2367 VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2368 if (result != VK_SUCCESS) {
2369 cmd->record_result = result;
2370 return;
2371 }
2372
2373 const struct tu_subpass *subpass = cmd->state.subpass++;
2374 /* TODO:
2375 * if msaa samples change between subpasses,
2376 * attachment store is broken for some attachments
2377 */
2378 if (subpass->resolve_attachments) {
2379 tu6_emit_blit_scissor(cmd, cs, true);
2380 for (unsigned i = 0; i < subpass->color_count; i++) {
2381 uint32_t a = subpass->resolve_attachments[i].attachment;
2382 if (a != VK_ATTACHMENT_UNUSED) {
2383 tu6_emit_store_attachment(cmd, cs, a,
2384 subpass->color_attachments[i].attachment);
2385 }
2386 }
2387 }
2388
2389 /* emit mrt/zs/msaa state for the subpass that is starting */
2390 tu6_emit_zs(cmd, cmd->state.subpass, cs);
2391 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2392 tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2393
2394 /* TODO:
2395 * since we don't know how to do GMEM->GMEM resolve,
2396 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2397 */
2398 if (subpass->resolve_attachments) {
2399 for (unsigned i = 0; i < subpass->color_count; i++) {
2400 uint32_t a = subpass->resolve_attachments[i].attachment;
2401 const struct tu_image_view *iview =
2402 cmd->state.framebuffer->attachments[a].attachment;
2403 if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].needs_gmem) {
2404 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2405 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
2406 tu6_emit_blit(cmd, cs);
2407 }
2408 }
2409 }
2410 }
2411
2412 void
2413 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2414 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2415 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2416 {
2417 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2418 }
2419
2420 struct tu_draw_info
2421 {
2422 /**
2423 * Number of vertices.
2424 */
2425 uint32_t count;
2426
2427 /**
2428 * Index of the first vertex.
2429 */
2430 int32_t vertex_offset;
2431
2432 /**
2433 * First instance id.
2434 */
2435 uint32_t first_instance;
2436
2437 /**
2438 * Number of instances.
2439 */
2440 uint32_t instance_count;
2441
2442 /**
2443 * First index (indexed draws only).
2444 */
2445 uint32_t first_index;
2446
2447 /**
2448 * Whether it's an indexed draw.
2449 */
2450 bool indexed;
2451
2452 /**
2453 * Indirect draw parameters resource.
2454 */
2455 struct tu_buffer *indirect;
2456 uint64_t indirect_offset;
2457 uint32_t stride;
2458
2459 /**
2460 * Draw count parameters resource.
2461 */
2462 struct tu_buffer *count_buffer;
2463 uint64_t count_buffer_offset;
2464 };
2465
2466 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2467 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2468
2469 enum tu_draw_state_group_id
2470 {
2471 TU_DRAW_STATE_PROGRAM,
2472 TU_DRAW_STATE_PROGRAM_BINNING,
2473 TU_DRAW_STATE_VI,
2474 TU_DRAW_STATE_VI_BINNING,
2475 TU_DRAW_STATE_VP,
2476 TU_DRAW_STATE_RAST,
2477 TU_DRAW_STATE_DS,
2478 TU_DRAW_STATE_BLEND,
2479 TU_DRAW_STATE_VS_CONST,
2480 TU_DRAW_STATE_FS_CONST,
2481 TU_DRAW_STATE_VS_TEX,
2482 TU_DRAW_STATE_FS_TEX,
2483 TU_DRAW_STATE_FS_IBO,
2484
2485 TU_DRAW_STATE_COUNT,
2486 };
2487
2488 struct tu_draw_state_group
2489 {
2490 enum tu_draw_state_group_id id;
2491 uint32_t enable_mask;
2492 struct tu_cs_entry ib;
2493 };
2494
2495 const static struct tu_sampler*
2496 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2497 const struct tu_descriptor_map *map, unsigned i,
2498 unsigned array_index)
2499 {
2500 assert(descriptors_state->valid & (1 << map->set[i]));
2501
2502 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2503 assert(map->binding[i] < set->layout->binding_count);
2504
2505 const struct tu_descriptor_set_binding_layout *layout =
2506 &set->layout->binding[map->binding[i]];
2507
2508 if (layout->immutable_samplers_offset) {
2509 const struct tu_sampler *immutable_samplers =
2510 tu_immutable_samplers(set->layout, layout);
2511
2512 return &immutable_samplers[array_index];
2513 }
2514
2515 switch (layout->type) {
2516 case VK_DESCRIPTOR_TYPE_SAMPLER:
2517 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2518 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2519 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2520 array_index *
2521 (A6XX_TEX_CONST_DWORDS +
2522 sizeof(struct tu_sampler) / 4)];
2523 default:
2524 unreachable("unimplemented descriptor type");
2525 break;
2526 }
2527 }
2528
2529 static void
2530 write_tex_const(struct tu_cmd_buffer *cmd,
2531 uint32_t *dst,
2532 struct tu_descriptor_state *descriptors_state,
2533 const struct tu_descriptor_map *map,
2534 unsigned i, unsigned array_index)
2535 {
2536 assert(descriptors_state->valid & (1 << map->set[i]));
2537
2538 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2539 assert(map->binding[i] < set->layout->binding_count);
2540
2541 const struct tu_descriptor_set_binding_layout *layout =
2542 &set->layout->binding[map->binding[i]];
2543
2544 switch (layout->type) {
2545 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2546 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2547 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2548 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2549 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2550 array_index * A6XX_TEX_CONST_DWORDS],
2551 A6XX_TEX_CONST_DWORDS * 4);
2552 break;
2553 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2554 memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2555 array_index *
2556 (A6XX_TEX_CONST_DWORDS +
2557 sizeof(struct tu_sampler) / 4)],
2558 A6XX_TEX_CONST_DWORDS * 4);
2559 break;
2560 default:
2561 unreachable("unimplemented descriptor type");
2562 break;
2563 }
2564
2565 if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2566 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2567 uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2568 array_index].attachment;
2569
2570 assert(cmd->state.pass->attachments[a].needs_gmem);
2571 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2572 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2573 dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2574 dst[2] |=
2575 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2576 A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * tiling->buffer_cpp[a]);
2577 dst[3] = 0;
2578 dst[4] = 0x100000 + tiling->gmem_offsets[a];
2579 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2580 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2581 dst[i] = 0;
2582 }
2583 }
2584
2585 static uint64_t
2586 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2587 const struct tu_descriptor_map *map,
2588 unsigned i, unsigned array_index)
2589 {
2590 assert(descriptors_state->valid & (1 << map->set[i]));
2591
2592 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2593 assert(map->binding[i] < set->layout->binding_count);
2594
2595 const struct tu_descriptor_set_binding_layout *layout =
2596 &set->layout->binding[map->binding[i]];
2597
2598 switch (layout->type) {
2599 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2600 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2601 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2602 array_index];
2603 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2604 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2605 return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2606 set->mapped_ptr[layout->offset / 4 + array_index * 2];
2607 default:
2608 unreachable("unimplemented descriptor type");
2609 break;
2610 }
2611 }
2612
2613 static inline uint32_t
2614 tu6_stage2opcode(gl_shader_stage type)
2615 {
2616 switch (type) {
2617 case MESA_SHADER_VERTEX:
2618 case MESA_SHADER_TESS_CTRL:
2619 case MESA_SHADER_TESS_EVAL:
2620 case MESA_SHADER_GEOMETRY:
2621 return CP_LOAD_STATE6_GEOM;
2622 case MESA_SHADER_FRAGMENT:
2623 case MESA_SHADER_COMPUTE:
2624 case MESA_SHADER_KERNEL:
2625 return CP_LOAD_STATE6_FRAG;
2626 default:
2627 unreachable("bad shader type");
2628 }
2629 }
2630
2631 static inline enum a6xx_state_block
2632 tu6_stage2shadersb(gl_shader_stage type)
2633 {
2634 switch (type) {
2635 case MESA_SHADER_VERTEX:
2636 return SB6_VS_SHADER;
2637 case MESA_SHADER_FRAGMENT:
2638 return SB6_FS_SHADER;
2639 case MESA_SHADER_COMPUTE:
2640 case MESA_SHADER_KERNEL:
2641 return SB6_CS_SHADER;
2642 default:
2643 unreachable("bad shader type");
2644 return ~0;
2645 }
2646 }
2647
2648 static void
2649 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2650 struct tu_descriptor_state *descriptors_state,
2651 gl_shader_stage type,
2652 uint32_t *push_constants)
2653 {
2654 const struct tu_program_descriptor_linkage *link =
2655 &pipeline->program.link[type];
2656 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2657
2658 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2659 if (state->range[i].start < state->range[i].end) {
2660 uint32_t size = state->range[i].end - state->range[i].start;
2661 uint32_t offset = state->range[i].start;
2662
2663 /* and even if the start of the const buffer is before
2664 * first_immediate, the end may not be:
2665 */
2666 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2667
2668 if (size == 0)
2669 continue;
2670
2671 /* things should be aligned to vec4: */
2672 debug_assert((state->range[i].offset % 16) == 0);
2673 debug_assert((size % 16) == 0);
2674 debug_assert((offset % 16) == 0);
2675
2676 if (i == 0) {
2677 /* push constants */
2678 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2679 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2680 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2681 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2682 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2683 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2684 tu_cs_emit(cs, 0);
2685 tu_cs_emit(cs, 0);
2686 for (unsigned i = 0; i < size / 4; i++)
2687 tu_cs_emit(cs, push_constants[i + offset / 4]);
2688 continue;
2689 }
2690
2691 /* Look through the UBO map to find our UBO index, and get the VA for
2692 * that UBO.
2693 */
2694 uint64_t va = 0;
2695 uint32_t ubo_idx = i - 1;
2696 uint32_t ubo_map_base = 0;
2697 for (int j = 0; j < link->ubo_map.num; j++) {
2698 if (ubo_idx >= ubo_map_base &&
2699 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2700 va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2701 ubo_idx - ubo_map_base);
2702 break;
2703 }
2704 ubo_map_base += link->ubo_map.array_size[j];
2705 }
2706 assert(va);
2707
2708 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2709 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2710 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2711 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2712 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2713 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2714 tu_cs_emit_qw(cs, va + offset);
2715 }
2716 }
2717 }
2718
2719 static void
2720 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2721 struct tu_descriptor_state *descriptors_state,
2722 gl_shader_stage type)
2723 {
2724 const struct tu_program_descriptor_linkage *link =
2725 &pipeline->program.link[type];
2726
2727 uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2728 uint32_t anum = align(num, 2);
2729
2730 if (!num)
2731 return;
2732
2733 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2734 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2735 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2736 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2737 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2738 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2739 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2740 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2741
2742 unsigned emitted = 0;
2743 for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2744 for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2745 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2746 emitted++;
2747 }
2748 }
2749
2750 for (; emitted < anum; emitted++) {
2751 tu_cs_emit(cs, 0xffffffff);
2752 tu_cs_emit(cs, 0xffffffff);
2753 }
2754 }
2755
2756 static struct tu_cs_entry
2757 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2758 const struct tu_pipeline *pipeline,
2759 struct tu_descriptor_state *descriptors_state,
2760 gl_shader_stage type)
2761 {
2762 struct tu_cs cs;
2763 tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2764
2765 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2766 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2767
2768 return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2769 }
2770
2771 static VkResult
2772 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2773 const struct tu_pipeline *pipeline,
2774 struct tu_descriptor_state *descriptors_state,
2775 gl_shader_stage type,
2776 struct tu_cs_entry *entry,
2777 bool *needs_border)
2778 {
2779 struct tu_device *device = cmd->device;
2780 struct tu_cs *draw_state = &cmd->sub_cs;
2781 const struct tu_program_descriptor_linkage *link =
2782 &pipeline->program.link[type];
2783 VkResult result;
2784
2785 if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
2786 *entry = (struct tu_cs_entry) {};
2787 return VK_SUCCESS;
2788 }
2789
2790 /* allocate and fill texture state */
2791 struct ts_cs_memory tex_const;
2792 result = tu_cs_alloc(device, draw_state, link->texture_map.num_desc,
2793 A6XX_TEX_CONST_DWORDS, &tex_const);
2794 if (result != VK_SUCCESS)
2795 return result;
2796
2797 int tex_index = 0;
2798 for (unsigned i = 0; i < link->texture_map.num; i++) {
2799 for (int j = 0; j < link->texture_map.array_size[i]; j++) {
2800 write_tex_const(cmd,
2801 &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
2802 descriptors_state, &link->texture_map, i, j);
2803 }
2804 }
2805
2806 /* allocate and fill sampler state */
2807 struct ts_cs_memory tex_samp = { 0 };
2808 if (link->sampler_map.num_desc) {
2809 result = tu_cs_alloc(device, draw_state, link->sampler_map.num_desc,
2810 A6XX_TEX_SAMP_DWORDS, &tex_samp);
2811 if (result != VK_SUCCESS)
2812 return result;
2813
2814 int sampler_index = 0;
2815 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2816 for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
2817 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
2818 &link->sampler_map,
2819 i, j);
2820 memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
2821 sampler->state, sizeof(sampler->state));
2822 *needs_border |= sampler->needs_border;
2823 }
2824 }
2825 }
2826
2827 unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2828 enum a6xx_state_block sb;
2829
2830 switch (type) {
2831 case MESA_SHADER_VERTEX:
2832 sb = SB6_VS_TEX;
2833 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2834 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2835 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2836 break;
2837 case MESA_SHADER_FRAGMENT:
2838 sb = SB6_FS_TEX;
2839 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2840 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2841 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2842 break;
2843 case MESA_SHADER_COMPUTE:
2844 sb = SB6_CS_TEX;
2845 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2846 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2847 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2848 break;
2849 default:
2850 unreachable("bad state block");
2851 }
2852
2853 struct tu_cs cs;
2854 result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2855 if (result != VK_SUCCESS)
2856 return result;
2857
2858 if (link->sampler_map.num_desc) {
2859 /* output sampler state: */
2860 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2861 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2862 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2863 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2864 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2865 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
2866 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2867
2868 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2869 tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2870 }
2871
2872 /* emit texture state: */
2873 tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2874 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2875 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2876 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2877 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2878 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
2879 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2880
2881 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2882 tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2883
2884 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2885 tu_cs_emit(&cs, link->texture_map.num_desc);
2886
2887 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2888 return VK_SUCCESS;
2889 }
2890
2891 static VkResult
2892 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
2893 const struct tu_pipeline *pipeline,
2894 struct tu_descriptor_state *descriptors_state,
2895 gl_shader_stage type,
2896 struct tu_cs_entry *entry)
2897 {
2898 struct tu_device *device = cmd->device;
2899 struct tu_cs *draw_state = &cmd->sub_cs;
2900 const struct tu_program_descriptor_linkage *link =
2901 &pipeline->program.link[type];
2902 VkResult result;
2903
2904 if (link->image_mapping.num_ibo == 0) {
2905 *entry = (struct tu_cs_entry) {};
2906 return VK_SUCCESS;
2907 }
2908
2909 struct ts_cs_memory ibo_const;
2910 result = tu_cs_alloc(device, draw_state, link->image_mapping.num_ibo,
2911 A6XX_TEX_CONST_DWORDS, &ibo_const);
2912 if (result != VK_SUCCESS)
2913 return result;
2914
2915 for (unsigned i = 0; i < link->image_mapping.num_ibo; i++) {
2916 unsigned idx = link->image_mapping.ibo_to_image[i];
2917 uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * i];
2918
2919 if (idx & IBO_SSBO) {
2920 idx &= ~IBO_SSBO;
2921
2922 uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, idx,
2923 0 /* XXX */);
2924 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2925 uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2926
2927 dst[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT);
2928 dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2929 A6XX_IBO_1_HEIGHT(sz >> 15);
2930 dst[2] = A6XX_IBO_2_UNK4 |
2931 A6XX_IBO_2_UNK31 |
2932 A6XX_IBO_2_TYPE(A6XX_TEX_1D);
2933 dst[3] = 0;
2934 dst[4] = va;
2935 dst[5] = va >> 32;
2936 for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2937 dst[i] = 0;
2938 } else {
2939 tu_finishme("Emit images");
2940 }
2941 }
2942
2943 struct tu_cs cs;
2944 result = tu_cs_begin_sub_stream(device, draw_state, 7, &cs);
2945 if (result != VK_SUCCESS)
2946 return result;
2947
2948 uint32_t opcode, ibo_addr_reg;
2949 enum a6xx_state_block sb;
2950 enum a6xx_state_type st;
2951
2952 switch (type) {
2953 case MESA_SHADER_FRAGMENT:
2954 opcode = CP_LOAD_STATE6;
2955 st = ST6_SHADER;
2956 sb = SB6_IBO;
2957 ibo_addr_reg = REG_A6XX_SP_IBO_LO;
2958 break;
2959 case MESA_SHADER_COMPUTE:
2960 opcode = CP_LOAD_STATE6_FRAG;
2961 st = ST6_IBO;
2962 sb = SB6_CS_SHADER;
2963 ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
2964 break;
2965 default:
2966 unreachable("unsupported stage for ibos");
2967 }
2968
2969 /* emit texture state: */
2970 tu_cs_emit_pkt7(&cs, opcode, 3);
2971 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2972 CP_LOAD_STATE6_0_STATE_TYPE(st) |
2973 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2974 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2975 CP_LOAD_STATE6_0_NUM_UNIT(link->image_mapping.num_ibo));
2976 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
2977
2978 tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
2979 tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
2980
2981 *entry = tu_cs_end_sub_stream(draw_state, &cs);
2982 return VK_SUCCESS;
2983 }
2984
2985 struct PACKED bcolor_entry {
2986 uint32_t fp32[4];
2987 uint16_t ui16[4];
2988 int16_t si16[4];
2989 uint16_t fp16[4];
2990 uint16_t rgb565;
2991 uint16_t rgb5a1;
2992 uint16_t rgba4;
2993 uint8_t __pad0[2];
2994 uint8_t ui8[4];
2995 int8_t si8[4];
2996 uint32_t rgb10a2;
2997 uint32_t z24; /* also s8? */
2998 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
2999 uint8_t __pad1[56];
3000 } border_color[] = {
3001 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3002 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3003 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3004 .fp32[3] = 0x3f800000,
3005 .ui16[3] = 0xffff,
3006 .si16[3] = 0x7fff,
3007 .fp16[3] = 0x3c00,
3008 .rgb5a1 = 0x8000,
3009 .rgba4 = 0xf000,
3010 .ui8[3] = 0xff,
3011 .si8[3] = 0x7f,
3012 .rgb10a2 = 0xc0000000,
3013 .srgb[3] = 0x3c00,
3014 },
3015 [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3016 .fp32[3] = 1,
3017 .fp16[3] = 1,
3018 },
3019 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3020 .fp32[0 ... 3] = 0x3f800000,
3021 .ui16[0 ... 3] = 0xffff,
3022 .si16[0 ... 3] = 0x7fff,
3023 .fp16[0 ... 3] = 0x3c00,
3024 .rgb565 = 0xffff,
3025 .rgb5a1 = 0xffff,
3026 .rgba4 = 0xffff,
3027 .ui8[0 ... 3] = 0xff,
3028 .si8[0 ... 3] = 0x7f,
3029 .rgb10a2 = 0xffffffff,
3030 .z24 = 0xffffff,
3031 .srgb[0 ... 3] = 0x3c00,
3032 },
3033 [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3034 .fp32[0 ... 3] = 1,
3035 .fp16[0 ... 3] = 1,
3036 },
3037 };
3038
3039 static VkResult
3040 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3041 struct tu_cs *cs)
3042 {
3043 STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3044
3045 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3046 struct tu_descriptor_state *descriptors_state =
3047 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3048 const struct tu_descriptor_map *vs_sampler =
3049 &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3050 const struct tu_descriptor_map *fs_sampler =
3051 &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3052 struct ts_cs_memory ptr;
3053
3054 VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
3055 vs_sampler->num_desc + fs_sampler->num_desc,
3056 128 / 4,
3057 &ptr);
3058 if (result != VK_SUCCESS)
3059 return result;
3060
3061 for (unsigned i = 0; i < vs_sampler->num; i++) {
3062 for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3063 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3064 vs_sampler, i, j);
3065 memcpy(ptr.map, &border_color[sampler->border], 128);
3066 ptr.map += 128 / 4;
3067 }
3068 }
3069
3070 for (unsigned i = 0; i < fs_sampler->num; i++) {
3071 for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3072 const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3073 fs_sampler, i, j);
3074 memcpy(ptr.map, &border_color[sampler->border], 128);
3075 ptr.map += 128 / 4;
3076 }
3077 }
3078
3079 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3080 tu_cs_emit_qw(cs, ptr.iova);
3081 return VK_SUCCESS;
3082 }
3083
3084 static VkResult
3085 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3086 struct tu_cs *cs,
3087 const struct tu_draw_info *draw)
3088 {
3089 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3090 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3091 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3092 uint32_t draw_state_group_count = 0;
3093
3094 struct tu_descriptor_state *descriptors_state =
3095 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3096
3097 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3098 if (result != VK_SUCCESS)
3099 return result;
3100
3101 /* TODO lrz */
3102
3103 uint32_t pc_primitive_cntl = 0;
3104 if (pipeline->ia.primitive_restart && draw->indexed)
3105 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
3106
3107 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3108 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3109 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3110
3111 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
3112 tu_cs_emit(cs, pc_primitive_cntl);
3113
3114 if (cmd->state.dirty &
3115 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3116 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3117 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3118 dynamic->line_width);
3119 }
3120
3121 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3122 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3123 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3124 dynamic->stencil_compare_mask.back);
3125 }
3126
3127 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3128 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3129 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3130 dynamic->stencil_write_mask.back);
3131 }
3132
3133 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3134 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3135 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3136 dynamic->stencil_reference.back);
3137 }
3138
3139 if (cmd->state.dirty &
3140 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3141 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3142 const uint32_t binding = pipeline->vi.bindings[i];
3143 const uint32_t stride = pipeline->vi.strides[i];
3144 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3145 const VkDeviceSize offset = buf->bo_offset +
3146 cmd->state.vb.offsets[binding] +
3147 pipeline->vi.offsets[i];
3148 const VkDeviceSize size =
3149 offset < buf->bo->size ? buf->bo->size - offset : 0;
3150
3151 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
3152 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3153 tu_cs_emit(cs, size);
3154 tu_cs_emit(cs, stride);
3155 }
3156 }
3157
3158 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3159 draw_state_groups[draw_state_group_count++] =
3160 (struct tu_draw_state_group) {
3161 .id = TU_DRAW_STATE_PROGRAM,
3162 .enable_mask = ENABLE_DRAW,
3163 .ib = pipeline->program.state_ib,
3164 };
3165 draw_state_groups[draw_state_group_count++] =
3166 (struct tu_draw_state_group) {
3167 .id = TU_DRAW_STATE_PROGRAM_BINNING,
3168 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3169 .ib = pipeline->program.binning_state_ib,
3170 };
3171 draw_state_groups[draw_state_group_count++] =
3172 (struct tu_draw_state_group) {
3173 .id = TU_DRAW_STATE_VI,
3174 .enable_mask = ENABLE_DRAW,
3175 .ib = pipeline->vi.state_ib,
3176 };
3177 draw_state_groups[draw_state_group_count++] =
3178 (struct tu_draw_state_group) {
3179 .id = TU_DRAW_STATE_VI_BINNING,
3180 .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3181 .ib = pipeline->vi.binning_state_ib,
3182 };
3183 draw_state_groups[draw_state_group_count++] =
3184 (struct tu_draw_state_group) {
3185 .id = TU_DRAW_STATE_VP,
3186 .enable_mask = ENABLE_ALL,
3187 .ib = pipeline->vp.state_ib,
3188 };
3189 draw_state_groups[draw_state_group_count++] =
3190 (struct tu_draw_state_group) {
3191 .id = TU_DRAW_STATE_RAST,
3192 .enable_mask = ENABLE_ALL,
3193 .ib = pipeline->rast.state_ib,
3194 };
3195 draw_state_groups[draw_state_group_count++] =
3196 (struct tu_draw_state_group) {
3197 .id = TU_DRAW_STATE_DS,
3198 .enable_mask = ENABLE_ALL,
3199 .ib = pipeline->ds.state_ib,
3200 };
3201 draw_state_groups[draw_state_group_count++] =
3202 (struct tu_draw_state_group) {
3203 .id = TU_DRAW_STATE_BLEND,
3204 .enable_mask = ENABLE_ALL,
3205 .ib = pipeline->blend.state_ib,
3206 };
3207 }
3208
3209 if (cmd->state.dirty &
3210 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3211 draw_state_groups[draw_state_group_count++] =
3212 (struct tu_draw_state_group) {
3213 .id = TU_DRAW_STATE_VS_CONST,
3214 .enable_mask = ENABLE_ALL,
3215 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3216 };
3217 draw_state_groups[draw_state_group_count++] =
3218 (struct tu_draw_state_group) {
3219 .id = TU_DRAW_STATE_FS_CONST,
3220 .enable_mask = ENABLE_DRAW,
3221 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3222 };
3223 }
3224
3225 if (cmd->state.dirty &
3226 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3227 bool needs_border = false;
3228 struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
3229
3230 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3231 MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3232 if (result != VK_SUCCESS)
3233 return result;
3234
3235 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3236 MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3237 if (result != VK_SUCCESS)
3238 return result;
3239
3240 result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3241 MESA_SHADER_FRAGMENT, &fs_ibo);
3242 if (result != VK_SUCCESS)
3243 return result;
3244
3245 draw_state_groups[draw_state_group_count++] =
3246 (struct tu_draw_state_group) {
3247 .id = TU_DRAW_STATE_VS_TEX,
3248 .enable_mask = ENABLE_ALL,
3249 .ib = vs_tex,
3250 };
3251 draw_state_groups[draw_state_group_count++] =
3252 (struct tu_draw_state_group) {
3253 .id = TU_DRAW_STATE_FS_TEX,
3254 .enable_mask = ENABLE_DRAW,
3255 .ib = fs_tex,
3256 };
3257 draw_state_groups[draw_state_group_count++] =
3258 (struct tu_draw_state_group) {
3259 .id = TU_DRAW_STATE_FS_IBO,
3260 .enable_mask = ENABLE_DRAW,
3261 .ib = fs_ibo,
3262 };
3263
3264 if (needs_border) {
3265 result = tu6_emit_border_color(cmd, cs);
3266 if (result != VK_SUCCESS)
3267 return result;
3268 }
3269 }
3270
3271 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3272 for (uint32_t i = 0; i < draw_state_group_count; i++) {
3273 const struct tu_draw_state_group *group = &draw_state_groups[i];
3274 debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3275 uint32_t cp_set_draw_state =
3276 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3277 group->enable_mask |
3278 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3279 uint64_t iova;
3280 if (group->ib.size) {
3281 iova = group->ib.bo->iova + group->ib.offset;
3282 } else {
3283 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3284 iova = 0;
3285 }
3286
3287 tu_cs_emit(cs, cp_set_draw_state);
3288 tu_cs_emit_qw(cs, iova);
3289 }
3290
3291 tu_cs_sanity_check(cs);
3292
3293 /* track BOs */
3294 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3295 for (uint32_t i = 0; i < MAX_VBS; i++) {
3296 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3297 if (buf)
3298 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3299 }
3300 }
3301 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3302 unsigned i;
3303 for_each_bit(i, descriptors_state->valid) {
3304 struct tu_descriptor_set *set = descriptors_state->sets[i];
3305 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3306 if (set->descriptors[j]) {
3307 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3308 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3309 }
3310 }
3311 }
3312
3313 /* Fragment shader state overwrites compute shader state, so flag the
3314 * compute pipeline for re-emit.
3315 */
3316 cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3317 return VK_SUCCESS;
3318 }
3319
3320 static void
3321 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3322 struct tu_cs *cs,
3323 const struct tu_draw_info *draw)
3324 {
3325
3326 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3327
3328 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
3329 tu_cs_emit(cs, draw->vertex_offset);
3330 tu_cs_emit(cs, draw->first_instance);
3331
3332 /* TODO hw binning */
3333 if (draw->indexed) {
3334 const enum a4xx_index_size index_size =
3335 tu6_index_size(cmd->state.index_type);
3336 const uint32_t index_bytes =
3337 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3338 const struct tu_buffer *buf = cmd->state.index_buffer;
3339 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3340 index_bytes * draw->first_index;
3341 const uint32_t size = index_bytes * draw->count;
3342
3343 const uint32_t cp_draw_indx =
3344 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3345 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3346 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3347 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3348
3349 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3350 tu_cs_emit(cs, cp_draw_indx);
3351 tu_cs_emit(cs, draw->instance_count);
3352 tu_cs_emit(cs, draw->count);
3353 tu_cs_emit(cs, 0x0); /* XXX */
3354 tu_cs_emit_qw(cs, buf->bo->iova + offset);
3355 tu_cs_emit(cs, size);
3356 } else {
3357 const uint32_t cp_draw_indx =
3358 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3359 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3360 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3361
3362 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3363 tu_cs_emit(cs, cp_draw_indx);
3364 tu_cs_emit(cs, draw->instance_count);
3365 tu_cs_emit(cs, draw->count);
3366 }
3367 }
3368
3369 static void
3370 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3371 {
3372 struct tu_cs *cs = &cmd->draw_cs;
3373 VkResult result;
3374
3375 result = tu6_bind_draw_states(cmd, cs, draw);
3376 if (result != VK_SUCCESS) {
3377 cmd->record_result = result;
3378 return;
3379 }
3380
3381 result = tu_cs_reserve_space(cmd->device, cs, 32);
3382 if (result != VK_SUCCESS) {
3383 cmd->record_result = result;
3384 return;
3385 }
3386
3387 if (draw->indirect) {
3388 tu_finishme("indirect draw");
3389 return;
3390 }
3391
3392 /* TODO tu6_emit_marker should pick different regs depending on cs */
3393
3394 tu6_emit_marker(cmd, cs);
3395 tu6_emit_draw_direct(cmd, cs, draw);
3396 tu6_emit_marker(cmd, cs);
3397
3398 cmd->wait_for_idle = true;
3399
3400 tu_cs_sanity_check(cs);
3401 }
3402
3403 void
3404 tu_CmdDraw(VkCommandBuffer commandBuffer,
3405 uint32_t vertexCount,
3406 uint32_t instanceCount,
3407 uint32_t firstVertex,
3408 uint32_t firstInstance)
3409 {
3410 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3411 struct tu_draw_info info = {};
3412
3413 info.count = vertexCount;
3414 info.instance_count = instanceCount;
3415 info.first_instance = firstInstance;
3416 info.vertex_offset = firstVertex;
3417
3418 tu_draw(cmd_buffer, &info);
3419 }
3420
3421 void
3422 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3423 uint32_t indexCount,
3424 uint32_t instanceCount,
3425 uint32_t firstIndex,
3426 int32_t vertexOffset,
3427 uint32_t firstInstance)
3428 {
3429 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3430 struct tu_draw_info info = {};
3431
3432 info.indexed = true;
3433 info.count = indexCount;
3434 info.instance_count = instanceCount;
3435 info.first_index = firstIndex;
3436 info.vertex_offset = vertexOffset;
3437 info.first_instance = firstInstance;
3438
3439 tu_draw(cmd_buffer, &info);
3440 }
3441
3442 void
3443 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3444 VkBuffer _buffer,
3445 VkDeviceSize offset,
3446 uint32_t drawCount,
3447 uint32_t stride)
3448 {
3449 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3450 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3451 struct tu_draw_info info = {};
3452
3453 info.count = drawCount;
3454 info.indirect = buffer;
3455 info.indirect_offset = offset;
3456 info.stride = stride;
3457
3458 tu_draw(cmd_buffer, &info);
3459 }
3460
3461 void
3462 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3463 VkBuffer _buffer,
3464 VkDeviceSize offset,
3465 uint32_t drawCount,
3466 uint32_t stride)
3467 {
3468 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3469 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3470 struct tu_draw_info info = {};
3471
3472 info.indexed = true;
3473 info.count = drawCount;
3474 info.indirect = buffer;
3475 info.indirect_offset = offset;
3476 info.stride = stride;
3477
3478 tu_draw(cmd_buffer, &info);
3479 }
3480
3481 struct tu_dispatch_info
3482 {
3483 /**
3484 * Determine the layout of the grid (in block units) to be used.
3485 */
3486 uint32_t blocks[3];
3487
3488 /**
3489 * A starting offset for the grid. If unaligned is set, the offset
3490 * must still be aligned.
3491 */
3492 uint32_t offsets[3];
3493 /**
3494 * Whether it's an unaligned compute dispatch.
3495 */
3496 bool unaligned;
3497
3498 /**
3499 * Indirect compute parameters resource.
3500 */
3501 struct tu_buffer *indirect;
3502 uint64_t indirect_offset;
3503 };
3504
3505 static void
3506 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3507 const struct tu_dispatch_info *info)
3508 {
3509 gl_shader_stage type = MESA_SHADER_COMPUTE;
3510 const struct tu_program_descriptor_linkage *link =
3511 &pipeline->program.link[type];
3512 const struct ir3_const_state *const_state = &link->const_state;
3513 uint32_t offset_dwords = const_state->offsets.driver_param;
3514
3515 if (link->constlen <= offset_dwords)
3516 return;
3517
3518 if (!info->indirect) {
3519 uint32_t driver_params[] = {
3520 info->blocks[0],
3521 info->blocks[1],
3522 info->blocks[2],
3523 pipeline->compute.local_size[0],
3524 pipeline->compute.local_size[1],
3525 pipeline->compute.local_size[2],
3526 };
3527 uint32_t num_consts = MIN2(const_state->num_driver_params,
3528 link->constlen - offset_dwords);
3529 uint32_t align_size = align(num_consts, 4);
3530
3531 /* push constants */
3532 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + align_size);
3533 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset_dwords / 4) |
3534 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3535 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3536 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3537 CP_LOAD_STATE6_0_NUM_UNIT(align_size / 4));
3538 tu_cs_emit(cs, 0);
3539 tu_cs_emit(cs, 0);
3540 uint32_t i;
3541 for (i = 0; i < num_consts; i++)
3542 tu_cs_emit(cs, driver_params[i]);
3543 for (; i < align_size; i++)
3544 tu_cs_emit(cs, 0);
3545 } else {
3546 tu_finishme("Indirect driver params");
3547 }
3548 }
3549
3550 static void
3551 tu_dispatch(struct tu_cmd_buffer *cmd,
3552 const struct tu_dispatch_info *info)
3553 {
3554 struct tu_cs *cs = &cmd->cs;
3555 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3556 struct tu_descriptor_state *descriptors_state =
3557 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3558
3559 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3560 if (result != VK_SUCCESS) {
3561 cmd->record_result = result;
3562 return;
3563 }
3564
3565 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3566 tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3567
3568 struct tu_cs_entry ib;
3569
3570 ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3571 if (ib.size)
3572 tu_cs_emit_ib(cs, &ib);
3573
3574 tu_emit_compute_driver_params(cs, pipeline, info);
3575
3576 bool needs_border;
3577 result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3578 MESA_SHADER_COMPUTE, &ib, &needs_border);
3579 if (result != VK_SUCCESS) {
3580 cmd->record_result = result;
3581 return;
3582 }
3583
3584 if (ib.size)
3585 tu_cs_emit_ib(cs, &ib);
3586
3587 if (needs_border)
3588 tu_finishme("compute border color");
3589
3590 result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3591 if (result != VK_SUCCESS) {
3592 cmd->record_result = result;
3593 return;
3594 }
3595
3596 if (ib.size)
3597 tu_cs_emit_ib(cs, &ib);
3598
3599 /* track BOs */
3600 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3601 unsigned i;
3602 for_each_bit(i, descriptors_state->valid) {
3603 struct tu_descriptor_set *set = descriptors_state->sets[i];
3604 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3605 if (set->descriptors[j]) {
3606 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3607 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3608 }
3609 }
3610 }
3611
3612 /* Compute shader state overwrites fragment shader state, so we flag the
3613 * graphics pipeline for re-emit.
3614 */
3615 cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3616
3617 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3618 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3619
3620 const uint32_t *local_size = pipeline->compute.local_size;
3621 const uint32_t *num_groups = info->blocks;
3622 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
3623 tu_cs_emit(cs,
3624 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3625 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
3626 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
3627 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
3628 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
3629 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3630 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
3631 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3632 tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
3633 tu_cs_emit(cs, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3634
3635 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
3636 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_X */
3637 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
3638 tu_cs_emit(cs, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
3639
3640 if (info->indirect) {
3641 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3642
3643 tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3644 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3645
3646 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3647 tu_cs_emit(cs, 0x00000000);
3648 tu_cs_emit_qw(cs, iova);
3649 tu_cs_emit(cs,
3650 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3651 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3652 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3653 } else {
3654 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3655 tu_cs_emit(cs, 0x00000000);
3656 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3657 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3658 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3659 }
3660
3661 tu_cs_emit_wfi(cs);
3662
3663 tu6_emit_cache_flush(cmd, cs);
3664 }
3665
3666 void
3667 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3668 uint32_t base_x,
3669 uint32_t base_y,
3670 uint32_t base_z,
3671 uint32_t x,
3672 uint32_t y,
3673 uint32_t z)
3674 {
3675 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3676 struct tu_dispatch_info info = {};
3677
3678 info.blocks[0] = x;
3679 info.blocks[1] = y;
3680 info.blocks[2] = z;
3681
3682 info.offsets[0] = base_x;
3683 info.offsets[1] = base_y;
3684 info.offsets[2] = base_z;
3685 tu_dispatch(cmd_buffer, &info);
3686 }
3687
3688 void
3689 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3690 uint32_t x,
3691 uint32_t y,
3692 uint32_t z)
3693 {
3694 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3695 }
3696
3697 void
3698 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3699 VkBuffer _buffer,
3700 VkDeviceSize offset)
3701 {
3702 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3703 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3704 struct tu_dispatch_info info = {};
3705
3706 info.indirect = buffer;
3707 info.indirect_offset = offset;
3708
3709 tu_dispatch(cmd_buffer, &info);
3710 }
3711
3712 void
3713 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3714 {
3715 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3716
3717 tu_cs_end(&cmd_buffer->draw_cs);
3718
3719 tu_cmd_render_tiles(cmd_buffer);
3720
3721 /* discard draw_cs entries now that the tiles are rendered */
3722 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3723 tu_cs_begin(&cmd_buffer->draw_cs);
3724
3725 cmd_buffer->state.pass = NULL;
3726 cmd_buffer->state.subpass = NULL;
3727 cmd_buffer->state.framebuffer = NULL;
3728 }
3729
3730 void
3731 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3732 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3733 {
3734 tu_CmdEndRenderPass(commandBuffer);
3735 }
3736
3737 struct tu_barrier_info
3738 {
3739 uint32_t eventCount;
3740 const VkEvent *pEvents;
3741 VkPipelineStageFlags srcStageMask;
3742 };
3743
3744 static void
3745 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3746 uint32_t memoryBarrierCount,
3747 const VkMemoryBarrier *pMemoryBarriers,
3748 uint32_t bufferMemoryBarrierCount,
3749 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3750 uint32_t imageMemoryBarrierCount,
3751 const VkImageMemoryBarrier *pImageMemoryBarriers,
3752 const struct tu_barrier_info *info)
3753 {
3754 }
3755
3756 void
3757 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3758 VkPipelineStageFlags srcStageMask,
3759 VkPipelineStageFlags destStageMask,
3760 VkBool32 byRegion,
3761 uint32_t memoryBarrierCount,
3762 const VkMemoryBarrier *pMemoryBarriers,
3763 uint32_t bufferMemoryBarrierCount,
3764 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3765 uint32_t imageMemoryBarrierCount,
3766 const VkImageMemoryBarrier *pImageMemoryBarriers)
3767 {
3768 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3769 struct tu_barrier_info info;
3770
3771 info.eventCount = 0;
3772 info.pEvents = NULL;
3773 info.srcStageMask = srcStageMask;
3774
3775 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3776 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3777 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3778 }
3779
3780 static void
3781 write_event(struct tu_cmd_buffer *cmd_buffer,
3782 struct tu_event *event,
3783 VkPipelineStageFlags stageMask,
3784 unsigned value)
3785 {
3786 }
3787
3788 void
3789 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3790 VkEvent _event,
3791 VkPipelineStageFlags stageMask)
3792 {
3793 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3794 TU_FROM_HANDLE(tu_event, event, _event);
3795
3796 write_event(cmd_buffer, event, stageMask, 1);
3797 }
3798
3799 void
3800 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3801 VkEvent _event,
3802 VkPipelineStageFlags stageMask)
3803 {
3804 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3805 TU_FROM_HANDLE(tu_event, event, _event);
3806
3807 write_event(cmd_buffer, event, stageMask, 0);
3808 }
3809
3810 void
3811 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3812 uint32_t eventCount,
3813 const VkEvent *pEvents,
3814 VkPipelineStageFlags srcStageMask,
3815 VkPipelineStageFlags dstStageMask,
3816 uint32_t memoryBarrierCount,
3817 const VkMemoryBarrier *pMemoryBarriers,
3818 uint32_t bufferMemoryBarrierCount,
3819 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3820 uint32_t imageMemoryBarrierCount,
3821 const VkImageMemoryBarrier *pImageMemoryBarriers)
3822 {
3823 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3824 struct tu_barrier_info info;
3825
3826 info.eventCount = eventCount;
3827 info.pEvents = pEvents;
3828 info.srcStageMask = 0;
3829
3830 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3831 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3832 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3833 }
3834
3835 void
3836 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3837 {
3838 /* No-op */
3839 }