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[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 for (uint32_t i = 0; i < list->count; ++i) {
66 if (list->bo_infos[i].handle == bo_info->handle) {
67 assert(list->bo_infos[i].presumed == bo_info->presumed);
68 list->bo_infos[i].flags |= bo_info->flags;
69 return i;
70 }
71 }
72
73 /* grow list->bo_infos if needed */
74 if (list->count == list->capacity) {
75 uint32_t new_capacity = MAX2(2 * list->count, 16);
76 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
77 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
78 if (!new_bo_infos)
79 return TU_BO_LIST_FAILED;
80 list->bo_infos = new_bo_infos;
81 list->capacity = new_capacity;
82 }
83
84 list->bo_infos[list->count] = *bo_info;
85 return list->count++;
86 }
87
88 uint32_t
89 tu_bo_list_add(struct tu_bo_list *list,
90 const struct tu_bo *bo,
91 uint32_t flags)
92 {
93 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
94 .flags = flags,
95 .handle = bo->gem_handle,
96 .presumed = bo->iova,
97 });
98 }
99
100 VkResult
101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
102 {
103 for (uint32_t i = 0; i < other->count; i++) {
104 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
105 return VK_ERROR_OUT_OF_HOST_MEMORY;
106 }
107
108 return VK_SUCCESS;
109 }
110
111 static VkResult
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
113 const struct tu_device *dev)
114 {
115 const uint32_t gmem_size = dev->physical_device->gmem_size;
116 uint32_t offset = 0;
117
118 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
119 /* 16KB-aligned */
120 offset = align(offset, 0x4000);
121
122 tiling->gmem_offsets[i] = offset;
123 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
124 tiling->buffer_cpp[i];
125 }
126
127 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
128 }
129
130 static void
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
132 const struct tu_device *dev)
133 {
134 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
135 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
136 const uint32_t max_tile_width = 1024; /* A6xx */
137
138 tiling->tile0.offset = (VkOffset2D) {
139 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
140 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
141 };
142
143 const uint32_t ra_width =
144 tiling->render_area.extent.width +
145 (tiling->render_area.offset.x - tiling->tile0.offset.x);
146 const uint32_t ra_height =
147 tiling->render_area.extent.height +
148 (tiling->render_area.offset.y - tiling->tile0.offset.y);
149
150 /* start from 1 tile */
151 tiling->tile_count = (VkExtent2D) {
152 .width = 1,
153 .height = 1,
154 };
155 tiling->tile0.extent = (VkExtent2D) {
156 .width = align(ra_width, tile_align_w),
157 .height = align(ra_height, tile_align_h),
158 };
159
160 /* do not exceed max tile width */
161 while (tiling->tile0.extent.width > max_tile_width) {
162 tiling->tile_count.width++;
163 tiling->tile0.extent.width =
164 align(ra_width / tiling->tile_count.width, tile_align_w);
165 }
166
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
169 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
170 tiling->tile_count.width++;
171 tiling->tile0.extent.width =
172 align(ra_width / tiling->tile_count.width, tile_align_w);
173 } else {
174 tiling->tile_count.height++;
175 tiling->tile0.extent.height =
176 align(ra_height / tiling->tile_count.height, tile_align_h);
177 }
178 }
179 }
180
181 static void
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
183 const struct tu_device *dev)
184 {
185 const uint32_t max_pipe_count = 32; /* A6xx */
186
187 /* start from 1 tile per pipe */
188 tiling->pipe0 = (VkExtent2D) {
189 .width = 1,
190 .height = 1,
191 };
192 tiling->pipe_count = tiling->tile_count;
193
194 /* do not exceed max pipe count vertically */
195 while (tiling->pipe_count.height > max_pipe_count) {
196 tiling->pipe0.height += 2;
197 tiling->pipe_count.height =
198 (tiling->tile_count.height + tiling->pipe0.height - 1) /
199 tiling->pipe0.height;
200 }
201
202 /* do not exceed max pipe count */
203 while (tiling->pipe_count.width * tiling->pipe_count.height >
204 max_pipe_count) {
205 tiling->pipe0.width += 1;
206 tiling->pipe_count.width =
207 (tiling->tile_count.width + tiling->pipe0.width - 1) /
208 tiling->pipe0.width;
209 }
210 }
211
212 static void
213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
214 const struct tu_device *dev)
215 {
216 const uint32_t max_pipe_count = 32; /* A6xx */
217 const uint32_t used_pipe_count =
218 tiling->pipe_count.width * tiling->pipe_count.height;
219 const VkExtent2D last_pipe = {
220 .width = tiling->tile_count.width % tiling->pipe0.width,
221 .height = tiling->tile_count.height % tiling->pipe0.height,
222 };
223
224 assert(used_pipe_count <= max_pipe_count);
225 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
226
227 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
228 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
229 const uint32_t pipe_x = tiling->pipe0.width * x;
230 const uint32_t pipe_y = tiling->pipe0.height * y;
231 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
232 ? last_pipe.width
233 : tiling->pipe0.width;
234 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
235 ? last_pipe.height
236 : tiling->pipe0.height;
237 const uint32_t n = tiling->pipe_count.width * y + x;
238
239 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
243 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
244 }
245 }
246
247 memset(tiling->pipe_config + used_pipe_count, 0,
248 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
249 }
250
251 static void
252 tu_tiling_config_update(struct tu_tiling_config *tiling,
253 const struct tu_device *dev,
254 const uint32_t *buffer_cpp,
255 uint32_t buffer_count,
256 const VkRect2D *render_area)
257 {
258 /* see if there is any real change */
259 const bool ra_changed =
260 render_area &&
261 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
262 const bool buf_changed = tiling->buffer_count != buffer_count ||
263 memcmp(tiling->buffer_cpp, buffer_cpp,
264 sizeof(*buffer_cpp) * buffer_count);
265 if (!ra_changed && !buf_changed)
266 return;
267
268 if (ra_changed)
269 tiling->render_area = *render_area;
270
271 if (buf_changed) {
272 memcpy(tiling->buffer_cpp, buffer_cpp,
273 sizeof(*buffer_cpp) * buffer_count);
274 tiling->buffer_count = buffer_count;
275 }
276
277 tu_tiling_config_update_tile_layout(tiling, dev);
278 tu_tiling_config_update_pipe_layout(tiling, dev);
279 tu_tiling_config_update_pipes(tiling, dev);
280 }
281
282 static void
283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
284 const struct tu_device *dev,
285 uint32_t tx,
286 uint32_t ty,
287 struct tu_tile *tile)
288 {
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px = tx / tiling->pipe0.width;
291 const uint32_t py = ty / tiling->pipe0.height;
292 const uint32_t sx = tx - tiling->pipe0.width * px;
293 const uint32_t sy = ty - tiling->pipe0.height * py;
294
295 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
296 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
297 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
298
299 /* convert to 1D indices */
300 tile->pipe = tiling->pipe_count.width * py + px;
301 tile->slot = tiling->pipe0.width * sy + sx;
302
303 /* get the blit area for the tile */
304 tile->begin = (VkOffset2D) {
305 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
306 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
307 };
308 tile->end.x =
309 (tx == tiling->tile_count.width - 1)
310 ? tiling->render_area.offset.x + tiling->render_area.extent.width
311 : tile->begin.x + tiling->tile0.extent.width;
312 tile->end.y =
313 (ty == tiling->tile_count.height - 1)
314 ? tiling->render_area.offset.y + tiling->render_area.extent.height
315 : tile->begin.y + tiling->tile0.extent.height;
316 }
317
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples)
320 {
321 switch (samples) {
322 case 1:
323 return MSAA_ONE;
324 case 2:
325 return MSAA_TWO;
326 case 4:
327 return MSAA_FOUR;
328 case 8:
329 return MSAA_EIGHT;
330 default:
331 assert(!"invalid sample count");
332 return MSAA_ONE;
333 }
334 }
335
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type)
338 {
339 switch (type) {
340 case VK_INDEX_TYPE_UINT16:
341 return INDEX4_SIZE_16_BIT;
342 case VK_INDEX_TYPE_UINT32:
343 return INDEX4_SIZE_32_BIT;
344 default:
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT;
347 }
348 }
349
350 static void
351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
354 }
355
356 void
357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
358 struct tu_cs *cs,
359 enum vgt_event_type event,
360 bool need_seqno)
361 {
362 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
363 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
364 if (need_seqno) {
365 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
366 tu_cs_emit(cs, ++cmd->scratch_seqno);
367 }
368 }
369
370 static void
371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
372 {
373 tu6_emit_event_write(cmd, cs, 0x31, false);
374 }
375
376 static void
377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
378 {
379 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
380 }
381
382 static void
383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
384 {
385 if (cmd->wait_for_idle) {
386 tu_cs_emit_wfi(cs);
387 cmd->wait_for_idle = false;
388 }
389 }
390
391 static void
392 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
393 {
394 const struct tu_framebuffer *fb = cmd->state.framebuffer;
395 const struct tu_subpass *subpass = cmd->state.subpass;
396 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
397
398 const uint32_t a = subpass->depth_stencil_attachment.attachment;
399 if (a == VK_ATTACHMENT_UNUSED) {
400 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
401 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
402 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
403 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
404 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
405 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
406 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
407
408 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
409 tu_cs_emit(cs,
410 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
411
412 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
413 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
414 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
415 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
416 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
417 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
418
419 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
420 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
421
422 return;
423 }
424
425 uint32_t gmem_index = 0;
426 for (uint32_t i = 0; i < subpass->color_count; ++i) {
427 uint32_t a = subpass->color_attachments[i].attachment;
428 if (a != VK_ATTACHMENT_UNUSED)
429 gmem_index++;
430 }
431
432 const struct tu_image_view *iview = fb->attachments[a].attachment;
433 const struct tu_image_level *slice = &iview->image->levels[iview->base_mip];
434 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
435
436 uint32_t offset = slice->offset + slice->size * iview->base_layer;
437 uint32_t stride = slice->pitch * iview->image->cpp;
438
439 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
440 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
441 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
442 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(slice->size));
443 tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset + offset);
444 tu_cs_emit(cs, tiling->gmem_offsets[gmem_index]);
445
446 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
447 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
448
449 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
450 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
451 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
452 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
453 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
454 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
455
456 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
457 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
458
459 /* enable zs? */
460 }
461
462 static void
463 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
464 {
465 const struct tu_framebuffer *fb = cmd->state.framebuffer;
466 const struct tu_subpass *subpass = cmd->state.subpass;
467 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
468 unsigned char mrt_comp[MAX_RTS] = { 0 };
469 unsigned srgb_cntl = 0;
470
471 uint32_t gmem_index = 0;
472 for (uint32_t i = 0; i < subpass->color_count; ++i) {
473 uint32_t a = subpass->color_attachments[i].attachment;
474 if (a == VK_ATTACHMENT_UNUSED)
475 continue;
476
477 const struct tu_image_view *iview = fb->attachments[a].attachment;
478 const struct tu_image_level *slice =
479 &iview->image->levels[iview->base_mip];
480 const enum a6xx_tile_mode tile_mode =
481 tu6_get_image_tile_mode(iview->image, iview->base_mip);
482 uint32_t stride = 0;
483 uint32_t offset = 0;
484
485 mrt_comp[i] = 0xf;
486
487 if (vk_format_is_srgb(iview->vk_format))
488 srgb_cntl |= (1 << i);
489
490 const struct tu_native_format *format =
491 tu6_get_native_format(iview->vk_format);
492 assert(format && format->rb >= 0);
493
494 offset = slice->offset + slice->size * iview->base_layer;
495 stride = slice->pitch * iview->image->cpp;
496
497 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
498 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
499 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
500 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
501 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(stride));
502 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(slice->size));
503 tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset +
504 offset); /* BASE_LO/HI */
505 tu_cs_emit(
506 cs, tiling->gmem_offsets[gmem_index++]); /* RB_MRT[i].BASE_GMEM */
507
508 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
509 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb));
510
511 #if 0
512 /* when we support UBWC, these would be the system memory
513 * addr/pitch/etc:
514 */
515 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
516 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
517 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
518 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
519 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
520 #endif
521 }
522
523 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
524 tu_cs_emit(cs, srgb_cntl);
525
526 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
527 tu_cs_emit(cs, srgb_cntl);
528
529 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
530 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
531 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
532 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
533 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
534 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
535 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
536 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
537 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
538
539 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
540 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
541 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
542 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
543 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
544 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
545 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
546 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
547 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
548 }
549
550 static void
551 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
552 {
553 const struct tu_subpass *subpass = cmd->state.subpass;
554 const enum a3xx_msaa_samples samples =
555 tu_msaa_samples(subpass->max_sample_count);
556
557 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
558 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
559 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
560 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
561
562 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
563 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
564 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
565 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
566
567 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
568 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
569 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
570 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
571
572 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
573 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
574 }
575
576 static void
577 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
578 {
579 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
580 const uint32_t bin_w = tiling->tile0.extent.width;
581 const uint32_t bin_h = tiling->tile0.extent.height;
582
583 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
584 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
585 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
586
587 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
588 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
589 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
590
591 /* no flag for RB_BIN_CONTROL2... */
592 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
593 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
594 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
595 }
596
597 static void
598 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
599 struct tu_cs *cs,
600 bool binning)
601 {
602 uint32_t cntl = 0;
603 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
604 if (binning)
605 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
606
607 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
608 tu_cs_emit(cs, 0x2);
609 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
610 tu_cs_emit(cs, cntl);
611 }
612
613 static void
614 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
615 {
616 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
617 const uint32_t x1 = render_area->offset.x;
618 const uint32_t y1 = render_area->offset.y;
619 const uint32_t x2 = x1 + render_area->extent.width - 1;
620 const uint32_t y2 = y1 + render_area->extent.height - 1;
621
622 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
623 tu_cs_emit(cs,
624 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
625 tu_cs_emit(cs,
626 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
627 }
628
629 static void
630 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
631 struct tu_cs *cs,
632 const struct tu_image_view *iview,
633 uint32_t gmem_offset,
634 uint32_t blit_info)
635 {
636 const struct tu_image_level *slice =
637 &iview->image->levels[iview->base_mip];
638 const uint32_t offset = slice->offset + slice->size * iview->base_layer;
639 const uint32_t stride = slice->pitch * iview->image->cpp;
640
641 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
642 tu_cs_emit(cs, blit_info);
643
644 const struct tu_native_format *format =
645 tu6_get_native_format(iview->vk_format);
646 assert(format && format->rb >= 0);
647
648 enum a6xx_tile_mode tile_mode =
649 tu6_get_image_tile_mode(iview->image, iview->base_mip);
650 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
651 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
652 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
653 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
654 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap));
655 tu_cs_emit_qw(cs,
656 iview->image->bo->iova + iview->image->bo_offset + offset);
657 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(stride));
658 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(slice->size));
659
660 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
661 tu_cs_emit(cs, gmem_offset);
662 }
663
664 static void
665 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
666 struct tu_cs *cs,
667 const struct tu_image_view *iview,
668 uint32_t gmem_offset,
669 const VkClearValue *clear_value)
670 {
671 const struct tu_native_format *format =
672 tu6_get_native_format(iview->vk_format);
673 assert(format && format->rb >= 0);
674 /* must be WZYX; other values are ignored */
675 const enum a3xx_color_swap swap = WZYX;
676
677 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
678 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
679 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
680 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
681 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
682
683 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
684 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
687 tu_cs_emit(cs, gmem_offset);
688
689 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
690 tu_cs_emit(cs, 0);
691
692 /* pack clear_value into WZYX order */
693 uint32_t clear_vals[4] = { 0 };
694 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
695
696 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
697 tu_cs_emit(cs, clear_vals[0]);
698 tu_cs_emit(cs, clear_vals[1]);
699 tu_cs_emit(cs, clear_vals[2]);
700 tu_cs_emit(cs, clear_vals[3]);
701 }
702
703 static void
704 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
705 {
706 tu6_emit_marker(cmd, cs);
707 tu6_emit_event_write(cmd, cs, BLIT, false);
708 tu6_emit_marker(cmd, cs);
709 }
710
711 static void
712 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
713 struct tu_cs *cs,
714 uint32_t x1,
715 uint32_t y1,
716 uint32_t x2,
717 uint32_t y2)
718 {
719 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
720 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
721 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
722 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
723 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
724
725 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
726 tu_cs_emit(
727 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
728 tu_cs_emit(
729 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
730 }
731
732 static void
733 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
734 struct tu_cs *cs,
735 uint32_t x1,
736 uint32_t y1)
737 {
738 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
739 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
740
741 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
742 tu_cs_emit(cs,
743 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
744
745 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
746 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
747
748 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
749 tu_cs_emit(
750 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
751 }
752
753 static void
754 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
755 struct tu_cs *cs,
756 const struct tu_tile *tile)
757 {
758 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
759 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
760
761 tu6_emit_marker(cmd, cs);
762 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
763 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
764 tu6_emit_marker(cmd, cs);
765
766 const uint32_t x1 = tile->begin.x;
767 const uint32_t y1 = tile->begin.y;
768 const uint32_t x2 = tile->end.x - 1;
769 const uint32_t y2 = tile->end.y - 1;
770 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
771 tu6_emit_window_offset(cmd, cs, x1, y1);
772
773 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
774 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
775
776 if (false) {
777 /* hw binning? */
778 } else {
779 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
780 tu_cs_emit(cs, 0x1);
781
782 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
783 tu_cs_emit(cs, 0x0);
784 }
785 }
786
787 static void
788 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
789 struct tu_cs *cs,
790 uint32_t a,
791 uint32_t gmem_index)
792 {
793 const struct tu_framebuffer *fb = cmd->state.framebuffer;
794 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
795 const struct tu_attachment_state *attachments = cmd->state.attachments;
796
797 const struct tu_image_view *iview = fb->attachments[a].attachment;
798 const struct tu_attachment_state *att = attachments + a;
799 if (att->pending_clear_aspects) {
800 tu6_emit_blit_clear(cmd, cs, iview,
801 tiling->gmem_offsets[gmem_index],
802 &att->clear_value);
803 } else {
804 tu6_emit_blit_info(cmd, cs, iview,
805 tiling->gmem_offsets[gmem_index],
806 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
807 }
808
809 tu6_emit_blit(cmd, cs);
810 }
811
812 static void
813 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
814 {
815 const struct tu_subpass *subpass = cmd->state.subpass;
816
817 tu6_emit_blit_scissor(cmd, cs);
818
819 uint32_t gmem_index = 0;
820 for (uint32_t i = 0; i < subpass->color_count; ++i) {
821 const uint32_t a = subpass->color_attachments[i].attachment;
822 if (a != VK_ATTACHMENT_UNUSED)
823 tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index++);
824 }
825
826 const uint32_t a = subpass->depth_stencil_attachment.attachment;
827 if (a != VK_ATTACHMENT_UNUSED)
828 tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index);
829 }
830
831 static void
832 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
833 {
834 const struct tu_framebuffer *fb = cmd->state.framebuffer;
835 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
836
837 if (false) {
838 /* hw binning? */
839 }
840
841 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
842 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
843 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
844 CP_SET_DRAW_STATE__0_GROUP_ID(0));
845 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
846 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
847
848 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
849 tu_cs_emit(cs, 0x0);
850
851 tu6_emit_marker(cmd, cs);
852 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
853 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
854 tu6_emit_marker(cmd, cs);
855
856 tu6_emit_blit_scissor(cmd, cs);
857
858 uint32_t gmem_index = 0;
859 for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
860 uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
861 if (a == VK_ATTACHMENT_UNUSED)
862 continue;
863
864 const struct tu_image_view *iview = fb->attachments[a].attachment;
865 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index++],
866 0);
867 tu6_emit_blit(cmd, cs);
868 }
869
870 const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
871 if (a != VK_ATTACHMENT_UNUSED) {
872 const struct tu_image_view *iview = fb->attachments[a].attachment;
873 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index],
874 0);
875 tu6_emit_blit(cmd, cs);
876 }
877 }
878
879 static void
880 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
881 {
882 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
883 tu_cs_emit(cs, restart_index);
884 }
885
886 static void
887 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
888 {
889 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
890 if (result != VK_SUCCESS) {
891 cmd->record_result = result;
892 return;
893 }
894
895 tu6_emit_cache_flush(cmd, cs);
896
897 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
898
899 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
900 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
901 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
902 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
903 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
904 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
905 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
906 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
907 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
908
909 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
910 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
911 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
912 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
913 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
914 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
915 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
916 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
917 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
918 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
919 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
920 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
921 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
922 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
923
924 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
925
926 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
928 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
929
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
940 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
941 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
942
943 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
944 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
945
946 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
947 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
948
949 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
950 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
951
952 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
953 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
954 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
955
956 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
957 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
958
959 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
960
961 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
962
963 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
965 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
966 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
967 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
971 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
972 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
973 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
974 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
975 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
976 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
977 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
978 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
983 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
984
985 tu6_emit_marker(cmd, cs);
986
987 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
988
989 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
990
991 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
992
993 /* we don't use this yet.. probably best to disable.. */
994 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
995 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
996 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
997 CP_SET_DRAW_STATE__0_GROUP_ID(0));
998 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
999 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1002 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1003 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1004 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1005
1006 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1007 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1008 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1009
1010 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1011 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1012
1013 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1014 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1015
1016 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1017 tu_cs_emit(cs, 0x00000000);
1018 tu_cs_emit(cs, 0x00000000);
1019 tu_cs_emit(cs, 0x00000000);
1020
1021 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1022 tu_cs_emit(cs, 0x00000000);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025 tu_cs_emit(cs, 0x00000000);
1026 tu_cs_emit(cs, 0x00000000);
1027 tu_cs_emit(cs, 0x00000000);
1028
1029 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1030 tu_cs_emit(cs, 0x00000000);
1031 tu_cs_emit(cs, 0x00000000);
1032 tu_cs_emit(cs, 0x00000000);
1033 tu_cs_emit(cs, 0x00000000);
1034 tu_cs_emit(cs, 0x00000000);
1035 tu_cs_emit(cs, 0x00000000);
1036
1037 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1038 tu_cs_emit(cs, 0x00000000);
1039 tu_cs_emit(cs, 0x00000000);
1040 tu_cs_emit(cs, 0x00000000);
1041
1042 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1043 tu_cs_emit(cs, 0x00000000);
1044
1045 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1046 tu_cs_emit(cs, 0x00000000);
1047
1048 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1049 tu_cs_emit(cs, 0x00000000);
1050
1051 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1052 tu_cs_emit(cs, 0x00000000);
1053
1054 tu_cs_sanity_check(cs);
1055 }
1056
1057 static void
1058 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1059 {
1060 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1061 if (result != VK_SUCCESS) {
1062 cmd->record_result = result;
1063 return;
1064 }
1065
1066 tu6_emit_lrz_flush(cmd, cs);
1067
1068 /* lrz clear? */
1069
1070 tu6_emit_cache_flush(cmd, cs);
1071
1072 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1073 tu_cs_emit(cs, 0x0);
1074
1075 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1076 tu6_emit_wfi(cmd, cs);
1077 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1078 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1079
1080 tu6_emit_zs(cmd, cs);
1081 tu6_emit_mrt(cmd, cs);
1082 tu6_emit_msaa(cmd, cs);
1083
1084 if (false) {
1085 /* hw binning? */
1086 } else {
1087 tu6_emit_bin_size(cmd, cs, 0x6000000);
1088 /* no draws */
1089 }
1090
1091 tu6_emit_render_cntl(cmd, cs, false);
1092
1093 tu_cs_sanity_check(cs);
1094 }
1095
1096 static void
1097 tu6_render_tile(struct tu_cmd_buffer *cmd,
1098 struct tu_cs *cs,
1099 const struct tu_tile *tile)
1100 {
1101 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1102 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1103 if (result != VK_SUCCESS) {
1104 cmd->record_result = result;
1105 return;
1106 }
1107
1108 tu6_emit_tile_select(cmd, cs, tile);
1109 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1110
1111 tu_cs_emit_call(cs, &cmd->draw_cs);
1112 cmd->wait_for_idle = true;
1113
1114 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1115
1116 tu_cs_sanity_check(cs);
1117 }
1118
1119 static void
1120 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1121 {
1122 const struct tu_subpass *subpass = cmd->state.subpass;
1123 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1124
1125 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1126 if (result != VK_SUCCESS) {
1127 cmd->record_result = result;
1128 return;
1129 }
1130
1131 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1132 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1133
1134 tu6_emit_lrz_flush(cmd, cs);
1135
1136 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1137
1138 if (subpass->has_resolve) {
1139 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1140 struct tu_subpass_attachment src_att = subpass->color_attachments[i];
1141 struct tu_subpass_attachment dst_att = subpass->resolve_attachments[i];
1142
1143 if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
1144 continue;
1145
1146 struct tu_image *src_img = fb->attachments[src_att.attachment].attachment->image;
1147 struct tu_image *dst_img = fb->attachments[dst_att.attachment].attachment->image;
1148
1149 assert(src_img->extent.width == dst_img->extent.width);
1150 assert(src_img->extent.height == dst_img->extent.height);
1151
1152 tu_bo_list_add(&cmd->bo_list, src_img->bo, MSM_SUBMIT_BO_READ);
1153 tu_bo_list_add(&cmd->bo_list, dst_img->bo, MSM_SUBMIT_BO_WRITE);
1154
1155 tu_blit(cmd, &(struct tu_blit) {
1156 .dst = tu_blit_surf_whole(dst_img),
1157 .src = tu_blit_surf_whole(src_img),
1158 .layers = 1,
1159 }, false);
1160 }
1161 }
1162
1163 tu_cs_sanity_check(cs);
1164 }
1165
1166 static void
1167 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1168 {
1169 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1170
1171 tu6_render_begin(cmd, &cmd->cs);
1172
1173 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1174 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1175 struct tu_tile tile;
1176 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1177 tu6_render_tile(cmd, &cmd->cs, &tile);
1178 }
1179 }
1180
1181 tu6_render_end(cmd, &cmd->cs);
1182 }
1183
1184 static void
1185 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1186 {
1187 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1188 const struct tu_subpass *subpass = cmd->state.subpass;
1189 struct tu_attachment_state *attachments = cmd->state.attachments;
1190 struct tu_cs sub_cs;
1191
1192 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1193 tile_load_space, &sub_cs);
1194 if (result != VK_SUCCESS) {
1195 cmd->record_result = result;
1196 return;
1197 }
1198
1199 /* emit to tile-load sub_cs */
1200 tu6_emit_tile_load(cmd, &sub_cs);
1201
1202 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1203
1204 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1205 const uint32_t a = subpass->color_attachments[i].attachment;
1206 if (a != VK_ATTACHMENT_UNUSED)
1207 attachments[a].pending_clear_aspects = 0;
1208 }
1209 }
1210
1211 static void
1212 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1213 {
1214 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1215 struct tu_cs sub_cs;
1216
1217 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1218 tile_store_space, &sub_cs);
1219 if (result != VK_SUCCESS) {
1220 cmd->record_result = result;
1221 return;
1222 }
1223
1224 /* emit to tile-store sub_cs */
1225 tu6_emit_tile_store(cmd, &sub_cs);
1226
1227 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1228 }
1229
1230 static void
1231 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1232 const VkRect2D *render_area)
1233 {
1234 const struct tu_device *dev = cmd->device;
1235 const struct tu_render_pass *pass = cmd->state.pass;
1236 const struct tu_subpass *subpass = cmd->state.subpass;
1237 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1238
1239 uint32_t buffer_cpp[MAX_RTS + 2];
1240 uint32_t buffer_count = 0;
1241
1242 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1243 const uint32_t a = subpass->color_attachments[i].attachment;
1244 if (a == VK_ATTACHMENT_UNUSED)
1245 continue;
1246
1247 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1248 buffer_cpp[buffer_count++] =
1249 vk_format_get_blocksize(att->format) * att->samples;
1250 }
1251
1252 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1253 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1254 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1255
1256 /* TODO */
1257 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1258
1259 buffer_cpp[buffer_count++] =
1260 vk_format_get_blocksize(att->format) * att->samples;
1261 }
1262
1263 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1264 render_area);
1265 }
1266
1267 const struct tu_dynamic_state default_dynamic_state = {
1268 .viewport =
1269 {
1270 .count = 0,
1271 },
1272 .scissor =
1273 {
1274 .count = 0,
1275 },
1276 .line_width = 1.0f,
1277 .depth_bias =
1278 {
1279 .bias = 0.0f,
1280 .clamp = 0.0f,
1281 .slope = 0.0f,
1282 },
1283 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1284 .depth_bounds =
1285 {
1286 .min = 0.0f,
1287 .max = 1.0f,
1288 },
1289 .stencil_compare_mask =
1290 {
1291 .front = ~0u,
1292 .back = ~0u,
1293 },
1294 .stencil_write_mask =
1295 {
1296 .front = ~0u,
1297 .back = ~0u,
1298 },
1299 .stencil_reference =
1300 {
1301 .front = 0u,
1302 .back = 0u,
1303 },
1304 };
1305
1306 static void UNUSED /* FINISHME */
1307 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1308 const struct tu_dynamic_state *src)
1309 {
1310 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1311 uint32_t copy_mask = src->mask;
1312 uint32_t dest_mask = 0;
1313
1314 tu_use_args(cmd_buffer); /* FINISHME */
1315
1316 /* Make sure to copy the number of viewports/scissors because they can
1317 * only be specified at pipeline creation time.
1318 */
1319 dest->viewport.count = src->viewport.count;
1320 dest->scissor.count = src->scissor.count;
1321 dest->discard_rectangle.count = src->discard_rectangle.count;
1322
1323 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1324 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1325 src->viewport.count * sizeof(VkViewport))) {
1326 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1327 src->viewport.count);
1328 dest_mask |= TU_DYNAMIC_VIEWPORT;
1329 }
1330 }
1331
1332 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1333 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1334 src->scissor.count * sizeof(VkRect2D))) {
1335 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1336 src->scissor.count);
1337 dest_mask |= TU_DYNAMIC_SCISSOR;
1338 }
1339 }
1340
1341 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1342 if (dest->line_width != src->line_width) {
1343 dest->line_width = src->line_width;
1344 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1345 }
1346 }
1347
1348 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1349 if (memcmp(&dest->depth_bias, &src->depth_bias,
1350 sizeof(src->depth_bias))) {
1351 dest->depth_bias = src->depth_bias;
1352 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1353 }
1354 }
1355
1356 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1357 if (memcmp(&dest->blend_constants, &src->blend_constants,
1358 sizeof(src->blend_constants))) {
1359 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1360 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1361 }
1362 }
1363
1364 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1365 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1366 sizeof(src->depth_bounds))) {
1367 dest->depth_bounds = src->depth_bounds;
1368 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1369 }
1370 }
1371
1372 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1373 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1374 sizeof(src->stencil_compare_mask))) {
1375 dest->stencil_compare_mask = src->stencil_compare_mask;
1376 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1377 }
1378 }
1379
1380 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1381 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1382 sizeof(src->stencil_write_mask))) {
1383 dest->stencil_write_mask = src->stencil_write_mask;
1384 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1385 }
1386 }
1387
1388 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1389 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1390 sizeof(src->stencil_reference))) {
1391 dest->stencil_reference = src->stencil_reference;
1392 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1393 }
1394 }
1395
1396 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1397 if (memcmp(&dest->discard_rectangle.rectangles,
1398 &src->discard_rectangle.rectangles,
1399 src->discard_rectangle.count * sizeof(VkRect2D))) {
1400 typed_memcpy(dest->discard_rectangle.rectangles,
1401 src->discard_rectangle.rectangles,
1402 src->discard_rectangle.count);
1403 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1404 }
1405 }
1406 }
1407
1408 static VkResult
1409 tu_create_cmd_buffer(struct tu_device *device,
1410 struct tu_cmd_pool *pool,
1411 VkCommandBufferLevel level,
1412 VkCommandBuffer *pCommandBuffer)
1413 {
1414 struct tu_cmd_buffer *cmd_buffer;
1415 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1416 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1417 if (cmd_buffer == NULL)
1418 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1419
1420 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1421 cmd_buffer->device = device;
1422 cmd_buffer->pool = pool;
1423 cmd_buffer->level = level;
1424
1425 if (pool) {
1426 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1427 cmd_buffer->queue_family_index = pool->queue_family_index;
1428
1429 } else {
1430 /* Init the pool_link so we can safely call list_del when we destroy
1431 * the command buffer
1432 */
1433 list_inithead(&cmd_buffer->pool_link);
1434 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1435 }
1436
1437 tu_bo_list_init(&cmd_buffer->bo_list);
1438 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1439 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1440 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1441 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1442
1443 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1444
1445 list_inithead(&cmd_buffer->upload.list);
1446
1447 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1448 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1449
1450 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1451 if (result != VK_SUCCESS)
1452 return result;
1453
1454 return VK_SUCCESS;
1455 }
1456
1457 static void
1458 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1459 {
1460 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1461
1462 list_del(&cmd_buffer->pool_link);
1463
1464 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1465 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1466
1467 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1468 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1469 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1470 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1471
1472 tu_bo_list_destroy(&cmd_buffer->bo_list);
1473 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1474 }
1475
1476 static VkResult
1477 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1478 {
1479 cmd_buffer->wait_for_idle = true;
1480
1481 cmd_buffer->record_result = VK_SUCCESS;
1482
1483 tu_bo_list_reset(&cmd_buffer->bo_list);
1484 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1485 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1486 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1487 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1488
1489 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1490 cmd_buffer->descriptors[i].dirty = 0;
1491 cmd_buffer->descriptors[i].valid = 0;
1492 cmd_buffer->descriptors[i].push_dirty = false;
1493 }
1494
1495 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1496
1497 return cmd_buffer->record_result;
1498 }
1499
1500 static VkResult
1501 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1502 const VkRenderPassBeginInfo *info)
1503 {
1504 struct tu_cmd_state *state = &cmd_buffer->state;
1505 const struct tu_framebuffer *fb = state->framebuffer;
1506 const struct tu_render_pass *pass = state->pass;
1507
1508 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1509 const struct tu_image_view *iview = fb->attachments[i].attachment;
1510 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1511 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1512 }
1513
1514 if (pass->attachment_count == 0) {
1515 state->attachments = NULL;
1516 return VK_SUCCESS;
1517 }
1518
1519 state->attachments =
1520 vk_alloc(&cmd_buffer->pool->alloc,
1521 pass->attachment_count * sizeof(state->attachments[0]), 8,
1522 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1523 if (state->attachments == NULL) {
1524 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1525 return cmd_buffer->record_result;
1526 }
1527
1528 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1529 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1530 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1531 VkImageAspectFlags clear_aspects = 0;
1532
1533 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1534 /* color attachment */
1535 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1536 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1537 }
1538 } else {
1539 /* depthstencil attachment */
1540 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1541 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1542 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1543 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1544 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1545 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1546 }
1547 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1548 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1549 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1550 }
1551 }
1552
1553 state->attachments[i].pending_clear_aspects = clear_aspects;
1554 state->attachments[i].cleared_views = 0;
1555 if (clear_aspects && info) {
1556 assert(info->clearValueCount > i);
1557 state->attachments[i].clear_value = info->pClearValues[i];
1558 }
1559
1560 state->attachments[i].current_layout = att->initial_layout;
1561 }
1562
1563 return VK_SUCCESS;
1564 }
1565
1566 VkResult
1567 tu_AllocateCommandBuffers(VkDevice _device,
1568 const VkCommandBufferAllocateInfo *pAllocateInfo,
1569 VkCommandBuffer *pCommandBuffers)
1570 {
1571 TU_FROM_HANDLE(tu_device, device, _device);
1572 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1573
1574 VkResult result = VK_SUCCESS;
1575 uint32_t i;
1576
1577 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1578
1579 if (!list_empty(&pool->free_cmd_buffers)) {
1580 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1581 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1582
1583 list_del(&cmd_buffer->pool_link);
1584 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1585
1586 result = tu_reset_cmd_buffer(cmd_buffer);
1587 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1588 cmd_buffer->level = pAllocateInfo->level;
1589
1590 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1591 } else {
1592 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1593 &pCommandBuffers[i]);
1594 }
1595 if (result != VK_SUCCESS)
1596 break;
1597 }
1598
1599 if (result != VK_SUCCESS) {
1600 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1601 pCommandBuffers);
1602
1603 /* From the Vulkan 1.0.66 spec:
1604 *
1605 * "vkAllocateCommandBuffers can be used to create multiple
1606 * command buffers. If the creation of any of those command
1607 * buffers fails, the implementation must destroy all
1608 * successfully created command buffer objects from this
1609 * command, set all entries of the pCommandBuffers array to
1610 * NULL and return the error."
1611 */
1612 memset(pCommandBuffers, 0,
1613 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1614 }
1615
1616 return result;
1617 }
1618
1619 void
1620 tu_FreeCommandBuffers(VkDevice device,
1621 VkCommandPool commandPool,
1622 uint32_t commandBufferCount,
1623 const VkCommandBuffer *pCommandBuffers)
1624 {
1625 for (uint32_t i = 0; i < commandBufferCount; i++) {
1626 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1627
1628 if (cmd_buffer) {
1629 if (cmd_buffer->pool) {
1630 list_del(&cmd_buffer->pool_link);
1631 list_addtail(&cmd_buffer->pool_link,
1632 &cmd_buffer->pool->free_cmd_buffers);
1633 } else
1634 tu_cmd_buffer_destroy(cmd_buffer);
1635 }
1636 }
1637 }
1638
1639 VkResult
1640 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1641 VkCommandBufferResetFlags flags)
1642 {
1643 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1644 return tu_reset_cmd_buffer(cmd_buffer);
1645 }
1646
1647 VkResult
1648 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1649 const VkCommandBufferBeginInfo *pBeginInfo)
1650 {
1651 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1652 VkResult result = VK_SUCCESS;
1653
1654 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1655 /* If the command buffer has already been resetted with
1656 * vkResetCommandBuffer, no need to do it again.
1657 */
1658 result = tu_reset_cmd_buffer(cmd_buffer);
1659 if (result != VK_SUCCESS)
1660 return result;
1661 }
1662
1663 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1664 cmd_buffer->usage_flags = pBeginInfo->flags;
1665
1666 tu_cs_begin(&cmd_buffer->cs);
1667
1668 cmd_buffer->marker_seqno = 0;
1669 cmd_buffer->scratch_seqno = 0;
1670
1671 /* setup initial configuration into command buffer */
1672 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1673 switch (cmd_buffer->queue_family_index) {
1674 case TU_QUEUE_GENERAL:
1675 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1676 break;
1677 default:
1678 break;
1679 }
1680 }
1681
1682 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1683
1684 return VK_SUCCESS;
1685 }
1686
1687 void
1688 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1689 uint32_t firstBinding,
1690 uint32_t bindingCount,
1691 const VkBuffer *pBuffers,
1692 const VkDeviceSize *pOffsets)
1693 {
1694 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1695
1696 assert(firstBinding + bindingCount <= MAX_VBS);
1697
1698 for (uint32_t i = 0; i < bindingCount; i++) {
1699 cmd->state.vb.buffers[firstBinding + i] =
1700 tu_buffer_from_handle(pBuffers[i]);
1701 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1702 }
1703
1704 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1705 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1706 }
1707
1708 void
1709 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1710 VkBuffer buffer,
1711 VkDeviceSize offset,
1712 VkIndexType indexType)
1713 {
1714 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1715 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1716
1717 /* initialize/update the restart index */
1718 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1719 struct tu_cs *draw_cs = &cmd->draw_cs;
1720 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1721 if (result != VK_SUCCESS) {
1722 cmd->record_result = result;
1723 return;
1724 }
1725
1726 tu6_emit_restart_index(
1727 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1728
1729 tu_cs_sanity_check(draw_cs);
1730 }
1731
1732 /* track the BO */
1733 if (cmd->state.index_buffer != buf)
1734 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1735
1736 cmd->state.index_buffer = buf;
1737 cmd->state.index_offset = offset;
1738 cmd->state.index_type = indexType;
1739 }
1740
1741 void
1742 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1743 VkPipelineBindPoint pipelineBindPoint,
1744 VkPipelineLayout _layout,
1745 uint32_t firstSet,
1746 uint32_t descriptorSetCount,
1747 const VkDescriptorSet *pDescriptorSets,
1748 uint32_t dynamicOffsetCount,
1749 const uint32_t *pDynamicOffsets)
1750 {
1751 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1752
1753 struct tu_descriptor_state *descriptors_state =
1754 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1755
1756 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1757 unsigned idx = i + firstSet;
1758 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1759
1760 descriptors_state->sets[idx] = set;
1761 descriptors_state->valid |= (1u << idx);
1762 }
1763
1764 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1765 }
1766
1767 void
1768 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1769 VkPipelineLayout layout,
1770 VkShaderStageFlags stageFlags,
1771 uint32_t offset,
1772 uint32_t size,
1773 const void *pValues)
1774 {
1775 }
1776
1777 VkResult
1778 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1779 {
1780 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1781
1782 if (cmd_buffer->scratch_seqno) {
1783 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1784 MSM_SUBMIT_BO_WRITE);
1785 }
1786
1787 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1788 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1789 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1790 }
1791
1792 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1793 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1794 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1795 }
1796
1797 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1798 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1799 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1800 }
1801
1802 tu_cs_end(&cmd_buffer->cs);
1803
1804 assert(!cmd_buffer->state.attachments);
1805
1806 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1807
1808 return cmd_buffer->record_result;
1809 }
1810
1811 void
1812 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1813 VkPipelineBindPoint pipelineBindPoint,
1814 VkPipeline _pipeline)
1815 {
1816 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1817 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1818
1819 switch (pipelineBindPoint) {
1820 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1821 cmd->state.pipeline = pipeline;
1822 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1823 break;
1824 case VK_PIPELINE_BIND_POINT_COMPUTE:
1825 tu_finishme("binding compute pipeline");
1826 break;
1827 default:
1828 unreachable("unrecognized pipeline bind point");
1829 break;
1830 }
1831 }
1832
1833 void
1834 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1835 uint32_t firstViewport,
1836 uint32_t viewportCount,
1837 const VkViewport *pViewports)
1838 {
1839 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1840 struct tu_cs *draw_cs = &cmd->draw_cs;
1841
1842 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1843 if (result != VK_SUCCESS) {
1844 cmd->record_result = result;
1845 return;
1846 }
1847
1848 assert(firstViewport == 0 && viewportCount == 1);
1849 tu6_emit_viewport(draw_cs, pViewports);
1850
1851 tu_cs_sanity_check(draw_cs);
1852 }
1853
1854 void
1855 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1856 uint32_t firstScissor,
1857 uint32_t scissorCount,
1858 const VkRect2D *pScissors)
1859 {
1860 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1861 struct tu_cs *draw_cs = &cmd->draw_cs;
1862
1863 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1864 if (result != VK_SUCCESS) {
1865 cmd->record_result = result;
1866 return;
1867 }
1868
1869 assert(firstScissor == 0 && scissorCount == 1);
1870 tu6_emit_scissor(draw_cs, pScissors);
1871
1872 tu_cs_sanity_check(draw_cs);
1873 }
1874
1875 void
1876 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1877 {
1878 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1879
1880 cmd->state.dynamic.line_width = lineWidth;
1881
1882 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1883 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1884 }
1885
1886 void
1887 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1888 float depthBiasConstantFactor,
1889 float depthBiasClamp,
1890 float depthBiasSlopeFactor)
1891 {
1892 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1893 struct tu_cs *draw_cs = &cmd->draw_cs;
1894
1895 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1896 if (result != VK_SUCCESS) {
1897 cmd->record_result = result;
1898 return;
1899 }
1900
1901 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1902 depthBiasSlopeFactor);
1903
1904 tu_cs_sanity_check(draw_cs);
1905 }
1906
1907 void
1908 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1909 const float blendConstants[4])
1910 {
1911 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1912 struct tu_cs *draw_cs = &cmd->draw_cs;
1913
1914 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1915 if (result != VK_SUCCESS) {
1916 cmd->record_result = result;
1917 return;
1918 }
1919
1920 tu6_emit_blend_constants(draw_cs, blendConstants);
1921
1922 tu_cs_sanity_check(draw_cs);
1923 }
1924
1925 void
1926 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1927 float minDepthBounds,
1928 float maxDepthBounds)
1929 {
1930 }
1931
1932 void
1933 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1934 VkStencilFaceFlags faceMask,
1935 uint32_t compareMask)
1936 {
1937 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1938
1939 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1940 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1941 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1942 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1943
1944 /* the front/back compare masks must be updated together */
1945 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1946 }
1947
1948 void
1949 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1950 VkStencilFaceFlags faceMask,
1951 uint32_t writeMask)
1952 {
1953 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1954
1955 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1956 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1957 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1958 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1959
1960 /* the front/back write masks must be updated together */
1961 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1962 }
1963
1964 void
1965 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1966 VkStencilFaceFlags faceMask,
1967 uint32_t reference)
1968 {
1969 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1970
1971 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1972 cmd->state.dynamic.stencil_reference.front = reference;
1973 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1974 cmd->state.dynamic.stencil_reference.back = reference;
1975
1976 /* the front/back references must be updated together */
1977 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1978 }
1979
1980 void
1981 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1982 uint32_t commandBufferCount,
1983 const VkCommandBuffer *pCmdBuffers)
1984 {
1985 }
1986
1987 VkResult
1988 tu_CreateCommandPool(VkDevice _device,
1989 const VkCommandPoolCreateInfo *pCreateInfo,
1990 const VkAllocationCallbacks *pAllocator,
1991 VkCommandPool *pCmdPool)
1992 {
1993 TU_FROM_HANDLE(tu_device, device, _device);
1994 struct tu_cmd_pool *pool;
1995
1996 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1997 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1998 if (pool == NULL)
1999 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2000
2001 if (pAllocator)
2002 pool->alloc = *pAllocator;
2003 else
2004 pool->alloc = device->alloc;
2005
2006 list_inithead(&pool->cmd_buffers);
2007 list_inithead(&pool->free_cmd_buffers);
2008
2009 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2010
2011 *pCmdPool = tu_cmd_pool_to_handle(pool);
2012
2013 return VK_SUCCESS;
2014 }
2015
2016 void
2017 tu_DestroyCommandPool(VkDevice _device,
2018 VkCommandPool commandPool,
2019 const VkAllocationCallbacks *pAllocator)
2020 {
2021 TU_FROM_HANDLE(tu_device, device, _device);
2022 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2023
2024 if (!pool)
2025 return;
2026
2027 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2028 &pool->cmd_buffers, pool_link)
2029 {
2030 tu_cmd_buffer_destroy(cmd_buffer);
2031 }
2032
2033 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2034 &pool->free_cmd_buffers, pool_link)
2035 {
2036 tu_cmd_buffer_destroy(cmd_buffer);
2037 }
2038
2039 vk_free2(&device->alloc, pAllocator, pool);
2040 }
2041
2042 VkResult
2043 tu_ResetCommandPool(VkDevice device,
2044 VkCommandPool commandPool,
2045 VkCommandPoolResetFlags flags)
2046 {
2047 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2048 VkResult result;
2049
2050 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2051 pool_link)
2052 {
2053 result = tu_reset_cmd_buffer(cmd_buffer);
2054 if (result != VK_SUCCESS)
2055 return result;
2056 }
2057
2058 return VK_SUCCESS;
2059 }
2060
2061 void
2062 tu_TrimCommandPool(VkDevice device,
2063 VkCommandPool commandPool,
2064 VkCommandPoolTrimFlags flags)
2065 {
2066 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2067
2068 if (!pool)
2069 return;
2070
2071 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2072 &pool->free_cmd_buffers, pool_link)
2073 {
2074 tu_cmd_buffer_destroy(cmd_buffer);
2075 }
2076 }
2077
2078 void
2079 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2080 const VkRenderPassBeginInfo *pRenderPassBegin,
2081 VkSubpassContents contents)
2082 {
2083 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2084 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2085 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2086 VkResult result;
2087
2088 cmd_buffer->state.pass = pass;
2089 cmd_buffer->state.subpass = pass->subpasses;
2090 cmd_buffer->state.framebuffer = framebuffer;
2091
2092 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2093 if (result != VK_SUCCESS)
2094 return;
2095
2096 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2097 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2098 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2099
2100 /* draw_cs should contain entries only for this render pass */
2101 assert(!cmd_buffer->draw_cs.entry_count);
2102 tu_cs_begin(&cmd_buffer->draw_cs);
2103 }
2104
2105 void
2106 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2107 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2108 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2109 {
2110 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2111 pSubpassBeginInfo->contents);
2112 }
2113
2114 void
2115 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2116 {
2117 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2118
2119 tu_cmd_render_tiles(cmd);
2120
2121 cmd->state.subpass++;
2122
2123 tu_cmd_update_tiling_config(cmd, NULL);
2124 tu_cmd_prepare_tile_load_ib(cmd);
2125 tu_cmd_prepare_tile_store_ib(cmd);
2126 }
2127
2128 void
2129 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2130 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2131 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2132 {
2133 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2134 }
2135
2136 struct tu_draw_info
2137 {
2138 /**
2139 * Number of vertices.
2140 */
2141 uint32_t count;
2142
2143 /**
2144 * Index of the first vertex.
2145 */
2146 int32_t vertex_offset;
2147
2148 /**
2149 * First instance id.
2150 */
2151 uint32_t first_instance;
2152
2153 /**
2154 * Number of instances.
2155 */
2156 uint32_t instance_count;
2157
2158 /**
2159 * First index (indexed draws only).
2160 */
2161 uint32_t first_index;
2162
2163 /**
2164 * Whether it's an indexed draw.
2165 */
2166 bool indexed;
2167
2168 /**
2169 * Indirect draw parameters resource.
2170 */
2171 struct tu_buffer *indirect;
2172 uint64_t indirect_offset;
2173 uint32_t stride;
2174
2175 /**
2176 * Draw count parameters resource.
2177 */
2178 struct tu_buffer *count_buffer;
2179 uint64_t count_buffer_offset;
2180 };
2181
2182 enum tu_draw_state_group_id
2183 {
2184 TU_DRAW_STATE_PROGRAM,
2185 TU_DRAW_STATE_PROGRAM_BINNING,
2186 TU_DRAW_STATE_VI,
2187 TU_DRAW_STATE_VI_BINNING,
2188 TU_DRAW_STATE_VP,
2189 TU_DRAW_STATE_RAST,
2190 TU_DRAW_STATE_DS,
2191 TU_DRAW_STATE_BLEND,
2192 TU_DRAW_STATE_VS_CONST,
2193 TU_DRAW_STATE_FS_CONST,
2194 TU_DRAW_STATE_VS_TEX,
2195 TU_DRAW_STATE_FS_TEX,
2196
2197 TU_DRAW_STATE_COUNT,
2198 };
2199
2200 struct tu_draw_state_group
2201 {
2202 enum tu_draw_state_group_id id;
2203 uint32_t enable_mask;
2204 struct tu_cs_entry ib;
2205 };
2206
2207 static uint32_t*
2208 map_get(struct tu_descriptor_state *descriptors_state,
2209 const struct tu_descriptor_map *map, unsigned i)
2210 {
2211 assert(descriptors_state->valid & (1 << map->set[i]));
2212
2213 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2214
2215 assert(map->binding[i] < set->layout->binding_count);
2216
2217 return &set->mapped_ptr[set->layout->binding[map->binding[i]].offset / 4];
2218 }
2219
2220 static inline uint32_t
2221 tu6_stage2opcode(gl_shader_stage type)
2222 {
2223 switch (type) {
2224 case MESA_SHADER_VERTEX:
2225 case MESA_SHADER_TESS_CTRL:
2226 case MESA_SHADER_TESS_EVAL:
2227 case MESA_SHADER_GEOMETRY:
2228 return CP_LOAD_STATE6_GEOM;
2229 case MESA_SHADER_FRAGMENT:
2230 case MESA_SHADER_COMPUTE:
2231 case MESA_SHADER_KERNEL:
2232 return CP_LOAD_STATE6_FRAG;
2233 default:
2234 unreachable("bad shader type");
2235 }
2236 }
2237
2238 static inline enum a6xx_state_block
2239 tu6_stage2shadersb(gl_shader_stage type)
2240 {
2241 switch (type) {
2242 case MESA_SHADER_VERTEX:
2243 return SB6_VS_SHADER;
2244 case MESA_SHADER_FRAGMENT:
2245 return SB6_FS_SHADER;
2246 case MESA_SHADER_COMPUTE:
2247 case MESA_SHADER_KERNEL:
2248 return SB6_CS_SHADER;
2249 default:
2250 unreachable("bad shader type");
2251 return ~0;
2252 }
2253 }
2254
2255 static void
2256 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2257 struct tu_descriptor_state *descriptors_state,
2258 gl_shader_stage type)
2259 {
2260 const struct tu_program_descriptor_linkage *link =
2261 &pipeline->program.link[type];
2262 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2263
2264 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2265 if (state->range[i].start < state->range[i].end) {
2266 assert(i && i - 1 < link->ubo_map.num);
2267 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i - 1);
2268
2269 uint32_t size = state->range[i].end - state->range[i].start;
2270 uint32_t offset = state->range[i].start;
2271
2272 /* and even if the start of the const buffer is before
2273 * first_immediate, the end may not be:
2274 */
2275 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2276
2277 if (size == 0)
2278 continue;
2279
2280 /* things should be aligned to vec4: */
2281 debug_assert((state->range[i].offset % 16) == 0);
2282 debug_assert((size % 16) == 0);
2283 debug_assert((offset % 16) == 0);
2284
2285 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2286 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2287 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2288 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2289 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2290 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2291 tu_cs_emit_qw(cs, ((uint64_t) ptr[1] << 32 | ptr[0]) + offset);
2292 }
2293 }
2294 }
2295
2296 static void
2297 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2298 struct tu_descriptor_state *descriptors_state,
2299 gl_shader_stage type)
2300 {
2301 const struct tu_program_descriptor_linkage *link =
2302 &pipeline->program.link[type];
2303
2304 uint32_t anum = align(link->ubo_map.num, 2);
2305 uint32_t i;
2306
2307 if (!link->ubo_map.num)
2308 return;
2309
2310 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2311 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->offset_ubo) |
2312 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2313 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2314 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2315 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2316 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2317 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2318
2319 for (i = 0; i < link->ubo_map.num; i++) {
2320 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i);
2321 tu_cs_emit(cs, ptr[0]);
2322 tu_cs_emit(cs, ptr[1]);
2323 }
2324
2325 for (; i < anum; i++) {
2326 tu_cs_emit(cs, 0xffffffff);
2327 tu_cs_emit(cs, 0xffffffff);
2328 }
2329 }
2330
2331 static struct tu_cs_entry
2332 tu6_emit_consts(struct tu_device *device, struct tu_cs *draw_state,
2333 const struct tu_pipeline *pipeline,
2334 struct tu_descriptor_state *descriptors_state,
2335 gl_shader_stage type)
2336 {
2337 struct tu_cs cs;
2338 tu_cs_begin_sub_stream(device, draw_state, 512, &cs); /* TODO: maximum size? */
2339
2340 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type);
2341 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2342
2343 return tu_cs_end_sub_stream(draw_state, &cs);
2344 }
2345
2346 static struct tu_cs_entry
2347 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2348 const struct tu_pipeline *pipeline,
2349 struct tu_descriptor_state *descriptors_state,
2350 gl_shader_stage type, bool *needs_border)
2351 {
2352 const struct tu_program_descriptor_linkage *link =
2353 &pipeline->program.link[type];
2354
2355 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2356 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2357 if (!size)
2358 return (struct tu_cs_entry) {};
2359
2360 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2361 enum a6xx_state_block sb;
2362
2363 switch (type) {
2364 case MESA_SHADER_VERTEX:
2365 sb = SB6_VS_TEX;
2366 opcode = CP_LOAD_STATE6_GEOM;
2367 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2368 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2369 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2370 break;
2371 case MESA_SHADER_FRAGMENT:
2372 sb = SB6_FS_TEX;
2373 opcode = CP_LOAD_STATE6_FRAG;
2374 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2375 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2376 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2377 break;
2378 case MESA_SHADER_COMPUTE:
2379 sb = SB6_CS_TEX;
2380 opcode = CP_LOAD_STATE6_FRAG;
2381 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2382 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2383 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2384 break;
2385 default:
2386 unreachable("bad state block");
2387 }
2388
2389 struct tu_cs cs;
2390 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2391
2392 for (unsigned i = 0; i < link->texture_map.num; i++) {
2393 uint32_t *ptr = map_get(descriptors_state, &link->texture_map, i);
2394
2395 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2396 tu_cs_emit(&cs, ptr[j]);
2397 }
2398
2399 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2400 uint32_t *ptr = map_get(descriptors_state, &link->sampler_map, i);
2401 struct tu_sampler *sampler = (void*) &ptr[A6XX_TEX_CONST_DWORDS];
2402
2403 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2404 tu_cs_emit(&cs, sampler->state[j]);
2405
2406 *needs_border |= sampler->needs_border;
2407 }
2408
2409 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2410
2411 uint64_t tex_addr = entry.bo->iova + entry.offset;
2412 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2413
2414 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2415
2416 /* output sampler state: */
2417 tu_cs_emit_pkt7(&cs, opcode, 3);
2418 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2419 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2420 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2421 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2422 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2423 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2424
2425 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2426 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2427
2428 /* emit texture state: */
2429 tu_cs_emit_pkt7(&cs, opcode, 3);
2430 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2431 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2432 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2433 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2434 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2435 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2436
2437 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2438 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2439
2440 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2441 tu_cs_emit(&cs, link->texture_map.num);
2442
2443 return tu_cs_end_sub_stream(draw_state, &cs);
2444 }
2445
2446 static void
2447 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2448 struct tu_cs *cs)
2449 {
2450 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2451
2452 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2453 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2454 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2455 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2456 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2457
2458 struct tu_cs border_cs;
2459 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2460
2461 /* TODO: actually fill with border color */
2462 for (unsigned i = 0; i < size; i++)
2463 tu_cs_emit(&border_cs, 0);
2464
2465 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2466
2467 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2468 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2469 }
2470
2471 static void
2472 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2473 struct tu_cs *cs,
2474 const struct tu_draw_info *draw)
2475 {
2476 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2477 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2478 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2479 uint32_t draw_state_group_count = 0;
2480
2481 struct tu_descriptor_state *descriptors_state =
2482 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2483
2484 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2485 if (result != VK_SUCCESS) {
2486 cmd->record_result = result;
2487 return;
2488 }
2489
2490 /* TODO lrz */
2491
2492 uint32_t pc_primitive_cntl = 0;
2493 if (pipeline->ia.primitive_restart && draw->indexed)
2494 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2495
2496 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2497 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2498 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2499
2500 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2501 tu_cs_emit(cs, pc_primitive_cntl);
2502
2503 if (cmd->state.dirty &
2504 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2505 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2506 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2507 dynamic->line_width);
2508 }
2509
2510 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2511 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2512 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2513 dynamic->stencil_compare_mask.back);
2514 }
2515
2516 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2517 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2518 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2519 dynamic->stencil_write_mask.back);
2520 }
2521
2522 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2523 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2524 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2525 dynamic->stencil_reference.back);
2526 }
2527
2528 if (cmd->state.dirty &
2529 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2530 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2531 const uint32_t binding = pipeline->vi.bindings[i];
2532 const uint32_t stride = pipeline->vi.strides[i];
2533 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2534 const VkDeviceSize offset = buf->bo_offset +
2535 cmd->state.vb.offsets[binding] +
2536 pipeline->vi.offsets[i];
2537 const VkDeviceSize size =
2538 offset < buf->bo->size ? buf->bo->size - offset : 0;
2539
2540 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2541 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2542 tu_cs_emit(cs, size);
2543 tu_cs_emit(cs, stride);
2544 }
2545 }
2546
2547 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2548 draw_state_groups[draw_state_group_count++] =
2549 (struct tu_draw_state_group) {
2550 .id = TU_DRAW_STATE_PROGRAM,
2551 .enable_mask = 0x6,
2552 .ib = pipeline->program.state_ib,
2553 };
2554 draw_state_groups[draw_state_group_count++] =
2555 (struct tu_draw_state_group) {
2556 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2557 .enable_mask = 0x1,
2558 .ib = pipeline->program.binning_state_ib,
2559 };
2560 draw_state_groups[draw_state_group_count++] =
2561 (struct tu_draw_state_group) {
2562 .id = TU_DRAW_STATE_VI,
2563 .enable_mask = 0x6,
2564 .ib = pipeline->vi.state_ib,
2565 };
2566 draw_state_groups[draw_state_group_count++] =
2567 (struct tu_draw_state_group) {
2568 .id = TU_DRAW_STATE_VI_BINNING,
2569 .enable_mask = 0x1,
2570 .ib = pipeline->vi.binning_state_ib,
2571 };
2572 draw_state_groups[draw_state_group_count++] =
2573 (struct tu_draw_state_group) {
2574 .id = TU_DRAW_STATE_VP,
2575 .enable_mask = 0x7,
2576 .ib = pipeline->vp.state_ib,
2577 };
2578 draw_state_groups[draw_state_group_count++] =
2579 (struct tu_draw_state_group) {
2580 .id = TU_DRAW_STATE_RAST,
2581 .enable_mask = 0x7,
2582 .ib = pipeline->rast.state_ib,
2583 };
2584 draw_state_groups[draw_state_group_count++] =
2585 (struct tu_draw_state_group) {
2586 .id = TU_DRAW_STATE_DS,
2587 .enable_mask = 0x7,
2588 .ib = pipeline->ds.state_ib,
2589 };
2590 draw_state_groups[draw_state_group_count++] =
2591 (struct tu_draw_state_group) {
2592 .id = TU_DRAW_STATE_BLEND,
2593 .enable_mask = 0x7,
2594 .ib = pipeline->blend.state_ib,
2595 };
2596 }
2597
2598 if (cmd->state.dirty &
2599 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2600 bool needs_border = false;
2601
2602 draw_state_groups[draw_state_group_count++] =
2603 (struct tu_draw_state_group) {
2604 .id = TU_DRAW_STATE_VS_CONST,
2605 .enable_mask = 0x7,
2606 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2607 descriptors_state, MESA_SHADER_VERTEX)
2608 };
2609 draw_state_groups[draw_state_group_count++] =
2610 (struct tu_draw_state_group) {
2611 .id = TU_DRAW_STATE_FS_CONST,
2612 .enable_mask = 0x6,
2613 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2614 descriptors_state, MESA_SHADER_FRAGMENT)
2615 };
2616 draw_state_groups[draw_state_group_count++] =
2617 (struct tu_draw_state_group) {
2618 .id = TU_DRAW_STATE_VS_TEX,
2619 .enable_mask = 0x7,
2620 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2621 descriptors_state, MESA_SHADER_VERTEX,
2622 &needs_border)
2623 };
2624 draw_state_groups[draw_state_group_count++] =
2625 (struct tu_draw_state_group) {
2626 .id = TU_DRAW_STATE_FS_TEX,
2627 .enable_mask = 0x6,
2628 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2629 descriptors_state, MESA_SHADER_FRAGMENT,
2630 &needs_border)
2631 };
2632
2633 if (needs_border)
2634 tu6_emit_border_color(cmd, cs);
2635 }
2636
2637 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2638 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2639 const struct tu_draw_state_group *group = &draw_state_groups[i];
2640
2641 uint32_t cp_set_draw_state =
2642 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2643 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2644 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2645 uint64_t iova;
2646 if (group->ib.size) {
2647 iova = group->ib.bo->iova + group->ib.offset;
2648 } else {
2649 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2650 iova = 0;
2651 }
2652
2653 tu_cs_emit(cs, cp_set_draw_state);
2654 tu_cs_emit_qw(cs, iova);
2655 }
2656
2657 tu_cs_sanity_check(cs);
2658
2659 /* track BOs */
2660 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2661 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2662 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2663 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2664 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2665 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2666 }
2667 }
2668 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2669 for (uint32_t i = 0; i < MAX_VBS; i++) {
2670 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2671 if (buf)
2672 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2673 }
2674 }
2675 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2676 unsigned i;
2677 for_each_bit(i, descriptors_state->valid) {
2678 struct tu_descriptor_set *set = descriptors_state->sets[i];
2679 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2680 if (set->descriptors[j]) {
2681 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2682 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2683 }
2684 }
2685 }
2686 cmd->state.dirty = 0;
2687 }
2688
2689 static void
2690 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2691 struct tu_cs *cs,
2692 const struct tu_draw_info *draw)
2693 {
2694
2695 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2696
2697 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2698 tu_cs_emit(cs, draw->vertex_offset);
2699 tu_cs_emit(cs, draw->first_instance);
2700
2701 /* TODO hw binning */
2702 if (draw->indexed) {
2703 const enum a4xx_index_size index_size =
2704 tu6_index_size(cmd->state.index_type);
2705 const uint32_t index_bytes =
2706 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2707 const struct tu_buffer *buf = cmd->state.index_buffer;
2708 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2709 index_bytes * draw->first_index;
2710 const uint32_t size = index_bytes * draw->count;
2711
2712 const uint32_t cp_draw_indx =
2713 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2714 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2715 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2716 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2717
2718 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2719 tu_cs_emit(cs, cp_draw_indx);
2720 tu_cs_emit(cs, draw->instance_count);
2721 tu_cs_emit(cs, draw->count);
2722 tu_cs_emit(cs, 0x0); /* XXX */
2723 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2724 tu_cs_emit(cs, size);
2725 } else {
2726 const uint32_t cp_draw_indx =
2727 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2728 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2729 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2730
2731 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2732 tu_cs_emit(cs, cp_draw_indx);
2733 tu_cs_emit(cs, draw->instance_count);
2734 tu_cs_emit(cs, draw->count);
2735 }
2736 }
2737
2738 static void
2739 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2740 {
2741 struct tu_cs *cs = &cmd->draw_cs;
2742
2743 tu6_bind_draw_states(cmd, cs, draw);
2744
2745 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2746 if (result != VK_SUCCESS) {
2747 cmd->record_result = result;
2748 return;
2749 }
2750
2751 if (draw->indirect) {
2752 tu_finishme("indirect draw");
2753 return;
2754 }
2755
2756 /* TODO tu6_emit_marker should pick different regs depending on cs */
2757 tu6_emit_marker(cmd, cs);
2758 tu6_emit_draw_direct(cmd, cs, draw);
2759 tu6_emit_marker(cmd, cs);
2760
2761 cmd->wait_for_idle = true;
2762
2763 tu_cs_sanity_check(cs);
2764 }
2765
2766 void
2767 tu_CmdDraw(VkCommandBuffer commandBuffer,
2768 uint32_t vertexCount,
2769 uint32_t instanceCount,
2770 uint32_t firstVertex,
2771 uint32_t firstInstance)
2772 {
2773 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2774 struct tu_draw_info info = {};
2775
2776 info.count = vertexCount;
2777 info.instance_count = instanceCount;
2778 info.first_instance = firstInstance;
2779 info.vertex_offset = firstVertex;
2780
2781 tu_draw(cmd_buffer, &info);
2782 }
2783
2784 void
2785 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2786 uint32_t indexCount,
2787 uint32_t instanceCount,
2788 uint32_t firstIndex,
2789 int32_t vertexOffset,
2790 uint32_t firstInstance)
2791 {
2792 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2793 struct tu_draw_info info = {};
2794
2795 info.indexed = true;
2796 info.count = indexCount;
2797 info.instance_count = instanceCount;
2798 info.first_index = firstIndex;
2799 info.vertex_offset = vertexOffset;
2800 info.first_instance = firstInstance;
2801
2802 tu_draw(cmd_buffer, &info);
2803 }
2804
2805 void
2806 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2807 VkBuffer _buffer,
2808 VkDeviceSize offset,
2809 uint32_t drawCount,
2810 uint32_t stride)
2811 {
2812 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2813 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2814 struct tu_draw_info info = {};
2815
2816 info.count = drawCount;
2817 info.indirect = buffer;
2818 info.indirect_offset = offset;
2819 info.stride = stride;
2820
2821 tu_draw(cmd_buffer, &info);
2822 }
2823
2824 void
2825 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2826 VkBuffer _buffer,
2827 VkDeviceSize offset,
2828 uint32_t drawCount,
2829 uint32_t stride)
2830 {
2831 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2832 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2833 struct tu_draw_info info = {};
2834
2835 info.indexed = true;
2836 info.count = drawCount;
2837 info.indirect = buffer;
2838 info.indirect_offset = offset;
2839 info.stride = stride;
2840
2841 tu_draw(cmd_buffer, &info);
2842 }
2843
2844 struct tu_dispatch_info
2845 {
2846 /**
2847 * Determine the layout of the grid (in block units) to be used.
2848 */
2849 uint32_t blocks[3];
2850
2851 /**
2852 * A starting offset for the grid. If unaligned is set, the offset
2853 * must still be aligned.
2854 */
2855 uint32_t offsets[3];
2856 /**
2857 * Whether it's an unaligned compute dispatch.
2858 */
2859 bool unaligned;
2860
2861 /**
2862 * Indirect compute parameters resource.
2863 */
2864 struct tu_buffer *indirect;
2865 uint64_t indirect_offset;
2866 };
2867
2868 static void
2869 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2870 const struct tu_dispatch_info *info)
2871 {
2872 }
2873
2874 void
2875 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2876 uint32_t base_x,
2877 uint32_t base_y,
2878 uint32_t base_z,
2879 uint32_t x,
2880 uint32_t y,
2881 uint32_t z)
2882 {
2883 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2884 struct tu_dispatch_info info = {};
2885
2886 info.blocks[0] = x;
2887 info.blocks[1] = y;
2888 info.blocks[2] = z;
2889
2890 info.offsets[0] = base_x;
2891 info.offsets[1] = base_y;
2892 info.offsets[2] = base_z;
2893 tu_dispatch(cmd_buffer, &info);
2894 }
2895
2896 void
2897 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2898 uint32_t x,
2899 uint32_t y,
2900 uint32_t z)
2901 {
2902 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2903 }
2904
2905 void
2906 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2907 VkBuffer _buffer,
2908 VkDeviceSize offset)
2909 {
2910 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2911 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2912 struct tu_dispatch_info info = {};
2913
2914 info.indirect = buffer;
2915 info.indirect_offset = offset;
2916
2917 tu_dispatch(cmd_buffer, &info);
2918 }
2919
2920 void
2921 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2922 {
2923 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2924
2925 tu_cs_end(&cmd_buffer->draw_cs);
2926
2927 tu_cmd_render_tiles(cmd_buffer);
2928
2929 /* discard draw_cs entries now that the tiles are rendered */
2930 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2931
2932 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2933 cmd_buffer->state.attachments = NULL;
2934
2935 cmd_buffer->state.pass = NULL;
2936 cmd_buffer->state.subpass = NULL;
2937 cmd_buffer->state.framebuffer = NULL;
2938 }
2939
2940 void
2941 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
2942 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2943 {
2944 tu_CmdEndRenderPass(commandBuffer);
2945 }
2946
2947 struct tu_barrier_info
2948 {
2949 uint32_t eventCount;
2950 const VkEvent *pEvents;
2951 VkPipelineStageFlags srcStageMask;
2952 };
2953
2954 static void
2955 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
2956 uint32_t memoryBarrierCount,
2957 const VkMemoryBarrier *pMemoryBarriers,
2958 uint32_t bufferMemoryBarrierCount,
2959 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2960 uint32_t imageMemoryBarrierCount,
2961 const VkImageMemoryBarrier *pImageMemoryBarriers,
2962 const struct tu_barrier_info *info)
2963 {
2964 }
2965
2966 void
2967 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
2968 VkPipelineStageFlags srcStageMask,
2969 VkPipelineStageFlags destStageMask,
2970 VkBool32 byRegion,
2971 uint32_t memoryBarrierCount,
2972 const VkMemoryBarrier *pMemoryBarriers,
2973 uint32_t bufferMemoryBarrierCount,
2974 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2975 uint32_t imageMemoryBarrierCount,
2976 const VkImageMemoryBarrier *pImageMemoryBarriers)
2977 {
2978 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2979 struct tu_barrier_info info;
2980
2981 info.eventCount = 0;
2982 info.pEvents = NULL;
2983 info.srcStageMask = srcStageMask;
2984
2985 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
2986 bufferMemoryBarrierCount, pBufferMemoryBarriers,
2987 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
2988 }
2989
2990 static void
2991 write_event(struct tu_cmd_buffer *cmd_buffer,
2992 struct tu_event *event,
2993 VkPipelineStageFlags stageMask,
2994 unsigned value)
2995 {
2996 }
2997
2998 void
2999 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3000 VkEvent _event,
3001 VkPipelineStageFlags stageMask)
3002 {
3003 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3004 TU_FROM_HANDLE(tu_event, event, _event);
3005
3006 write_event(cmd_buffer, event, stageMask, 1);
3007 }
3008
3009 void
3010 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3011 VkEvent _event,
3012 VkPipelineStageFlags stageMask)
3013 {
3014 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3015 TU_FROM_HANDLE(tu_event, event, _event);
3016
3017 write_event(cmd_buffer, event, stageMask, 0);
3018 }
3019
3020 void
3021 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3022 uint32_t eventCount,
3023 const VkEvent *pEvents,
3024 VkPipelineStageFlags srcStageMask,
3025 VkPipelineStageFlags dstStageMask,
3026 uint32_t memoryBarrierCount,
3027 const VkMemoryBarrier *pMemoryBarriers,
3028 uint32_t bufferMemoryBarrierCount,
3029 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3030 uint32_t imageMemoryBarrierCount,
3031 const VkImageMemoryBarrier *pImageMemoryBarriers)
3032 {
3033 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3034 struct tu_barrier_info info;
3035
3036 info.eventCount = eventCount;
3037 info.pEvents = pEvents;
3038 info.srcStageMask = 0;
3039
3040 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3041 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3042 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3043 }
3044
3045 void
3046 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3047 {
3048 /* No-op */
3049 }