2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
34 #include "vk_format.h"
39 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
42 tu_bo_list_init(struct tu_bo_list
*list
)
44 list
->count
= list
->capacity
= 0;
45 list
->bo_infos
= NULL
;
49 tu_bo_list_destroy(struct tu_bo_list
*list
)
55 tu_bo_list_reset(struct tu_bo_list
*list
)
61 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
64 tu_bo_list_add_info(struct tu_bo_list
*list
,
65 const struct drm_msm_gem_submit_bo
*bo_info
)
67 assert(bo_info
->handle
!= 0);
69 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
70 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
71 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
72 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
77 /* grow list->bo_infos if needed */
78 if (list
->count
== list
->capacity
) {
79 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
80 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
81 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
83 return TU_BO_LIST_FAILED
;
84 list
->bo_infos
= new_bo_infos
;
85 list
->capacity
= new_capacity
;
88 list
->bo_infos
[list
->count
] = *bo_info
;
93 tu_bo_list_add(struct tu_bo_list
*list
,
94 const struct tu_bo
*bo
,
97 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
99 .handle
= bo
->gem_handle
,
100 .presumed
= bo
->iova
,
105 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
107 for (uint32_t i
= 0; i
< other
->count
; i
++) {
108 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
109 return VK_ERROR_OUT_OF_HOST_MEMORY
;
116 tu_tiling_config_update_gmem_layout(struct tu_tiling_config
*tiling
,
117 const struct tu_device
*dev
)
119 const uint32_t gmem_size
= dev
->physical_device
->gmem_size
;
122 for (uint32_t i
= 0; i
< tiling
->buffer_count
; i
++) {
124 offset
= align(offset
, 0x4000);
126 tiling
->gmem_offsets
[i
] = offset
;
127 offset
+= tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
*
128 tiling
->buffer_cpp
[i
];
131 return offset
<= gmem_size
? VK_SUCCESS
: VK_ERROR_OUT_OF_DEVICE_MEMORY
;
135 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
136 const struct tu_device
*dev
)
138 const uint32_t tile_align_w
= dev
->physical_device
->tile_align_w
;
139 const uint32_t tile_align_h
= dev
->physical_device
->tile_align_h
;
140 const uint32_t max_tile_width
= 1024; /* A6xx */
142 tiling
->tile0
.offset
= (VkOffset2D
) {
143 .x
= tiling
->render_area
.offset
.x
& ~(tile_align_w
- 1),
144 .y
= tiling
->render_area
.offset
.y
& ~(tile_align_h
- 1),
147 const uint32_t ra_width
=
148 tiling
->render_area
.extent
.width
+
149 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
150 const uint32_t ra_height
=
151 tiling
->render_area
.extent
.height
+
152 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
154 /* start from 1 tile */
155 tiling
->tile_count
= (VkExtent2D
) {
159 tiling
->tile0
.extent
= (VkExtent2D
) {
160 .width
= align(ra_width
, tile_align_w
),
161 .height
= align(ra_height
, tile_align_h
),
164 /* do not exceed max tile width */
165 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
166 tiling
->tile_count
.width
++;
167 tiling
->tile0
.extent
.width
=
168 align(ra_width
/ tiling
->tile_count
.width
, tile_align_w
);
171 /* do not exceed gmem size */
172 while (tu_tiling_config_update_gmem_layout(tiling
, dev
) != VK_SUCCESS
) {
173 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
174 tiling
->tile_count
.width
++;
175 tiling
->tile0
.extent
.width
=
176 align(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
178 /* if this assert fails then layout is impossible.. */
179 assert(tiling
->tile0
.extent
.height
> tile_align_h
);
180 tiling
->tile_count
.height
++;
181 tiling
->tile0
.extent
.height
=
182 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), tile_align_h
);
188 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
189 const struct tu_device
*dev
)
191 const uint32_t max_pipe_count
= 32; /* A6xx */
193 /* start from 1 tile per pipe */
194 tiling
->pipe0
= (VkExtent2D
) {
198 tiling
->pipe_count
= tiling
->tile_count
;
200 /* do not exceed max pipe count vertically */
201 while (tiling
->pipe_count
.height
> max_pipe_count
) {
202 tiling
->pipe0
.height
+= 2;
203 tiling
->pipe_count
.height
=
204 (tiling
->tile_count
.height
+ tiling
->pipe0
.height
- 1) /
205 tiling
->pipe0
.height
;
208 /* do not exceed max pipe count */
209 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
>
211 tiling
->pipe0
.width
+= 1;
212 tiling
->pipe_count
.width
=
213 (tiling
->tile_count
.width
+ tiling
->pipe0
.width
- 1) /
219 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
220 const struct tu_device
*dev
)
222 const uint32_t max_pipe_count
= 32; /* A6xx */
223 const uint32_t used_pipe_count
=
224 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
225 const VkExtent2D last_pipe
= {
226 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
227 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
230 assert(used_pipe_count
<= max_pipe_count
);
231 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
233 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
234 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
235 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
236 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
237 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
239 : tiling
->pipe0
.width
;
240 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
242 : tiling
->pipe0
.height
;
243 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
245 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
246 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
247 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
248 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
249 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
253 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
254 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
258 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
259 const struct tu_device
*dev
,
262 struct tu_tile
*tile
)
264 /* find the pipe and the slot for tile (tx, ty) */
265 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
266 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
267 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
268 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
270 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
271 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
272 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
274 /* convert to 1D indices */
275 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
276 tile
->slot
= tiling
->pipe0
.width
* sy
+ sx
;
278 /* get the blit area for the tile */
279 tile
->begin
= (VkOffset2D
) {
280 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
281 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
284 (tx
== tiling
->tile_count
.width
- 1)
285 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
286 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
288 (ty
== tiling
->tile_count
.height
- 1)
289 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
290 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
293 enum a3xx_msaa_samples
294 tu_msaa_samples(uint32_t samples
)
306 assert(!"invalid sample count");
311 static enum a4xx_index_size
312 tu6_index_size(VkIndexType type
)
315 case VK_INDEX_TYPE_UINT16
:
316 return INDEX4_SIZE_16_BIT
;
317 case VK_INDEX_TYPE_UINT32
:
318 return INDEX4_SIZE_32_BIT
;
320 unreachable("invalid VkIndexType");
321 return INDEX4_SIZE_8_BIT
;
326 tu6_emit_marker(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
328 tu_cs_emit_write_reg(cs
, cmd
->marker_reg
, ++cmd
->marker_seqno
);
332 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
334 enum vgt_event_type event
,
339 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
340 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
342 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
343 seqno
= ++cmd
->scratch_seqno
;
344 tu_cs_emit(cs
, seqno
);
351 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
353 tu6_emit_event_write(cmd
, cs
, 0x31, false);
357 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
359 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
363 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
365 if (cmd
->wait_for_idle
) {
367 cmd
->wait_for_idle
= false;
372 tu6_emit_flag_buffer(struct tu_cs
*cs
, const struct tu_image_view
*iview
)
374 uint64_t va
= tu_image_ubwc_base(iview
->image
, iview
->base_mip
, iview
->base_layer
);
375 uint32_t pitch
= tu_image_ubwc_pitch(iview
->image
, iview
->base_mip
);
376 uint32_t size
= tu_image_ubwc_size(iview
->image
, iview
->base_mip
);
377 if (iview
->image
->layout
.ubwc_size
) {
378 tu_cs_emit_qw(cs
, va
);
379 tu_cs_emit(cs
, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch
) |
380 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size
>> 2));
382 tu_cs_emit_qw(cs
, 0);
388 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
389 const struct tu_subpass
*subpass
,
392 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
393 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
395 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
396 if (a
== VK_ATTACHMENT_UNUSED
) {
397 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
398 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
399 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
400 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
401 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
402 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
403 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
405 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
409 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
410 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
411 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
412 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
413 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
414 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
416 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 1);
417 tu_cs_emit(cs
, 0x00000000); /* RB_STENCIL_INFO */
422 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
423 enum a6xx_depth_format fmt
= tu6_pipe2depth(iview
->vk_format
);
425 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
426 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
427 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
428 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview
->image
->layout
.layer_size
));
429 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
430 tu_cs_emit(cs
, tiling
->gmem_offsets
[a
]);
432 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
433 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
435 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
436 tu6_emit_flag_buffer(cs
, iview
);
438 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
439 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
440 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
441 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
442 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
443 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
445 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 1);
446 tu_cs_emit(cs
, 0x00000000); /* RB_STENCIL_INFO */
452 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
453 const struct tu_subpass
*subpass
,
456 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
457 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
458 unsigned char mrt_comp
[MAX_RTS
] = { 0 };
459 unsigned srgb_cntl
= 0;
461 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
462 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
463 if (a
== VK_ATTACHMENT_UNUSED
)
466 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
467 const enum a6xx_tile_mode tile_mode
=
468 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
472 if (vk_format_is_srgb(iview
->vk_format
))
473 srgb_cntl
|= (1 << i
);
475 const struct tu_native_format
*format
=
476 tu6_get_native_format(iview
->vk_format
);
477 assert(format
&& format
->rb
>= 0);
479 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
480 tu_cs_emit(cs
, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
->rb
) |
481 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
482 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format
->swap
));
483 tu_cs_emit(cs
, A6XX_RB_MRT_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
484 tu_cs_emit(cs
, A6XX_RB_MRT_ARRAY_PITCH(iview
->image
->layout
.layer_size
));
485 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
487 cs
, tiling
->gmem_offsets
[a
]); /* RB_MRT[i].BASE_GMEM */
489 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_MRT_REG(i
), 1);
490 tu_cs_emit(cs
, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format
->rb
) |
491 COND(vk_format_is_sint(iview
->vk_format
), A6XX_SP_FS_MRT_REG_COLOR_SINT
) |
492 COND(vk_format_is_uint(iview
->vk_format
), A6XX_SP_FS_MRT_REG_COLOR_UINT
));
494 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
495 tu6_emit_flag_buffer(cs
, iview
);
498 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SRGB_CNTL
, 1);
499 tu_cs_emit(cs
, srgb_cntl
);
501 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_SRGB_CNTL
, 1);
502 tu_cs_emit(cs
, srgb_cntl
);
504 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_COMPONENTS
, 1);
505 tu_cs_emit(cs
, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
506 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
507 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
508 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
509 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
510 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
511 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
512 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
514 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_RENDER_COMPONENTS
, 1);
515 tu_cs_emit(cs
, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
516 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
517 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
518 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
519 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
520 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
521 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
522 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
526 tu6_emit_msaa(struct tu_cmd_buffer
*cmd
,
527 const struct tu_subpass
*subpass
,
530 const enum a3xx_msaa_samples samples
= tu_msaa_samples(subpass
->samples
);
532 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
533 tu_cs_emit(cs
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
534 tu_cs_emit(cs
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
535 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
537 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
538 tu_cs_emit(cs
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
539 tu_cs_emit(cs
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
540 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
542 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
543 tu_cs_emit(cs
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
544 tu_cs_emit(cs
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
545 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
547 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MSAA_CNTL
, 1);
548 tu_cs_emit(cs
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
552 tu6_emit_bin_size(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t flags
)
554 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
555 const uint32_t bin_w
= tiling
->tile0
.extent
.width
;
556 const uint32_t bin_h
= tiling
->tile0
.extent
.height
;
558 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_BIN_CONTROL
, 1);
559 tu_cs_emit(cs
, A6XX_GRAS_BIN_CONTROL_BINW(bin_w
) |
560 A6XX_GRAS_BIN_CONTROL_BINH(bin_h
) | flags
);
562 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BIN_CONTROL
, 1);
563 tu_cs_emit(cs
, A6XX_RB_BIN_CONTROL_BINW(bin_w
) |
564 A6XX_RB_BIN_CONTROL_BINH(bin_h
) | flags
);
566 /* no flag for RB_BIN_CONTROL2... */
567 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BIN_CONTROL2
, 1);
568 tu_cs_emit(cs
, A6XX_RB_BIN_CONTROL2_BINW(bin_w
) |
569 A6XX_RB_BIN_CONTROL2_BINH(bin_h
));
573 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
578 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
580 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
582 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
584 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
585 tu_cs_emit(cs
, cntl
);
589 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
591 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
592 uint32_t x1
= render_area
->offset
.x
;
593 uint32_t y1
= render_area
->offset
.y
;
594 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
595 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
597 /* TODO: alignment requirement seems to be less than tile_align_w/h */
599 x1
= x1
& ~cmd
->device
->physical_device
->tile_align_w
;
600 y1
= y1
& ~cmd
->device
->physical_device
->tile_align_h
;
601 x2
= ALIGN_POT(x2
+ 1, cmd
->device
->physical_device
->tile_align_w
) - 1;
602 y2
= ALIGN_POT(y2
+ 1, cmd
->device
->physical_device
->tile_align_h
) - 1;
605 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
607 A6XX_RB_BLIT_SCISSOR_TL_X(x1
) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1
));
609 A6XX_RB_BLIT_SCISSOR_BR_X(x2
) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2
));
613 tu6_emit_blit_info(struct tu_cmd_buffer
*cmd
,
615 const struct tu_image_view
*iview
,
616 uint32_t gmem_offset
,
619 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_INFO
, 1);
620 tu_cs_emit(cs
, resolve
? 0 : (A6XX_RB_BLIT_INFO_UNK0
| A6XX_RB_BLIT_INFO_GMEM
));
622 const struct tu_native_format
*format
=
623 tu6_get_native_format(iview
->vk_format
);
624 assert(format
&& format
->rb
>= 0);
626 enum a6xx_tile_mode tile_mode
=
627 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
628 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_DST_INFO
, 5);
629 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode
) |
630 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview
->image
->samples
)) |
631 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
->rb
) |
632 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format
->swap
) |
633 COND(iview
->image
->layout
.ubwc_size
,
634 A6XX_RB_BLIT_DST_INFO_FLAGS
));
635 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
636 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
637 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview
->image
->layout
.layer_size
));
639 if (iview
->image
->layout
.ubwc_size
) {
640 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
641 tu6_emit_flag_buffer(cs
, iview
);
644 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
645 tu_cs_emit(cs
, gmem_offset
);
649 tu6_emit_blit(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
651 tu6_emit_marker(cmd
, cs
);
652 tu6_emit_event_write(cmd
, cs
, BLIT
, false);
653 tu6_emit_marker(cmd
, cs
);
657 tu6_emit_window_scissor(struct tu_cmd_buffer
*cmd
,
664 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
665 tu_cs_emit(cs
, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
666 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
667 tu_cs_emit(cs
, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
668 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
670 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
672 cs
, A6XX_GRAS_RESOLVE_CNTL_1_X(x1
) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1
));
674 cs
, A6XX_GRAS_RESOLVE_CNTL_2_X(x2
) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2
));
678 tu6_emit_window_offset(struct tu_cmd_buffer
*cmd
,
683 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
684 tu_cs_emit(cs
, A6XX_RB_WINDOW_OFFSET_X(x1
) | A6XX_RB_WINDOW_OFFSET_Y(y1
));
686 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
688 A6XX_RB_WINDOW_OFFSET2_X(x1
) | A6XX_RB_WINDOW_OFFSET2_Y(y1
));
690 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
691 tu_cs_emit(cs
, A6XX_SP_WINDOW_OFFSET_X(x1
) | A6XX_SP_WINDOW_OFFSET_Y(y1
));
693 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
695 cs
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
699 use_hw_binning(struct tu_cmd_buffer
*cmd
)
701 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
703 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
706 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
710 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
712 const struct tu_tile
*tile
)
714 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
715 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x7));
717 tu6_emit_marker(cmd
, cs
);
718 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
719 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
720 tu6_emit_marker(cmd
, cs
);
722 const uint32_t x1
= tile
->begin
.x
;
723 const uint32_t y1
= tile
->begin
.y
;
724 const uint32_t x2
= tile
->end
.x
- 1;
725 const uint32_t y2
= tile
->end
.y
- 1;
726 tu6_emit_window_scissor(cmd
, cs
, x1
, y1
, x2
, y2
);
727 tu6_emit_window_offset(cmd
, cs
, x1
, y1
);
729 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
730 tu_cs_emit(cs
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
732 if (use_hw_binning(cmd
)) {
733 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
735 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
738 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
739 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
740 A6XX_CP_REG_TEST_0_BIT(0) |
741 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
743 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
744 tu_cs_emit(cs
, 0x10000000);
745 tu_cs_emit(cs
, 11); /* conditionally execute next 11 dwords */
747 /* if (no overflow) */ {
748 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
749 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
750 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
751 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ tile
->pipe
* cmd
->vsc_data_pitch
);
752 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_data_pitch
));
753 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
+ (tile
->pipe
* cmd
->vsc_data2_pitch
));
755 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
758 /* use a NOP packet to skip over the 'else' side: */
759 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
761 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
765 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
768 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_UNKNOWN_8804
, 1);
771 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 1);
774 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 1);
777 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
780 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
786 tu6_emit_load_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
)
788 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
789 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
790 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
791 const struct tu_render_pass_attachment
*attachment
=
792 &cmd
->state
.pass
->attachments
[a
];
794 if (!attachment
->needs_gmem
)
797 const uint32_t x1
= tiling
->render_area
.offset
.x
;
798 const uint32_t y1
= tiling
->render_area
.offset
.y
;
799 const uint32_t x2
= x1
+ tiling
->render_area
.extent
.width
;
800 const uint32_t y2
= y1
+ tiling
->render_area
.extent
.height
;
801 const uint32_t tile_x2
=
802 tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tiling
->tile_count
.width
;
803 const uint32_t tile_y2
=
804 tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* tiling
->tile_count
.height
;
806 x1
!= tiling
->tile0
.offset
.x
|| x2
!= MIN2(fb
->width
, tile_x2
) ||
807 y1
!= tiling
->tile0
.offset
.y
|| y2
!= MIN2(fb
->height
, tile_y2
);
810 tu_finishme("improve handling of unaligned render area");
812 if (attachment
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
)
815 if (vk_format_has_stencil(iview
->vk_format
) &&
816 attachment
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
)
820 tu6_emit_blit_info(cmd
, cs
, iview
, tiling
->gmem_offsets
[a
], false);
821 tu6_emit_blit(cmd
, cs
);
826 tu6_emit_clear_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
828 const VkRenderPassBeginInfo
*info
)
830 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
831 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
832 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
833 const struct tu_render_pass_attachment
*attachment
=
834 &cmd
->state
.pass
->attachments
[a
];
835 unsigned clear_mask
= 0;
837 /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
838 if (!attachment
->needs_gmem
)
841 if (attachment
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
)
844 if (vk_format_has_stencil(iview
->vk_format
)) {
846 if (attachment
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
)
852 const struct tu_native_format
*format
=
853 tu6_get_native_format(iview
->vk_format
);
854 assert(format
&& format
->rb
>= 0);
856 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
857 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
->rb
));
859 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_INFO
, 1);
860 tu_cs_emit(cs
, A6XX_RB_BLIT_INFO_GMEM
| A6XX_RB_BLIT_INFO_CLEAR_MASK(clear_mask
));
862 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
863 tu_cs_emit(cs
, tiling
->gmem_offsets
[a
]);
865 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
868 uint32_t clear_vals
[4] = { 0 };
869 tu_pack_clear_value(&info
->pClearValues
[a
], iview
->vk_format
, clear_vals
);
871 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
872 tu_cs_emit(cs
, clear_vals
[0]);
873 tu_cs_emit(cs
, clear_vals
[1]);
874 tu_cs_emit(cs
, clear_vals
[2]);
875 tu_cs_emit(cs
, clear_vals
[3]);
877 tu6_emit_blit(cmd
, cs
);
881 tu6_emit_store_attachment(struct tu_cmd_buffer
*cmd
,
886 if (cmd
->state
.pass
->attachments
[a
].store_op
== VK_ATTACHMENT_STORE_OP_DONT_CARE
)
889 tu6_emit_blit_info(cmd
, cs
,
890 cmd
->state
.framebuffer
->attachments
[a
].attachment
,
891 cmd
->state
.tiling_config
.gmem_offsets
[gmem_a
], true);
892 tu6_emit_blit(cmd
, cs
);
896 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
898 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
899 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
901 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
902 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
903 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
904 CP_SET_DRAW_STATE__0_GROUP_ID(0));
905 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
906 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
908 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
911 tu6_emit_marker(cmd
, cs
);
912 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
913 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
914 tu6_emit_marker(cmd
, cs
);
916 tu6_emit_blit_scissor(cmd
, cs
, true);
918 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
919 if (pass
->attachments
[a
].needs_gmem
)
920 tu6_emit_store_attachment(cmd
, cs
, a
, a
);
923 if (subpass
->resolve_attachments
) {
924 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
925 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
926 if (a
!= VK_ATTACHMENT_UNUSED
)
927 tu6_emit_store_attachment(cmd
, cs
, a
,
928 subpass
->color_attachments
[i
].attachment
);
934 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
936 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_RESTART_INDEX
, 1);
937 tu_cs_emit(cs
, restart_index
);
941 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
943 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
944 if (result
!= VK_SUCCESS
) {
945 cmd
->record_result
= result
;
949 tu6_emit_cache_flush(cmd
, cs
);
951 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_CCU_CNTL
, 0x7c400004);
954 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
955 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
957 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
958 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
959 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
960 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
961 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
963 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
965 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
966 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
970 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
973 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
974 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
975 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
976 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
978 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
980 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 0);
981 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 0);
982 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
984 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
985 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
986 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
987 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 0);
988 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
989 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
990 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
991 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
992 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
993 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
994 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
995 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
997 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
998 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
1000 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
1001 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
1003 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
1004 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
1006 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
1007 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
1008 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
1010 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
1011 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
1013 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
1015 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
1017 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
1018 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
1019 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
1020 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
1021 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
1022 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
1023 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
1024 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
1025 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
1026 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
1027 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
1028 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
1029 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8804
, 0);
1030 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
1031 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
1032 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
1033 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8805
, 0);
1034 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8806
, 0);
1035 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
1036 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
1037 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
1039 tu6_emit_marker(cmd
, cs
);
1041 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
1043 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
1045 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
1047 /* we don't use this yet.. probably best to disable.. */
1048 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1049 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1050 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1051 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1052 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1053 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1055 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1056 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1057 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1058 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1060 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1061 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1062 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1064 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUF_CNTL
, 1);
1065 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUF_CNTL */
1067 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1068 tu_cs_emit(cs
, 0x00000000); /* UNKNOWN_E2AB */
1070 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1071 tu_cs_emit(cs
, 0x00000000);
1072 tu_cs_emit(cs
, 0x00000000);
1073 tu_cs_emit(cs
, 0x00000000);
1075 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1076 tu_cs_emit(cs
, 0x00000000);
1077 tu_cs_emit(cs
, 0x00000000);
1078 tu_cs_emit(cs
, 0x00000000);
1079 tu_cs_emit(cs
, 0x00000000);
1080 tu_cs_emit(cs
, 0x00000000);
1081 tu_cs_emit(cs
, 0x00000000);
1083 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1084 tu_cs_emit(cs
, 0x00000000);
1085 tu_cs_emit(cs
, 0x00000000);
1086 tu_cs_emit(cs
, 0x00000000);
1087 tu_cs_emit(cs
, 0x00000000);
1088 tu_cs_emit(cs
, 0x00000000);
1089 tu_cs_emit(cs
, 0x00000000);
1091 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1092 tu_cs_emit(cs
, 0x00000000);
1093 tu_cs_emit(cs
, 0x00000000);
1094 tu_cs_emit(cs
, 0x00000000);
1096 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
1097 tu_cs_emit(cs
, 0x00000000);
1099 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
1100 tu_cs_emit(cs
, 0x00000000);
1102 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1103 tu_cs_emit(cs
, 0x00000000);
1105 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_LRZ_CNTL
, 1);
1106 tu_cs_emit(cs
, 0x00000000);
1108 tu_cs_sanity_check(cs
);
1112 tu6_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1116 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_AND_INV_EVENT
, true);
1118 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
1119 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
1120 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
1121 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
1122 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(seqno
));
1123 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0));
1124 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1126 seqno
= tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1128 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_GTE
, 4);
1129 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_0_RESERVED(0));
1130 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
1131 tu_cs_emit(cs
, CP_WAIT_MEM_GTE_3_REF(seqno
));
1135 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1137 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1139 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_BIN_SIZE
, 3);
1140 tu_cs_emit(cs
, A6XX_VSC_BIN_SIZE_WIDTH(tiling
->tile0
.extent
.width
) |
1141 A6XX_VSC_BIN_SIZE_HEIGHT(tiling
->tile0
.extent
.height
));
1142 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
+ 32 * cmd
->vsc_data_pitch
); /* VSC_SIZE_ADDRESS_LO/HI */
1144 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_BIN_COUNT
, 1);
1145 tu_cs_emit(cs
, A6XX_VSC_BIN_COUNT_NX(tiling
->tile_count
.width
) |
1146 A6XX_VSC_BIN_COUNT_NY(tiling
->tile_count
.height
));
1148 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1149 for (unsigned i
= 0; i
< 32; i
++)
1150 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
1152 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO
, 4);
1153 tu_cs_emit_qw(cs
, cmd
->vsc_data2
.iova
);
1154 tu_cs_emit(cs
, cmd
->vsc_data2_pitch
);
1155 tu_cs_emit(cs
, cmd
->vsc_data2
.size
);
1157 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO
, 4);
1158 tu_cs_emit_qw(cs
, cmd
->vsc_data
.iova
);
1159 tu_cs_emit(cs
, cmd
->vsc_data_pitch
);
1160 tu_cs_emit(cs
, cmd
->vsc_data
.size
);
1164 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1166 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1167 const uint32_t used_pipe_count
=
1168 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1170 /* Clear vsc_scratch: */
1171 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1172 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1173 tu_cs_emit(cs
, 0x0);
1175 /* Check for overflow, write vsc_scratch if detected: */
1176 for (int i
= 0; i
< used_pipe_count
; i
++) {
1177 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1178 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1179 CP_COND_WRITE5_0_WRITE_MEMORY
);
1180 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
1181 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1182 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data_pitch
));
1183 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1184 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1185 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_data_pitch
));
1187 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1188 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1189 CP_COND_WRITE5_0_WRITE_MEMORY
);
1190 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
1191 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1192 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_data2_pitch
));
1193 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1194 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1195 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_data2_pitch
));
1198 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1200 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1202 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1203 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
1204 CP_MEM_TO_REG_0_CNT(1 - 1));
1205 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_SCRATCH
);
1208 * This is a bit awkward, we really want a way to invert the
1209 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1210 * execute cmds to use hwbinning when a bit is *not* set. This
1211 * dance is to invert OVERFLOW_FLAG_REG
1213 * A CP_NOP packet is used to skip executing the 'else' clause
1217 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1218 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1219 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1220 A6XX_CP_REG_TEST_0_BIT(0) |
1221 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1223 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1224 tu_cs_emit(cs
, 0x10000000);
1225 tu_cs_emit(cs
, 7); /* conditionally execute next 7 dwords */
1229 * On overflow, mirror the value to control->vsc_overflow
1230 * which CPU is checking to detect overflow (see
1231 * check_vsc_overflow())
1233 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1234 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1235 CP_REG_TO_MEM_0_CNT(0));
1236 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ VSC_OVERFLOW
);
1238 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1239 tu_cs_emit(cs
, 0x0);
1241 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1243 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1244 tu_cs_emit(cs
, 0x1);
1249 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1251 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1253 uint32_t x1
= tiling
->tile0
.offset
.x
;
1254 uint32_t y1
= tiling
->tile0
.offset
.y
;
1255 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1256 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1258 tu6_emit_window_scissor(cmd
, cs
, x1
, y1
, x2
, y2
);
1260 tu6_emit_marker(cmd
, cs
);
1261 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1262 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1263 tu6_emit_marker(cmd
, cs
);
1265 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1266 tu_cs_emit(cs
, 0x1);
1268 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1269 tu_cs_emit(cs
, 0x1);
1273 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_MODE_CNTL
, 1);
1274 tu_cs_emit(cs
, A6XX_VFD_MODE_CNTL_BINNING_PASS
);
1276 update_vsc_pipe(cmd
, cs
);
1278 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9805
, 1);
1279 tu_cs_emit(cs
, 0x1);
1281 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
1282 tu_cs_emit(cs
, 0x1);
1284 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1285 tu_cs_emit(cs
, UNK_2C
);
1287 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
1288 tu_cs_emit(cs
, A6XX_RB_WINDOW_OFFSET_X(0) |
1289 A6XX_RB_WINDOW_OFFSET_Y(0));
1291 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
1292 tu_cs_emit(cs
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
1293 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
1295 /* emit IB to binning drawcmds: */
1296 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1298 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1299 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1300 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1301 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1302 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1303 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1305 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1306 tu_cs_emit(cs
, UNK_2D
);
1308 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
1309 tu6_cache_flush(cmd
, cs
);
1313 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1315 emit_vsc_overflow_test(cmd
, cs
);
1317 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1318 tu_cs_emit(cs
, 0x0);
1320 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1321 tu_cs_emit(cs
, 0x0);
1325 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_CCU_CNTL
, 1);
1326 tu_cs_emit(cs
, 0x7c400004);
1328 cmd
->wait_for_idle
= false;
1332 tu6_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1334 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 1024);
1335 if (result
!= VK_SUCCESS
) {
1336 cmd
->record_result
= result
;
1340 tu6_emit_lrz_flush(cmd
, cs
);
1344 tu6_emit_cache_flush(cmd
, cs
);
1346 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1347 tu_cs_emit(cs
, 0x0);
1349 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1350 tu6_emit_wfi(cmd
, cs
);
1351 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_CCU_CNTL
, 1);
1352 tu_cs_emit(cs
, 0x7c400004); /* RB_CCU_CNTL */
1354 if (use_hw_binning(cmd
)) {
1355 tu6_emit_bin_size(cmd
, cs
, A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1357 tu6_emit_render_cntl(cmd
, cs
, true);
1359 tu6_emit_binning_pass(cmd
, cs
);
1361 tu6_emit_bin_size(cmd
, cs
, A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1363 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_MODE_CNTL
, 1);
1364 tu_cs_emit(cs
, 0x0);
1366 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9805
, 1);
1367 tu_cs_emit(cs
, 0x1);
1369 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
1370 tu_cs_emit(cs
, 0x1);
1372 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1373 tu_cs_emit(cs
, 0x1);
1375 tu6_emit_bin_size(cmd
, cs
, 0x6000000);
1378 tu6_emit_render_cntl(cmd
, cs
, false);
1380 tu_cs_sanity_check(cs
);
1384 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1386 const struct tu_tile
*tile
)
1388 const uint32_t render_tile_space
= 256 + tu_cs_get_call_size(&cmd
->draw_cs
);
1389 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, render_tile_space
);
1390 if (result
!= VK_SUCCESS
) {
1391 cmd
->record_result
= result
;
1395 tu6_emit_tile_select(cmd
, cs
, tile
);
1396 tu_cs_emit_ib(cs
, &cmd
->state
.tile_load_ib
);
1398 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1399 cmd
->wait_for_idle
= true;
1401 if (use_hw_binning(cmd
)) {
1402 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1403 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1404 A6XX_CP_REG_TEST_0_BIT(0) |
1405 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1407 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1408 tu_cs_emit(cs
, 0x10000000);
1409 tu_cs_emit(cs
, 2); /* conditionally execute next 2 dwords */
1411 /* if (no overflow) */ {
1412 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1413 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1417 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1419 tu_cs_sanity_check(cs
);
1423 tu6_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1425 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 16);
1426 if (result
!= VK_SUCCESS
) {
1427 cmd
->record_result
= result
;
1431 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1434 tu6_emit_lrz_flush(cmd
, cs
);
1436 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1438 tu_cs_sanity_check(cs
);
1442 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1444 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1446 tu6_render_begin(cmd
, &cmd
->cs
);
1448 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1449 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1450 struct tu_tile tile
;
1451 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1452 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1456 tu6_render_end(cmd
, &cmd
->cs
);
1460 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer
*cmd
,
1461 const VkRenderPassBeginInfo
*info
)
1463 const uint32_t tile_load_space
=
1464 8 + (23+19) * cmd
->state
.pass
->attachment_count
+
1465 21 + (13 * cmd
->state
.subpass
->color_count
+ 8) + 11;
1467 struct tu_cs sub_cs
;
1469 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
,
1470 tile_load_space
, &sub_cs
);
1471 if (result
!= VK_SUCCESS
) {
1472 cmd
->record_result
= result
;
1476 tu6_emit_blit_scissor(cmd
, &sub_cs
, true);
1478 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1479 tu6_emit_load_attachment(cmd
, &sub_cs
, i
);
1481 tu6_emit_blit_scissor(cmd
, &sub_cs
, false);
1483 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1484 tu6_emit_clear_attachment(cmd
, &sub_cs
, i
, info
);
1486 /* invalidate because reading input attachments will cache GMEM and
1487 * the cache isn''t updated when GMEM is written
1488 * TODO: is there a no-cache bit for textures?
1490 if (cmd
->state
.subpass
->input_count
)
1491 tu6_emit_event_write(cmd
, &sub_cs
, CACHE_INVALIDATE
, false);
1493 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &sub_cs
);
1494 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &sub_cs
);
1495 tu6_emit_msaa(cmd
, cmd
->state
.subpass
, &sub_cs
);
1497 cmd
->state
.tile_load_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1501 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1503 const uint32_t tile_store_space
= 32 + 23 * cmd
->state
.pass
->attachment_count
;
1504 struct tu_cs sub_cs
;
1506 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
,
1507 tile_store_space
, &sub_cs
);
1508 if (result
!= VK_SUCCESS
) {
1509 cmd
->record_result
= result
;
1513 /* emit to tile-store sub_cs */
1514 tu6_emit_tile_store(cmd
, &sub_cs
);
1516 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1520 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1521 const VkRect2D
*render_area
)
1523 const struct tu_device
*dev
= cmd
->device
;
1524 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
1525 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1527 tiling
->render_area
= *render_area
;
1528 for (uint32_t a
= 0; a
< pass
->attachment_count
; a
++) {
1529 if (pass
->attachments
[a
].needs_gmem
)
1530 tiling
->buffer_cpp
[a
] = pass
->attachments
[a
].cpp
;
1532 tiling
->buffer_cpp
[a
] = 0;
1534 tiling
->buffer_count
= pass
->attachment_count
;
1536 tu_tiling_config_update_tile_layout(tiling
, dev
);
1537 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1538 tu_tiling_config_update_pipes(tiling
, dev
);
1541 const struct tu_dynamic_state default_dynamic_state
= {
1557 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1563 .stencil_compare_mask
=
1568 .stencil_write_mask
=
1573 .stencil_reference
=
1580 static void UNUSED
/* FINISHME */
1581 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1582 const struct tu_dynamic_state
*src
)
1584 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1585 uint32_t copy_mask
= src
->mask
;
1586 uint32_t dest_mask
= 0;
1588 tu_use_args(cmd_buffer
); /* FINISHME */
1590 /* Make sure to copy the number of viewports/scissors because they can
1591 * only be specified at pipeline creation time.
1593 dest
->viewport
.count
= src
->viewport
.count
;
1594 dest
->scissor
.count
= src
->scissor
.count
;
1595 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1597 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1598 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1599 src
->viewport
.count
* sizeof(VkViewport
))) {
1600 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1601 src
->viewport
.count
);
1602 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1606 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1607 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1608 src
->scissor
.count
* sizeof(VkRect2D
))) {
1609 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1610 src
->scissor
.count
);
1611 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1615 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1616 if (dest
->line_width
!= src
->line_width
) {
1617 dest
->line_width
= src
->line_width
;
1618 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1622 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1623 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1624 sizeof(src
->depth_bias
))) {
1625 dest
->depth_bias
= src
->depth_bias
;
1626 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1630 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1631 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1632 sizeof(src
->blend_constants
))) {
1633 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1634 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1638 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1639 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1640 sizeof(src
->depth_bounds
))) {
1641 dest
->depth_bounds
= src
->depth_bounds
;
1642 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1646 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1647 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1648 sizeof(src
->stencil_compare_mask
))) {
1649 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1650 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1654 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1655 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1656 sizeof(src
->stencil_write_mask
))) {
1657 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1658 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1662 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1663 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1664 sizeof(src
->stencil_reference
))) {
1665 dest
->stencil_reference
= src
->stencil_reference
;
1666 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1670 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1671 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1672 &src
->discard_rectangle
.rectangles
,
1673 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1674 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1675 src
->discard_rectangle
.rectangles
,
1676 src
->discard_rectangle
.count
);
1677 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1683 tu_create_cmd_buffer(struct tu_device
*device
,
1684 struct tu_cmd_pool
*pool
,
1685 VkCommandBufferLevel level
,
1686 VkCommandBuffer
*pCommandBuffer
)
1688 struct tu_cmd_buffer
*cmd_buffer
;
1689 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1690 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1691 if (cmd_buffer
== NULL
)
1692 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1694 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1695 cmd_buffer
->device
= device
;
1696 cmd_buffer
->pool
= pool
;
1697 cmd_buffer
->level
= level
;
1700 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1701 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1704 /* Init the pool_link so we can safely call list_del when we destroy
1705 * the command buffer
1707 list_inithead(&cmd_buffer
->pool_link
);
1708 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1711 tu_bo_list_init(&cmd_buffer
->bo_list
);
1712 tu_cs_init(&cmd_buffer
->cs
, TU_CS_MODE_GROW
, 4096);
1713 tu_cs_init(&cmd_buffer
->draw_cs
, TU_CS_MODE_GROW
, 4096);
1714 tu_cs_init(&cmd_buffer
->sub_cs
, TU_CS_MODE_SUB_STREAM
, 2048);
1716 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1718 list_inithead(&cmd_buffer
->upload
.list
);
1720 cmd_buffer
->marker_reg
= REG_A6XX_CP_SCRATCH_REG(
1721 cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
? 7 : 6);
1723 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1724 if (result
!= VK_SUCCESS
)
1727 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
1728 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1730 /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1731 cmd_buffer
->vsc_data_pitch
= 0x440 * 4;
1732 cmd_buffer
->vsc_data2_pitch
= 0x1040 * 4;
1734 result
= tu_bo_init_new(device
, &cmd_buffer
->vsc_data
, VSC_DATA_SIZE(cmd_buffer
->vsc_data_pitch
));
1735 if (result
!= VK_SUCCESS
)
1738 result
= tu_bo_init_new(device
, &cmd_buffer
->vsc_data2
, VSC_DATA2_SIZE(cmd_buffer
->vsc_data2_pitch
));
1739 if (result
!= VK_SUCCESS
)
1740 goto fail_vsc_data2
;
1745 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data
);
1747 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1752 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1754 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1755 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data
);
1756 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->vsc_data2
);
1758 list_del(&cmd_buffer
->pool_link
);
1760 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1761 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1763 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->cs
);
1764 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1765 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->sub_cs
);
1767 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1768 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1772 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1774 cmd_buffer
->wait_for_idle
= true;
1776 cmd_buffer
->record_result
= VK_SUCCESS
;
1778 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1779 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->cs
);
1780 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1781 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->sub_cs
);
1783 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1784 cmd_buffer
->descriptors
[i
].dirty
= 0;
1785 cmd_buffer
->descriptors
[i
].valid
= 0;
1786 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1789 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1791 return cmd_buffer
->record_result
;
1795 tu_AllocateCommandBuffers(VkDevice _device
,
1796 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1797 VkCommandBuffer
*pCommandBuffers
)
1799 TU_FROM_HANDLE(tu_device
, device
, _device
);
1800 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1802 VkResult result
= VK_SUCCESS
;
1805 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1807 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1808 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1809 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1811 list_del(&cmd_buffer
->pool_link
);
1812 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1814 result
= tu_reset_cmd_buffer(cmd_buffer
);
1815 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1816 cmd_buffer
->level
= pAllocateInfo
->level
;
1818 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1820 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1821 &pCommandBuffers
[i
]);
1823 if (result
!= VK_SUCCESS
)
1827 if (result
!= VK_SUCCESS
) {
1828 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1831 /* From the Vulkan 1.0.66 spec:
1833 * "vkAllocateCommandBuffers can be used to create multiple
1834 * command buffers. If the creation of any of those command
1835 * buffers fails, the implementation must destroy all
1836 * successfully created command buffer objects from this
1837 * command, set all entries of the pCommandBuffers array to
1838 * NULL and return the error."
1840 memset(pCommandBuffers
, 0,
1841 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1848 tu_FreeCommandBuffers(VkDevice device
,
1849 VkCommandPool commandPool
,
1850 uint32_t commandBufferCount
,
1851 const VkCommandBuffer
*pCommandBuffers
)
1853 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1854 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1857 if (cmd_buffer
->pool
) {
1858 list_del(&cmd_buffer
->pool_link
);
1859 list_addtail(&cmd_buffer
->pool_link
,
1860 &cmd_buffer
->pool
->free_cmd_buffers
);
1862 tu_cmd_buffer_destroy(cmd_buffer
);
1868 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1869 VkCommandBufferResetFlags flags
)
1871 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1872 return tu_reset_cmd_buffer(cmd_buffer
);
1876 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1877 const VkCommandBufferBeginInfo
*pBeginInfo
)
1879 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1880 VkResult result
= VK_SUCCESS
;
1882 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1883 /* If the command buffer has already been resetted with
1884 * vkResetCommandBuffer, no need to do it again.
1886 result
= tu_reset_cmd_buffer(cmd_buffer
);
1887 if (result
!= VK_SUCCESS
)
1891 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1892 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1894 tu_cs_begin(&cmd_buffer
->cs
);
1895 tu_cs_begin(&cmd_buffer
->draw_cs
);
1897 cmd_buffer
->marker_seqno
= 0;
1898 cmd_buffer
->scratch_seqno
= 0;
1900 /* setup initial configuration into command buffer */
1901 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1902 switch (cmd_buffer
->queue_family_index
) {
1903 case TU_QUEUE_GENERAL
:
1904 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1911 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1917 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1918 uint32_t firstBinding
,
1919 uint32_t bindingCount
,
1920 const VkBuffer
*pBuffers
,
1921 const VkDeviceSize
*pOffsets
)
1923 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1925 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1927 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1928 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1929 tu_buffer_from_handle(pBuffers
[i
]);
1930 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1933 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1934 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1938 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1940 VkDeviceSize offset
,
1941 VkIndexType indexType
)
1943 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1944 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1946 /* initialize/update the restart index */
1947 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1948 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1949 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 2);
1950 if (result
!= VK_SUCCESS
) {
1951 cmd
->record_result
= result
;
1955 tu6_emit_restart_index(
1956 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1958 tu_cs_sanity_check(draw_cs
);
1962 if (cmd
->state
.index_buffer
!= buf
)
1963 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1965 cmd
->state
.index_buffer
= buf
;
1966 cmd
->state
.index_offset
= offset
;
1967 cmd
->state
.index_type
= indexType
;
1971 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1972 VkPipelineBindPoint pipelineBindPoint
,
1973 VkPipelineLayout _layout
,
1975 uint32_t descriptorSetCount
,
1976 const VkDescriptorSet
*pDescriptorSets
,
1977 uint32_t dynamicOffsetCount
,
1978 const uint32_t *pDynamicOffsets
)
1980 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1981 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1982 unsigned dyn_idx
= 0;
1984 struct tu_descriptor_state
*descriptors_state
=
1985 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1987 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1988 unsigned idx
= i
+ firstSet
;
1989 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1991 descriptors_state
->sets
[idx
] = set
;
1992 descriptors_state
->valid
|= (1u << idx
);
1994 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1995 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
1996 assert(dyn_idx
< dynamicOffsetCount
);
1998 descriptors_state
->dynamic_buffers
[idx
] =
1999 set
->dynamic_descriptors
[j
].va
+ pDynamicOffsets
[dyn_idx
];
2003 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
2007 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
2008 VkPipelineLayout layout
,
2009 VkShaderStageFlags stageFlags
,
2012 const void *pValues
)
2014 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2015 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
2016 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
2020 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
2022 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2024 if (cmd_buffer
->scratch_seqno
) {
2025 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2026 MSM_SUBMIT_BO_WRITE
);
2029 if (cmd_buffer
->use_vsc_data
) {
2030 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data
,
2031 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2032 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_data2
,
2033 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2036 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2037 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2038 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2041 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2042 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2043 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2046 tu_cs_end(&cmd_buffer
->cs
);
2047 tu_cs_end(&cmd_buffer
->draw_cs
);
2049 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2051 return cmd_buffer
->record_result
;
2055 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2056 VkPipelineBindPoint pipelineBindPoint
,
2057 VkPipeline _pipeline
)
2059 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2060 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2062 switch (pipelineBindPoint
) {
2063 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2064 cmd
->state
.pipeline
= pipeline
;
2065 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
2067 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2068 cmd
->state
.compute_pipeline
= pipeline
;
2069 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2072 unreachable("unrecognized pipeline bind point");
2076 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2077 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2078 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2079 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2080 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2085 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2086 uint32_t firstViewport
,
2087 uint32_t viewportCount
,
2088 const VkViewport
*pViewports
)
2090 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2091 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2093 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 12);
2094 if (result
!= VK_SUCCESS
) {
2095 cmd
->record_result
= result
;
2099 assert(firstViewport
== 0 && viewportCount
== 1);
2100 tu6_emit_viewport(draw_cs
, pViewports
);
2102 tu_cs_sanity_check(draw_cs
);
2106 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2107 uint32_t firstScissor
,
2108 uint32_t scissorCount
,
2109 const VkRect2D
*pScissors
)
2111 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2112 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2114 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 3);
2115 if (result
!= VK_SUCCESS
) {
2116 cmd
->record_result
= result
;
2120 assert(firstScissor
== 0 && scissorCount
== 1);
2121 tu6_emit_scissor(draw_cs
, pScissors
);
2123 tu_cs_sanity_check(draw_cs
);
2127 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2129 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2131 cmd
->state
.dynamic
.line_width
= lineWidth
;
2133 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2134 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2138 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2139 float depthBiasConstantFactor
,
2140 float depthBiasClamp
,
2141 float depthBiasSlopeFactor
)
2143 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2144 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2146 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 4);
2147 if (result
!= VK_SUCCESS
) {
2148 cmd
->record_result
= result
;
2152 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2153 depthBiasSlopeFactor
);
2155 tu_cs_sanity_check(draw_cs
);
2159 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2160 const float blendConstants
[4])
2162 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2163 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2165 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 5);
2166 if (result
!= VK_SUCCESS
) {
2167 cmd
->record_result
= result
;
2171 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2173 tu_cs_sanity_check(draw_cs
);
2177 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2178 float minDepthBounds
,
2179 float maxDepthBounds
)
2184 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2185 VkStencilFaceFlags faceMask
,
2186 uint32_t compareMask
)
2188 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2190 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2191 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2192 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2193 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2195 /* the front/back compare masks must be updated together */
2196 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2200 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2201 VkStencilFaceFlags faceMask
,
2204 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2206 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2207 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2208 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2209 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2211 /* the front/back write masks must be updated together */
2212 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2216 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2217 VkStencilFaceFlags faceMask
,
2220 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2222 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2223 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2224 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2225 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2227 /* the front/back references must be updated together */
2228 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2232 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2233 uint32_t commandBufferCount
,
2234 const VkCommandBuffer
*pCmdBuffers
)
2239 tu_CreateCommandPool(VkDevice _device
,
2240 const VkCommandPoolCreateInfo
*pCreateInfo
,
2241 const VkAllocationCallbacks
*pAllocator
,
2242 VkCommandPool
*pCmdPool
)
2244 TU_FROM_HANDLE(tu_device
, device
, _device
);
2245 struct tu_cmd_pool
*pool
;
2247 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2248 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2250 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2253 pool
->alloc
= *pAllocator
;
2255 pool
->alloc
= device
->alloc
;
2257 list_inithead(&pool
->cmd_buffers
);
2258 list_inithead(&pool
->free_cmd_buffers
);
2260 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2262 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2268 tu_DestroyCommandPool(VkDevice _device
,
2269 VkCommandPool commandPool
,
2270 const VkAllocationCallbacks
*pAllocator
)
2272 TU_FROM_HANDLE(tu_device
, device
, _device
);
2273 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2278 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2279 &pool
->cmd_buffers
, pool_link
)
2281 tu_cmd_buffer_destroy(cmd_buffer
);
2284 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2285 &pool
->free_cmd_buffers
, pool_link
)
2287 tu_cmd_buffer_destroy(cmd_buffer
);
2290 vk_free2(&device
->alloc
, pAllocator
, pool
);
2294 tu_ResetCommandPool(VkDevice device
,
2295 VkCommandPool commandPool
,
2296 VkCommandPoolResetFlags flags
)
2298 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2301 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2304 result
= tu_reset_cmd_buffer(cmd_buffer
);
2305 if (result
!= VK_SUCCESS
)
2313 tu_TrimCommandPool(VkDevice device
,
2314 VkCommandPool commandPool
,
2315 VkCommandPoolTrimFlags flags
)
2317 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2322 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2323 &pool
->free_cmd_buffers
, pool_link
)
2325 tu_cmd_buffer_destroy(cmd_buffer
);
2330 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2331 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2332 VkSubpassContents contents
)
2334 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2335 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2336 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2338 cmd
->state
.pass
= pass
;
2339 cmd
->state
.subpass
= pass
->subpasses
;
2340 cmd
->state
.framebuffer
= fb
;
2342 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2343 tu_cmd_prepare_tile_load_ib(cmd
, pRenderPassBegin
);
2344 tu_cmd_prepare_tile_store_ib(cmd
);
2346 /* note: use_hw_binning only checks tiling config */
2347 if (use_hw_binning(cmd
))
2348 cmd
->use_vsc_data
= true;
2350 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2351 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2352 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2353 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2358 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer
,
2359 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2360 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2362 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2363 pSubpassBeginInfo
->contents
);
2367 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2369 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2370 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2371 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2372 struct tu_cs
*cs
= &cmd
->draw_cs
;
2374 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 1024);
2375 if (result
!= VK_SUCCESS
) {
2376 cmd
->record_result
= result
;
2380 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2382 * if msaa samples change between subpasses,
2383 * attachment store is broken for some attachments
2385 if (subpass
->resolve_attachments
) {
2386 tu6_emit_blit_scissor(cmd
, cs
, true);
2387 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2388 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2389 if (a
!= VK_ATTACHMENT_UNUSED
) {
2390 tu6_emit_store_attachment(cmd
, cs
, a
,
2391 subpass
->color_attachments
[i
].attachment
);
2396 /* invalidate because reading input attachments will cache GMEM and
2397 * the cache isn''t updated when GMEM is written
2398 * TODO: is there a no-cache bit for textures?
2400 if (cmd
->state
.subpass
->input_count
)
2401 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
, false);
2403 /* emit mrt/zs/msaa state for the subpass that is starting */
2404 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2405 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2406 tu6_emit_msaa(cmd
, cmd
->state
.subpass
, cs
);
2409 * since we don't know how to do GMEM->GMEM resolve,
2410 * resolve attachments are resolved to memory then loaded to GMEM again if needed
2412 if (subpass
->resolve_attachments
) {
2413 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2414 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2415 const struct tu_image_view
*iview
=
2416 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
2417 if (a
!= VK_ATTACHMENT_UNUSED
&& pass
->attachments
[a
].needs_gmem
) {
2418 tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2419 tu6_emit_blit_info(cmd
, cs
, iview
, tiling
->gmem_offsets
[a
], false);
2420 tu6_emit_blit(cmd
, cs
);
2427 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer
,
2428 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2429 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2431 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2437 * Number of vertices.
2442 * Index of the first vertex.
2444 int32_t vertex_offset
;
2447 * First instance id.
2449 uint32_t first_instance
;
2452 * Number of instances.
2454 uint32_t instance_count
;
2457 * First index (indexed draws only).
2459 uint32_t first_index
;
2462 * Whether it's an indexed draw.
2467 * Indirect draw parameters resource.
2469 struct tu_buffer
*indirect
;
2470 uint64_t indirect_offset
;
2474 * Draw count parameters resource.
2476 struct tu_buffer
*count_buffer
;
2477 uint64_t count_buffer_offset
;
2480 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2481 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2483 enum tu_draw_state_group_id
2485 TU_DRAW_STATE_PROGRAM
,
2486 TU_DRAW_STATE_PROGRAM_BINNING
,
2488 TU_DRAW_STATE_VI_BINNING
,
2492 TU_DRAW_STATE_BLEND
,
2493 TU_DRAW_STATE_VS_CONST
,
2494 TU_DRAW_STATE_FS_CONST
,
2495 TU_DRAW_STATE_VS_TEX
,
2496 TU_DRAW_STATE_FS_TEX
,
2497 TU_DRAW_STATE_FS_IBO
,
2499 TU_DRAW_STATE_COUNT
,
2502 struct tu_draw_state_group
2504 enum tu_draw_state_group_id id
;
2505 uint32_t enable_mask
;
2506 struct tu_cs_entry ib
;
2509 const static struct tu_sampler
*
2510 sampler_ptr(struct tu_descriptor_state
*descriptors_state
,
2511 const struct tu_descriptor_map
*map
, unsigned i
,
2512 unsigned array_index
)
2514 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2516 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2517 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2519 const struct tu_descriptor_set_binding_layout
*layout
=
2520 &set
->layout
->binding
[map
->binding
[i
]];
2522 if (layout
->immutable_samplers_offset
) {
2523 const struct tu_sampler
*immutable_samplers
=
2524 tu_immutable_samplers(set
->layout
, layout
);
2526 return &immutable_samplers
[array_index
];
2529 switch (layout
->type
) {
2530 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2531 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4];
2532 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2533 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4 + A6XX_TEX_CONST_DWORDS
+
2535 (A6XX_TEX_CONST_DWORDS
+
2536 sizeof(struct tu_sampler
) / 4)];
2538 unreachable("unimplemented descriptor type");
2544 write_tex_const(struct tu_cmd_buffer
*cmd
,
2546 struct tu_descriptor_state
*descriptors_state
,
2547 const struct tu_descriptor_map
*map
,
2548 unsigned i
, unsigned array_index
)
2550 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2552 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2553 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2555 const struct tu_descriptor_set_binding_layout
*layout
=
2556 &set
->layout
->binding
[map
->binding
[i
]];
2558 switch (layout
->type
) {
2559 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
2560 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2561 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2562 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2563 memcpy(dst
, &set
->mapped_ptr
[layout
->offset
/ 4 +
2564 array_index
* A6XX_TEX_CONST_DWORDS
],
2565 A6XX_TEX_CONST_DWORDS
* 4);
2567 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2568 memcpy(dst
, &set
->mapped_ptr
[layout
->offset
/ 4 +
2570 (A6XX_TEX_CONST_DWORDS
+
2571 sizeof(struct tu_sampler
) / 4)],
2572 A6XX_TEX_CONST_DWORDS
* 4);
2575 unreachable("unimplemented descriptor type");
2579 if (layout
->type
== VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
) {
2580 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2581 uint32_t a
= cmd
->state
.subpass
->input_attachments
[map
->value
[i
] +
2582 array_index
].attachment
;
2584 assert(cmd
->state
.pass
->attachments
[a
].needs_gmem
);
2585 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2586 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2587 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2589 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2590 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* tiling
->buffer_cpp
[a
]);
2592 dst
[4] = 0x100000 + tiling
->gmem_offsets
[a
];
2593 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2594 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2600 buffer_ptr(struct tu_descriptor_state
*descriptors_state
,
2601 const struct tu_descriptor_map
*map
,
2602 unsigned i
, unsigned array_index
)
2604 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2606 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2607 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2609 const struct tu_descriptor_set_binding_layout
*layout
=
2610 &set
->layout
->binding
[map
->binding
[i
]];
2612 switch (layout
->type
) {
2613 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2614 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
2615 return descriptors_state
->dynamic_buffers
[layout
->dynamic_offset_offset
+
2617 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2618 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2619 return (uint64_t) set
->mapped_ptr
[layout
->offset
/ 4 + array_index
* 2 + 1] << 32 |
2620 set
->mapped_ptr
[layout
->offset
/ 4 + array_index
* 2];
2622 unreachable("unimplemented descriptor type");
2627 static inline uint32_t
2628 tu6_stage2opcode(gl_shader_stage type
)
2631 case MESA_SHADER_VERTEX
:
2632 case MESA_SHADER_TESS_CTRL
:
2633 case MESA_SHADER_TESS_EVAL
:
2634 case MESA_SHADER_GEOMETRY
:
2635 return CP_LOAD_STATE6_GEOM
;
2636 case MESA_SHADER_FRAGMENT
:
2637 case MESA_SHADER_COMPUTE
:
2638 case MESA_SHADER_KERNEL
:
2639 return CP_LOAD_STATE6_FRAG
;
2641 unreachable("bad shader type");
2645 static inline enum a6xx_state_block
2646 tu6_stage2shadersb(gl_shader_stage type
)
2649 case MESA_SHADER_VERTEX
:
2650 return SB6_VS_SHADER
;
2651 case MESA_SHADER_FRAGMENT
:
2652 return SB6_FS_SHADER
;
2653 case MESA_SHADER_COMPUTE
:
2654 case MESA_SHADER_KERNEL
:
2655 return SB6_CS_SHADER
;
2657 unreachable("bad shader type");
2663 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2664 struct tu_descriptor_state
*descriptors_state
,
2665 gl_shader_stage type
,
2666 uint32_t *push_constants
)
2668 const struct tu_program_descriptor_linkage
*link
=
2669 &pipeline
->program
.link
[type
];
2670 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2672 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
2673 if (state
->range
[i
].start
< state
->range
[i
].end
) {
2674 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2675 uint32_t offset
= state
->range
[i
].start
;
2677 /* and even if the start of the const buffer is before
2678 * first_immediate, the end may not be:
2680 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2685 /* things should be aligned to vec4: */
2686 debug_assert((state
->range
[i
].offset
% 16) == 0);
2687 debug_assert((size
% 16) == 0);
2688 debug_assert((offset
% 16) == 0);
2691 /* push constants */
2692 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (size
/ 4));
2693 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2694 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2695 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2696 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2697 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2700 for (unsigned i
= 0; i
< size
/ 4; i
++)
2701 tu_cs_emit(cs
, push_constants
[i
+ offset
/ 4]);
2705 /* Look through the UBO map to find our UBO index, and get the VA for
2709 uint32_t ubo_idx
= i
- 1;
2710 uint32_t ubo_map_base
= 0;
2711 for (int j
= 0; j
< link
->ubo_map
.num
; j
++) {
2712 if (ubo_idx
>= ubo_map_base
&&
2713 ubo_idx
< ubo_map_base
+ link
->ubo_map
.array_size
[j
]) {
2714 va
= buffer_ptr(descriptors_state
, &link
->ubo_map
, j
,
2715 ubo_idx
- ubo_map_base
);
2718 ubo_map_base
+= link
->ubo_map
.array_size
[j
];
2722 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2723 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2724 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2725 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2726 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2727 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2728 tu_cs_emit_qw(cs
, va
+ offset
);
2734 tu6_emit_ubos(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2735 struct tu_descriptor_state
*descriptors_state
,
2736 gl_shader_stage type
)
2738 const struct tu_program_descriptor_linkage
*link
=
2739 &pipeline
->program
.link
[type
];
2741 uint32_t num
= MIN2(link
->ubo_map
.num_desc
, link
->const_state
.num_ubos
);
2742 uint32_t anum
= align(num
, 2);
2747 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (2 * anum
));
2748 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(link
->const_state
.offsets
.ubo
) |
2749 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2750 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2751 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2752 CP_LOAD_STATE6_0_NUM_UNIT(anum
/2));
2753 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2754 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2756 unsigned emitted
= 0;
2757 for (unsigned i
= 0; emitted
< num
&& i
< link
->ubo_map
.num
; i
++) {
2758 for (unsigned j
= 0; emitted
< num
&& j
< link
->ubo_map
.array_size
[i
]; j
++) {
2759 tu_cs_emit_qw(cs
, buffer_ptr(descriptors_state
, &link
->ubo_map
, i
, j
));
2764 for (; emitted
< anum
; emitted
++) {
2765 tu_cs_emit(cs
, 0xffffffff);
2766 tu_cs_emit(cs
, 0xffffffff);
2770 static struct tu_cs_entry
2771 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2772 const struct tu_pipeline
*pipeline
,
2773 struct tu_descriptor_state
*descriptors_state
,
2774 gl_shader_stage type
)
2777 tu_cs_begin_sub_stream(cmd
->device
, &cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2779 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2780 tu6_emit_ubos(&cs
, pipeline
, descriptors_state
, type
);
2782 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2786 tu6_emit_textures(struct tu_cmd_buffer
*cmd
,
2787 const struct tu_pipeline
*pipeline
,
2788 struct tu_descriptor_state
*descriptors_state
,
2789 gl_shader_stage type
,
2790 struct tu_cs_entry
*entry
,
2793 struct tu_device
*device
= cmd
->device
;
2794 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2795 const struct tu_program_descriptor_linkage
*link
=
2796 &pipeline
->program
.link
[type
];
2799 if (link
->texture_map
.num_desc
== 0 && link
->sampler_map
.num_desc
== 0) {
2800 *entry
= (struct tu_cs_entry
) {};
2804 /* allocate and fill texture state */
2805 struct ts_cs_memory tex_const
;
2806 result
= tu_cs_alloc(device
, draw_state
, link
->texture_map
.num_desc
,
2807 A6XX_TEX_CONST_DWORDS
, &tex_const
);
2808 if (result
!= VK_SUCCESS
)
2812 for (unsigned i
= 0; i
< link
->texture_map
.num
; i
++) {
2813 for (int j
= 0; j
< link
->texture_map
.array_size
[i
]; j
++) {
2814 write_tex_const(cmd
,
2815 &tex_const
.map
[A6XX_TEX_CONST_DWORDS
* tex_index
++],
2816 descriptors_state
, &link
->texture_map
, i
, j
);
2820 /* allocate and fill sampler state */
2821 struct ts_cs_memory tex_samp
= { 0 };
2822 if (link
->sampler_map
.num_desc
) {
2823 result
= tu_cs_alloc(device
, draw_state
, link
->sampler_map
.num_desc
,
2824 A6XX_TEX_SAMP_DWORDS
, &tex_samp
);
2825 if (result
!= VK_SUCCESS
)
2828 int sampler_index
= 0;
2829 for (unsigned i
= 0; i
< link
->sampler_map
.num
; i
++) {
2830 for (int j
= 0; j
< link
->sampler_map
.array_size
[i
]; j
++) {
2831 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
2834 memcpy(&tex_samp
.map
[A6XX_TEX_SAMP_DWORDS
* sampler_index
++],
2835 sampler
->state
, sizeof(sampler
->state
));
2836 *needs_border
|= sampler
->needs_border
;
2841 unsigned tex_samp_reg
, tex_const_reg
, tex_count_reg
;
2842 enum a6xx_state_block sb
;
2845 case MESA_SHADER_VERTEX
:
2847 tex_samp_reg
= REG_A6XX_SP_VS_TEX_SAMP_LO
;
2848 tex_const_reg
= REG_A6XX_SP_VS_TEX_CONST_LO
;
2849 tex_count_reg
= REG_A6XX_SP_VS_TEX_COUNT
;
2851 case MESA_SHADER_FRAGMENT
:
2853 tex_samp_reg
= REG_A6XX_SP_FS_TEX_SAMP_LO
;
2854 tex_const_reg
= REG_A6XX_SP_FS_TEX_CONST_LO
;
2855 tex_count_reg
= REG_A6XX_SP_FS_TEX_COUNT
;
2857 case MESA_SHADER_COMPUTE
:
2859 tex_samp_reg
= REG_A6XX_SP_CS_TEX_SAMP_LO
;
2860 tex_const_reg
= REG_A6XX_SP_CS_TEX_CONST_LO
;
2861 tex_count_reg
= REG_A6XX_SP_CS_TEX_COUNT
;
2864 unreachable("bad state block");
2868 result
= tu_cs_begin_sub_stream(device
, draw_state
, 16, &cs
);
2869 if (result
!= VK_SUCCESS
)
2872 if (link
->sampler_map
.num_desc
) {
2873 /* output sampler state: */
2874 tu_cs_emit_pkt7(&cs
, tu6_stage2opcode(type
), 3);
2875 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2876 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
2877 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2878 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2879 CP_LOAD_STATE6_0_NUM_UNIT(link
->sampler_map
.num_desc
));
2880 tu_cs_emit_qw(&cs
, tex_samp
.iova
); /* SRC_ADDR_LO/HI */
2882 tu_cs_emit_pkt4(&cs
, tex_samp_reg
, 2);
2883 tu_cs_emit_qw(&cs
, tex_samp
.iova
); /* SRC_ADDR_LO/HI */
2886 /* emit texture state: */
2887 tu_cs_emit_pkt7(&cs
, tu6_stage2opcode(type
), 3);
2888 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2889 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2890 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2891 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2892 CP_LOAD_STATE6_0_NUM_UNIT(link
->texture_map
.num_desc
));
2893 tu_cs_emit_qw(&cs
, tex_const
.iova
); /* SRC_ADDR_LO/HI */
2895 tu_cs_emit_pkt4(&cs
, tex_const_reg
, 2);
2896 tu_cs_emit_qw(&cs
, tex_const
.iova
); /* SRC_ADDR_LO/HI */
2898 tu_cs_emit_pkt4(&cs
, tex_count_reg
, 1);
2899 tu_cs_emit(&cs
, link
->texture_map
.num_desc
);
2901 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2906 tu6_emit_ibo(struct tu_cmd_buffer
*cmd
,
2907 const struct tu_pipeline
*pipeline
,
2908 struct tu_descriptor_state
*descriptors_state
,
2909 gl_shader_stage type
,
2910 struct tu_cs_entry
*entry
)
2912 struct tu_device
*device
= cmd
->device
;
2913 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2914 const struct tu_program_descriptor_linkage
*link
=
2915 &pipeline
->program
.link
[type
];
2918 if (link
->image_mapping
.num_ibo
== 0) {
2919 *entry
= (struct tu_cs_entry
) {};
2923 struct ts_cs_memory ibo_const
;
2924 result
= tu_cs_alloc(device
, draw_state
, link
->image_mapping
.num_ibo
,
2925 A6XX_TEX_CONST_DWORDS
, &ibo_const
);
2926 if (result
!= VK_SUCCESS
)
2929 for (unsigned i
= 0; i
< link
->image_mapping
.num_ibo
; i
++) {
2930 unsigned idx
= link
->image_mapping
.ibo_to_image
[i
];
2931 uint32_t *dst
= &ibo_const
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2933 if (idx
& IBO_SSBO
) {
2936 uint64_t va
= buffer_ptr(descriptors_state
, &link
->ssbo_map
, idx
,
2938 /* We don't expose robustBufferAccess, so leave the size unlimited. */
2939 uint32_t sz
= MAX_STORAGE_BUFFER_RANGE
/ 4;
2941 dst
[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT
);
2942 dst
[1] = A6XX_IBO_1_WIDTH(sz
& MASK(15)) |
2943 A6XX_IBO_1_HEIGHT(sz
>> 15);
2944 dst
[2] = A6XX_IBO_2_UNK4
|
2946 A6XX_IBO_2_TYPE(A6XX_TEX_1D
);
2950 for (int i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2953 tu_finishme("Emit images");
2958 result
= tu_cs_begin_sub_stream(device
, draw_state
, 7, &cs
);
2959 if (result
!= VK_SUCCESS
)
2962 uint32_t opcode
, ibo_addr_reg
;
2963 enum a6xx_state_block sb
;
2964 enum a6xx_state_type st
;
2967 case MESA_SHADER_FRAGMENT
:
2968 opcode
= CP_LOAD_STATE6
;
2971 ibo_addr_reg
= REG_A6XX_SP_IBO_LO
;
2973 case MESA_SHADER_COMPUTE
:
2974 opcode
= CP_LOAD_STATE6_FRAG
;
2977 ibo_addr_reg
= REG_A6XX_SP_CS_IBO_LO
;
2980 unreachable("unsupported stage for ibos");
2983 /* emit texture state: */
2984 tu_cs_emit_pkt7(&cs
, opcode
, 3);
2985 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2986 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
2987 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2988 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2989 CP_LOAD_STATE6_0_NUM_UNIT(link
->image_mapping
.num_ibo
));
2990 tu_cs_emit_qw(&cs
, ibo_const
.iova
); /* SRC_ADDR_LO/HI */
2992 tu_cs_emit_pkt4(&cs
, ibo_addr_reg
, 2);
2993 tu_cs_emit_qw(&cs
, ibo_const
.iova
); /* SRC_ADDR_LO/HI */
2995 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2999 struct PACKED bcolor_entry
{
3011 uint32_t z24
; /* also s8? */
3012 uint16_t srgb
[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
3014 } border_color
[] = {
3015 [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
] = {},
3016 [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
] = {},
3017 [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
] = {
3018 .fp32
[3] = 0x3f800000,
3026 .rgb10a2
= 0xc0000000,
3029 [VK_BORDER_COLOR_INT_OPAQUE_BLACK
] = {
3033 [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
] = {
3034 .fp32
[0 ... 3] = 0x3f800000,
3035 .ui16
[0 ... 3] = 0xffff,
3036 .si16
[0 ... 3] = 0x7fff,
3037 .fp16
[0 ... 3] = 0x3c00,
3041 .ui8
[0 ... 3] = 0xff,
3042 .si8
[0 ... 3] = 0x7f,
3043 .rgb10a2
= 0xffffffff,
3045 .srgb
[0 ... 3] = 0x3c00,
3047 [VK_BORDER_COLOR_INT_OPAQUE_WHITE
] = {
3054 tu6_emit_border_color(struct tu_cmd_buffer
*cmd
,
3057 STATIC_ASSERT(sizeof(struct bcolor_entry
) == 128);
3059 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3060 struct tu_descriptor_state
*descriptors_state
=
3061 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3062 const struct tu_descriptor_map
*vs_sampler
=
3063 &pipeline
->program
.link
[MESA_SHADER_VERTEX
].sampler_map
;
3064 const struct tu_descriptor_map
*fs_sampler
=
3065 &pipeline
->program
.link
[MESA_SHADER_FRAGMENT
].sampler_map
;
3066 struct ts_cs_memory ptr
;
3068 VkResult result
= tu_cs_alloc(cmd
->device
, &cmd
->sub_cs
,
3069 vs_sampler
->num_desc
+ fs_sampler
->num_desc
,
3072 if (result
!= VK_SUCCESS
)
3075 for (unsigned i
= 0; i
< vs_sampler
->num
; i
++) {
3076 for (unsigned j
= 0; j
< vs_sampler
->array_size
[i
]; j
++) {
3077 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
3079 memcpy(ptr
.map
, &border_color
[sampler
->border
], 128);
3084 for (unsigned i
= 0; i
< fs_sampler
->num
; i
++) {
3085 for (unsigned j
= 0; j
< fs_sampler
->array_size
[i
]; j
++) {
3086 const struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
,
3088 memcpy(ptr
.map
, &border_color
[sampler
->border
], 128);
3093 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
3094 tu_cs_emit_qw(cs
, ptr
.iova
);
3099 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
3101 const struct tu_draw_info
*draw
)
3103 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3104 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
3105 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
3106 uint32_t draw_state_group_count
= 0;
3108 struct tu_descriptor_state
*descriptors_state
=
3109 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3111 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
3112 if (result
!= VK_SUCCESS
)
3117 uint32_t pc_primitive_cntl
= 0;
3118 if (pipeline
->ia
.primitive_restart
&& draw
->indexed
)
3119 pc_primitive_cntl
|= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART
;
3121 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
3122 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
3123 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
3125 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_0
, 1);
3126 tu_cs_emit(cs
, pc_primitive_cntl
);
3128 if (cmd
->state
.dirty
&
3129 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
3130 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
3131 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
3132 dynamic
->line_width
);
3135 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
3136 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
3137 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
3138 dynamic
->stencil_compare_mask
.back
);
3141 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
3142 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
3143 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
3144 dynamic
->stencil_write_mask
.back
);
3147 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
3148 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
3149 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
3150 dynamic
->stencil_reference
.back
);
3153 if (cmd
->state
.dirty
&
3154 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
3155 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
3156 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
3157 const uint32_t stride
= pipeline
->vi
.strides
[i
];
3158 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
3159 const VkDeviceSize offset
= buf
->bo_offset
+
3160 cmd
->state
.vb
.offsets
[binding
] +
3161 pipeline
->vi
.offsets
[i
];
3162 const VkDeviceSize size
=
3163 offset
< buf
->bo
->size
? buf
->bo
->size
- offset
: 0;
3165 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_FETCH(i
), 4);
3166 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3167 tu_cs_emit(cs
, size
);
3168 tu_cs_emit(cs
, stride
);
3172 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
3173 draw_state_groups
[draw_state_group_count
++] =
3174 (struct tu_draw_state_group
) {
3175 .id
= TU_DRAW_STATE_PROGRAM
,
3176 .enable_mask
= ENABLE_DRAW
,
3177 .ib
= pipeline
->program
.state_ib
,
3179 draw_state_groups
[draw_state_group_count
++] =
3180 (struct tu_draw_state_group
) {
3181 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
3182 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
3183 .ib
= pipeline
->program
.binning_state_ib
,
3185 draw_state_groups
[draw_state_group_count
++] =
3186 (struct tu_draw_state_group
) {
3187 .id
= TU_DRAW_STATE_VI
,
3188 .enable_mask
= ENABLE_DRAW
,
3189 .ib
= pipeline
->vi
.state_ib
,
3191 draw_state_groups
[draw_state_group_count
++] =
3192 (struct tu_draw_state_group
) {
3193 .id
= TU_DRAW_STATE_VI_BINNING
,
3194 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
3195 .ib
= pipeline
->vi
.binning_state_ib
,
3197 draw_state_groups
[draw_state_group_count
++] =
3198 (struct tu_draw_state_group
) {
3199 .id
= TU_DRAW_STATE_VP
,
3200 .enable_mask
= ENABLE_ALL
,
3201 .ib
= pipeline
->vp
.state_ib
,
3203 draw_state_groups
[draw_state_group_count
++] =
3204 (struct tu_draw_state_group
) {
3205 .id
= TU_DRAW_STATE_RAST
,
3206 .enable_mask
= ENABLE_ALL
,
3207 .ib
= pipeline
->rast
.state_ib
,
3209 draw_state_groups
[draw_state_group_count
++] =
3210 (struct tu_draw_state_group
) {
3211 .id
= TU_DRAW_STATE_DS
,
3212 .enable_mask
= ENABLE_ALL
,
3213 .ib
= pipeline
->ds
.state_ib
,
3215 draw_state_groups
[draw_state_group_count
++] =
3216 (struct tu_draw_state_group
) {
3217 .id
= TU_DRAW_STATE_BLEND
,
3218 .enable_mask
= ENABLE_ALL
,
3219 .ib
= pipeline
->blend
.state_ib
,
3223 if (cmd
->state
.dirty
&
3224 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
3225 draw_state_groups
[draw_state_group_count
++] =
3226 (struct tu_draw_state_group
) {
3227 .id
= TU_DRAW_STATE_VS_CONST
,
3228 .enable_mask
= ENABLE_ALL
,
3229 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
3231 draw_state_groups
[draw_state_group_count
++] =
3232 (struct tu_draw_state_group
) {
3233 .id
= TU_DRAW_STATE_FS_CONST
,
3234 .enable_mask
= ENABLE_DRAW
,
3235 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3239 if (cmd
->state
.dirty
&
3240 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
)) {
3241 bool needs_border
= false;
3242 struct tu_cs_entry vs_tex
, fs_tex
, fs_ibo
;
3244 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3245 MESA_SHADER_VERTEX
, &vs_tex
, &needs_border
);
3246 if (result
!= VK_SUCCESS
)
3249 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3250 MESA_SHADER_FRAGMENT
, &fs_tex
, &needs_border
);
3251 if (result
!= VK_SUCCESS
)
3254 result
= tu6_emit_ibo(cmd
, pipeline
, descriptors_state
,
3255 MESA_SHADER_FRAGMENT
, &fs_ibo
);
3256 if (result
!= VK_SUCCESS
)
3259 draw_state_groups
[draw_state_group_count
++] =
3260 (struct tu_draw_state_group
) {
3261 .id
= TU_DRAW_STATE_VS_TEX
,
3262 .enable_mask
= ENABLE_ALL
,
3265 draw_state_groups
[draw_state_group_count
++] =
3266 (struct tu_draw_state_group
) {
3267 .id
= TU_DRAW_STATE_FS_TEX
,
3268 .enable_mask
= ENABLE_DRAW
,
3271 draw_state_groups
[draw_state_group_count
++] =
3272 (struct tu_draw_state_group
) {
3273 .id
= TU_DRAW_STATE_FS_IBO
,
3274 .enable_mask
= ENABLE_DRAW
,
3279 result
= tu6_emit_border_color(cmd
, cs
);
3280 if (result
!= VK_SUCCESS
)
3285 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3286 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3287 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3288 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3289 uint32_t cp_set_draw_state
=
3290 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3291 group
->enable_mask
|
3292 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3294 if (group
->ib
.size
) {
3295 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3297 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3301 tu_cs_emit(cs
, cp_set_draw_state
);
3302 tu_cs_emit_qw(cs
, iova
);
3305 tu_cs_sanity_check(cs
);
3308 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3309 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
3310 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
3312 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3315 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3317 for_each_bit(i
, descriptors_state
->valid
) {
3318 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3319 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3320 if (set
->descriptors
[j
]) {
3321 tu_bo_list_add(&cmd
->bo_list
, set
->descriptors
[j
],
3322 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3327 /* Fragment shader state overwrites compute shader state, so flag the
3328 * compute pipeline for re-emit.
3330 cmd
->state
.dirty
= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3335 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3337 const struct tu_draw_info
*draw
)
3340 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3342 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_INDEX_OFFSET
, 2);
3343 tu_cs_emit(cs
, draw
->vertex_offset
);
3344 tu_cs_emit(cs
, draw
->first_instance
);
3346 /* TODO hw binning */
3347 if (draw
->indexed
) {
3348 const enum a4xx_index_size index_size
=
3349 tu6_index_size(cmd
->state
.index_type
);
3350 const uint32_t index_bytes
=
3351 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3352 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3353 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3354 index_bytes
* draw
->first_index
;
3355 const uint32_t size
= index_bytes
* draw
->count
;
3357 const uint32_t cp_draw_indx
=
3358 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3359 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3360 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3361 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) | 0x2000;
3363 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3364 tu_cs_emit(cs
, cp_draw_indx
);
3365 tu_cs_emit(cs
, draw
->instance_count
);
3366 tu_cs_emit(cs
, draw
->count
);
3367 tu_cs_emit(cs
, 0x0); /* XXX */
3368 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3369 tu_cs_emit(cs
, size
);
3371 const uint32_t cp_draw_indx
=
3372 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3373 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3374 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) | 0x2000;
3376 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3377 tu_cs_emit(cs
, cp_draw_indx
);
3378 tu_cs_emit(cs
, draw
->instance_count
);
3379 tu_cs_emit(cs
, draw
->count
);
3384 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3386 struct tu_cs
*cs
= &cmd
->draw_cs
;
3389 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3390 if (result
!= VK_SUCCESS
) {
3391 cmd
->record_result
= result
;
3395 result
= tu_cs_reserve_space(cmd
->device
, cs
, 32);
3396 if (result
!= VK_SUCCESS
) {
3397 cmd
->record_result
= result
;
3401 if (draw
->indirect
) {
3402 tu_finishme("indirect draw");
3406 /* TODO tu6_emit_marker should pick different regs depending on cs */
3408 tu6_emit_marker(cmd
, cs
);
3409 tu6_emit_draw_direct(cmd
, cs
, draw
);
3410 tu6_emit_marker(cmd
, cs
);
3412 cmd
->wait_for_idle
= true;
3414 tu_cs_sanity_check(cs
);
3418 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3419 uint32_t vertexCount
,
3420 uint32_t instanceCount
,
3421 uint32_t firstVertex
,
3422 uint32_t firstInstance
)
3424 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3425 struct tu_draw_info info
= {};
3427 info
.count
= vertexCount
;
3428 info
.instance_count
= instanceCount
;
3429 info
.first_instance
= firstInstance
;
3430 info
.vertex_offset
= firstVertex
;
3432 tu_draw(cmd_buffer
, &info
);
3436 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3437 uint32_t indexCount
,
3438 uint32_t instanceCount
,
3439 uint32_t firstIndex
,
3440 int32_t vertexOffset
,
3441 uint32_t firstInstance
)
3443 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3444 struct tu_draw_info info
= {};
3446 info
.indexed
= true;
3447 info
.count
= indexCount
;
3448 info
.instance_count
= instanceCount
;
3449 info
.first_index
= firstIndex
;
3450 info
.vertex_offset
= vertexOffset
;
3451 info
.first_instance
= firstInstance
;
3453 tu_draw(cmd_buffer
, &info
);
3457 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3459 VkDeviceSize offset
,
3463 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3464 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3465 struct tu_draw_info info
= {};
3467 info
.count
= drawCount
;
3468 info
.indirect
= buffer
;
3469 info
.indirect_offset
= offset
;
3470 info
.stride
= stride
;
3472 tu_draw(cmd_buffer
, &info
);
3476 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3478 VkDeviceSize offset
,
3482 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3483 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3484 struct tu_draw_info info
= {};
3486 info
.indexed
= true;
3487 info
.count
= drawCount
;
3488 info
.indirect
= buffer
;
3489 info
.indirect_offset
= offset
;
3490 info
.stride
= stride
;
3492 tu_draw(cmd_buffer
, &info
);
3495 struct tu_dispatch_info
3498 * Determine the layout of the grid (in block units) to be used.
3503 * A starting offset for the grid. If unaligned is set, the offset
3504 * must still be aligned.
3506 uint32_t offsets
[3];
3508 * Whether it's an unaligned compute dispatch.
3513 * Indirect compute parameters resource.
3515 struct tu_buffer
*indirect
;
3516 uint64_t indirect_offset
;
3520 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3521 const struct tu_dispatch_info
*info
)
3523 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3524 const struct tu_program_descriptor_linkage
*link
=
3525 &pipeline
->program
.link
[type
];
3526 const struct ir3_const_state
*const_state
= &link
->const_state
;
3527 uint32_t offset_dwords
= const_state
->offsets
.driver_param
;
3529 if (link
->constlen
<= offset_dwords
)
3532 if (!info
->indirect
) {
3533 uint32_t driver_params
[] = {
3537 pipeline
->compute
.local_size
[0],
3538 pipeline
->compute
.local_size
[1],
3539 pipeline
->compute
.local_size
[2],
3541 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3542 link
->constlen
- offset_dwords
);
3543 uint32_t align_size
= align(num_consts
, 4);
3545 /* push constants */
3546 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + align_size
);
3547 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset_dwords
/ 4) |
3548 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3549 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3550 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3551 CP_LOAD_STATE6_0_NUM_UNIT(align_size
/ 4));
3555 for (i
= 0; i
< num_consts
; i
++)
3556 tu_cs_emit(cs
, driver_params
[i
]);
3557 for (; i
< align_size
; i
++)
3560 tu_finishme("Indirect driver params");
3565 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3566 const struct tu_dispatch_info
*info
)
3568 struct tu_cs
*cs
= &cmd
->cs
;
3569 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3570 struct tu_descriptor_state
*descriptors_state
=
3571 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3573 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
3574 if (result
!= VK_SUCCESS
) {
3575 cmd
->record_result
= result
;
3579 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3580 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3582 struct tu_cs_entry ib
;
3584 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3586 tu_cs_emit_ib(cs
, &ib
);
3588 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3591 result
= tu6_emit_textures(cmd
, pipeline
, descriptors_state
,
3592 MESA_SHADER_COMPUTE
, &ib
, &needs_border
);
3593 if (result
!= VK_SUCCESS
) {
3594 cmd
->record_result
= result
;
3599 tu_cs_emit_ib(cs
, &ib
);
3602 tu_finishme("compute border color");
3604 result
= tu6_emit_ibo(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
, &ib
);
3605 if (result
!= VK_SUCCESS
) {
3606 cmd
->record_result
= result
;
3611 tu_cs_emit_ib(cs
, &ib
);
3614 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3616 for_each_bit(i
, descriptors_state
->valid
) {
3617 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3618 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3619 if (set
->descriptors
[j
]) {
3620 tu_bo_list_add(&cmd
->bo_list
, set
->descriptors
[j
],
3621 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3626 /* Compute shader state overwrites fragment shader state, so we flag the
3627 * graphics pipeline for re-emit.
3629 cmd
->state
.dirty
= TU_CMD_DIRTY_PIPELINE
;
3631 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3632 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x8));
3634 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3635 const uint32_t *num_groups
= info
->blocks
;
3636 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_NDRANGE_0
, 7);
3638 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3639 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size
[0] - 1) |
3640 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size
[1] - 1) |
3641 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size
[2] - 1));
3642 tu_cs_emit(cs
, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size
[0] * num_groups
[0]));
3643 tu_cs_emit(cs
, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3644 tu_cs_emit(cs
, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size
[1] * num_groups
[1]));
3645 tu_cs_emit(cs
, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3646 tu_cs_emit(cs
, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size
[2] * num_groups
[2]));
3647 tu_cs_emit(cs
, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3649 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X
, 3);
3650 tu_cs_emit(cs
, 1); /* HLSQ_CS_KERNEL_GROUP_X */
3651 tu_cs_emit(cs
, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
3652 tu_cs_emit(cs
, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
3654 if (info
->indirect
) {
3655 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3657 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3658 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3660 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3661 tu_cs_emit(cs
, 0x00000000);
3662 tu_cs_emit_qw(cs
, iova
);
3664 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3665 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3666 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3668 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3669 tu_cs_emit(cs
, 0x00000000);
3670 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3671 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3672 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3677 tu6_emit_cache_flush(cmd
, cs
);
3681 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3689 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3690 struct tu_dispatch_info info
= {};
3696 info
.offsets
[0] = base_x
;
3697 info
.offsets
[1] = base_y
;
3698 info
.offsets
[2] = base_z
;
3699 tu_dispatch(cmd_buffer
, &info
);
3703 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3708 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3712 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3714 VkDeviceSize offset
)
3716 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3717 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3718 struct tu_dispatch_info info
= {};
3720 info
.indirect
= buffer
;
3721 info
.indirect_offset
= offset
;
3723 tu_dispatch(cmd_buffer
, &info
);
3727 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3729 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3731 tu_cs_end(&cmd_buffer
->draw_cs
);
3733 tu_cmd_render_tiles(cmd_buffer
);
3735 /* discard draw_cs entries now that the tiles are rendered */
3736 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3737 tu_cs_begin(&cmd_buffer
->draw_cs
);
3739 cmd_buffer
->state
.pass
= NULL
;
3740 cmd_buffer
->state
.subpass
= NULL
;
3741 cmd_buffer
->state
.framebuffer
= NULL
;
3745 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer
,
3746 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3748 tu_CmdEndRenderPass(commandBuffer
);
3751 struct tu_barrier_info
3753 uint32_t eventCount
;
3754 const VkEvent
*pEvents
;
3755 VkPipelineStageFlags srcStageMask
;
3759 tu_barrier(struct tu_cmd_buffer
*cmd_buffer
,
3760 uint32_t memoryBarrierCount
,
3761 const VkMemoryBarrier
*pMemoryBarriers
,
3762 uint32_t bufferMemoryBarrierCount
,
3763 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3764 uint32_t imageMemoryBarrierCount
,
3765 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3766 const struct tu_barrier_info
*info
)
3771 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3772 VkPipelineStageFlags srcStageMask
,
3773 VkPipelineStageFlags destStageMask
,
3775 uint32_t memoryBarrierCount
,
3776 const VkMemoryBarrier
*pMemoryBarriers
,
3777 uint32_t bufferMemoryBarrierCount
,
3778 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3779 uint32_t imageMemoryBarrierCount
,
3780 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3782 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3783 struct tu_barrier_info info
;
3785 info
.eventCount
= 0;
3786 info
.pEvents
= NULL
;
3787 info
.srcStageMask
= srcStageMask
;
3789 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3790 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3791 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3795 write_event(struct tu_cmd_buffer
*cmd_buffer
,
3796 struct tu_event
*event
,
3797 VkPipelineStageFlags stageMask
,
3803 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3805 VkPipelineStageFlags stageMask
)
3807 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3808 TU_FROM_HANDLE(tu_event
, event
, _event
);
3810 write_event(cmd_buffer
, event
, stageMask
, 1);
3814 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3816 VkPipelineStageFlags stageMask
)
3818 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3819 TU_FROM_HANDLE(tu_event
, event
, _event
);
3821 write_event(cmd_buffer
, event
, stageMask
, 0);
3825 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3826 uint32_t eventCount
,
3827 const VkEvent
*pEvents
,
3828 VkPipelineStageFlags srcStageMask
,
3829 VkPipelineStageFlags dstStageMask
,
3830 uint32_t memoryBarrierCount
,
3831 const VkMemoryBarrier
*pMemoryBarriers
,
3832 uint32_t bufferMemoryBarrierCount
,
3833 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3834 uint32_t imageMemoryBarrierCount
,
3835 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3837 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3838 struct tu_barrier_info info
;
3840 info
.eventCount
= eventCount
;
3841 info
.pEvents
= pEvents
;
3842 info
.srcStageMask
= 0;
3844 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3845 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3846 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3850 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)