projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
turnip: fix integer render targets
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37 #include "tu_blit.h"
38
39 void
40 tu_bo_list_init(struct tu_bo_list *list)
41 {
42 list->count = list->capacity = 0;
43 list->bo_infos = NULL;
44 }
45
46 void
47 tu_bo_list_destroy(struct tu_bo_list *list)
48 {
49 free(list->bo_infos);
50 }
51
52 void
53 tu_bo_list_reset(struct tu_bo_list *list)
54 {
55 list->count = 0;
56 }
57
58 /**
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 */
61 static uint32_t
62 tu_bo_list_add_info(struct tu_bo_list *list,
63 const struct drm_msm_gem_submit_bo *bo_info)
64 {
65 for (uint32_t i = 0; i < list->count; ++i) {
66 if (list->bo_infos[i].handle == bo_info->handle) {
67 assert(list->bo_infos[i].presumed == bo_info->presumed);
68 list->bo_infos[i].flags |= bo_info->flags;
69 return i;
70 }
71 }
72
73 /* grow list->bo_infos if needed */
74 if (list->count == list->capacity) {
75 uint32_t new_capacity = MAX2(2 * list->count, 16);
76 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
77 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
78 if (!new_bo_infos)
79 return TU_BO_LIST_FAILED;
80 list->bo_infos = new_bo_infos;
81 list->capacity = new_capacity;
82 }
83
84 list->bo_infos[list->count] = *bo_info;
85 return list->count++;
86 }
87
88 uint32_t
89 tu_bo_list_add(struct tu_bo_list *list,
90 const struct tu_bo *bo,
91 uint32_t flags)
92 {
93 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
94 .flags = flags,
95 .handle = bo->gem_handle,
96 .presumed = bo->iova,
97 });
98 }
99
100 VkResult
101 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
102 {
103 for (uint32_t i = 0; i < other->count; i++) {
104 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
105 return VK_ERROR_OUT_OF_HOST_MEMORY;
106 }
107
108 return VK_SUCCESS;
109 }
110
111 static VkResult
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
113 const struct tu_device *dev)
114 {
115 const uint32_t gmem_size = dev->physical_device->gmem_size;
116 uint32_t offset = 0;
117
118 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
119 /* 16KB-aligned */
120 offset = align(offset, 0x4000);
121
122 tiling->gmem_offsets[i] = offset;
123 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
124 tiling->buffer_cpp[i];
125 }
126
127 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
128 }
129
130 static void
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
132 const struct tu_device *dev)
133 {
134 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
135 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
136 const uint32_t max_tile_width = 1024; /* A6xx */
137
138 tiling->tile0.offset = (VkOffset2D) {
139 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
140 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
141 };
142
143 const uint32_t ra_width =
144 tiling->render_area.extent.width +
145 (tiling->render_area.offset.x - tiling->tile0.offset.x);
146 const uint32_t ra_height =
147 tiling->render_area.extent.height +
148 (tiling->render_area.offset.y - tiling->tile0.offset.y);
149
150 /* start from 1 tile */
151 tiling->tile_count = (VkExtent2D) {
152 .width = 1,
153 .height = 1,
154 };
155 tiling->tile0.extent = (VkExtent2D) {
156 .width = align(ra_width, tile_align_w),
157 .height = align(ra_height, tile_align_h),
158 };
159
160 /* do not exceed max tile width */
161 while (tiling->tile0.extent.width > max_tile_width) {
162 tiling->tile_count.width++;
163 tiling->tile0.extent.width =
164 align(ra_width / tiling->tile_count.width, tile_align_w);
165 }
166
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
169 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
170 tiling->tile_count.width++;
171 tiling->tile0.extent.width =
172 align(ra_width / tiling->tile_count.width, tile_align_w);
173 } else {
174 tiling->tile_count.height++;
175 tiling->tile0.extent.height =
176 align(ra_height / tiling->tile_count.height, tile_align_h);
177 }
178 }
179 }
180
181 static void
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
183 const struct tu_device *dev)
184 {
185 const uint32_t max_pipe_count = 32; /* A6xx */
186
187 /* start from 1 tile per pipe */
188 tiling->pipe0 = (VkExtent2D) {
189 .width = 1,
190 .height = 1,
191 };
192 tiling->pipe_count = tiling->tile_count;
193
194 /* do not exceed max pipe count vertically */
195 while (tiling->pipe_count.height > max_pipe_count) {
196 tiling->pipe0.height += 2;
197 tiling->pipe_count.height =
198 (tiling->tile_count.height + tiling->pipe0.height - 1) /
199 tiling->pipe0.height;
200 }
201
202 /* do not exceed max pipe count */
203 while (tiling->pipe_count.width * tiling->pipe_count.height >
204 max_pipe_count) {
205 tiling->pipe0.width += 1;
206 tiling->pipe_count.width =
207 (tiling->tile_count.width + tiling->pipe0.width - 1) /
208 tiling->pipe0.width;
209 }
210 }
211
212 static void
213 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
214 const struct tu_device *dev)
215 {
216 const uint32_t max_pipe_count = 32; /* A6xx */
217 const uint32_t used_pipe_count =
218 tiling->pipe_count.width * tiling->pipe_count.height;
219 const VkExtent2D last_pipe = {
220 .width = tiling->tile_count.width % tiling->pipe0.width,
221 .height = tiling->tile_count.height % tiling->pipe0.height,
222 };
223
224 assert(used_pipe_count <= max_pipe_count);
225 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
226
227 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
228 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
229 const uint32_t pipe_x = tiling->pipe0.width * x;
230 const uint32_t pipe_y = tiling->pipe0.height * y;
231 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
232 ? last_pipe.width
233 : tiling->pipe0.width;
234 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
235 ? last_pipe.height
236 : tiling->pipe0.height;
237 const uint32_t n = tiling->pipe_count.width * y + x;
238
239 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
243 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
244 }
245 }
246
247 memset(tiling->pipe_config + used_pipe_count, 0,
248 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
249 }
250
251 static void
252 tu_tiling_config_update(struct tu_tiling_config *tiling,
253 const struct tu_device *dev,
254 const uint32_t *buffer_cpp,
255 uint32_t buffer_count,
256 const VkRect2D *render_area)
257 {
258 /* see if there is any real change */
259 const bool ra_changed =
260 render_area &&
261 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
262 const bool buf_changed = tiling->buffer_count != buffer_count ||
263 memcmp(tiling->buffer_cpp, buffer_cpp,
264 sizeof(*buffer_cpp) * buffer_count);
265 if (!ra_changed && !buf_changed)
266 return;
267
268 if (ra_changed)
269 tiling->render_area = *render_area;
270
271 if (buf_changed) {
272 memcpy(tiling->buffer_cpp, buffer_cpp,
273 sizeof(*buffer_cpp) * buffer_count);
274 tiling->buffer_count = buffer_count;
275 }
276
277 tu_tiling_config_update_tile_layout(tiling, dev);
278 tu_tiling_config_update_pipe_layout(tiling, dev);
279 tu_tiling_config_update_pipes(tiling, dev);
280 }
281
282 static void
283 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
284 const struct tu_device *dev,
285 uint32_t tx,
286 uint32_t ty,
287 struct tu_tile *tile)
288 {
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px = tx / tiling->pipe0.width;
291 const uint32_t py = ty / tiling->pipe0.height;
292 const uint32_t sx = tx - tiling->pipe0.width * px;
293 const uint32_t sy = ty - tiling->pipe0.height * py;
294
295 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
296 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
297 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
298
299 /* convert to 1D indices */
300 tile->pipe = tiling->pipe_count.width * py + px;
301 tile->slot = tiling->pipe0.width * sy + sx;
302
303 /* get the blit area for the tile */
304 tile->begin = (VkOffset2D) {
305 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
306 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
307 };
308 tile->end.x =
309 (tx == tiling->tile_count.width - 1)
310 ? tiling->render_area.offset.x + tiling->render_area.extent.width
311 : tile->begin.x + tiling->tile0.extent.width;
312 tile->end.y =
313 (ty == tiling->tile_count.height - 1)
314 ? tiling->render_area.offset.y + tiling->render_area.extent.height
315 : tile->begin.y + tiling->tile0.extent.height;
316 }
317
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples)
320 {
321 switch (samples) {
322 case 1:
323 return MSAA_ONE;
324 case 2:
325 return MSAA_TWO;
326 case 4:
327 return MSAA_FOUR;
328 case 8:
329 return MSAA_EIGHT;
330 default:
331 assert(!"invalid sample count");
332 return MSAA_ONE;
333 }
334 }
335
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type)
338 {
339 switch (type) {
340 case VK_INDEX_TYPE_UINT16:
341 return INDEX4_SIZE_16_BIT;
342 case VK_INDEX_TYPE_UINT32:
343 return INDEX4_SIZE_32_BIT;
344 default:
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT;
347 }
348 }
349
350 static void
351 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
352 {
353 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
354 }
355
356 void
357 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
358 struct tu_cs *cs,
359 enum vgt_event_type event,
360 bool need_seqno)
361 {
362 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
363 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
364 if (need_seqno) {
365 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
366 tu_cs_emit(cs, ++cmd->scratch_seqno);
367 }
368 }
369
370 static void
371 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
372 {
373 tu6_emit_event_write(cmd, cs, 0x31, false);
374 }
375
376 static void
377 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
378 {
379 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
380 }
381
382 static void
383 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
384 {
385 if (cmd->wait_for_idle) {
386 tu_cs_emit_wfi(cs);
387 cmd->wait_for_idle = false;
388 }
389 }
390
391 static void
392 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
393 {
394 uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
395 uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
396 uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
397 if (iview->image->ubwc_size) {
398 tu_cs_emit_qw(cs, va);
399 tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
401 } else {
402 tu_cs_emit_qw(cs, 0);
403 tu_cs_emit(cs, 0);
404 }
405 }
406
407 static void
408 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
409 {
410 const struct tu_framebuffer *fb = cmd->state.framebuffer;
411 const struct tu_subpass *subpass = cmd->state.subpass;
412 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
413
414 const uint32_t a = subpass->depth_stencil_attachment.attachment;
415 if (a == VK_ATTACHMENT_UNUSED) {
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
417 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
418 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
419 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
420 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
421 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
422 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
423
424 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
425 tu_cs_emit(cs,
426 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
429 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
430 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
431 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
432 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
433 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
436 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
437
438 return;
439 }
440
441 uint32_t gmem_index = 0;
442 for (uint32_t i = 0; i < subpass->color_count; ++i) {
443 uint32_t a = subpass->color_attachments[i].attachment;
444 if (a != VK_ATTACHMENT_UNUSED)
445 gmem_index++;
446 }
447
448 const struct tu_image_view *iview = fb->attachments[a].attachment;
449 enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
452 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
453 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
454 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layer_size));
455 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
456 tu_cs_emit(cs, tiling->gmem_offsets[gmem_index]);
457
458 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
459 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
460
461 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
462 tu6_emit_flag_buffer(cs, iview);
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
465 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
466 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
467 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
468 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
469 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
472 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
473
474 /* enable zs? */
475 }
476
477 static void
478 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
479 {
480 const struct tu_framebuffer *fb = cmd->state.framebuffer;
481 const struct tu_subpass *subpass = cmd->state.subpass;
482 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
483 unsigned char mrt_comp[MAX_RTS] = { 0 };
484 unsigned srgb_cntl = 0;
485
486 uint32_t gmem_index = 0;
487 for (uint32_t i = 0; i < subpass->color_count; ++i) {
488 uint32_t a = subpass->color_attachments[i].attachment;
489 if (a == VK_ATTACHMENT_UNUSED)
490 continue;
491
492 const struct tu_image_view *iview = fb->attachments[a].attachment;
493 const enum a6xx_tile_mode tile_mode =
494 tu6_get_image_tile_mode(iview->image, iview->base_mip);
495
496 mrt_comp[i] = 0xf;
497
498 if (vk_format_is_srgb(iview->vk_format))
499 srgb_cntl |= (1 << i);
500
501 const struct tu_native_format *format =
502 tu6_get_native_format(iview->vk_format);
503 assert(format && format->rb >= 0);
504
505 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
506 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
507 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
508 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
509 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
510 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layer_size));
511 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
512 tu_cs_emit(
513 cs, tiling->gmem_offsets[gmem_index++]); /* RB_MRT[i].BASE_GMEM */
514
515 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
516 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
517 COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
518 COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
519
520 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
521 tu6_emit_flag_buffer(cs, iview);
522 }
523
524 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
525 tu_cs_emit(cs, srgb_cntl);
526
527 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
528 tu_cs_emit(cs, srgb_cntl);
529
530 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
531 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
532 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
533 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
534 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
535 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
536 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
537 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
538 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
539
540 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
541 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
542 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
543 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
544 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
545 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
546 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
547 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
548 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
549 }
550
551 static void
552 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
553 {
554 const struct tu_subpass *subpass = cmd->state.subpass;
555 const enum a3xx_msaa_samples samples =
556 tu_msaa_samples(subpass->max_sample_count);
557
558 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
559 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
560 tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
561 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
562
563 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
564 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
565 tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
566 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
567
568 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
569 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
570 tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
571 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
572
573 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
574 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
575 }
576
577 static void
578 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
579 {
580 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
581 const uint32_t bin_w = tiling->tile0.extent.width;
582 const uint32_t bin_h = tiling->tile0.extent.height;
583
584 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
585 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
586 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
587
588 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
589 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
590 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
591
592 /* no flag for RB_BIN_CONTROL2... */
593 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
594 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
595 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
596 }
597
598 static void
599 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
600 struct tu_cs *cs,
601 bool binning)
602 {
603 uint32_t cntl = 0;
604 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
605 if (binning)
606 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
607
608 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
609 tu_cs_emit(cs, 0x2);
610 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
611 tu_cs_emit(cs, cntl);
612 }
613
614 static void
615 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
616 {
617 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
618 const uint32_t x1 = render_area->offset.x;
619 const uint32_t y1 = render_area->offset.y;
620 const uint32_t x2 = x1 + render_area->extent.width - 1;
621 const uint32_t y2 = y1 + render_area->extent.height - 1;
622
623 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
624 tu_cs_emit(cs,
625 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
626 tu_cs_emit(cs,
627 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
628 }
629
630 static void
631 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
632 struct tu_cs *cs,
633 const struct tu_image_view *iview,
634 uint32_t gmem_offset,
635 uint32_t blit_info)
636 {
637 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
638 tu_cs_emit(cs, blit_info);
639
640 const struct tu_native_format *format =
641 tu6_get_native_format(iview->vk_format);
642 assert(format && format->rb >= 0);
643
644 enum a6xx_tile_mode tile_mode =
645 tu6_get_image_tile_mode(iview->image, iview->base_mip);
646 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
647 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
648 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
649 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
650 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
651 COND(iview->image->ubwc_size, A6XX_RB_BLIT_DST_INFO_FLAGS));
652 tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
653 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
654 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layer_size));
655
656 if (iview->image->ubwc_size) {
657 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
658 tu6_emit_flag_buffer(cs, iview);
659 }
660
661 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
662 tu_cs_emit(cs, gmem_offset);
663 }
664
665 static void
666 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
667 struct tu_cs *cs,
668 const struct tu_image_view *iview,
669 uint32_t gmem_offset,
670 const VkClearValue *clear_value)
671 {
672 const struct tu_native_format *format =
673 tu6_get_native_format(iview->vk_format);
674 assert(format && format->rb >= 0);
675 /* must be WZYX; other values are ignored */
676 const enum a3xx_color_swap swap = WZYX;
677
678 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
679 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
680 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
681 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
682 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
683
684 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
685 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
686
687 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
688 tu_cs_emit(cs, gmem_offset);
689
690 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
691 tu_cs_emit(cs, 0);
692
693 /* pack clear_value into WZYX order */
694 uint32_t clear_vals[4] = { 0 };
695 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
696
697 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
698 tu_cs_emit(cs, clear_vals[0]);
699 tu_cs_emit(cs, clear_vals[1]);
700 tu_cs_emit(cs, clear_vals[2]);
701 tu_cs_emit(cs, clear_vals[3]);
702 }
703
704 static void
705 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
706 {
707 tu6_emit_marker(cmd, cs);
708 tu6_emit_event_write(cmd, cs, BLIT, false);
709 tu6_emit_marker(cmd, cs);
710 }
711
712 static void
713 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
714 struct tu_cs *cs,
715 uint32_t x1,
716 uint32_t y1,
717 uint32_t x2,
718 uint32_t y2)
719 {
720 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
721 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
722 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
723 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
724 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
725
726 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
727 tu_cs_emit(
728 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
729 tu_cs_emit(
730 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
731 }
732
733 static void
734 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
735 struct tu_cs *cs,
736 uint32_t x1,
737 uint32_t y1)
738 {
739 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
740 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
741
742 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
743 tu_cs_emit(cs,
744 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
745
746 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
747 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
748
749 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
750 tu_cs_emit(
751 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
752 }
753
754 static void
755 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
756 struct tu_cs *cs,
757 const struct tu_tile *tile)
758 {
759 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
760 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
761
762 tu6_emit_marker(cmd, cs);
763 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
764 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
765 tu6_emit_marker(cmd, cs);
766
767 const uint32_t x1 = tile->begin.x;
768 const uint32_t y1 = tile->begin.y;
769 const uint32_t x2 = tile->end.x - 1;
770 const uint32_t y2 = tile->end.y - 1;
771 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
772 tu6_emit_window_offset(cmd, cs, x1, y1);
773
774 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
775 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
776
777 if (false) {
778 /* hw binning? */
779 } else {
780 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
781 tu_cs_emit(cs, 0x1);
782
783 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
784 tu_cs_emit(cs, 0x0);
785 }
786 }
787
788 static void
789 tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
790 struct tu_cs *cs,
791 uint32_t a,
792 uint32_t gmem_index)
793 {
794 const struct tu_framebuffer *fb = cmd->state.framebuffer;
795 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
796 const struct tu_attachment_state *attachments = cmd->state.attachments;
797
798 const struct tu_image_view *iview = fb->attachments[a].attachment;
799 const struct tu_attachment_state *att = attachments + a;
800 if (att->pending_clear_aspects) {
801 tu6_emit_blit_clear(cmd, cs, iview,
802 tiling->gmem_offsets[gmem_index],
803 &att->clear_value);
804 } else {
805 tu6_emit_blit_info(cmd, cs, iview,
806 tiling->gmem_offsets[gmem_index],
807 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
808 }
809
810 tu6_emit_blit(cmd, cs);
811 }
812
813 static void
814 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
815 {
816 const struct tu_subpass *subpass = cmd->state.subpass;
817
818 tu6_emit_blit_scissor(cmd, cs);
819
820 uint32_t gmem_index = 0;
821 for (uint32_t i = 0; i < subpass->color_count; ++i) {
822 const uint32_t a = subpass->color_attachments[i].attachment;
823 if (a != VK_ATTACHMENT_UNUSED)
824 tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index++);
825 }
826
827 const uint32_t a = subpass->depth_stencil_attachment.attachment;
828 if (a != VK_ATTACHMENT_UNUSED)
829 tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index);
830 }
831
832 static void
833 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
834 {
835 const struct tu_framebuffer *fb = cmd->state.framebuffer;
836 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
837
838 if (false) {
839 /* hw binning? */
840 }
841
842 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
843 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
844 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
845 CP_SET_DRAW_STATE__0_GROUP_ID(0));
846 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
847 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
848
849 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
850 tu_cs_emit(cs, 0x0);
851
852 tu6_emit_marker(cmd, cs);
853 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
854 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
855 tu6_emit_marker(cmd, cs);
856
857 tu6_emit_blit_scissor(cmd, cs);
858
859 uint32_t gmem_index = 0;
860 for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
861 uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
862 if (a == VK_ATTACHMENT_UNUSED)
863 continue;
864
865 const struct tu_image_view *iview = fb->attachments[a].attachment;
866 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index++],
867 0);
868 tu6_emit_blit(cmd, cs);
869 }
870
871 const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
872 if (a != VK_ATTACHMENT_UNUSED) {
873 const struct tu_image_view *iview = fb->attachments[a].attachment;
874 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index],
875 0);
876 tu6_emit_blit(cmd, cs);
877 }
878 }
879
880 static void
881 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
882 {
883 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
884 tu_cs_emit(cs, restart_index);
885 }
886
887 static void
888 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
889 {
890 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
891 if (result != VK_SUCCESS) {
892 cmd->record_result = result;
893 return;
894 }
895
896 tu6_emit_cache_flush(cmd, cs);
897
898 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
899
900 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
901 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
902 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
903 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
904 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
905 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
906 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
907 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
908 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
909
910 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
911 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
912 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
913 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
914 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
915 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
916 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
917 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
918 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
919 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
920 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
921 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
922 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
923 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
924
925 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
926
927 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
928 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
930
931 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
932 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
939 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
940 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
941 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
942 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
943
944 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
945 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
946
947 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
948 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
949
950 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
951 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
952
953 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
954 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
955 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
956
957 tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
958 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
959
960 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
961
962 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
963
964 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
965 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
966 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
967 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
968 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
969 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
970 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
971 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
972 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
973 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
974 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
975 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
976 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
977 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
978 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
979 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
980 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
981 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
982 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
983 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
984 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
985
986 tu6_emit_marker(cmd, cs);
987
988 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
989
990 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
991
992 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
993
994 /* we don't use this yet.. probably best to disable.. */
995 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
996 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
997 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
998 CP_SET_DRAW_STATE__0_GROUP_ID(0));
999 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1000 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1001
1002 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1003 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1004 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1005 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1008 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1009 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1010
1011 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1012 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1013
1014 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1015 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1016
1017 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1018 tu_cs_emit(cs, 0x00000000);
1019 tu_cs_emit(cs, 0x00000000);
1020 tu_cs_emit(cs, 0x00000000);
1021
1022 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1023 tu_cs_emit(cs, 0x00000000);
1024 tu_cs_emit(cs, 0x00000000);
1025 tu_cs_emit(cs, 0x00000000);
1026 tu_cs_emit(cs, 0x00000000);
1027 tu_cs_emit(cs, 0x00000000);
1028 tu_cs_emit(cs, 0x00000000);
1029
1030 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1031 tu_cs_emit(cs, 0x00000000);
1032 tu_cs_emit(cs, 0x00000000);
1033 tu_cs_emit(cs, 0x00000000);
1034 tu_cs_emit(cs, 0x00000000);
1035 tu_cs_emit(cs, 0x00000000);
1036 tu_cs_emit(cs, 0x00000000);
1037
1038 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1039 tu_cs_emit(cs, 0x00000000);
1040 tu_cs_emit(cs, 0x00000000);
1041 tu_cs_emit(cs, 0x00000000);
1042
1043 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1044 tu_cs_emit(cs, 0x00000000);
1045
1046 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1047 tu_cs_emit(cs, 0x00000000);
1048
1049 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1050 tu_cs_emit(cs, 0x00000000);
1051
1052 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1053 tu_cs_emit(cs, 0x00000000);
1054
1055 tu_cs_sanity_check(cs);
1056 }
1057
1058 static void
1059 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1060 {
1061 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1062 if (result != VK_SUCCESS) {
1063 cmd->record_result = result;
1064 return;
1065 }
1066
1067 tu6_emit_lrz_flush(cmd, cs);
1068
1069 /* lrz clear? */
1070
1071 tu6_emit_cache_flush(cmd, cs);
1072
1073 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1074 tu_cs_emit(cs, 0x0);
1075
1076 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1077 tu6_emit_wfi(cmd, cs);
1078 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1079 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1080
1081 tu6_emit_zs(cmd, cs);
1082 tu6_emit_mrt(cmd, cs);
1083 tu6_emit_msaa(cmd, cs);
1084
1085 if (false) {
1086 /* hw binning? */
1087 } else {
1088 tu6_emit_bin_size(cmd, cs, 0x6000000);
1089 /* no draws */
1090 }
1091
1092 tu6_emit_render_cntl(cmd, cs, false);
1093
1094 tu_cs_sanity_check(cs);
1095 }
1096
1097 static void
1098 tu6_render_tile(struct tu_cmd_buffer *cmd,
1099 struct tu_cs *cs,
1100 const struct tu_tile *tile)
1101 {
1102 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1103 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1104 if (result != VK_SUCCESS) {
1105 cmd->record_result = result;
1106 return;
1107 }
1108
1109 tu6_emit_tile_select(cmd, cs, tile);
1110 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1111
1112 tu_cs_emit_call(cs, &cmd->draw_cs);
1113 cmd->wait_for_idle = true;
1114
1115 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1116
1117 tu_cs_sanity_check(cs);
1118 }
1119
1120 static void
1121 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1122 {
1123 const struct tu_subpass *subpass = cmd->state.subpass;
1124 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1125
1126 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1127 if (result != VK_SUCCESS) {
1128 cmd->record_result = result;
1129 return;
1130 }
1131
1132 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1133 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1134
1135 tu6_emit_lrz_flush(cmd, cs);
1136
1137 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1138
1139 if (subpass->has_resolve) {
1140 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1141 struct tu_subpass_attachment src_att = subpass->color_attachments[i];
1142 struct tu_subpass_attachment dst_att = subpass->resolve_attachments[i];
1143
1144 if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
1145 continue;
1146
1147 struct tu_image *src_img = fb->attachments[src_att.attachment].attachment->image;
1148 struct tu_image *dst_img = fb->attachments[dst_att.attachment].attachment->image;
1149
1150 assert(src_img->extent.width == dst_img->extent.width);
1151 assert(src_img->extent.height == dst_img->extent.height);
1152
1153 tu_bo_list_add(&cmd->bo_list, src_img->bo, MSM_SUBMIT_BO_READ);
1154 tu_bo_list_add(&cmd->bo_list, dst_img->bo, MSM_SUBMIT_BO_WRITE);
1155
1156 tu_blit(cmd, &(struct tu_blit) {
1157 .dst = tu_blit_surf_whole(dst_img, 0, 0),
1158 .src = tu_blit_surf_whole(src_img, 0, 0),
1159 .layers = 1,
1160 });
1161 }
1162 }
1163
1164 tu_cs_sanity_check(cs);
1165 }
1166
1167 static void
1168 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1169 {
1170 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1171
1172 tu6_render_begin(cmd, &cmd->cs);
1173
1174 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1175 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1176 struct tu_tile tile;
1177 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1178 tu6_render_tile(cmd, &cmd->cs, &tile);
1179 }
1180 }
1181
1182 tu6_render_end(cmd, &cmd->cs);
1183 }
1184
1185 static void
1186 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1187 {
1188 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1189 const struct tu_subpass *subpass = cmd->state.subpass;
1190 struct tu_attachment_state *attachments = cmd->state.attachments;
1191 struct tu_cs sub_cs;
1192
1193 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1194 tile_load_space, &sub_cs);
1195 if (result != VK_SUCCESS) {
1196 cmd->record_result = result;
1197 return;
1198 }
1199
1200 /* emit to tile-load sub_cs */
1201 tu6_emit_tile_load(cmd, &sub_cs);
1202
1203 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1204
1205 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1206 const uint32_t a = subpass->color_attachments[i].attachment;
1207 if (a != VK_ATTACHMENT_UNUSED)
1208 attachments[a].pending_clear_aspects = 0;
1209 }
1210 }
1211
1212 static void
1213 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1214 {
1215 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1216 struct tu_cs sub_cs;
1217
1218 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1219 tile_store_space, &sub_cs);
1220 if (result != VK_SUCCESS) {
1221 cmd->record_result = result;
1222 return;
1223 }
1224
1225 /* emit to tile-store sub_cs */
1226 tu6_emit_tile_store(cmd, &sub_cs);
1227
1228 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1229 }
1230
1231 static void
1232 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1233 const VkRect2D *render_area)
1234 {
1235 const struct tu_device *dev = cmd->device;
1236 const struct tu_render_pass *pass = cmd->state.pass;
1237 const struct tu_subpass *subpass = cmd->state.subpass;
1238 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1239
1240 uint32_t buffer_cpp[MAX_RTS + 2];
1241 uint32_t buffer_count = 0;
1242
1243 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1244 const uint32_t a = subpass->color_attachments[i].attachment;
1245 if (a == VK_ATTACHMENT_UNUSED)
1246 continue;
1247
1248 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1249 buffer_cpp[buffer_count++] =
1250 vk_format_get_blocksize(att->format) * att->samples;
1251 }
1252
1253 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1254 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1255 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1256
1257 /* TODO */
1258 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1259
1260 buffer_cpp[buffer_count++] =
1261 vk_format_get_blocksize(att->format) * att->samples;
1262 }
1263
1264 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1265 render_area);
1266 }
1267
1268 const struct tu_dynamic_state default_dynamic_state = {
1269 .viewport =
1270 {
1271 .count = 0,
1272 },
1273 .scissor =
1274 {
1275 .count = 0,
1276 },
1277 .line_width = 1.0f,
1278 .depth_bias =
1279 {
1280 .bias = 0.0f,
1281 .clamp = 0.0f,
1282 .slope = 0.0f,
1283 },
1284 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1285 .depth_bounds =
1286 {
1287 .min = 0.0f,
1288 .max = 1.0f,
1289 },
1290 .stencil_compare_mask =
1291 {
1292 .front = ~0u,
1293 .back = ~0u,
1294 },
1295 .stencil_write_mask =
1296 {
1297 .front = ~0u,
1298 .back = ~0u,
1299 },
1300 .stencil_reference =
1301 {
1302 .front = 0u,
1303 .back = 0u,
1304 },
1305 };
1306
1307 static void UNUSED /* FINISHME */
1308 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1309 const struct tu_dynamic_state *src)
1310 {
1311 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1312 uint32_t copy_mask = src->mask;
1313 uint32_t dest_mask = 0;
1314
1315 tu_use_args(cmd_buffer); /* FINISHME */
1316
1317 /* Make sure to copy the number of viewports/scissors because they can
1318 * only be specified at pipeline creation time.
1319 */
1320 dest->viewport.count = src->viewport.count;
1321 dest->scissor.count = src->scissor.count;
1322 dest->discard_rectangle.count = src->discard_rectangle.count;
1323
1324 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1325 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1326 src->viewport.count * sizeof(VkViewport))) {
1327 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1328 src->viewport.count);
1329 dest_mask |= TU_DYNAMIC_VIEWPORT;
1330 }
1331 }
1332
1333 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1334 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1335 src->scissor.count * sizeof(VkRect2D))) {
1336 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1337 src->scissor.count);
1338 dest_mask |= TU_DYNAMIC_SCISSOR;
1339 }
1340 }
1341
1342 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1343 if (dest->line_width != src->line_width) {
1344 dest->line_width = src->line_width;
1345 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1346 }
1347 }
1348
1349 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1350 if (memcmp(&dest->depth_bias, &src->depth_bias,
1351 sizeof(src->depth_bias))) {
1352 dest->depth_bias = src->depth_bias;
1353 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1354 }
1355 }
1356
1357 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1358 if (memcmp(&dest->blend_constants, &src->blend_constants,
1359 sizeof(src->blend_constants))) {
1360 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1361 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1362 }
1363 }
1364
1365 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1366 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1367 sizeof(src->depth_bounds))) {
1368 dest->depth_bounds = src->depth_bounds;
1369 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1370 }
1371 }
1372
1373 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1374 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1375 sizeof(src->stencil_compare_mask))) {
1376 dest->stencil_compare_mask = src->stencil_compare_mask;
1377 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1378 }
1379 }
1380
1381 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1382 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1383 sizeof(src->stencil_write_mask))) {
1384 dest->stencil_write_mask = src->stencil_write_mask;
1385 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1386 }
1387 }
1388
1389 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1390 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1391 sizeof(src->stencil_reference))) {
1392 dest->stencil_reference = src->stencil_reference;
1393 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1394 }
1395 }
1396
1397 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1398 if (memcmp(&dest->discard_rectangle.rectangles,
1399 &src->discard_rectangle.rectangles,
1400 src->discard_rectangle.count * sizeof(VkRect2D))) {
1401 typed_memcpy(dest->discard_rectangle.rectangles,
1402 src->discard_rectangle.rectangles,
1403 src->discard_rectangle.count);
1404 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1405 }
1406 }
1407 }
1408
1409 static VkResult
1410 tu_create_cmd_buffer(struct tu_device *device,
1411 struct tu_cmd_pool *pool,
1412 VkCommandBufferLevel level,
1413 VkCommandBuffer *pCommandBuffer)
1414 {
1415 struct tu_cmd_buffer *cmd_buffer;
1416 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1417 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1418 if (cmd_buffer == NULL)
1419 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1420
1421 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1422 cmd_buffer->device = device;
1423 cmd_buffer->pool = pool;
1424 cmd_buffer->level = level;
1425
1426 if (pool) {
1427 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1428 cmd_buffer->queue_family_index = pool->queue_family_index;
1429
1430 } else {
1431 /* Init the pool_link so we can safely call list_del when we destroy
1432 * the command buffer
1433 */
1434 list_inithead(&cmd_buffer->pool_link);
1435 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1436 }
1437
1438 tu_bo_list_init(&cmd_buffer->bo_list);
1439 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1440 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1441 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1442 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1443
1444 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1445
1446 list_inithead(&cmd_buffer->upload.list);
1447
1448 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1449 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1450
1451 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1452 if (result != VK_SUCCESS)
1453 return result;
1454
1455 return VK_SUCCESS;
1456 }
1457
1458 static void
1459 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1460 {
1461 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1462
1463 list_del(&cmd_buffer->pool_link);
1464
1465 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1466 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1467
1468 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1469 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1470 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1471 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1472
1473 tu_bo_list_destroy(&cmd_buffer->bo_list);
1474 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1475 }
1476
1477 static VkResult
1478 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1479 {
1480 cmd_buffer->wait_for_idle = true;
1481
1482 cmd_buffer->record_result = VK_SUCCESS;
1483
1484 tu_bo_list_reset(&cmd_buffer->bo_list);
1485 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1486 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1487 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1488 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1489
1490 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1491 cmd_buffer->descriptors[i].dirty = 0;
1492 cmd_buffer->descriptors[i].valid = 0;
1493 cmd_buffer->descriptors[i].push_dirty = false;
1494 }
1495
1496 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1497
1498 return cmd_buffer->record_result;
1499 }
1500
1501 static VkResult
1502 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1503 const VkRenderPassBeginInfo *info)
1504 {
1505 struct tu_cmd_state *state = &cmd_buffer->state;
1506 const struct tu_framebuffer *fb = state->framebuffer;
1507 const struct tu_render_pass *pass = state->pass;
1508
1509 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1510 const struct tu_image_view *iview = fb->attachments[i].attachment;
1511 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1512 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1513 }
1514
1515 if (pass->attachment_count == 0) {
1516 state->attachments = NULL;
1517 return VK_SUCCESS;
1518 }
1519
1520 state->attachments =
1521 vk_alloc(&cmd_buffer->pool->alloc,
1522 pass->attachment_count * sizeof(state->attachments[0]), 8,
1523 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1524 if (state->attachments == NULL) {
1525 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1526 return cmd_buffer->record_result;
1527 }
1528
1529 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1530 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1531 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1532 VkImageAspectFlags clear_aspects = 0;
1533
1534 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1535 /* color attachment */
1536 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1537 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1538 }
1539 } else {
1540 /* depthstencil attachment */
1541 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1542 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1543 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1544 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1545 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1546 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1547 }
1548 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1549 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1550 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1551 }
1552 }
1553
1554 state->attachments[i].pending_clear_aspects = clear_aspects;
1555 state->attachments[i].cleared_views = 0;
1556 if (clear_aspects && info) {
1557 assert(info->clearValueCount > i);
1558 state->attachments[i].clear_value = info->pClearValues[i];
1559 }
1560
1561 state->attachments[i].current_layout = att->initial_layout;
1562 }
1563
1564 return VK_SUCCESS;
1565 }
1566
1567 VkResult
1568 tu_AllocateCommandBuffers(VkDevice _device,
1569 const VkCommandBufferAllocateInfo *pAllocateInfo,
1570 VkCommandBuffer *pCommandBuffers)
1571 {
1572 TU_FROM_HANDLE(tu_device, device, _device);
1573 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1574
1575 VkResult result = VK_SUCCESS;
1576 uint32_t i;
1577
1578 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1579
1580 if (!list_is_empty(&pool->free_cmd_buffers)) {
1581 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1582 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1583
1584 list_del(&cmd_buffer->pool_link);
1585 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1586
1587 result = tu_reset_cmd_buffer(cmd_buffer);
1588 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1589 cmd_buffer->level = pAllocateInfo->level;
1590
1591 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1592 } else {
1593 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1594 &pCommandBuffers[i]);
1595 }
1596 if (result != VK_SUCCESS)
1597 break;
1598 }
1599
1600 if (result != VK_SUCCESS) {
1601 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1602 pCommandBuffers);
1603
1604 /* From the Vulkan 1.0.66 spec:
1605 *
1606 * "vkAllocateCommandBuffers can be used to create multiple
1607 * command buffers. If the creation of any of those command
1608 * buffers fails, the implementation must destroy all
1609 * successfully created command buffer objects from this
1610 * command, set all entries of the pCommandBuffers array to
1611 * NULL and return the error."
1612 */
1613 memset(pCommandBuffers, 0,
1614 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1615 }
1616
1617 return result;
1618 }
1619
1620 void
1621 tu_FreeCommandBuffers(VkDevice device,
1622 VkCommandPool commandPool,
1623 uint32_t commandBufferCount,
1624 const VkCommandBuffer *pCommandBuffers)
1625 {
1626 for (uint32_t i = 0; i < commandBufferCount; i++) {
1627 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1628
1629 if (cmd_buffer) {
1630 if (cmd_buffer->pool) {
1631 list_del(&cmd_buffer->pool_link);
1632 list_addtail(&cmd_buffer->pool_link,
1633 &cmd_buffer->pool->free_cmd_buffers);
1634 } else
1635 tu_cmd_buffer_destroy(cmd_buffer);
1636 }
1637 }
1638 }
1639
1640 VkResult
1641 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1642 VkCommandBufferResetFlags flags)
1643 {
1644 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1645 return tu_reset_cmd_buffer(cmd_buffer);
1646 }
1647
1648 VkResult
1649 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1650 const VkCommandBufferBeginInfo *pBeginInfo)
1651 {
1652 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1653 VkResult result = VK_SUCCESS;
1654
1655 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1656 /* If the command buffer has already been resetted with
1657 * vkResetCommandBuffer, no need to do it again.
1658 */
1659 result = tu_reset_cmd_buffer(cmd_buffer);
1660 if (result != VK_SUCCESS)
1661 return result;
1662 }
1663
1664 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1665 cmd_buffer->usage_flags = pBeginInfo->flags;
1666
1667 tu_cs_begin(&cmd_buffer->cs);
1668
1669 cmd_buffer->marker_seqno = 0;
1670 cmd_buffer->scratch_seqno = 0;
1671
1672 /* setup initial configuration into command buffer */
1673 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1674 switch (cmd_buffer->queue_family_index) {
1675 case TU_QUEUE_GENERAL:
1676 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1677 break;
1678 default:
1679 break;
1680 }
1681 }
1682
1683 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1684
1685 return VK_SUCCESS;
1686 }
1687
1688 void
1689 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1690 uint32_t firstBinding,
1691 uint32_t bindingCount,
1692 const VkBuffer *pBuffers,
1693 const VkDeviceSize *pOffsets)
1694 {
1695 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1696
1697 assert(firstBinding + bindingCount <= MAX_VBS);
1698
1699 for (uint32_t i = 0; i < bindingCount; i++) {
1700 cmd->state.vb.buffers[firstBinding + i] =
1701 tu_buffer_from_handle(pBuffers[i]);
1702 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1703 }
1704
1705 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1706 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1707 }
1708
1709 void
1710 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1711 VkBuffer buffer,
1712 VkDeviceSize offset,
1713 VkIndexType indexType)
1714 {
1715 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1716 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1717
1718 /* initialize/update the restart index */
1719 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1720 struct tu_cs *draw_cs = &cmd->draw_cs;
1721 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1722 if (result != VK_SUCCESS) {
1723 cmd->record_result = result;
1724 return;
1725 }
1726
1727 tu6_emit_restart_index(
1728 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1729
1730 tu_cs_sanity_check(draw_cs);
1731 }
1732
1733 /* track the BO */
1734 if (cmd->state.index_buffer != buf)
1735 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1736
1737 cmd->state.index_buffer = buf;
1738 cmd->state.index_offset = offset;
1739 cmd->state.index_type = indexType;
1740 }
1741
1742 void
1743 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1744 VkPipelineBindPoint pipelineBindPoint,
1745 VkPipelineLayout _layout,
1746 uint32_t firstSet,
1747 uint32_t descriptorSetCount,
1748 const VkDescriptorSet *pDescriptorSets,
1749 uint32_t dynamicOffsetCount,
1750 const uint32_t *pDynamicOffsets)
1751 {
1752 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1753 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1754 unsigned dyn_idx = 0;
1755
1756 struct tu_descriptor_state *descriptors_state =
1757 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1758
1759 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1760 unsigned idx = i + firstSet;
1761 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1762
1763 descriptors_state->sets[idx] = set;
1764 descriptors_state->valid |= (1u << idx);
1765
1766 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1767 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1768 assert(dyn_idx < dynamicOffsetCount);
1769
1770 descriptors_state->dynamic_buffers[idx] =
1771 set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
1772 }
1773 }
1774
1775 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1776 }
1777
1778 void
1779 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1780 VkPipelineLayout layout,
1781 VkShaderStageFlags stageFlags,
1782 uint32_t offset,
1783 uint32_t size,
1784 const void *pValues)
1785 {
1786 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1787 memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
1788 }
1789
1790 VkResult
1791 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1792 {
1793 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1794
1795 if (cmd_buffer->scratch_seqno) {
1796 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1797 MSM_SUBMIT_BO_WRITE);
1798 }
1799
1800 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1801 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1802 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1803 }
1804
1805 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1806 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1807 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1808 }
1809
1810 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1811 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1812 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1813 }
1814
1815 tu_cs_end(&cmd_buffer->cs);
1816
1817 assert(!cmd_buffer->state.attachments);
1818
1819 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1820
1821 return cmd_buffer->record_result;
1822 }
1823
1824 void
1825 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1826 VkPipelineBindPoint pipelineBindPoint,
1827 VkPipeline _pipeline)
1828 {
1829 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1830 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1831
1832 switch (pipelineBindPoint) {
1833 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1834 cmd->state.pipeline = pipeline;
1835 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1836 break;
1837 case VK_PIPELINE_BIND_POINT_COMPUTE:
1838 tu_finishme("binding compute pipeline");
1839 break;
1840 default:
1841 unreachable("unrecognized pipeline bind point");
1842 break;
1843 }
1844 }
1845
1846 void
1847 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1848 uint32_t firstViewport,
1849 uint32_t viewportCount,
1850 const VkViewport *pViewports)
1851 {
1852 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1853 struct tu_cs *draw_cs = &cmd->draw_cs;
1854
1855 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1856 if (result != VK_SUCCESS) {
1857 cmd->record_result = result;
1858 return;
1859 }
1860
1861 assert(firstViewport == 0 && viewportCount == 1);
1862 tu6_emit_viewport(draw_cs, pViewports);
1863
1864 tu_cs_sanity_check(draw_cs);
1865 }
1866
1867 void
1868 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1869 uint32_t firstScissor,
1870 uint32_t scissorCount,
1871 const VkRect2D *pScissors)
1872 {
1873 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1874 struct tu_cs *draw_cs = &cmd->draw_cs;
1875
1876 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1877 if (result != VK_SUCCESS) {
1878 cmd->record_result = result;
1879 return;
1880 }
1881
1882 assert(firstScissor == 0 && scissorCount == 1);
1883 tu6_emit_scissor(draw_cs, pScissors);
1884
1885 tu_cs_sanity_check(draw_cs);
1886 }
1887
1888 void
1889 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1890 {
1891 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1892
1893 cmd->state.dynamic.line_width = lineWidth;
1894
1895 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1896 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1897 }
1898
1899 void
1900 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1901 float depthBiasConstantFactor,
1902 float depthBiasClamp,
1903 float depthBiasSlopeFactor)
1904 {
1905 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1906 struct tu_cs *draw_cs = &cmd->draw_cs;
1907
1908 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1909 if (result != VK_SUCCESS) {
1910 cmd->record_result = result;
1911 return;
1912 }
1913
1914 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1915 depthBiasSlopeFactor);
1916
1917 tu_cs_sanity_check(draw_cs);
1918 }
1919
1920 void
1921 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1922 const float blendConstants[4])
1923 {
1924 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1925 struct tu_cs *draw_cs = &cmd->draw_cs;
1926
1927 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1928 if (result != VK_SUCCESS) {
1929 cmd->record_result = result;
1930 return;
1931 }
1932
1933 tu6_emit_blend_constants(draw_cs, blendConstants);
1934
1935 tu_cs_sanity_check(draw_cs);
1936 }
1937
1938 void
1939 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1940 float minDepthBounds,
1941 float maxDepthBounds)
1942 {
1943 }
1944
1945 void
1946 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1947 VkStencilFaceFlags faceMask,
1948 uint32_t compareMask)
1949 {
1950 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1951
1952 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1953 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1954 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1955 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1956
1957 /* the front/back compare masks must be updated together */
1958 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1959 }
1960
1961 void
1962 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1963 VkStencilFaceFlags faceMask,
1964 uint32_t writeMask)
1965 {
1966 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1967
1968 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1969 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1970 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1971 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1972
1973 /* the front/back write masks must be updated together */
1974 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1975 }
1976
1977 void
1978 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1979 VkStencilFaceFlags faceMask,
1980 uint32_t reference)
1981 {
1982 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1983
1984 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1985 cmd->state.dynamic.stencil_reference.front = reference;
1986 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1987 cmd->state.dynamic.stencil_reference.back = reference;
1988
1989 /* the front/back references must be updated together */
1990 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1991 }
1992
1993 void
1994 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1995 uint32_t commandBufferCount,
1996 const VkCommandBuffer *pCmdBuffers)
1997 {
1998 }
1999
2000 VkResult
2001 tu_CreateCommandPool(VkDevice _device,
2002 const VkCommandPoolCreateInfo *pCreateInfo,
2003 const VkAllocationCallbacks *pAllocator,
2004 VkCommandPool *pCmdPool)
2005 {
2006 TU_FROM_HANDLE(tu_device, device, _device);
2007 struct tu_cmd_pool *pool;
2008
2009 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2010 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2011 if (pool == NULL)
2012 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2013
2014 if (pAllocator)
2015 pool->alloc = *pAllocator;
2016 else
2017 pool->alloc = device->alloc;
2018
2019 list_inithead(&pool->cmd_buffers);
2020 list_inithead(&pool->free_cmd_buffers);
2021
2022 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2023
2024 *pCmdPool = tu_cmd_pool_to_handle(pool);
2025
2026 return VK_SUCCESS;
2027 }
2028
2029 void
2030 tu_DestroyCommandPool(VkDevice _device,
2031 VkCommandPool commandPool,
2032 const VkAllocationCallbacks *pAllocator)
2033 {
2034 TU_FROM_HANDLE(tu_device, device, _device);
2035 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2036
2037 if (!pool)
2038 return;
2039
2040 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2041 &pool->cmd_buffers, pool_link)
2042 {
2043 tu_cmd_buffer_destroy(cmd_buffer);
2044 }
2045
2046 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2047 &pool->free_cmd_buffers, pool_link)
2048 {
2049 tu_cmd_buffer_destroy(cmd_buffer);
2050 }
2051
2052 vk_free2(&device->alloc, pAllocator, pool);
2053 }
2054
2055 VkResult
2056 tu_ResetCommandPool(VkDevice device,
2057 VkCommandPool commandPool,
2058 VkCommandPoolResetFlags flags)
2059 {
2060 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2061 VkResult result;
2062
2063 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2064 pool_link)
2065 {
2066 result = tu_reset_cmd_buffer(cmd_buffer);
2067 if (result != VK_SUCCESS)
2068 return result;
2069 }
2070
2071 return VK_SUCCESS;
2072 }
2073
2074 void
2075 tu_TrimCommandPool(VkDevice device,
2076 VkCommandPool commandPool,
2077 VkCommandPoolTrimFlags flags)
2078 {
2079 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2080
2081 if (!pool)
2082 return;
2083
2084 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2085 &pool->free_cmd_buffers, pool_link)
2086 {
2087 tu_cmd_buffer_destroy(cmd_buffer);
2088 }
2089 }
2090
2091 void
2092 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2093 const VkRenderPassBeginInfo *pRenderPassBegin,
2094 VkSubpassContents contents)
2095 {
2096 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2097 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2098 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2099 VkResult result;
2100
2101 cmd_buffer->state.pass = pass;
2102 cmd_buffer->state.subpass = pass->subpasses;
2103 cmd_buffer->state.framebuffer = framebuffer;
2104
2105 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2106 if (result != VK_SUCCESS)
2107 return;
2108
2109 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2110 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2111 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2112
2113 /* draw_cs should contain entries only for this render pass */
2114 assert(!cmd_buffer->draw_cs.entry_count);
2115 tu_cs_begin(&cmd_buffer->draw_cs);
2116 }
2117
2118 void
2119 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2120 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2121 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2122 {
2123 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2124 pSubpassBeginInfo->contents);
2125 }
2126
2127 void
2128 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2129 {
2130 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2131
2132 tu_cmd_render_tiles(cmd);
2133
2134 cmd->state.subpass++;
2135
2136 tu_cmd_update_tiling_config(cmd, NULL);
2137 tu_cmd_prepare_tile_load_ib(cmd);
2138 tu_cmd_prepare_tile_store_ib(cmd);
2139 }
2140
2141 void
2142 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2143 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2144 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2145 {
2146 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2147 }
2148
2149 struct tu_draw_info
2150 {
2151 /**
2152 * Number of vertices.
2153 */
2154 uint32_t count;
2155
2156 /**
2157 * Index of the first vertex.
2158 */
2159 int32_t vertex_offset;
2160
2161 /**
2162 * First instance id.
2163 */
2164 uint32_t first_instance;
2165
2166 /**
2167 * Number of instances.
2168 */
2169 uint32_t instance_count;
2170
2171 /**
2172 * First index (indexed draws only).
2173 */
2174 uint32_t first_index;
2175
2176 /**
2177 * Whether it's an indexed draw.
2178 */
2179 bool indexed;
2180
2181 /**
2182 * Indirect draw parameters resource.
2183 */
2184 struct tu_buffer *indirect;
2185 uint64_t indirect_offset;
2186 uint32_t stride;
2187
2188 /**
2189 * Draw count parameters resource.
2190 */
2191 struct tu_buffer *count_buffer;
2192 uint64_t count_buffer_offset;
2193 };
2194
2195 enum tu_draw_state_group_id
2196 {
2197 TU_DRAW_STATE_PROGRAM,
2198 TU_DRAW_STATE_PROGRAM_BINNING,
2199 TU_DRAW_STATE_VI,
2200 TU_DRAW_STATE_VI_BINNING,
2201 TU_DRAW_STATE_VP,
2202 TU_DRAW_STATE_RAST,
2203 TU_DRAW_STATE_DS,
2204 TU_DRAW_STATE_BLEND,
2205 TU_DRAW_STATE_VS_CONST,
2206 TU_DRAW_STATE_FS_CONST,
2207 TU_DRAW_STATE_VS_TEX,
2208 TU_DRAW_STATE_FS_TEX,
2209
2210 TU_DRAW_STATE_COUNT,
2211 };
2212
2213 struct tu_draw_state_group
2214 {
2215 enum tu_draw_state_group_id id;
2216 uint32_t enable_mask;
2217 struct tu_cs_entry ib;
2218 };
2219
2220 static struct tu_sampler*
2221 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2222 const struct tu_descriptor_map *map, unsigned i)
2223 {
2224 assert(descriptors_state->valid & (1 << map->set[i]));
2225
2226 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2227 assert(map->binding[i] < set->layout->binding_count);
2228
2229 const struct tu_descriptor_set_binding_layout *layout =
2230 &set->layout->binding[map->binding[i]];
2231
2232 switch (layout->type) {
2233 case VK_DESCRIPTOR_TYPE_SAMPLER:
2234 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2235 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2236 return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS];
2237 default:
2238 unreachable("unimplemented descriptor type");
2239 break;
2240 }
2241 }
2242
2243 static uint32_t*
2244 texture_ptr(struct tu_descriptor_state *descriptors_state,
2245 const struct tu_descriptor_map *map, unsigned i)
2246 {
2247 assert(descriptors_state->valid & (1 << map->set[i]));
2248
2249 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2250 assert(map->binding[i] < set->layout->binding_count);
2251
2252 const struct tu_descriptor_set_binding_layout *layout =
2253 &set->layout->binding[map->binding[i]];
2254
2255 switch (layout->type) {
2256 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2257 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2258 return &set->mapped_ptr[layout->offset / 4];
2259 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2260 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2261 return &set->mapped_ptr[layout->offset / 4];
2262 default:
2263 unreachable("unimplemented descriptor type");
2264 break;
2265 }
2266 }
2267
2268 static uint64_t
2269 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2270 const struct tu_descriptor_map *map,
2271 unsigned i)
2272 {
2273 assert(descriptors_state->valid & (1 << map->set[i]));
2274
2275 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2276 assert(map->binding[i] < set->layout->binding_count);
2277
2278 const struct tu_descriptor_set_binding_layout *layout =
2279 &set->layout->binding[map->binding[i]];
2280
2281 switch (layout->type) {
2282 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2283 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2284 return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset];
2285 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2286 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2287 return (uint64_t) set->mapped_ptr[layout->offset / 4 + 1] << 32 |
2288 set->mapped_ptr[layout->offset / 4];
2289 default:
2290 unreachable("unimplemented descriptor type");
2291 break;
2292 }
2293 }
2294
2295 static inline uint32_t
2296 tu6_stage2opcode(gl_shader_stage type)
2297 {
2298 switch (type) {
2299 case MESA_SHADER_VERTEX:
2300 case MESA_SHADER_TESS_CTRL:
2301 case MESA_SHADER_TESS_EVAL:
2302 case MESA_SHADER_GEOMETRY:
2303 return CP_LOAD_STATE6_GEOM;
2304 case MESA_SHADER_FRAGMENT:
2305 case MESA_SHADER_COMPUTE:
2306 case MESA_SHADER_KERNEL:
2307 return CP_LOAD_STATE6_FRAG;
2308 default:
2309 unreachable("bad shader type");
2310 }
2311 }
2312
2313 static inline enum a6xx_state_block
2314 tu6_stage2shadersb(gl_shader_stage type)
2315 {
2316 switch (type) {
2317 case MESA_SHADER_VERTEX:
2318 return SB6_VS_SHADER;
2319 case MESA_SHADER_FRAGMENT:
2320 return SB6_FS_SHADER;
2321 case MESA_SHADER_COMPUTE:
2322 case MESA_SHADER_KERNEL:
2323 return SB6_CS_SHADER;
2324 default:
2325 unreachable("bad shader type");
2326 return ~0;
2327 }
2328 }
2329
2330 static void
2331 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2332 struct tu_descriptor_state *descriptors_state,
2333 gl_shader_stage type,
2334 uint32_t *push_constants)
2335 {
2336 const struct tu_program_descriptor_linkage *link =
2337 &pipeline->program.link[type];
2338 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2339
2340 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2341 if (state->range[i].start < state->range[i].end) {
2342 uint32_t size = state->range[i].end - state->range[i].start;
2343 uint32_t offset = state->range[i].start;
2344
2345 /* and even if the start of the const buffer is before
2346 * first_immediate, the end may not be:
2347 */
2348 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2349
2350 if (size == 0)
2351 continue;
2352
2353 /* things should be aligned to vec4: */
2354 debug_assert((state->range[i].offset % 16) == 0);
2355 debug_assert((size % 16) == 0);
2356 debug_assert((offset % 16) == 0);
2357
2358 if (i == 0) {
2359 /* push constants */
2360 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2361 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2362 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2363 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2364 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2365 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2366 tu_cs_emit(cs, 0);
2367 tu_cs_emit(cs, 0);
2368 for (unsigned i = 0; i < size / 4; i++)
2369 tu_cs_emit(cs, push_constants[i + offset / 4]);
2370 continue;
2371 }
2372
2373 uint64_t va = buffer_ptr(descriptors_state, &link->ubo_map, i - 1);
2374
2375 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2376 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2377 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2378 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2379 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2380 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2381 tu_cs_emit_qw(cs, va + offset);
2382 }
2383 }
2384 }
2385
2386 static void
2387 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2388 struct tu_descriptor_state *descriptors_state,
2389 gl_shader_stage type)
2390 {
2391 const struct tu_program_descriptor_linkage *link =
2392 &pipeline->program.link[type];
2393
2394 uint32_t num = MIN2(link->ubo_map.num, link->const_state.num_ubos);
2395 uint32_t anum = align(num, 2);
2396 uint32_t i;
2397
2398 if (!num)
2399 return;
2400
2401 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2402 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2403 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2404 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2405 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2406 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2407 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2408 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2409
2410 for (i = 0; i < num; i++)
2411 tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i));
2412
2413 for (; i < anum; i++) {
2414 tu_cs_emit(cs, 0xffffffff);
2415 tu_cs_emit(cs, 0xffffffff);
2416 }
2417 }
2418
2419 static struct tu_cs_entry
2420 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2421 const struct tu_pipeline *pipeline,
2422 struct tu_descriptor_state *descriptors_state,
2423 gl_shader_stage type)
2424 {
2425 struct tu_cs cs;
2426 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
2427
2428 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2429 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2430
2431 return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
2432 }
2433
2434 static struct tu_cs_entry
2435 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2436 const struct tu_pipeline *pipeline,
2437 struct tu_descriptor_state *descriptors_state,
2438 gl_shader_stage type, bool *needs_border)
2439 {
2440 const struct tu_program_descriptor_linkage *link =
2441 &pipeline->program.link[type];
2442
2443 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2444 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2445 if (!size)
2446 return (struct tu_cs_entry) {};
2447
2448 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2449 enum a6xx_state_block sb;
2450
2451 switch (type) {
2452 case MESA_SHADER_VERTEX:
2453 sb = SB6_VS_TEX;
2454 opcode = CP_LOAD_STATE6_GEOM;
2455 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2456 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2457 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2458 break;
2459 case MESA_SHADER_FRAGMENT:
2460 sb = SB6_FS_TEX;
2461 opcode = CP_LOAD_STATE6_FRAG;
2462 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2463 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2464 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2465 break;
2466 case MESA_SHADER_COMPUTE:
2467 sb = SB6_CS_TEX;
2468 opcode = CP_LOAD_STATE6_FRAG;
2469 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2470 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2471 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2472 break;
2473 default:
2474 unreachable("bad state block");
2475 }
2476
2477 struct tu_cs cs;
2478 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2479
2480 for (unsigned i = 0; i < link->texture_map.num; i++) {
2481 uint32_t *ptr = texture_ptr(descriptors_state, &link->texture_map, i);
2482
2483 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2484 tu_cs_emit(&cs, ptr[j]);
2485 }
2486
2487 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2488 struct tu_sampler *sampler = sampler_ptr(descriptors_state, &link->sampler_map, i);
2489
2490 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2491 tu_cs_emit(&cs, sampler->state[j]);
2492
2493 *needs_border |= sampler->needs_border;
2494 }
2495
2496 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2497
2498 uint64_t tex_addr = entry.bo->iova + entry.offset;
2499 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2500
2501 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2502
2503 /* output sampler state: */
2504 tu_cs_emit_pkt7(&cs, opcode, 3);
2505 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2506 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2507 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2508 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2509 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2510 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2511
2512 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2513 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2514
2515 /* emit texture state: */
2516 tu_cs_emit_pkt7(&cs, opcode, 3);
2517 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2518 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2519 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2520 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2521 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2522 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2523
2524 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2525 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2526
2527 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2528 tu_cs_emit(&cs, link->texture_map.num);
2529
2530 return tu_cs_end_sub_stream(draw_state, &cs);
2531 }
2532
2533 static void
2534 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2535 struct tu_cs *cs)
2536 {
2537 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2538
2539 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2540 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2541 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2542 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2543 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2544
2545 struct tu_cs border_cs;
2546 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2547
2548 /* TODO: actually fill with border color */
2549 for (unsigned i = 0; i < size; i++)
2550 tu_cs_emit(&border_cs, 0);
2551
2552 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2553
2554 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2555 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2556 }
2557
2558 static void
2559 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2560 struct tu_cs *cs,
2561 const struct tu_draw_info *draw)
2562 {
2563 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2564 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2565 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2566 uint32_t draw_state_group_count = 0;
2567
2568 struct tu_descriptor_state *descriptors_state =
2569 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2570
2571 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2572 if (result != VK_SUCCESS) {
2573 cmd->record_result = result;
2574 return;
2575 }
2576
2577 /* TODO lrz */
2578
2579 uint32_t pc_primitive_cntl = 0;
2580 if (pipeline->ia.primitive_restart && draw->indexed)
2581 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2582
2583 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2584 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2585 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2586
2587 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2588 tu_cs_emit(cs, pc_primitive_cntl);
2589
2590 if (cmd->state.dirty &
2591 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2592 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2593 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2594 dynamic->line_width);
2595 }
2596
2597 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2598 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2599 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2600 dynamic->stencil_compare_mask.back);
2601 }
2602
2603 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2604 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2605 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2606 dynamic->stencil_write_mask.back);
2607 }
2608
2609 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2610 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2611 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2612 dynamic->stencil_reference.back);
2613 }
2614
2615 if (cmd->state.dirty &
2616 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2617 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2618 const uint32_t binding = pipeline->vi.bindings[i];
2619 const uint32_t stride = pipeline->vi.strides[i];
2620 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2621 const VkDeviceSize offset = buf->bo_offset +
2622 cmd->state.vb.offsets[binding] +
2623 pipeline->vi.offsets[i];
2624 const VkDeviceSize size =
2625 offset < buf->bo->size ? buf->bo->size - offset : 0;
2626
2627 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2628 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2629 tu_cs_emit(cs, size);
2630 tu_cs_emit(cs, stride);
2631 }
2632 }
2633
2634 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2635 draw_state_groups[draw_state_group_count++] =
2636 (struct tu_draw_state_group) {
2637 .id = TU_DRAW_STATE_PROGRAM,
2638 .enable_mask = 0x6,
2639 .ib = pipeline->program.state_ib,
2640 };
2641 draw_state_groups[draw_state_group_count++] =
2642 (struct tu_draw_state_group) {
2643 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2644 .enable_mask = 0x1,
2645 .ib = pipeline->program.binning_state_ib,
2646 };
2647 draw_state_groups[draw_state_group_count++] =
2648 (struct tu_draw_state_group) {
2649 .id = TU_DRAW_STATE_VI,
2650 .enable_mask = 0x6,
2651 .ib = pipeline->vi.state_ib,
2652 };
2653 draw_state_groups[draw_state_group_count++] =
2654 (struct tu_draw_state_group) {
2655 .id = TU_DRAW_STATE_VI_BINNING,
2656 .enable_mask = 0x1,
2657 .ib = pipeline->vi.binning_state_ib,
2658 };
2659 draw_state_groups[draw_state_group_count++] =
2660 (struct tu_draw_state_group) {
2661 .id = TU_DRAW_STATE_VP,
2662 .enable_mask = 0x7,
2663 .ib = pipeline->vp.state_ib,
2664 };
2665 draw_state_groups[draw_state_group_count++] =
2666 (struct tu_draw_state_group) {
2667 .id = TU_DRAW_STATE_RAST,
2668 .enable_mask = 0x7,
2669 .ib = pipeline->rast.state_ib,
2670 };
2671 draw_state_groups[draw_state_group_count++] =
2672 (struct tu_draw_state_group) {
2673 .id = TU_DRAW_STATE_DS,
2674 .enable_mask = 0x7,
2675 .ib = pipeline->ds.state_ib,
2676 };
2677 draw_state_groups[draw_state_group_count++] =
2678 (struct tu_draw_state_group) {
2679 .id = TU_DRAW_STATE_BLEND,
2680 .enable_mask = 0x7,
2681 .ib = pipeline->blend.state_ib,
2682 };
2683 }
2684
2685 if (cmd->state.dirty &
2686 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2687 bool needs_border = false;
2688
2689 draw_state_groups[draw_state_group_count++] =
2690 (struct tu_draw_state_group) {
2691 .id = TU_DRAW_STATE_VS_CONST,
2692 .enable_mask = 0x7,
2693 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2694 };
2695 draw_state_groups[draw_state_group_count++] =
2696 (struct tu_draw_state_group) {
2697 .id = TU_DRAW_STATE_FS_CONST,
2698 .enable_mask = 0x6,
2699 .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
2700 };
2701 draw_state_groups[draw_state_group_count++] =
2702 (struct tu_draw_state_group) {
2703 .id = TU_DRAW_STATE_VS_TEX,
2704 .enable_mask = 0x7,
2705 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2706 descriptors_state, MESA_SHADER_VERTEX,
2707 &needs_border)
2708 };
2709 draw_state_groups[draw_state_group_count++] =
2710 (struct tu_draw_state_group) {
2711 .id = TU_DRAW_STATE_FS_TEX,
2712 .enable_mask = 0x6,
2713 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2714 descriptors_state, MESA_SHADER_FRAGMENT,
2715 &needs_border)
2716 };
2717
2718 if (needs_border)
2719 tu6_emit_border_color(cmd, cs);
2720 }
2721
2722 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2723 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2724 const struct tu_draw_state_group *group = &draw_state_groups[i];
2725
2726 uint32_t cp_set_draw_state =
2727 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2728 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2729 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2730 uint64_t iova;
2731 if (group->ib.size) {
2732 iova = group->ib.bo->iova + group->ib.offset;
2733 } else {
2734 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2735 iova = 0;
2736 }
2737
2738 tu_cs_emit(cs, cp_set_draw_state);
2739 tu_cs_emit_qw(cs, iova);
2740 }
2741
2742 tu_cs_sanity_check(cs);
2743
2744 /* track BOs */
2745 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2746 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2747 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2748 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2749 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2750 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2751 }
2752 }
2753 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2754 for (uint32_t i = 0; i < MAX_VBS; i++) {
2755 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2756 if (buf)
2757 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2758 }
2759 }
2760 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2761 unsigned i;
2762 for_each_bit(i, descriptors_state->valid) {
2763 struct tu_descriptor_set *set = descriptors_state->sets[i];
2764 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2765 if (set->descriptors[j]) {
2766 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2767 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2768 }
2769 }
2770 }
2771 cmd->state.dirty = 0;
2772 }
2773
2774 static void
2775 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2776 struct tu_cs *cs,
2777 const struct tu_draw_info *draw)
2778 {
2779
2780 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2781
2782 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2783 tu_cs_emit(cs, draw->vertex_offset);
2784 tu_cs_emit(cs, draw->first_instance);
2785
2786 /* TODO hw binning */
2787 if (draw->indexed) {
2788 const enum a4xx_index_size index_size =
2789 tu6_index_size(cmd->state.index_type);
2790 const uint32_t index_bytes =
2791 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2792 const struct tu_buffer *buf = cmd->state.index_buffer;
2793 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2794 index_bytes * draw->first_index;
2795 const uint32_t size = index_bytes * draw->count;
2796
2797 const uint32_t cp_draw_indx =
2798 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2799 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2800 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2801 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2802
2803 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2804 tu_cs_emit(cs, cp_draw_indx);
2805 tu_cs_emit(cs, draw->instance_count);
2806 tu_cs_emit(cs, draw->count);
2807 tu_cs_emit(cs, 0x0); /* XXX */
2808 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2809 tu_cs_emit(cs, size);
2810 } else {
2811 const uint32_t cp_draw_indx =
2812 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2813 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2814 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2815
2816 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2817 tu_cs_emit(cs, cp_draw_indx);
2818 tu_cs_emit(cs, draw->instance_count);
2819 tu_cs_emit(cs, draw->count);
2820 }
2821 }
2822
2823 static void
2824 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2825 {
2826 struct tu_cs *cs = &cmd->draw_cs;
2827
2828 tu6_bind_draw_states(cmd, cs, draw);
2829
2830 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2831 if (result != VK_SUCCESS) {
2832 cmd->record_result = result;
2833 return;
2834 }
2835
2836 if (draw->indirect) {
2837 tu_finishme("indirect draw");
2838 return;
2839 }
2840
2841 /* TODO tu6_emit_marker should pick different regs depending on cs */
2842 tu6_emit_marker(cmd, cs);
2843 tu6_emit_draw_direct(cmd, cs, draw);
2844 tu6_emit_marker(cmd, cs);
2845
2846 cmd->wait_for_idle = true;
2847
2848 tu_cs_sanity_check(cs);
2849 }
2850
2851 void
2852 tu_CmdDraw(VkCommandBuffer commandBuffer,
2853 uint32_t vertexCount,
2854 uint32_t instanceCount,
2855 uint32_t firstVertex,
2856 uint32_t firstInstance)
2857 {
2858 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2859 struct tu_draw_info info = {};
2860
2861 info.count = vertexCount;
2862 info.instance_count = instanceCount;
2863 info.first_instance = firstInstance;
2864 info.vertex_offset = firstVertex;
2865
2866 tu_draw(cmd_buffer, &info);
2867 }
2868
2869 void
2870 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2871 uint32_t indexCount,
2872 uint32_t instanceCount,
2873 uint32_t firstIndex,
2874 int32_t vertexOffset,
2875 uint32_t firstInstance)
2876 {
2877 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2878 struct tu_draw_info info = {};
2879
2880 info.indexed = true;
2881 info.count = indexCount;
2882 info.instance_count = instanceCount;
2883 info.first_index = firstIndex;
2884 info.vertex_offset = vertexOffset;
2885 info.first_instance = firstInstance;
2886
2887 tu_draw(cmd_buffer, &info);
2888 }
2889
2890 void
2891 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2892 VkBuffer _buffer,
2893 VkDeviceSize offset,
2894 uint32_t drawCount,
2895 uint32_t stride)
2896 {
2897 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2898 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2899 struct tu_draw_info info = {};
2900
2901 info.count = drawCount;
2902 info.indirect = buffer;
2903 info.indirect_offset = offset;
2904 info.stride = stride;
2905
2906 tu_draw(cmd_buffer, &info);
2907 }
2908
2909 void
2910 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2911 VkBuffer _buffer,
2912 VkDeviceSize offset,
2913 uint32_t drawCount,
2914 uint32_t stride)
2915 {
2916 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2917 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2918 struct tu_draw_info info = {};
2919
2920 info.indexed = true;
2921 info.count = drawCount;
2922 info.indirect = buffer;
2923 info.indirect_offset = offset;
2924 info.stride = stride;
2925
2926 tu_draw(cmd_buffer, &info);
2927 }
2928
2929 struct tu_dispatch_info
2930 {
2931 /**
2932 * Determine the layout of the grid (in block units) to be used.
2933 */
2934 uint32_t blocks[3];
2935
2936 /**
2937 * A starting offset for the grid. If unaligned is set, the offset
2938 * must still be aligned.
2939 */
2940 uint32_t offsets[3];
2941 /**
2942 * Whether it's an unaligned compute dispatch.
2943 */
2944 bool unaligned;
2945
2946 /**
2947 * Indirect compute parameters resource.
2948 */
2949 struct tu_buffer *indirect;
2950 uint64_t indirect_offset;
2951 };
2952
2953 static void
2954 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2955 const struct tu_dispatch_info *info)
2956 {
2957 }
2958
2959 void
2960 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2961 uint32_t base_x,
2962 uint32_t base_y,
2963 uint32_t base_z,
2964 uint32_t x,
2965 uint32_t y,
2966 uint32_t z)
2967 {
2968 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2969 struct tu_dispatch_info info = {};
2970
2971 info.blocks[0] = x;
2972 info.blocks[1] = y;
2973 info.blocks[2] = z;
2974
2975 info.offsets[0] = base_x;
2976 info.offsets[1] = base_y;
2977 info.offsets[2] = base_z;
2978 tu_dispatch(cmd_buffer, &info);
2979 }
2980
2981 void
2982 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2983 uint32_t x,
2984 uint32_t y,
2985 uint32_t z)
2986 {
2987 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2988 }
2989
2990 void
2991 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2992 VkBuffer _buffer,
2993 VkDeviceSize offset)
2994 {
2995 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2996 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2997 struct tu_dispatch_info info = {};
2998
2999 info.indirect = buffer;
3000 info.indirect_offset = offset;
3001
3002 tu_dispatch(cmd_buffer, &info);
3003 }
3004
3005 void
3006 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3007 {
3008 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3009
3010 tu_cs_end(&cmd_buffer->draw_cs);
3011
3012 tu_cmd_render_tiles(cmd_buffer);
3013
3014 /* discard draw_cs entries now that the tiles are rendered */
3015 tu_cs_discard_entries(&cmd_buffer->draw_cs);
3016
3017 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3018 cmd_buffer->state.attachments = NULL;
3019
3020 cmd_buffer->state.pass = NULL;
3021 cmd_buffer->state.subpass = NULL;
3022 cmd_buffer->state.framebuffer = NULL;
3023 }
3024
3025 void
3026 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3027 const VkSubpassEndInfoKHR *pSubpassEndInfo)
3028 {
3029 tu_CmdEndRenderPass(commandBuffer);
3030 }
3031
3032 struct tu_barrier_info
3033 {
3034 uint32_t eventCount;
3035 const VkEvent *pEvents;
3036 VkPipelineStageFlags srcStageMask;
3037 };
3038
3039 static void
3040 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3041 uint32_t memoryBarrierCount,
3042 const VkMemoryBarrier *pMemoryBarriers,
3043 uint32_t bufferMemoryBarrierCount,
3044 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3045 uint32_t imageMemoryBarrierCount,
3046 const VkImageMemoryBarrier *pImageMemoryBarriers,
3047 const struct tu_barrier_info *info)
3048 {
3049 }
3050
3051 void
3052 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3053 VkPipelineStageFlags srcStageMask,
3054 VkPipelineStageFlags destStageMask,
3055 VkBool32 byRegion,
3056 uint32_t memoryBarrierCount,
3057 const VkMemoryBarrier *pMemoryBarriers,
3058 uint32_t bufferMemoryBarrierCount,
3059 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3060 uint32_t imageMemoryBarrierCount,
3061 const VkImageMemoryBarrier *pImageMemoryBarriers)
3062 {
3063 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3064 struct tu_barrier_info info;
3065
3066 info.eventCount = 0;
3067 info.pEvents = NULL;
3068 info.srcStageMask = srcStageMask;
3069
3070 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3071 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3072 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3073 }
3074
3075 static void
3076 write_event(struct tu_cmd_buffer *cmd_buffer,
3077 struct tu_event *event,
3078 VkPipelineStageFlags stageMask,
3079 unsigned value)
3080 {
3081 }
3082
3083 void
3084 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3085 VkEvent _event,
3086 VkPipelineStageFlags stageMask)
3087 {
3088 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3089 TU_FROM_HANDLE(tu_event, event, _event);
3090
3091 write_event(cmd_buffer, event, stageMask, 1);
3092 }
3093
3094 void
3095 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3096 VkEvent _event,
3097 VkPipelineStageFlags stageMask)
3098 {
3099 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3100 TU_FROM_HANDLE(tu_event, event, _event);
3101
3102 write_event(cmd_buffer, event, stageMask, 0);
3103 }
3104
3105 void
3106 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3107 uint32_t eventCount,
3108 const VkEvent *pEvents,
3109 VkPipelineStageFlags srcStageMask,
3110 VkPipelineStageFlags dstStageMask,
3111 uint32_t memoryBarrierCount,
3112 const VkMemoryBarrier *pMemoryBarriers,
3113 uint32_t bufferMemoryBarrierCount,
3114 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3115 uint32_t imageMemoryBarrierCount,
3116 const VkImageMemoryBarrier *pImageMemoryBarriers)
3117 {
3118 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3119 struct tu_barrier_info info;
3120
3121 info.eventCount = eventCount;
3122 info.pEvents = pEvents;
3123 info.srcStageMask = 0;
3124
3125 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3126 bufferMemoryBarrierCount, pBufferMemoryBarriers,
3127 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3128 }
3129
3130 void
3131 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3132 {
3133 /* No-op */
3134 }